Display panel and display device

Abstract

The invention relates to a display panel and a display device. The display panel comprises a substrate, a semiconductor layer, a first metal layer and a second metal layer. The semiconductor layer is arranged on one side of the substrate; the first metal layer is arranged on the side, away from the substrate, of the semiconductor layer; the first metal layer forms a grid electrode of a transistor device of the pixel circuit; the second metal layer is arranged on the side, away from the substrate, of the first metal layer; the second metal layer comprises a first electrode, a data line, a first power line and a first polar plate. The display panel provided by the invention is low in cost.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Organic light-emitting diode (OLED) display panels are widely used due to their advantages such as thinness, active light emission, fast response speed, wide viewing angle, rich colors and high brightness, low power consumption, high and low temperature resistance, etc. With the development of OLED display devices, low cost demand has become a key point pursued by OLED display panels.

[0003] In the traditional technology, OLED display panels usually use 8 masks in the array process stage to prepare the semiconductor layer, first metal layer, second metal layer, interlayer insulation layer, third metal layer, planarization layer, anode and pixel definition layer multilayer structure in the OLED display panel. However, the cost of OLED display panels in the traditional technology is relatively high. Summary of the invention

[0004] Based on this, it is necessary to provide a display panel and a display device that can reduce costs in order to solve the above technical problems.

[0005] In a first aspect, an embodiment of the present application provides a display panel, including:

[0006] substrate;

[0007] A semiconductor layer is disposed on one side of the substrate;

[0008] A first metal layer is disposed on a side of the semiconductor layer away from the substrate; the first metal layer forms a gate of a transistor device of a pixel circuit;

[0009] The second metal layer is arranged on the side of the first metal layer away from the substrate; the second metal layer includes a first electrode, a data line, a first power line and a first electrode plate.

[0010] In one embodiment, the first metal layer includes a second power supply line, a reference voltage signal line, a light emitting control signal line, a scanning signal line, and a second electrode plate; the first electrode plate and the second electrode plate form a storage capacitor of the pixel circuit;

[0011] Optionally, the first power line and the second power line are electrically connected, the second power line extends along a first direction perpendicular to the thickness direction of the substrate, and the first power line extends along a second direction perpendicular to the thickness direction of the substrate; the first direction and the second direction intersect.

[0012] In one embodiment, the display panel further comprises:

[0013] A pixel defining layer is disposed on a side of the second metal layer facing away from the substrate, the pixel defining layer includes a pixel opening, and the first electrode is disposed corresponding to the pixel opening;

[0014] Optionally, an orthographic projection of the pixel opening on the substrate intersects with an orthographic projection portion of the light emission control signal line on the substrate.

[0015] In one embodiment, the orthographic projection of the data line on the substrate, the orthographic projection of the first power line on the substrate, and the orthographic projection of the first electrode plate on the substrate are all located outside the orthographic projection range of the pixel opening on the substrate;

[0016] Optionally, the orthographic projection of the reference voltage signal line on the substrate, the orthographic projection of the second electrode plate on the substrate, and the orthographic projection of the scanning signal line on the substrate are all located outside the orthographic projection range of the pixel opening on the substrate;

[0017] Optionally, the scanning signal line includes a first scanning signal line, a second scanning signal line and a third scanning signal line; the pixel circuit is used to apply the signal received by the reference voltage signal line to the transistor device according to the signal received by the first scanning signal line, the pixel circuit is used to apply the signal received by the data line to the transistor device according to the signal received by the second scanning signal line, the pixel circuit is used to apply the signal received by the reference voltage signal line to the first electrode according to the signal received by the third scanning signal line, and the orthographic projection of the pixel opening on the substrate is located between the orthographic projection of the second electrode plate on the substrate and the orthographic projection of the third scanning signal line on the substrate.

[0018] In one embodiment, the display panel further comprises:

[0019] A light emitting portion is disposed in the pixel opening;

[0020] The display panel also includes:

[0021] a second electrode, wherein a first portion of the second electrode is disposed on a side of the second metal layer away from the substrate, and a second portion of the second electrode is disposed on a side of the pixel defining layer away from the substrate;

[0022] Optionally, the display panel further includes:

[0023] A supporting structure is arranged on a side of the pixel defining layer facing away from the substrate;

[0024] Optionally, the display panel further includes:

[0025] A first insulating layer, disposed between the first metal layer and the second metal layer;

[0026] The second insulating layer is arranged between the semiconductor layer and the first metal layer.

[0027] In one of the embodiments, there are multiple reference voltage signal lines, and adjacent reference voltage signal lines in the first direction are connected through the second metal layer.

[0028] In one embodiment, the transistor device includes a reset transistor and a normally-on transistor, a first terminal of the normally-on transistor is connected to the reset transistor, a second terminal of the normally-on transistor is connected to the first electrode,

[0029] The reference voltage signal line extends along a first direction, an orthographic projection of the reference voltage signal line on the substrate overlaps with an orthographic projection of the semiconductor layer on the substrate, and a portion of the reference voltage signal line corresponding to the overlap forms a gate of a normally-on transistor.

[0030] In one of the embodiments, the orthographic projection of the data line on the substrate, the orthographic projection of the first power line on the substrate, and the orthographic projection of the first electrode on the substrate are all outside the orthographic projection range of the pixel opening on the substrate; and a partial area of ​​the orthographic projection of the reference voltage signal line on the substrate and a partial area of ​​the orthographic projection of the scanning signal line on the substrate are located within the orthographic projection range of the pixel opening on the substrate.

[0031] In one of the embodiments, the second electrode plate includes a connected main body portion and an extension portion; in the second direction, the orthographic projection of the main body portion on the substrate is located between the orthographic projection of the second scanning signal line on the substrate and the orthographic projection of the pixel opening on the substrate; the extension portion is connected to a side of the main body away from the second scanning signal line and extends along the second direction, and the orthographic projection of the extension portion on the substrate is located between the orthographic projection of the pixel opening on the substrate and the orthographic projection of the data line on the substrate.

[0032] In a second aspect, an embodiment of the present application further provides a display device, comprising the display panel provided in the first aspect above.

[0033] The embodiment of the present application provides a display panel and a display device. The display panel includes a substrate, a semiconductor layer, a first metal layer and a second metal layer. The semiconductor layer is arranged on one side of the substrate; the first metal layer is arranged on the side of the semiconductor layer away from the substrate, and the first metal layer forms the gate of the transistor device of the pixel circuit; the second metal layer is arranged on the side of the first metal layer away from the substrate; the second metal layer includes a first electrode, a data line, a first power line and a first electrode. In this embodiment, the transistor device of the pixel circuit of the display panel can be formed by the semiconductor layer and the first metal layer, and the storage capacitor of the pixel circuit of the display panel can be formed by the first metal layer and the second metal layer, and the second metal layer can be used as the first electrode. Compared with the traditional technology, this reduces one metal layer, a planarization layer and an Anode layer, and can optimize the pixel circuit layout of the display panel. In other words, it can optimize the layout of the pixel circuit of the display panel while reducing the cost, so that the display panel has higher applicability. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of the present application, the drawings required for use in the description of the embodiments or exemplary embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0035] Figure 1 A schematic diagram of an Array process flow diagram provided for an embodiment;

[0036] Figure 2 A schematic diagram of the structure of a display panel provided by an embodiment;

[0037] Figure 3 A schematic diagram of the structure of a pixel circuit provided by an embodiment;

[0038] Figure 4 A schematic diagram of a waveform of a driving signal of a pixel circuit provided by an embodiment;

[0039] Figure 5 A schematic structural diagram of a display panel provided in another embodiment;

[0040] Figure 6 A schematic diagram of the structure of a display panel provided by an embodiment from a macroscopic perspective;

[0041] Figure 7 A partial structural schematic diagram of a display panel provided in another embodiment;

[0042] Figure 8 A schematic diagram of the structure of a display panel provided in another embodiment from a macroscopic perspective;

[0043] Fig. 9 A partial structural schematic diagram of a display panel provided in another embodiment;

[0044] Fig.10 A schematic diagram of the structure of a display panel provided in another embodiment from a macroscopic perspective;

[0045] Fig.11 A schematic structural diagram of a pixel circuit provided by another embodiment;

[0046] Fig.12 A schematic flow chart of a method for preparing a display panel provided in one embodiment.

[0047] Description of reference numerals:

[0048] 1. cathode overlapping area; 2. scanning circuit area; 10. display panel; 100. substrate; 200. semiconductor layer; 300. first metal layer; 310. main body; 320. extension part; 400. second metal layer; 401. first electrode; 500. pixel defining layer; 501. pixel opening; 502. light-emitting part; 600. second electrode; 601. first partial area; 602. second partial area; 700. supporting structure; 800. first insulating layer; 900. second insulating layer. DETAILED DESCRIPTION

[0049] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive.

[0050] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, they do not represent any order, quantity or importance, but are only used to distinguish different components. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present application, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element. "Include" or "comprising" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0051] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0052] Organic light-emitting diode (OLED) display panels are widely used due to their advantages such as thinness, active light emission, fast response speed, wide viewing angle, rich colors and high brightness, low power consumption, high and low temperature resistance, etc. With the development of OLED display devices, low cost demand has become a key point pursued by OLED display panels.

[0053] In traditional technology, such as Figure 1As shown, OLED display panels usually use 8 masks in the array process stage to sequentially prepare the semiconductor layer (P-Si), the first metal layer (M1), the second metal layer (M2), the interlayer insulation layer (ILD), the third metal layer (M3), the planarization layer (PLA), the anode (Anode) and the semi-transparent membrane layer (HTM) multi-layer structure in the OLED display panel. The semi-transparent membrane layer may include a pixel definition layer (PDL) / support layer (SPC). Among them, P-Si and M1 form a transistor device, M1 and M2 form a storage capacitor, M3 is used as a power supply line, and ILD is used to bridge P-Si, M1, M2 and M3.

[0054] However, in traditional technology, OLED display panels have many steps in the array process stage, which will limit the cost reduction of OLED display panels. Costs can be reduced by reducing M2, PLA and Anode, but the reduction in the number of layers will make it difficult to layout the circuits in the OLED display panel, such as the 7T1C pixel circuit, and the peripheral circuit layout, such as the inability to effectively overlap the cathode of the peripheral frame.

[0055] In view of the above problems, the embodiments of the present application provide a display panel and a display device. The display panel includes a substrate, a semiconductor layer, a first metal layer and a second metal layer. The semiconductor layer is arranged on one side of the substrate; the first metal layer is arranged on the side of the semiconductor layer away from the substrate, and the first metal layer forms the gate of the transistor device of the pixel circuit; the second metal layer is arranged on the side of the first metal layer away from the substrate, and the second metal layer includes a first electrode, a data line, a first power line and a first electrode plate. The display panel provided in the present application can optimize the layout of the pixel circuit in the display panel of the OLED display panel while reducing the number of layers and reducing costs, and realize the effective overlap of the cathode of the outer frame.

[0056] The technical solution of the present application and how the technical solution of the present application solves the technical problem are described in detail below with specific embodiments.

[0057] In one embodiment, Figure 2 As shown, a display panel 10 is provided, including a substrate 100 , a semiconductor layer 200 , a first metal layer 300 and a second metal layer 400 .

[0058] The semiconductor layer 200 is disposed on one side of the substrate 100; the first metal layer 300 is disposed on the side of the semiconductor layer 200 away from the substrate 100; the second metal layer 400 is disposed on the side of the first metal layer 300 away from the substrate 100; the second metal layer 400 includes a first electrode, a data line, a first power line and a first electrode plate. The semiconductor layer 200 and the first metal layer 300 can form a transistor device of a pixel circuit. The pixel circuit includes multiple transistor devices, and the semiconductor layer 200 and the first metal layer 300 can form multiple transistor devices.

[0059] The substrate 100 may be a substrate of an inorganic material, a substrate of an organic material, or a composite substrate formed by stacking an inorganic material substrate and an organic material substrate. This embodiment does not limit the material and structure of the substrate 100 as long as it can achieve its function.

[0060] The semiconductor layer 200, the first metal layer 300 and the second metal layer 400 are stacked in sequence along the thickness direction of the substrate 100. The semiconductor layer 200 may be a P-Si layer, and the semiconductor layer 200 may include a channel region and a source region and a drain region doped with a dopant, which may be used as the source and drain of the transistor device of the pixel circuit in the display panel 10, respectively. The first metal layer 300 may form a gate of the transistor device, so that the first metal layer 300 and the semiconductor layer 200 form a transistor device. The second metal layer 400 includes a first electrode, a data line, a first power line and a first plate. The first electrode is an anode in the display panel 10, the data line is a wire that provides pixel data, and the first power line refers to a wire that provides a power supply voltage for the pixel circuit. The first plate may refer to an upper plate of a storage capacitor in the display panel 10. The first plate in the second metal layer 400 may form a storage capacitor with the first metal layer 300. This embodiment does not limit the materials and specific structures of the semiconductor layer 200, the first metal layer 300 and the second metal layer 400, as long as their functions can be achieved.

[0061] In an optional embodiment, the second metal layer 400 may adopt an ITO (indium tin oxide) / Ti (titanium) / Al (aluminum) / Ti laminated structure, with ITO serving as the first electrode. In the structure of the second metal layer 400, a metal with high reflectivity, such as Ti, may be preferably used under the ITO layer, or other metals, such as Ag (silver), that is, the second metal layer 400 adopts an ITO / Ag / Al / Ti laminated structure.

[0062] In an optional embodiment, if Figure 3As shown, the pixel circuit includes multiple transistor devices (T1-T7) and a storage capacitor C, wherein S1, S2, and S3 are scanning signals input to the pixel circuit, em is a light emitting control signal input to the pixel circuit, data refers to data input to the pixel circuit through a data line, V2 is a first power supply input through a first power supply line, V1 is a reference voltage, and V3 is a cathode signal. Figure 4 The semiconductor layer 200 and the first metal layer 300 form transistor devices in the pixel circuit, and the first metal layer 300 and the second metal layer 400 form storage capacitors in the pixel circuit.

[0063] The display panel 10 provided in the embodiment of the present application includes a substrate 100, a semiconductor layer 200, a first metal layer 300 and a second metal layer 400. The semiconductor layer 200 is disposed on one side of the substrate 100; the first metal layer 300 is disposed on the side of the semiconductor layer 200 away from the substrate 100, and the first metal layer 300 forms the gate of the transistor device of the pixel circuit; the second metal layer 400 is disposed on the side of the first metal layer 300 away from the substrate 100; the second metal layer 400 includes a first electrode, a data line, a first power line and a first plate. In the present embodiment, a transistor device of a pixel circuit of the display panel 10 can be formed by the semiconductor layer 200 and the first metal layer 300, a storage capacitor of the pixel circuit of the display panel 10 can be formed by the first metal layer 300 and the second metal layer 400, and the second metal layer 400 can serve as a first electrode. Compared with the conventional technology, this reduces one metal layer, a planarization layer and an Anode layer, and can optimize the layout of the pixel circuit of the display panel 10. That is to say, it is possible to optimize the layout of the pixel circuit of the display panel 10 while reducing costs, so that the display panel 10 has higher applicability.

[0064] In one embodiment, Figure 5 As shown, the display panel 10 further includes: a pixel defining layer 500. The pixel defining layer 500 is disposed on the side of the second metal layer 400 away from the substrate 100. That is, the semiconductor layer 200, the first metal layer 300, the second metal layer 400 and the pixel defining layer 500 in the display panel 10 are sequentially stacked along the thickness direction of the substrate 100.

[0065] The pixel defining layer 500 includes a pixel opening 501, and the first electrode 401 is arranged corresponding to the pixel opening 501. That is, an opening is opened at a position corresponding to the first electrode 401 in the pixel defining layer 500 to expose the first electrode 401. In the case where there are multiple first electrodes 401, multiple pixel openings 501 are opened on the pixel defining layer 500 accordingly. The pixel defining layer 500 can be made of inorganic materials, organic materials, or both organic materials and inorganic materials. This embodiment does not limit the material and structure of the pixel defining layer 500, as long as its function can be achieved.

[0066] In this embodiment, a pixel opening 501 is provided at a position corresponding to the first electrode 401 in the pixel defining layer 500, so as to form a pixel unit at the pixel opening 501. In this way, the pixel defining layer 500 can prevent cross-color from occurring between adjacent pixel units, thereby improving the practicality of the display panel 10.

[0067] In one embodiment, Figure 6 As shown, the first metal layer 300 includes a second power line ELVDD2, a reference voltage signal line Vrefn, a light emitting control signal line EM, a scanning signal line (Scan1 / 3 and Scan2), and a second electrode plate. The first electrode plate and the second electrode plate form a storage capacitor C in the pixel circuit.

[0068] The second power line ELVDD2 is the same as the first power line ELVDD1, and both are wires for providing power supply voltage to the pixel circuit. The reference voltage signal line Vrefn is a wire for providing reference voltage to the pixel circuit. The light-emitting control signal line EM is a wire for transmitting a signal for controlling whether the light-emitting device in the display panel 10 emits light. The scan signal lines (Scan1 / 3 and Scan2) are wires for sending scan signals to the pixel circuit. The second electrode in the first metal layer 300 and the first electrode in the second metal layer 400 can form a storage capacitor C in the pixel circuit.

[0069] In this embodiment, the first metal layer 300 can be used as the second power line ELVDD2 , the reference voltage signal line Vrefn, the light emitting control signal line EM and the scanning signal lines ( Scan1 / 3 and Scan2 ), as well as the second electrode plate, improving the practicality of the display panel 10 .

[0070] In one embodiment, Figure 6 As shown, the first power line ELVDD1 and the second power line ELVDD2 are electrically connected, the second power line ELVDD2 extends along a first direction perpendicular to the thickness direction of the substrate 100, and the first power line ELVDD1 extends along a second direction perpendicular to the thickness direction of the substrate 100, and the first direction and the second direction intersect.

[0071] The first direction is the X direction, the second direction is the Y direction, the first power line LVDD1 and the second power line ELVDD2 are not located in the same metal layer, and are connected through vias. Preferably, the first direction and the second direction are perpendicular to each other.

[0072] In one embodiment, Figure 6 As shown, the orthographic projection of the pixel opening 501 on the substrate 100 intersects with the orthographic projection portion of the light emission control signal line EM on the substrate 100 .

[0073] The light-emitting control signal line EM is the first metal layer 300, the pixel defining layer 500 includes a pixel opening 501, and the pixel defining layer 500 is arranged on the side of the second metal layer 400 away from the substrate 100, that is, along the thickness direction of the display panel 10, when the substrate 100 is located at the bottom layer, the light-emitting control signal line EM is located below the pixel opening 501.

[0074] In this embodiment, the orthographic projection of the pixel opening 501 on the substrate 100 intersects with the orthographic projection of the light emitting control signal line EM on the substrate 100 , so that the arrangement of the light emitting control signal line EM does not affect the arrangement of the pixel opening 501 .

[0075] In one embodiment, Figure 6 As shown, Figure 6 As shown, the orthographic projection of the data line Data on the substrate 100 , the orthographic projection of the first power line ELVDD1 on the substrate 100 , and the orthographic projection of the first electrode on the substrate 100 are all located outside the orthographic projection range of the pixel opening 501 on the substrate 100 .

[0076] The first electrode 401, the data line Data, the first power line ELVDD1, and the first electrode plate are all located in the second metal layer 400, wherein the orthographic projection of the data line Data on the substrate 100, the orthographic projection of the first power line ELVDD1 on the substrate 100, and the orthographic projection of the first electrode plate on the substrate 100 are all located outside the orthographic projection of the pixel opening 501 corresponding to the first electrode 401 on the substrate 100. That is to say, the data line Data, the first power line ELVDD1, and the first electrode plate are arranged in other areas of the second metal layer 400 except the first electrode 401, the second metal layer 400 corresponding to the pixel opening area opened on the pixel defining layer 500 includes the first electrode 401, and the second metal layer 400 corresponding to the non-pixel opening area on the pixel defining layer 500 includes the data line Data, the first power line ELVDD1, and the first electrode plate.

[0077] In this embodiment, the orthographic projection of the data line Data on the substrate 100, the orthographic projection of the first power line ELVDD1 on the substrate 100, and the orthographic projection of the first electrode on the substrate 100 are all located outside the orthographic projection range of the pixel opening 501 on the substrate 100. This can increase the opening area of ​​the pixel opening 501 and improve the luminous effect, thereby improving the display effect of the display panel 10.

[0078] In one embodiment, the orthographic projection of the reference voltage signal line Vrefn on the substrate 100 , the orthographic projection of the second electrode on the substrate 100 , and the orthographic projection of the scanning signal lines (Scan1 / 3 and Scan2) on the substrate 100 are all located outside the orthographic projection range of the pixel opening 501 on the substrate 100 .

[0079] like Figure 6 As shown, the reference voltage signal line Vrefn, the second electrode, and the scanning signal lines (Scan1 / 3 and Scan2) are located at the periphery of the pixel opening 501, so that a position can be reserved for the pixel opening 501 to increase the opening area of ​​the pixel opening 501 and improve the luminous effect, thereby improving the display effect of the display panel 10.

[0080] See also Figure 3 and Figure 6 In one embodiment, the scan signal lines include a first scan signal line Scan1, a second scan signal line Scan2 and a third scan signal line Scan3.

[0081] The pixel circuit is used to apply the signal received by the reference voltage signal line Vrefn to the transistor device according to the signal received by the first scanning signal line Scan1. Figure 3 As shown, the scan signal S1 received by the first scan signal line Scan1 applies the signal V1 received by the reference voltage signal line Vrefn to the transistor T4.

[0082] The pixel circuit is used to apply the signal received by the data line Data to the transistor device according to the signal received by the second scanning signal line Scan2. Figure 3 As shown, the scan signal S2 received by the second scan signal line Scan2 applies the signal received by the data line Data to the transistor T2. In addition, the scan signal S2 received by the second scan signal line Scan2 is also used to apply the electrical signal released by the storage capacitor C to the transistor T3.

[0083] The pixel circuit is used to apply the signal received by the reference voltage signal line Vrefn to the first electrode according to the signal received by the third scan signal line Scan3. Figure 3As shown, the scan signal S3 received by the third scan signal line Scan3 applies the signal V1 received by the reference voltage signal line Vrefn to the first electrode through the reset transistor T7.

[0084] like Figure 6 As shown, the orthographic projection of the pixel opening 501 on the substrate 100 is located between the orthographic projection of the second electrode plate on the substrate 100 and the orthographic projection of the third scanning signal line Scan3 on the substrate.

[0085] In this embodiment, corresponding signals are provided to the transistor device and the first electrode in the pixel circuit through the first scanning signal line Scan1, the second scanning signal line Scan2 and the third scanning signal line Scan3, so as to ensure the normal operation of the pixel circuit.

[0086] In one embodiment, Figure 5 As shown, the display panel 10 further includes a light emitting portion 502, which is disposed in the pixel opening 501. The semiconductor layer 200, the first metal layer 300, the second metal layer 400 and the light emitting portion 502 may form a plurality of pixel circuits.

[0087] The display panel 10 includes a plurality of pixel units, each of which corresponds to a pixel circuit. The semiconductor layer 200, the first metal layer 300, the second metal layer 400 and the light-emitting portion 502 in the display panel 10 can form a pixel circuit. Specifically, the semiconductor layer 200 and the first metal layer 300 can form a plurality of transistor devices in the pixel circuit, the first electrode in the second metal layer 400 and the second electrode in the first metal layer 300 can form a storage capacitor in the pixel circuit, and the light-emitting portion 502 can form a light-emitting device in the pixel circuit.

[0088] In this embodiment, a plurality of pixel circuits can be formed using the semiconductor layer 200, the first metal layer 300, the second metal layer 400 and the light-emitting portion 502 in the display panel 10. This can reduce the number of layers, thereby reducing costs, and can optimize the layout of the pixel circuits, thereby making the display panel 10 more practical.

[0089] In one embodiment, Figure 7 As shown, the display panel 10 further includes a second electrode 600 , a first portion of the second electrode 600 is disposed on a side of the second metal layer 400 facing away from the substrate 100 , and a second portion of the second electrode 600 is disposed on a side of the pixel defining layer 500 facing away from the substrate 100 .

[0090] A pixel opening 501 is provided on the pixel defining layer 500, exposing the first electrode 401 in the second metal layer 400, and the first partial region 601 of the formed second electrode 600 is arranged on the side of the first electrode 401 in the second metal layer 400 away from the substrate 100, and the second partial region 602 of the second electrode 600 is arranged on the side of the pixel defining layer 500 away from the substrate 100. The second electrode 600 is a cathode. The second electrode 600 can be made of a magnesium (Mg) / silver (Ag) alloy. This embodiment does not limit the material of the second electrode 600, as long as the second electrode 600 and the first electrode 401 have a better matching work function.

[0091] In this embodiment, the second metal layer 400 is electrically connected to the second electrode 600 through the pixel opening 501, so that the effective overlap of the second electrode 600 of the outer frame of the display panel 10 can be achieved, and the pixel defining layer 500 is provided on the second metal layer 400 except for the area corresponding to the pixel opening 501, so that the short circuit between the other metal layers away from the pixel defining layer 500 and the second electrode 600 can be avoided. Figure 8 As shown, the area where the second electrode 600 intersects with the second metal layer 400 is the cathode overlapping area 1 , and the other area is the scanning circuit area 2 .

[0092] In one embodiment, Fig. 9 As shown, the display panel 10 further includes a support structure 700 . The support structure 700 is disposed on a side of the pixel defining layer 500 away from the second metal layer 400 .

[0093] In this embodiment, a support structure 700 is provided on the side of the pixel defining layer 500 away from the second metal layer 400. The support structure 700 can support the glass cover required in the subsequent preparation process, and can prevent the film layer of the support structure 700 close to the substrate 100 from being damaged. In addition, the support structure 700 can also serve as an isolation column.

[0094] In one embodiment, Fig. 9 As shown, the display panel 10 further includes a first insulating layer 800 . The first insulating layer 800 is disposed between the first metal layer 300 and the second metal layer 400 .

[0095] A first insulating layer 800 is provided on the side of the first metal layer 300 facing away from the substrate 100. The first insulating layer 800 may constitute an insulating dielectric layer of a storage capacitor formed by the first electrode of the first metal layer 300 and the second metal layer 400. The material of the first insulating layer 800 may include chlorine (CI) or SiO x In this embodiment, there is no limitation on the material of the first insulating layer 800 as long as it can achieve its function.

[0096] In this embodiment, a first insulating layer 800 is formed between the first metal layer 300 and the second metal layer 400 to avoid electrical connection between the first metal layer 300 and the second metal layer 400, so that the first plates in the first metal layer 300 and the second metal layer 400 form a storage capacitor.

[0097] In one embodiment, Fig. 9 As shown, the display panel 10 further includes a second insulating layer 900 . The second insulating layer 900 is disposed between the semiconductor layer 200 and the first metal layer 300 .

[0098] The second insulating layer 900 may be a gate insulating layer (GI), which may isolate the first metal layer 300 and the semiconductor layer 200 , that is, isolate the gate in the first metal layer 300 from the semiconductor layer 200 , so that the first metal layer 300 and the semiconductor layer 200 form a transistor.

[0099] In an optional embodiment, the display panel 10 further includes a buffer layer. The buffer layer is disposed between the substrate 100 and the semiconductor layer 200 .

[0100] In one embodiment, there are a plurality of reference voltage signal lines Vrefn, and adjacent reference voltage signal lines Vrefn in the first direction are connected through the second metal layer 400 .

[0101] like Figure 6 As shown, each pixel circuit corresponds to a reference voltage signal line Vrefn, the reference voltage signal lines Vrefn corresponding to adjacent pixel circuits are disconnected, and the reference voltage signal lines Vrefn corresponding to adjacent pixel circuits are connected through the second metal layer 400 .

[0102] In one embodiment, Fig.10 and Fig.11 As shown, the transistor device includes a reset transistor T7 and a normally-on transistor T8, a first end of the normally-on transistor T8 is connected to the reset transistor T7, and a second end of the normally-on transistor T8 is connected to the first electrode.

[0103] The reference voltage signal line Vrefn extends along the first direction, and an orthographic projection of the reference voltage signal line Vrefn on the substrate 100 overlaps with an orthographic projection of the semiconductor layer 200 on the substrate 100 . The portion of the reference voltage signal line Vrefn corresponding to the overlapping region forms the gate of the normally-on transistor T8 .

[0104] The reference voltage signal lines Vrefn corresponding to each pixel circuit are connected and extend along the first direction. The orthographic projection of the connected portion of the reference voltage signal lines Vrefn corresponding to two adjacent pixel circuits on the substrate 100 overlaps with the orthographic projection of the corresponding portion of the semiconductor layer 200 on the substrate 100, and the portion of the reference voltage signal line Vrefn corresponding to the overlapping region forms the gate of the normally-on transistor T8.

[0105] like Fig.10 As shown, the reference voltage signal line Vrefn extending along the first direction is continuous, and between adjacent pixel opening 501 areas, the connected area in the reference voltage signal line Vrefn and part of the semiconductor layer 200 can form a normally-on transistor T8, and the reference voltage signal line Vrefn serves as the gate of the normally-on transistor T8.

[0106] In this embodiment, the reference voltage signal line Vrefn extends along the first direction, and there is an overlapping area between the orthographic projection of the reference voltage signal line Vrefn on the substrate 100 and the orthographic projection of the semiconductor layer 200 on the substrate 100. In this way, there is no need to set a second metal layer 400 between the reference voltage signal lines Vrefn corresponding to adjacent pixel circuits, so that the area of ​​the pixel opening 501 can be extended to the second direction, thereby increasing the area of ​​the pixel opening 501, which can improve the pixel aperture ratio of the display panel 10, and further improve the display effect of the display panel 10.

[0107] In addition, the reference voltage signal line Vrefn is connected to the semiconductor layer 200 to form a normally-on transistor T8 in the pixel circuit, which can reduce the leakage of the first electrode 401 in the second metal layer 400 and improve the display stability of the display panel 10. The reference voltage signal line Vrefn serves as the gate of the normally-on transistor T8 to keep the normally-on transistor T8 in a normally-on state, which will not affect the reset transistor T7 in the pixel circuit to reset the first electrode 401, thereby improving the practicality of the display panel 10.

[0108] In one embodiment, Fig.10 As shown, the orthographic projection of the data line Data on the substrate 100, the orthographic projection of the first power line ELVDD1 on the substrate 100, and the orthographic projection of the first electrode on the substrate 100 are all located outside the orthographic projection range of the pixel opening on the substrate 100, and the target area on the pixel defining layer 500 is outside the orthographic projection on the substrate 100; a partial area of ​​the orthographic projection of the reference voltage signal line Vrefn on the substrate 100, and a partial area of ​​the orthographic projection of the scan signal lines (Scan1 / 3 and Scan2) on the substrate 100 are located within the orthographic projection range of the pixel opening 501 on the substrate 100.

[0109] The orthographic projection of the data line Data on the substrate 100, the orthographic projection of the first power line ELVDD1 on the substrate 100, and the orthographic projection of the first electrode on the substrate 100 are all located at the periphery of the pixel opening 501 area. Part of the orthographic projection of the reference voltage signal line Vrefn on the substrate 100 intersects with the orthographic projection of the pixel opening 501 on the substrate 100. Part of the orthographic projection of the scan signal lines (Scan1 / 3 and Scan2) on the substrate 100 intersects with the orthographic projection of the pixel opening 501 on the substrate 100.

[0110] In this embodiment, the data line Data, the first power line ELVDD1, the reference voltage signal line Vrefn and the scan signal lines (Scan1 / 3 and Scan2) are centrally arranged, which can increase the area of ​​the pixel opening 501, thereby improving the pixel aperture ratio of the display panel 10 and further improving the display effect of the display panel 10.

[0111] In one embodiment, Fig.10 As shown, the second electrode plate includes a main body portion 310 and an extension portion 320 that are connected; in the second direction, the orthographic projection of the main body portion 310 on the substrate 100 is located between the orthographic projection of the second scanning signal line Scan2 on the substrate 100 and the orthographic projection of the pixel opening 501 on the substrate 100, the extension portion 320 is connected to the side of the main body 310 away from the second scanning signal line Scan2, and extends along the second direction, and the orthographic projection of the extension portion 320 on the substrate 100 is located between the orthographic projection of the pixel opening 501 on the substrate 100 and the orthographic projection of the data line Data on the substrate 100.

[0112] The main body 310 and the extension 320 in the second electrode plate form a shape similar to “G”. In the second direction, one end of the extension 320 away from the main body 310 is spaced apart from the light emission control signal line.

[0113] like Fig.10 As shown, the extension portion 320 of the second electrode in the first metal layer 300 extends along the second direction toward the peripheral area of ​​the pixel opening 501. The second metal layer 400 is disposed in the peripheral area along the second direction toward the pixel opening 501, and by extending a portion of the first electrode in the first metal layer 300 along the second direction toward the peripheral area of ​​the pixel opening 501, the first electrode of the extended portion and the corresponding second metal layer 400 can form a storage capacitor.

[0114] In this embodiment, the second electrode plate includes a main body portion 310 and an extension portion 320. The extension portion 320 is formed by extending a partial area of ​​the main body portion 310 in the second direction. This can increase the area of ​​the storage capacitor, thereby improving the gate voltage holding capability of the pixel circuit including the storage capacitor, thereby making the display panel 10 more practical.

[0115] In an optional embodiment, if Fig.10 As shown, the power line ELVDD2 in the second direction is bridged by the second metal layer 400, and the first metal layer 300 connected to the power line ELVDD2 in the first direction is deleted, so that the pixel opening 501 can be extended to the position where the deleted first metal layer 300 is located, thereby increasing the pixel opening 501, and further improving the pixel aperture ratio of the display panel 10, thereby improving the display effect of the display panel 10.

[0116] In one embodiment, Figure 6 and Fig.10 As shown, the orthographic projection of the semiconductor layer 200 on the substrate 100 intersects with the orthographic projection of the corresponding first electrode plate on the substrate 100 .

[0117] Likewise, the orthographic projection of the semiconductor layer 200 on the substrate 100 intersects with the orthographic projection of the corresponding second electrode plate on the substrate 100 .

[0118] The semiconductor layer 200, the first metal layer 300, and the second metal layer 400 are sequentially arranged along the thickness direction of the substrate 100, and the second electrode plate in the first metal layer 300 and the first electrode plate in the second metal layer 400 form a storage capacitor. The orthographic projection of a part of the semiconductor layer 200 on the substrate 100 intersects with the orthographic projection of the first electrode plate on the substrate 100. It can be understood that, along the thickness direction of the display panel 10, if the substrate 100 is the bottom layer, the semiconductor layer 200 passes through the bottom of the second electrode plate.

[0119] Optionally, the orthographic projection profile of the semiconductor layer 200 on the substrate 100 may be in the shape of a straight line.

[0120] In this embodiment, the orthographic projection of the semiconductor layer 200 on the substrate 100 intersects with the orthographic projection of the corresponding second electrode plate on the substrate 100. In this way, the semiconductor layer 200 can be prevented from occupying a large space, so that a large space can be reserved for the pixel opening 501, thereby improving the pixel opening ratio of the display panel 10, so that the display panel 10 has higher practicality.

[0121] See also Fig.12 An embodiment of the present application provides a method for preparing a display panel, the steps of the preparation method comprising:

[0122] Step 120: providing a substrate;

[0123] Step 121, forming a semiconductor layer on one side of the substrate;

[0124] Step 122, forming a first metal layer on a side of the semiconductor layer facing away from the substrate;

[0125] Step 123, forming a second metal layer on a side of the first metal layer away from the substrate; the second metal layer includes a first electrode, a data line, a first power line and a first electrode plate.

[0126] That is, a semiconductor layer is first prepared on the substrate, and then a first metal layer is prepared, so that the semiconductor layer and the first metal layer can form a transistor device. A second metal material layer is prepared on the first metal layer, and the second metal material layer is patterned to form a second metal layer including a first electrode, a data line, a first power line, and a first electrode plate, so that the first electrode plate included in the second metal layer and the second electrode plate included in the first metal layer form a storage capacitor. The description of the substrate, the semiconductor layer, the first metal layer, and the second metal layer can refer to the specific description of the above embodiment, and will not be repeated here.

[0127] The method for preparing the display panel provided in this embodiment comprises providing a substrate; forming a semiconductor layer on one side of the substrate; forming a first metal layer on the side of the semiconductor layer facing away from the substrate; forming a second metal layer on the side of the first metal layer facing away from the substrate; the second metal layer comprises a first electrode, a data line, a first power line and a first electrode plate. Compared with the conventional technology, the display panel prepared by the method for preparing the display panel provided in this embodiment reduces one metal layer, a planarization layer and an Anode, and can optimize the pixel circuit layout of the display panel, that is, can optimize the layout of the pixel circuit of the display panel while reducing the cost.

[0128] It should be noted that in the method for preparing the display panel provided in the embodiment of the present application, each film layer can be prepared by sputtering, chemical vapor deposition (CVD), vacuum deposition, pulsed laser deposition (PLD), atomic layer deposition (ALD), etc. The CVD method includes plasma enhanced chemical vapor deposition (PECVD), laser chemical vapor deposition (LCVD), low pressure chemical vapor deposition (LPCVD), etc.

[0129] An embodiment of the present application further provides a display device, which includes the display panel 10 provided in the above embodiment.

[0130] The display device provided in the embodiment of the present application includes the display panel 10 , and the display device has all the beneficial effects of the display panel 10 , which will not be described in detail herein.

[0131] The display device can be a laptop computer, a mobile phone, a wireless device, a personal digital assistant (PDA), a handheld or portable computer, a GPS receiver / navigator, a camera, an MP4 video player, a camcorder, a game console, a watch, a clock, a calculator, a television monitor, a flat-panel display, a computer monitor, a car display (e.g., an odometer display, etc.), a navigator, a cockpit controller and / or display, a display of a camera view (e.g., a display of a rearview camera in a vehicle), an electronic photo, an electronic billboard or sign, a projector, etc.

[0132] In the case of using “including”, “having”, and “comprising” described herein, another component may be added unless a clear limiting term such as “only”, “consisting of”, etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be understood as being one in number.

[0133] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0134] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A display panel, characterized in that: include: substrate; A semiconductor layer, disposed on one side of the substrate; A first metal layer is disposed on a side of the semiconductor layer away from the substrate; The first metal layer forms a gate of a transistor device of a pixel circuit; The second metal layer is arranged on a side of the first metal layer away from the substrate; the second metal layer includes a first electrode, a data line, a first power line and a first electrode plate.

2. The display panel according to claim 1, characterized in that: The first metal layer includes a second power supply line, a reference voltage signal line, a light emitting control signal line, a scanning signal line and a second electrode plate; the first electrode plate and the second electrode plate form a storage capacitor of the pixel circuit; Optionally, the first power line and the second power line are electrically connected, the second power line extends along a first direction perpendicular to the thickness direction of the substrate, and the first power line extends along a second direction perpendicular to the thickness direction of the substrate; the first direction and the second direction intersect.

3. The display panel according to claim 2, characterized in that: The display panel further includes: A pixel defining layer, disposed on a side of the second metal layer away from the substrate, the pixel defining layer comprising a pixel opening, the first electrode being disposed corresponding to the pixel opening; Optionally, an orthographic projection of the pixel opening on the substrate intersects with an orthographic projection portion of the light emitting control signal line on the substrate.

4. The display panel according to claim 3, characterized in that: The orthographic projection of the data line on the substrate, the orthographic projection of the first power line on the substrate, and the orthographic projection of the first electrode plate on the substrate are all located outside the orthographic projection range of the pixel opening on the substrate; Optionally, the orthographic projection of the reference voltage signal line on the substrate, the orthographic projection of the second electrode plate on the substrate, and the orthographic projection of the scanning signal line on the substrate are all located outside the orthographic projection range of the pixel opening on the substrate; Optionally, the scan signal line includes a first scan signal line, a second scan signal line and a third scan signal line, the pixel circuit is used to apply the signal received by the reference voltage signal line to the transistor device according to the signal received by the first scan signal line, the pixel circuit is used to apply the signal received by the data line to the transistor device according to the signal received by the second scan signal line, and the pixel circuit is used to apply the signal received by the reference voltage signal line to the first electrode according to the signal received by the third scan signal line; The orthographic projection of the pixel opening on the substrate is located between the orthographic projection of the second electrode plate on the substrate and the orthographic projection of the third scanning signal line on the substrate.

5. The display panel according to claim 3 or 4, characterized in that: The display panel further includes: A light emitting portion, disposed in the pixel opening; The display panel further includes: a second electrode, wherein a first portion of the second electrode is disposed on a side of the second metal layer away from the substrate, and a second portion of the second electrode is disposed on a side of the pixel defining layer away from the substrate; Optionally, the display panel further includes: A supporting structure, disposed on a side of the pixel defining layer away from the substrate; Optionally, the display panel further includes: A first insulating layer, disposed between the first metal layer and the second metal layer; The second insulating layer is disposed between the semiconductor layer and the first metal layer.

6. The display panel according to claim 5, characterized in that: There are multiple reference voltage signal lines, and adjacent reference voltage signal lines in the first direction are connected through the second metal layer.

7. The display panel according to claim 5, characterized in that: The transistor device comprises a reset transistor and a normally-on transistor, a first end of the normally-on transistor is connected to the reset transistor, and a second end of the normally-on transistor is connected to the first electrode; The reference voltage signal line extends along the first direction, an orthographic projection of the reference voltage signal line on the substrate and an orthographic projection of the semiconductor layer on the substrate have an overlapping area, and a portion of the reference voltage signal line corresponding to the overlapping area forms a gate of the normally-on transistor.

8. The display panel according to claim 3, characterized in that: The orthographic projection of the data line on the substrate, the orthographic projection of the first power line on the substrate, and the orthographic projection of the first electrode plate on the substrate are all located outside the orthographic projection range of the pixel opening on the substrate; A partial area of ​​the orthographic projection of the reference voltage signal line on the substrate and a partial area of ​​the orthographic projection of the scanning signal line on the substrate are located within the orthographic projection range of the pixel opening on the substrate.

9. The display panel according to claim 4, characterized in that: The second electrode plate includes a connected main body and an extension portion; in the second direction, the orthographic projection of the main body on the substrate is located between the orthographic projection of the second scanning signal line on the substrate and the orthographic projection of the pixel opening on the substrate; the extension portion is connected to a side of the main body away from the second scanning signal line and extends along the second direction, and the orthographic projection of the extension portion on the substrate is located between the orthographic projection of the pixel opening on the substrate and the orthographic projection of the data line on the substrate.

10. A display device, characterized in that: The invention comprises a display panel as claimed in any one of claims 1 to 9.

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