Device preparation method, equipment and application

Abstract

The invention provides a device preparation method, equipment and application, and relates to a semiconductor material preparation technology. The device comprises a substrate and at least one epitaxial layer, the method comprises the following steps: before epitaxial deposition is carried out on a substrate or an xth epitaxial layer in a reactor, introducing a doping source into the reactor; and after the introduction duration of the doping source reaches a preset duration, performing epitaxial deposition on the substrate or the xth epitaxial layer to obtain an epitaxial layer located on the surface of the substrate or the xth epitaxial layer. Through the method provided by the invention, the defect of non-uniform resistivity distribution of the multiple epitaxial layers in the vertical direction can be effectively improved, so that the performance and the reliability of the device can be guaranteed.

Description

Technical Field

[0001] The present application relates to semiconductor material preparation technology, and in particular to a device preparation method, equipment and application. Background Art

[0002] Multilayer epitaxial growth refers to the process of continuously growing multiple layers of material on a substrate, which is often used in semiconductor device manufacturing to obtain high-performance electronic devices.

[0003] In the known technology, the multilayer epitaxial growth process under normal pressure generally includes the following steps: substrate and reactor preparation, gas introduction and epitaxial deposition, cooling and unloading. Among them, the substrate and reactor preparation step is used to clean the substrate and reactor and make the temperature and pressure of the reactor in a suitable state. The gas introduction and epitaxial deposition process is used to grow a multilayer structure by introducing a doping source and a silicon source. The cooling and unloading steps are used to reduce the reactor temperature to room temperature and remove the wafer from the reactor for subsequent processing steps.

[0004] However, in the above process, there is a defect of uneven resistivity distribution in the vertical direction after multi-layer epitaxy, which will affect the device performance. Summary of the invention

[0005] Based on this, the present application provides a device preparation method, equipment and application, wherein the method is used to solve the problem of uneven longitudinal resistivity distribution after multi-layer epitaxy to ensure the performance of the device.

[0006] In a first aspect, the present application provides a method for preparing a device, wherein the device comprises a substrate and at least one epitaxial layer; the method comprises:

[0007] Before epitaxial deposition is performed on the substrate or the xth epitaxial layer in the reactor, a doping source is introduced into the reactor;

[0008] After the introduction time of the doping source reaches a preset time, epitaxial deposition is performed on the substrate or the x-th epitaxial layer to obtain an epitaxial layer located on the surface of the substrate or the x-th epitaxial layer.

[0009] In a possible implementation, the preset time length is used to make the concentration state of the doping substance in the stagnation layer reach the target concentration state required in the epitaxial deposition process;

[0010] The stagnant layer is located on the surface of the substrate or the xth epitaxial layer.

[0011] In a possible implementation, before epitaxial deposition is performed on the substrate or the xth epitaxial layer in the reactor, introducing a doping source into the reactor includes:

[0012] Before epitaxial deposition is performed on the substrate or the x-th epitaxial layer, the doping source is introduced into the reactor at a preset concentration and a preset flow rate corresponding to the preset time.

[0013] In a possible implementation, the preset time length is the time length during which the target sample device can be obtained among the different time lengths corresponding to multiple groups of experiments; the resistivity distribution of the target sample device in the vertical direction is uniform; other experimental conditions of the multiple groups of experiments are consistent, and the other experimental conditions are used to indicate the preset concentration, the preset flow rate and the reactor.

[0014] In a possible implementation, the preset duration is any value between 2 and 5 seconds.

[0015] In a possible implementation, after the introduction time of the doping source reaches a preset time, epitaxial deposition is performed on the substrate or the x-th epitaxial layer, including:

[0016] After the introduction time of the doping source reaches a preset time, while the doping source is still introduced into the reactor, a silicon source is simultaneously introduced into the reactor to perform epitaxial deposition on the substrate or the xth epitaxial layer.

[0017] In a possible implementation, during the epitaxial deposition process, the input concentration and the input flow rate of the doping source are related to the input concentration and the input flow rate of the silicon source.

[0018] In a possible implementation, during the epitaxial deposition process, the introduction concentration and introduction flow rate of the doping source are related to the required doping concentration of the epitaxial layer of the device located on the surface of the substrate or the xth epitaxial layer.

[0019] In a possible implementation, before the epitaxial deposition, the preset concentration of the doping source introduced into the reactor is consistent with the concentration of the doping source introduced into the reactor during the epitaxial deposition process.

[0020] In a possible implementation, the step of introducing a doping source into the reactor includes:

[0021] When the pipeline purging action of the doping source is completed, the doping source is introduced into the reactor.

[0022] In a possible implementation, the method further includes:

[0023] When the pipeline purging action of the silicon source is completed, it is determined that the silicon source is introduced into the reactor.

[0024] In a possible implementation, the method further includes:

[0025] Before the doping source is introduced into the reactor, the reactor is purged with an inert gas.

[0026] In a possible implementation, the method further includes:

[0027] Before the doping source is introduced into the reactor, the substrate or the x-th epitaxial layer is heated.

[0028] In a possible implementation, the method further includes:

[0029] Before the doping source is introduced into the reactor, hydrogen gas is introduced into the reactor for purging.

[0030] In a possible implementation, the method further includes:

[0031] When the epitaxial layer located on the surface of the substrate or the x-th epitaxial layer is obtained, hydrogen gas is introduced into the reactor to perform a purge operation.

[0032] In a possible implementation, the method further includes:

[0033] When the epitaxial layer located on the surface of the substrate or the x-th epitaxial layer is obtained, a temperature reduction treatment is performed.

[0034] In a possible implementation manner, when the epitaxial layer located on the surface of the substrate or the x-th epitaxial layer is an N-type epitaxial layer, the doping source is phosphine.

[0035] In a possible implementation manner, when the epitaxial layer located on the surface of the substrate or the x-th epitaxial layer is a P-type epitaxial layer, the doping source is borane.

[0036] In a second aspect, the present application provides a device preparation equipment, which is used to implement the device preparation method as described in any one of the first aspects; the device preparation equipment includes a reactor and multiple pipelines, and the multiple pipelines are used to introduce the gas required for device preparation into the reactor.

[0037] In a third aspect, the present application provides a semiconductor device, wherein the semiconductor device is obtained by the device preparation method as described in any one of the first aspects.

[0038] In a fourth aspect, the present application provides an electronic device, comprising the switching device described in the third aspect.

[0039] The present application provides a device preparation method, equipment and application, wherein in a device preparation method provided by the present application, before epitaxial deposition is performed on a substrate or an x-th epitaxial layer, a doping source is introduced into the reactor in advance, and after maintaining the substrate or the x-th epitaxial layer for a preset period of time, epitaxial deposition is performed on the substrate to obtain a corresponding epitaxial layer. The device preparation method of the present application can effectively solve the defect of uneven resistivity distribution in the vertical direction during multi-layer epitaxy, which is caused by the fact that the front epitaxial layer blocks the doping source overflowing from the substrate surface and the doping source introduced is initially diluted, thereby effectively ensuring device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0041] Figure 1 A schematic diagram of the structure of a super junction MOSFET provided in an embodiment of the present application;

[0042] Figure 2 A schematic diagram of the concept of the device preparation method provided in the embodiment of the present application;

[0043] Figure 3 A schematic diagram of a device manufacturing method provided in an embodiment of the present application Figure 1 ;

[0044] Figure 4 A schematic diagram of a stagnation layer model for an epitaxial process provided in an embodiment of the present application;

[0045] Figure 5 A comparison chart of multilayer epitaxial resistivity under different deposition conditions provided in an embodiment of the present application;

[0046] Figure 6 A schematic diagram of a device manufacturing method provided in an embodiment of the present application Figure 2 .

[0047] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical scheme and advantages of the present application clearer, the technical scheme in the embodiment of the present application will be described in more detail below in conjunction with the drawings in the preferred embodiments of the present application. In the drawings, the same or similar reference numerals throughout represent the same or similar parts or parts with the same or similar functions. The described embodiments are part of the embodiments of the present application, not all of the embodiments. The embodiments described below with reference to the drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limitations on the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application. The embodiments of the present application are described in detail below in conjunction with the drawings.

[0049] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, or it can be an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0050] In the description of the present application, it should be understood that the terms "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are orientations or positional relationships based on the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0051] The terms "first", "second" and "third" (if any) in the specification and claims of this application and the above drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0052] In addition, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, for example, a process, method, system, product, or display comprising a series of steps or elements is not necessarily limited to those steps or elements explicitly listed, but may include other steps or elements not explicitly listed or inherent to such process, method, product, or display.

[0053] In the field of semiconductor device manufacturing, multilayer epitaxial growth technology is often involved. Multilayer epitaxial growth refers to the process of continuously growing multiple layers of materials on a substrate. It is worth noting that the multilayer epitaxial growth process under normal pressure conditions generally includes the following steps: ① substrate and reactor preparation; ② gas introduction and epitaxial deposition; ③ cooling and unloading.

[0054] Among them, step ① specifically includes: using a chemical solution (such as sulfuric acid, hydrofluoric acid) to clean the silicon wafer to remove organic matter, metal ions and oxide layers, and using high-temperature annealing or other methods to treat the surface of the silicon wafer; loading the cleaned silicon wafer into an epitaxial growth reactor, and setting the temperature and pressure of the reactor according to the process requirements.

[0055] Step ② specifically includes: introducing silane or other silicon source gas to start growing a silicon layer, and introducing a doping source as needed to form an N-type epitaxial layer or a P-type epitaxial layer;

[0056] Step ③ specifically includes: gradually lowering the temperature of the reactor to room temperature; taking the wafer out of the reactor to perform subsequent processing steps.

[0057] Repeat the above three steps until the required multi-layer epitaxial structure is obtained.

[0058] However, in the above process, the front epitaxy is equivalent to a physical barrier that prevents impurities or dopants in the substrate from diffusing into subsequent layers. On this basis, due to the interface effect and doping non-uniformity, the rear epitaxy can only rely on the introduced doping source to reduce the resistivity. In the early stage of the doping source entering the reactor, since the reactor is always filled with hydrogen, the newly introduced doping source will be diluted by hydrogen, and it will take a period of time to reach a stable equilibrium state, so that a small transition area with high resistivity will be formed in the early stage of the rear epitaxy, which will lead to uneven resistivity distribution of multiple epitaxial layers in the vertical direction, affecting the performance of the device.

[0059] For example, Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), as a key switching device, has undergone significant development. The multi-sub characteristic of MOSFET enables it to have relatively small switching losses in switching applications. However, since its on-resistance is limited by material properties and device design, especially by breakdown voltage, that is, due to the limitation of silicon limit, the power consumption of traditional MOSFET in the on state is high.

[0060] At present, among the known technologies, super junction MOSFET technology has effectively broken through the silicon limit by introducing a super junction structure. Specifically, the super junction structure forms an alternating PN junction array by embedding a P-type column (P column) in the N-type drift region. The design of this structure allows the on-resistance to be reduced by 80%-90% on the same chip area while maintaining a high breakdown voltage. This significant performance improvement enables super junction MOSFET to perform well in high-efficiency and high-switching speed applications. For example, it is a mainstream semiconductor switching device in the field of small and medium power, and is mainly used in power management, switching, etc. in the fields of switching power supplies, uninterruptible power supplies, industrial automation, computers, mobile phones, cameras, electric vehicles, automotive electronics, etc.

[0061] More specifically, the manufacturing of superjunction MOSFETs involves complex processes, especially when forming superjunction structures. In known technologies, mainstream superjunction MOSFETs form p-pillars by stacking epitaxy (EPI) and ion implantation. Specifically, Figure 1 A schematic diagram of the structure of a super junction MOSFET provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, Nepi-x is used to represent the xth N-type epitaxial layer, and P imp-x is used to form P-type pillars, which are alternately arranged in the N-type drift region. It can be understood that x is any value among 1, 2, 3, 4, 5, and 6. It should be understood that the resistivity of the EPI layer and the concentration of ion implantation play a decisive role in the performance of the device.

[0062] However, for the above-mentioned super junction MOSFET, in the process of obtaining the N-type epitaxial layer by normal pressure epitaxy, since the front epitaxy layer will prevent the solid-state self-doping effect of the substrate, and the initial concentration of the doping source is difficult to stabilize, a small transition region with high resistivity will be formed in the early stage of the rear epitaxy layer, resulting in uneven longitudinal resistivity distribution after multi-layer epitaxy, which in turn affects the performance of the device.

[0063] Therefore, the present application provides a device preparation method, equipment and application. Specifically, after repeated thinking and verification, the inventors found that in the above-mentioned normal pressure epitaxial process, if the doping source is introduced into the reactor in advance before epitaxial deposition, it will affect the actual multi-layer epitaxial interlayer resistivity morphology. Furthermore, after the doping source is introduced in advance for a preset time, epitaxial deposition is performed again, which can make the multi-layer epitaxial interlayer resistivity morphology equivalent to the single-layer epitaxial morphology, thereby solving the problem of uneven longitudinal resistivity distribution after multi-layer epitaxy and ensuring the performance of the device. Specifically, Figure 2 A schematic diagram of the concept of the device preparation method provided in the embodiment of the present application, such as Figure 2As shown, the inventors propose that before epitaxial deposition, a doping source is first introduced into the reactor and maintained for a preset time, and then epitaxial deposition is performed to obtain the required epitaxial layer.

[0064] Understandably, Figure 2 The “…” in the first rectangular box in the figure is used to indicate the steps before the doping source is introduced into the reactor, which may be, for example, processes such as purging and heating the reactor. Figure 2 The “…” in the last rectangular box is used to indicate the steps after the epitaxial deposition, which may be, for example, a cooling process, etc. This is not limited in the embodiments of the present application.

[0065] In view of this, the present application provides a device preparation method. The contents of the present application will be described in detail below in conjunction with the accompanying drawings so that those skilled in the art can understand the contents of the present application more clearly and in detail.

[0066] It is worth noting that, in the embodiment of the present application, the device includes a substrate and at least one epitaxial layer. Figure 3 A schematic diagram of a device manufacturing method provided in an embodiment of the present application Figure 1 ,like Figure 3 As shown, the device preparation method provided in the embodiment of the present application includes the following contents:

[0067] S301, before epitaxial deposition is performed on the substrate or the xth epitaxial layer in the reactor, a doping source is introduced into the reactor.

[0068] The epitaxial deposition is performed on the substrate or the x-th epitaxial layer to obtain an epitaxial layer located on the upper surface of the substrate or the x-th epitaxial layer. x is an integer greater than 0, and the specific value is related to the device preparation requirements.

[0069] Specifically, when epitaxial deposition is performed on the substrate or the xth epitaxial layer, it is necessary to introduce a material source gas and a doping source simultaneously to grow an epitaxial layer located on the surface of the substrate or the xth epitaxial layer. The material source gas is used to grow semiconductor materials. In this embodiment, the material source gas may be a silicon source.

[0070] It is understandable that by controlling the doping concentration, the conductivity of the corresponding epitaxial layer can be accurately controlled. Among them, the selection of the doping source is specifically related to the type of epitaxial layer. Exemplarily, if it is required to grow an N-type epitaxial layer, the doping source can be phosphine or phosphorus trichloride, which is not limited in this embodiment. If it is required to grow a P-type epitaxial layer, the doping source can be trivalent elements such as boron (B), aluminum (Al) and gallium (Ga), which is not limited in this embodiment.

[0071] S302, after the introduction time of the doping source reaches a preset time, epitaxial deposition is performed on the substrate or the xth epitaxial layer to obtain an epitaxial layer located on the surface of the substrate or the xth epitaxial layer.

[0072] Specifically, the preset time length is used to make the doping concentration on the surface of the substrate or the xth epitaxial layer reach the required doping concentration.

[0073] It is understandable that the epitaxial process is a dynamic equilibrium process, and the stagnation layer model can concisely describe the epitaxial process. Specifically, in the epitaxial process, the stagnation layer refers to the phenomenon that certain substances stay or accumulate in a specific area due to the slowing of flow velocity or change of flow direction during the flow of fluid.

[0074] For example, Figure 4 A schematic diagram of a stagnation layer model for an epitaxial process provided in an embodiment of the present application is shown in FIG. Figure 4 As shown, when growing an N-type epitaxial layer, the reaction product (silicon source SiHCL 3 Phosphine PH 3 ) diffuses to the substrate or the surface of the xth epitaxial layer due to concentration differences in the stagnation layer to deposit an epitaxial layer. Among them, the silicon source SiHCL 3 Used to communicate with the hydrogen H introduced into the reactor in advance 2 Reaction, obtain silicon Si precipitation, phosphine PH 3 Used to decompose into hydrogen H after heating 2 And doping material phosphorus P.

[0075] It can be understood that the flow rate and concentration of the introduced reaction gas can control the concentration of the reaction products at the upper surface of the stagnant layer, and then affect the concentration of the silicon source and doping source at the surface of the substrate or the xth epitaxial layer through diffusion within the stagnant layer, that is, the effective concentration in the epitaxial process in the figure, controlling the epitaxial growth rate and doping concentration.

[0076] Therefore, in this embodiment, the preset time is specifically used to make the concentration state of the doping substance in the stagnation layer reach the target concentration state required in the epitaxial deposition process. Wherein, the stagnation layer is located on the upper surface of the substrate or the xth epitaxial layer.

[0077] More specifically, in this embodiment, the preset duration is obtained by testing and verifying different durations through a large number of experiments. During the experiment, other quantities except the preset duration should remain consistent, such as the reactor, the preset concentration of the doping source, the preset flow rate, etc.

[0078] It can be understood that the preset time length is the time length during which the target sample device can be obtained among the different time lengths corresponding to multiple groups of experiments; the resistivity distribution of the target sample device in the vertical direction is uniform; the other experimental conditions of multiple groups of experiments are consistent, and the other experimental conditions are used to indicate the preset concentration, preset flow rate and reactor.

[0079] Specifically, in this embodiment, the preset duration is determined by the following method:

[0080] Under fixed experimental conditions, multiple groups of experiments are set, each group of experiments corresponds to a different pre-introduction time; the experimental conditions are used to indicate a preset concentration, a preset flow rate, a reactor, and an epitaxial deposition condition; the pre-introduction time is used to indicate the time for which the doping source is introduced before epitaxial deposition is performed on the substrate or the xth epitaxial layer;

[0081] Analyze the sample devices obtained from each group of experiments by a preset analysis method to obtain the resistivity distribution of the sample devices, and determine a target sample device for indicating that the resistivity distribution of the multi-layer epitaxial layer in the vertical direction is uniform;

[0082] Verify the pre-input time corresponding to the target sample device, record the verification result, and determine the preset time according to the verification result.

[0083] Based on the above content, in this embodiment, before epitaxial deposition is performed on the substrate or the xth epitaxial layer, a doping source is introduced into the reactor at a preset concentration and a preset flow rate corresponding to the preset time length to ensure that after the preset time length, the doping concentration on the surface of the substrate or the xth epitaxial layer can reach the required doping concentration.

[0084] As a possible implementation manner, the preset duration is any value between 2 and 5 seconds.

[0085] As an illustration, Figure 5 A comparison chart of the resistivity of a multilayer epitaxial layer under different deposition conditions provided for an embodiment of the present application, specifically, the deposition conditions here include whether a doping source is introduced into the reactor in advance, and a preset duration of the introduction. In the figure, the horizontal axis is used to represent the thickness of the epitaxial layer, and the vertical axis is used to represent the resistivity of the epitaxial layer. Among them, curve ① is used to represent the resistivity distribution of the multilayer epitaxial layer in the vertical direction when the preset duration is 3s. Curve ② is used to represent the resistivity distribution of the multilayer epitaxial layer in the vertical direction when the preset duration is 20s. Curve ③ is used to represent the resistivity distribution of the multilayer epitaxial layer in the vertical direction when the doping source is not introduced into the reactor in advance.

[0086] Depend on Figure 5 It can be seen that, under the premise that other conditions except the above-mentioned deposition conditions remain the same, failure to introduce the doping source into the reactor in advance and the preset time of introduction are too long will lead to uneven resistivity distribution of the multi-layer epitaxial layer in the vertical direction. After a large number of experiments, in this embodiment, when it is determined that the preset time is within the range of 2-5s, the resistivity distribution of the multi-layer epitaxial layer in the vertical direction can be uniform.

[0087] It should be understood that when other conditions except the above-mentioned deposition conditions change, the preset time may change, which is not limited in the present embodiment, as long as the resistivity distribution of the multiple epitaxial layers in the vertical direction can be uniform.

[0088] Further, in this embodiment, after the doping source is introduced for a preset time, while the doping source is still introduced into the reactor, a material source gas is introduced into the reactor to perform epitaxial deposition on the substrate or the xth epitaxial layer. Specifically, the material source gas is a silicon source.

[0089] More specifically, during the epitaxial deposition process, the concentration and flow rate of the doping source are related to the concentration and flow rate of the silicon source. Exemplarily, the concentration and flow rate of the doping source can be consistent with the concentration and flow rate of the silicon source; the concentration of the doping source can also be consistent with the concentration of the silicon source, but the flow rate of the doping source is set to half the flow rate of the silicon source.

[0090] It is understandable that, during the epitaxial deposition process, the input concentration and the input flow rate of the doping source are also related to the required doping concentration of the epitaxial layer of the device located on the substrate or the xth epitaxial layer surface. Specifically, when the input concentration and the input flow rate of the silicon source are known, the input concentration and the input flow rate of the doping source can be determined based on the required doping concentration required for the epitaxial layer on the substrate surface or the x+1th epitaxial layer.

[0091] In the device preparation method provided in the embodiment of the present application, when growing multiple epitaxial layers by normal pressure epitaxy, before growing each epitaxial layer based on epitaxial deposition, a doping source is introduced in advance so that the doping concentration of the doping source on the substrate used to grow the current epitaxial layer or the surface of the x-th epitaxial layer reaches the required doping concentration, so as to avoid the formation of a region with high resistivity between the epitaxial layers, thereby effectively improving the resistivity morphology between the multiple epitaxial layers under normal pressure, making the consistency of the resistivity distribution of the multiple epitaxy in the vertical direction equivalent to that of a single layer, thereby improving the performance and stability of devices manufactured using the multi-layer epitaxial process.

[0092] It can be understood that for single-layer epitaxy, since the self-doping effect of the substrate is much higher than the influence of the gaseous doping source, the method of this embodiment will not change the characteristics of the single-layer epitaxy when processing the single-layer epitaxy, thereby ensuring the applicability of the method of this embodiment.

[0093] Based on the above content, as a design, the embodiment of the present application provides a whole process of epitaxial layer growth, Figure 6 A schematic diagram of a device manufacturing method provided in an embodiment of the present application Figure 2 ,like Figure 6 As shown, the method provided in this embodiment includes:

[0094] S601, purging the reactor with an inert gas.

[0095] It is understandable that before epitaxial growth, air or other unwanted gases may remain in the reactor chamber. If these gases are not removed, they may react with the reaction gas in an undesirable chemical reaction, affecting the quality of the epitaxial layer. By purging, these residual gases can be effectively removed.

[0096] In this embodiment, the reactor is purged by introducing an inert gas into the reactor. Specifically, the inert gas may be a gas such as nitrogen or argon that does not chemically react with the reaction gas. On the one hand, by purging the reactor cavity, a stable atmosphere can be established in the reactor to provide a pure environment for subsequent epitaxial growth. On the other hand, there may be tiny particles or other contaminants in the reactor, and these impurities may be deposited on the substrate surface, resulting in epitaxial layer defects. The purging process helps to remove these particles and contaminants and ensure the cleanliness of the cavity.

[0097] In addition, by performing a purging action inside the reactor, in some cases, it is also helpful to homogenize the temperature distribution inside the reactor and ensure that the substrate is heated evenly over the entire surface, which ultimately helps to improve the performance and reliability of the semiconductor device.

[0098] S602, introducing hydrogen into the reactor for purging.

[0099] In this embodiment, after the reactor is purged with the inert gas, hydrogen is introduced into the reactor cavity for purging to exhaust the previously used inert gas. Hydrogen is a commonly used reducing gas with multiple functions.

[0100] By introducing hydrogen into the reactor, on the one hand, the oxide layer and other minor contaminants on the surface of the substrate or the xth epitaxial layer can be effectively removed, which helps to provide a clean surface and is conducive to the high-quality growth of the epitaxial layer. On the other hand, by purging with hydrogen, the atmosphere in the reactor can be further stabilized to ensure the controllability of the environmental conditions at the beginning of epitaxial growth.

[0101] S603, heating the substrate or the xth epitaxial layer.

[0102] It is understood that before epitaxial growth, the substrate or the xth epitaxial layer needs to be heated to a specific temperature. This temperature usually depends on the material used and the epitaxial conditions, and may be between several hundred degrees Celsius and one thousand degrees Celsius. Specifically, a heating element is generally provided in the reactor, and the temperature is increased by controlling the heating element.

[0103] Through the above steps, the initial conditions of epitaxial growth can be significantly improved, the influence of defects and impurities can be reduced, and the quality of the epitaxial layer and the performance of the final device can be improved.

[0104] S604, when the pipeline purging action of the doping source is completed, the doping source is introduced into the reactor.

[0105] In this embodiment, the doping source is introduced into the reactor only after the pipeline purging action of the doping source is completed, which is beneficial to ensure the accuracy of the preset concentration of the doping source.

[0106] In a preferred embodiment, the preset concentration of the doping source introduced is consistent with the concentration of the doping source introduced into the reactor during the epitaxial deposition process.

[0107] By keeping the preset concentration of the doping source consistent with the input concentration, the stability of the preparation process is ensured, which is beneficial to ensuring the stability of epitaxial growth.

[0108] S605, after the introduction time of the doping source reaches a preset time, epitaxial deposition is performed on the substrate or the xth epitaxial layer to obtain an epitaxial layer located on the surface of the substrate or the xth epitaxial layer.

[0109] Specifically, epitaxial deposition is achieved by introducing a silicon source and a doping source.

[0110] In a preferred embodiment, when the silicon source pipeline purge is completed, the silicon source is introduced into the reactor.

[0111] The silicon source is introduced into the reactor only after the silicon source pipeline purge action is completed, which is beneficial to ensure the accuracy of the silicon source introduction concentration.

[0112] S606, when the epitaxial layer located on the surface of the substrate or the xth epitaxial layer is obtained, hydrogen is introduced into the reactor for purging and a temperature reduction treatment is performed.

[0113] It is understandable that during the epitaxial growth process, some byproducts and residual gases will be generated in the reactor, which may affect the subsequent growth quality. The introduction of hydrogen for purging can effectively remove these residues and ensure a pure environment in the reactor.

[0114] In this embodiment, when the epitaxial layer located on the surface of the substrate or the xth epitaxial layer is obtained, a cooling treatment is performed to gradually reduce the temperature of the reactor and the substrate or the xth epitaxial layer, thereby avoiding thermal stress and lattice defects caused by rapid cooling.

[0115] From the above, it should be understood that the purging and cooling at this time are to prepare the reactor environment for the next process and ensure that the reactor is at an appropriate temperature and atmosphere for subsequent epitaxial growth or other processing steps.

[0116] By using the method of this embodiment, each time an epitaxial layer is grown, steps S601 to S606 are performed, which can effectively ensure the accuracy of epitaxial layer growth, thereby facilitating the performance and reliability of the device.

[0117] It is understandable that, as another design, when growing each epitaxial layer, steps S601-S604 and S606 are appropriately reduced, which is also within the protection scope of the present application and will not be described in detail here.

[0118] An embodiment of the present application also provides a device preparation device, which is used to implement the device preparation method as described in the above embodiment; specifically, the device preparation device includes a reactor and multiple pipelines, and the multiple pipelines are used to introduce gases required for device preparation into the reactor.

[0119] Exemplarily, the device preparation equipment includes a reactor, and a pipeline for introducing a doping source into the reactor, a pipeline for introducing hydrogen into the reactor, a pipeline for introducing a silicon source into the reactor, and the like.

[0120] In addition, an embodiment of the present application further provides a semiconductor device, which is obtained by the device preparation method in the aforementioned embodiment.

[0121] It is understandable that the above device preparation method can be applied to any device involving a multi-layer epitaxial process, for example, the super junction MOSFET mentioned above.

[0122] In view of the fact that the semiconductor device in this embodiment is obtained by the device preparation method described in any of the above embodiments, the multi-layer epitaxial layers included in the semiconductor device have the characteristic of uniform interlayer resistivity distribution, thereby achieving the beneficial effect of ensuring the performance and reliability of the semiconductor device. This embodiment will not be described in detail here.

[0123] In one possible implementation, the semiconductor device includes at least two epitaxial layers, and the standard deviation of the resistivity of at least two epitaxial layers in the vertical direction is less than a preset value. The standard deviation of the resistivity is determined based on the resistivity distribution morphology of the epitaxial layer at different epitaxial layer thicknesses corresponding to the semiconductor device, and the resistivity distribution morphology of the epitaxial layer at different epitaxial layer thicknesses is obtained by measuring the semiconductor device using a spreading resistance probe (SRP) technology.

[0124] It is understandable that the preset value is related to at least one of the manufacturing tolerance, device preparation requirements, and the measurement environment. Among them, the manufacturing tolerance specifically refers to the deviation range of parameters such as size, shape, performance, etc. allowed in the preparation process of the semiconductor device, such as key parameters such as the thickness of the epitaxial layer. The device preparation requirements specifically refer to the technical and process requirements that need to be met by the semiconductor device during the preparation process, such as material selection, layer structure design, process steps, etc. The measurement environment specifically refers to the physical and operating conditions when measuring the resistivity distribution of semiconductor devices based on SPR technology, such as temperature, humidity, equipment calibration status, etc.

[0125] In this embodiment, the resistivity standard deviation is a relative standard deviation, which is specifically used to indicate the percentage of the standard deviation to the average resistivity value. The standard deviation is used to indicate the difference between the resistivity of the epitaxial layer and the average resistivity.

[0126] Based on the above content, in this embodiment, the preset value is specifically 1%.

[0127] In this embodiment, the semiconductor device includes at least two epitaxial layers, and the standard deviation of the resistivity in the vertical direction is less than a preset value, thereby ensuring the uniformity of the resistivity of at least two epitaxial layers, which is beneficial to ensure the uniform distribution of current and electric field in the semiconductor device, and further beneficial to improving the stability and reliability of the semiconductor device.

[0128] The embodiment of the present application further provides an electronic device, comprising the above-mentioned semiconductor device. The electronic device may be a mobile phone, a portable device, a notebook computer, an electric toy, an electric tool or a vehicle.

[0129] It can be understood that the electronic device provided by the present application adopts the semiconductor device provided by the present application, and the semiconductor device adopts the above-mentioned device preparation method. That is, the electronic device also adopts the device preparation method provided by the present application, and the device preparation method provided by the present application can effectively improve the uneven resistivity distribution of the multi-layer epitaxial layer in the vertical direction, thereby effectively ensuring the performance of the electronic device provided by the present application.

[0130] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A device preparation method, characterized in that: The device comprises a substrate and at least one epitaxial layer; the method comprises: Before epitaxial deposition is performed on the substrate or the xth epitaxial layer in the reactor, a doping source is introduced into the reactor; After the introduction time of the doping source reaches a preset time, epitaxial deposition is performed on the substrate or the x-th epitaxial layer to obtain an epitaxial layer located on the surface of the substrate or the x-th epitaxial layer.

2. The method according to claim 1, characterized in that: The preset time length is used to make the concentration state of the doping substance in the stagnation layer reach the target concentration state required in the epitaxial deposition process; The stagnant layer is located on the surface of the substrate or the xth epitaxial layer.

3. The method according to claim 1 or 2, characterized in that: Before epitaxial deposition is performed on the substrate or the xth epitaxial layer in the reactor, a doping source is introduced into the reactor, comprising: Before epitaxial deposition is performed on the substrate or the x-th epitaxial layer, the doping source is introduced into the reactor at a preset concentration and a preset flow rate corresponding to the preset time.

4. The method according to claim 3, characterized in that: The preset time length is the time length during which the target sample device can be obtained among the different time lengths corresponding to multiple groups of experiments; the resistivity distribution of the target sample device in the vertical direction is uniform; the other experimental conditions of the multiple groups of experiments are consistent, and the other experimental conditions are used to indicate the preset concentration, the preset flow rate and the reactor.

5. The method according to claim 1 or 2, characterized in that: The preset duration is any value between 2 and 5 seconds.

6. The method according to claim 1 or 2, characterized in that: After the introduction time of the doping source reaches a preset time, epitaxial deposition is performed on the substrate or the x-th epitaxial layer, including: After the introduction time of the doping source reaches a preset time, while the doping source is still introduced into the reactor, a silicon source is simultaneously introduced into the reactor to perform epitaxial deposition on the substrate or the xth epitaxial layer.

7. The method according to claim 6, characterized in that During the epitaxial deposition process, the input concentration and the input flow rate of the doping source are related to the input concentration and the input flow rate of the silicon source.

8. The method according to claim 6, characterized in that During the epitaxial deposition process, the input concentration and the input flow rate of the doping source are related to the required doping concentration of the epitaxial layer of the device located on the surface of the substrate or the xth epitaxial layer.

9. The method according to claim 6, characterized in that Before the epitaxial deposition, the preset concentration of the doping source introduced into the reactor is consistent with the concentration of the doping source introduced into the reactor during the epitaxial deposition process.

10. The method according to claim 1 or 2, characterized in that: The step of introducing a doping source into the reactor comprises: When the pipeline purging action of the doping source is completed, the doping source is introduced into the reactor.

11. The method according to claim 6, characterized in that The method further comprises: When the pipeline purging action of the silicon source is completed, it is determined that the silicon source is introduced into the reactor.

12. The method according to claim 1 or 2, characterized in that: The method further comprises: Before the doping source is introduced into the reactor, the reactor is purged with an inert gas.

13. The method according to claim 1 or 2, characterized in that: The method further comprises: Before the doping source is introduced into the reactor, the substrate or the x-th epitaxial layer is heated.

14. The method according to claim 1 or 2, characterized in that: The method further comprises: Before the doping source is introduced into the reactor, hydrogen gas is introduced into the reactor for purging.

15. The method according to claim 1 or 2, characterized in that: The method further comprises: When the epitaxial layer located on the surface of the substrate or the x-th epitaxial layer is obtained, hydrogen gas is introduced into the reactor to perform a purge operation.

16. The method according to claim 1 or 2, characterized in that: The method further comprises: When the epitaxial layer located on the surface of the substrate or the x-th epitaxial layer is obtained, a temperature reduction treatment is performed.

17. The method according to claim 1 or 2, characterized in that: When the epitaxial layer located on the surface of the substrate or the x-th epitaxial layer is an N-type epitaxial layer, the doping source is phosphine.

18. The method according to claim 1 or 2, characterized in that: When the epitaxial layer located on the surface of the substrate or the x-th epitaxial layer is a P-type epitaxial layer, the doping source is borane.

19. A device manufacturing apparatus, characterized in that: The device preparation equipment is used to implement the device preparation method as described in any one of claims 1 to 18; the device preparation equipment includes a reactor and a plurality of pipelines, and the plurality of pipelines are used to introduce the gas required for device preparation into the reactor.

20. A semiconductor device, characterized in that: The semiconductor device is obtained by the device preparation method according to any one of claims 1 to 18.

21. The semiconductor device according to claim 20, characterized in that The semiconductor device includes at least two epitaxial layers, and the standard deviation of the resistivity of the at least two epitaxial layers in the vertical direction is less than a preset value; the resistivity standard deviation is determined based on the resistivity distribution morphology of the epitaxial layers under different epitaxial layer thicknesses corresponding to the semiconductor device, and the resistivity distribution morphology of the epitaxial layers under different epitaxial layer thicknesses is obtained by measuring the semiconductor device through the extended resistance probe technology.

22. The semiconductor device according to claim 21, characterized in that The preset value is related to at least one of a manufacturing tolerance, a device preparation requirement, and a measurement environment corresponding to the semiconductor device.

23. The semiconductor device according to claim 21, characterized in that When the resistivity standard deviation is a relative standard deviation, the preset value is 1%.

24. An electronic device, characterized in that: Comprising a semiconductor device as claimed in any one of claims 20 to 23.

Images