Minimum power supply voltage selection circuit and multi-power supply chip

Abstract

The embodiment of the present disclosure provides a minimum power supply voltage selection circuit and a multi-power supply chip, which comprises a first switch tube, a second switch tube, a third switch tube, a fourth switch tube and a fifth switch tube; the source of the first switch tube inputs a first voltage, and the drain of the fourth switch tube inputs a second voltage; the gate of the first switch tube is connected with the gate and the source of the second switch tube, the drain of the first switch tube is connected with the gate of the fourth switch tube, the source of the fourth switch tube is connected with the drain of the second switch tube, and a minimum output voltage is input to an internal circuit; a bias voltage is input to the gate of the third switch tube and the gate of the fifth switch tube, the gates of the third switch tube and the fifth switch tube are connected, the sources are grounded, and the drains are connected with the drain of the first switch tube and the drain of the second switch tube respectively.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of electronic circuit, in particular, to a minimum power voltage selection circuit and a multi-power chip. BACKGROUND

[0002] The multi-power chip is a power management chip for electronic devices, which has multiple input and output channels and can provide multiple stable output voltages to meet the power supply requirements of different components in electronic devices. How to provide stable power supply for electronic devices through a power voltage selection circuit has become a key research direction.

[0003] The minimum power voltage selection circuit selects the minimum voltage output by comparing two or more input voltages. At present, most of the researches are focused on selecting the highest voltage comparison circuit in the multi-power chip, and there is no circuit for selecting the lowest voltage. Or although the lowest voltage comparison circuit is set, the output of the lowest power voltage is inaccurate or cannot be loaded, and the level is inaccurate under the load, which affects the performance of the circuit. SUMMARY

[0004] In order to generate a minimum voltage that can adapt to multiple comparison conditions and process conditions and can be loaded, the embodiments described herein provide a minimum power voltage selection circuit and a multi-power chip.

[0005] According to a first aspect of the present disclosure, a minimum power voltage selection circuit is provided, comprising: a first switch tube, a second switch tube, a third switch tube, a fourth switch tube and a fifth switch tube; the source of the first switch tube inputs a first voltage, and the drain of the fourth switch tube inputs a second voltage; the gate of the first switch tube is connected to the gate and drain of the second switch tube, the drain of the first switch tube is connected to the gate of the fourth switch tube, the source of the fourth switch tube is connected to the source of the second switch tube, and the minimum output voltage is input to an internal circuit; a bias voltage is input to the gate of the third switch tube and the gate of the fifth switch tube, the gates of the third switch tube and the fifth switch tube are connected, the sources are grounded, the drain of the third switch tube is connected to the drain of the first switch tube, and the drain of the fifth switch tube is connected to the drain of the second switch tube.

[0006] In some embodiments of the present disclosure, the width-length ratio of the third switch tube and the fifth switch tube is proportional, constituting a bias current source for providing proportional reference currents for the first switch tube and the second switch tube.

[0007] In some embodiments of the present disclosure, the width-length ratio of the first switch tube and the second switch tube is proportional to the width-length ratio of the third switch tube and the fifth switch tube.

[0008] In some embodiments of the present disclosure, when the first voltage is higher than the second voltage, the first switch tube is turned on, the drain voltage of the first switch tube is equal to the first voltage, the fourth switch tube is turned on, and the minimum output voltage is equal to the second voltage.

[0009] In some embodiments of the present disclosure, when the second voltage is higher than the first voltage, the first switch tube is turned on, the drain voltage of the first switch tube is equal to the second voltage, the fourth switch tube is turned on, and the minimum output voltage is equal to the first voltage. min = V1-V gsMp1 + V gsMp2 , wherein V min is the minimum output voltage, V1 is the first voltage, V gsMp1 is the gate-source voltage of the first switch tube, V gsMp2 is the gate-source voltage of the second switch tube, the gate-source voltages of the first switch tube and the second switch tube are equal, V gsMp1 = V gsMp2 , so that the minimum output voltage is equal to the first voltage, i.e., V min = V1.

[0010] In some embodiments of the present disclosure, the minimum output voltage port is connected to an internal circuit, and when the first voltage is greater than the second voltage, the second voltage is taken as the power supply potential of the internal circuit, and when the first voltage is less than the second voltage, the first voltage is taken as the power supply potential of the internal circuit.

[0011] In some embodiments of the present disclosure, the first switch tube and the second switch tube are PMOS tubes.

[0012] In some embodiments of the present disclosure, the third switch tube, the fourth switch tube, and the fifth switch tube are NMOS tubes.

[0013] In the above circuit, the gate-source voltages of the first switch tube and the second switch tube directly affect their working states, and then determine the minimum output voltage. The third switch tube and the fifth switch tube constitute a bias current source through proportional width-length ratios. This provides the first switch tube and the second switch tube with proportional reference currents, so as to ensure that their gate-source voltages can be kept at the same level, avoid excessive voltage difference, ensure the stability of the circuit, and thus realize accurate control of the minimum voltage selection.

[0014] According to a second aspect of the present disclosure, a multi-power supply chip is provided. The chip comprises the minimum power supply voltage selection circuit according to the first aspect of the present disclosure.

[0015] According to a third aspect of the present disclosure, an electronic device is provided. The electronic device comprises the multi-power supply chip according to the second aspect of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to make the technical solutions of the embodiments of the present disclosure clearer, the drawings of the embodiments will be briefly described below, and it should be known that the following described drawings only relate to some embodiments of the present disclosure, rather than limit the present disclosure, wherein:

[0017] Figure 1 is the minimum power supply voltage selection circuit structure diagram using two switching tubes;

[0018] Figure 2 is the minimum voltage output schematic diagram using two switching tubes;

[0019] Figure 3 is the minimum power supply voltage selection circuit structure diagram using a single NMOS tube;

[0020] Figure 4 is the voltage comparison circuit structure diagram using an operational amplifier;

[0021] Figure 5 is the circuit structure diagram of the minimum power supply voltage selection circuit 100 according to the embodiments of the present disclosure;

[0022] Figure 6 is the minimum power supply voltage with load output result schematic diagram according to the embodiments of the present disclosure.

[0023] It should be noted that the elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION

[0024] In order to make the purposes, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below in conjunction with the drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person skilled in the art without any creative effort also belong to the scope of protection of the present disclosure.

[0025] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this present subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, the statement that two or more parts are "connected" or "coupled" together will mean that the parts are joined together either directly or through one or more intermediate parts.

[0026] The applicant found in the research that the common minimum power supply voltage selection circuit such as Figure 1As shown, using two PN junctions or two switches, low-level selection is achieved by comparing the input voltage. When the voltage on the opposite side (V1) is higher than the voltage on the local side (V2), the gate-source voltage of the NMOS on the local side (Q2) reaches the threshold value, so that the NMOS on the local side (Q2) is turned on to generate a low-level selection path, but when the voltages on both sides tend to be consistent, the reference Figure 2 As shown, when V1 = V2, Vgs = Vds ≈ 0V, and the current of the nA level can greatly lower Vmin, resulting in the NMOS being unable to effectively turn on, so that the minimum output voltage cannot be used for load operation, and the offset effect can cause the output voltage to be unstable, thereby increasing the deviation of the minimum output voltage, affecting the accuracy and stability of the entire circuit.

[0027] If only one NMOS (Q3) with a threshold voltage Vth ≈ 0 is used to implement the minimum voltage selection circuit, as shown in Figure 3 As shown, when V1 is small, Vmin = V1 due to Vth = 0; when V2 is small, Q3 is fully open, so Vmin = V2. However, in reality, such an NMOS can achieve Vth = 0 under the tt process angle, but cannot achieve Vth = 0V under other process angles, and has limited load capacity, and is affected by the offset effect, cannot meet the requirement that the impedance be infinitely large when the switch is off and the impedance be very small when the switch is on, although it can carry a load, but cannot make Vmin differ from the two voltages by a small amount.

[0028] Figure 4 An operational amplifier is used as a voltage comparison circuit, and for minimum voltage output, the conduction of the NMOS (Q4 or Q5) is controlled by the comparison result of the operational amplifier. In this circuit structure, the operational amplifiers A1, A2, and A3 will generate a large static power consumption, and when the voltage difference is small, the voltage comparison will be inaccurate due to factors such as input offset voltage and input bias current of the operational amplifier.

[0029] In low-voltage power supply design, especially in applications where the load condition changes greatly, a stable and efficient power supply selection circuit is needed to ensure that the minimum loadable voltage can be generated under various conditions. In order to generate a minimum power supply voltage that can adapt to various comparison conditions and can be loaded, an embodiment of the present disclosure proposes a minimum power supply voltage selection circuit that can select the lowest loadable voltage according to the size of the input voltage, and can ensure that the circuit can work stably under different process conditions and load changes.

[0030] Figure 5 is a circuit structure diagram of the minimum power supply voltage selection circuit 100 according to an embodiment of the present disclosure. Referring to Figure 5As shown, the minimum power supply voltage selection circuit 100 includes a first switch tube Mp1, a second switch tube Mp2, a third switch tube Mn1, a fourth switch tube Mn2, and a fifth switch tube Mn3. The source of the first switch tube Mp1 inputs a first voltage V1, the drain of the fourth switch tube Mn2 inputs a second voltage V2, the gate of the first switch tube Mp1 is connected to the gate and the drain of the second switch tube Mp2, the drain of the first switch tube Mp1 is connected to the drain of the third switch tube Mn1, the source of the fourth switch tube Mn2 is connected to the source of the second switch tube Mp2, and the minimum output voltage Vmin is output to an internal circuit.

[0031] A bias voltage Vbias is input to the gates of the third switch tube Mn1 and the fifth switch tube Mn3, the gates of the third switch tube Mn1 and the fifth switch tube Mn3 are connected, the sources are grounded, the drain of the third switch tube Mn1 is connected to the drain of the first switch tube Mp1, and the drain of the fifth switch tube Mn3 is connected to the drain of the second switch tube Mp2. The third switch tube Mn1 and the fifth switch tube Mn3 form a current mirror and provide proportional reference currents for the first switch tube Mp1 and the second switch tube Mp2 as a bias current source.

[0032] In an embodiment of the present disclosure, the bias current source is implemented through a current mirror structure. In order to ensure the accuracy of the bias current source, the third switch tube Mn1 and the fifth switch tube Mn3 in the bias current source have proportional width-length ratios (W / L). W represents the width of the switch tube, and L represents the length of the switch tube. The width-length ratio (W / L) determines the current transmission capability of the switch tube. The greater the width-length ratio, the greater the current that the switch tube can transmit. The bias voltage Vbias should be within a reasonable voltage range to avoid distortion in the saturation region or linear region. This design ensures the current matching between multiple switch tubes, improves the accuracy, stability, and power efficiency of the circuit.

[0033] In an embodiment of the present disclosure, the width-length ratios of the first switch tube Mp1 and the second switch tube Mp2 are proportional to the width-length ratios of the third switch tube Mn1 and the fifth switch tube Mn3, so that the currents of the first switch tube Mp1 and the second switch tube Mp2 are accurately matched, ensuring that the two transistors can carry the same current, so that the gate-source voltages of the first switch tube Mp1 and the second switch tube Mp2 are the same.

[0034] In an embodiment of the present disclosure, the first switch tube Mp1 and the second switch tube Mp2 are PMOS tubes, and the third switch tube Mn1, the fourth switch tube Mn2, and the fifth switch tube Mn3 are NMOS tubes.

[0035] In Figure 5In the shown circuit, due to the linkage of the first switch tube Mp1 and the second switch tube Mp2, it is determined which voltage (V1 or V2) is smaller according to the input voltage. When the first voltage V1 is higher than the second voltage V2, the first switch tube Mp1 is turned on, the drain voltage of the first switch tube Mp1 is equal to the first voltage V1, and the fourth switch tube Mn2 is also turned on, so that the minimum output voltage Vmin is equal to the second voltage V2.

[0036] Specifically, when the input voltage V1 is relatively large, Mp1 is fully opened. For a PMOS tube, it is fully turned on when the gate-source voltage Vgs is large enough. When V1 is relatively large, the drain voltage of Mp1 is close to V1. In this case, due to the large V1, Mp1 is in the saturation region, and when Mp1 is fully turned on, Mn2 is fully turned on through the voltage condition connected to Mn2, and the load current can flow. At this time, V min is controlled to V2.

[0037] When the second voltage V2 is higher than the first voltage V1, the first switch tube Mp1 is still turned on, but its opening state is not fully saturated as before, and at this time there is a bias condition: V min = V1-V gsMp1 + V gsMp2 , wherein V min is the minimum output voltage, V1 is the first voltage, V gsMp1 is the gate-source voltage of the first switch tube Mp1, and V gsMp2 is the gate-source voltage of the second switch tube Mp2.

[0038] Since the currents of Mp1 and Mp2 are matched, their gate-source voltages are the same. This means that in this state, VgsMp1 = VgsMp2, and the minimum output voltage V min is equal to the first voltage V1.

[0039] The purpose of the minimum power supply voltage selection circuit is to connect the minimum output voltage to the internal circuit to ensure that the circuit can stably operate at the minimum operating voltage. V1 and V2 can be input into the comparator. The function of the comparator is to monitor the size relationship of the two voltages in real time, and when the first voltage is greater than the second voltage, the second voltage is used as the power potential of the internal circuit, and when the first voltage is less than the second voltage, the first voltage is used as the power potential of the internal circuit. Therefore, the circuit can dynamically select and adjust the minimum voltage, and through precise switching control, it is ensured that when the voltage is selected, the selected voltage will not be disturbed by other factors (such as load changes), thereby ensuring the stability of the power supply voltage.

[0040] Figure 6 Figure 1 is a schematic diagram of the minimum power supply voltage load output result according to an embodiment of the present disclosure. Referring to Figure 1, the minimum power supply voltage selection circuit is used to select the minimum voltage V Figure 6As shown, when V1>V2, V2 is the internal power supply potential, when V1V2, the source voltage of Mn2 will be pressed to V1, and V1 is the internal power supply potential. In the case of V1=V2, the minimum output voltage does not fluctuate. The Vmin voltage can stably output under different load conditions and allows the circuit to operate with load.

[0041] Since the threshold voltage (Vth) of the independent NMOS (especially the native NMOS) can change greatly at different process corners, this causes the circuit to be unable to completely close the switch tube or to be unable to work stably at some corners. Through the switch tube and current matching mechanism, it can be ensured that the circuit can work stably under different process and temperature conditions, so that the Vmin maintains a relatively stable output. It can also avoid the current passing through an undesired conduction path when a comparison cannot be made. Through accurate control of the conduction state of the switch tube and current matching, it can avoid unnecessary large current through regions in the comparison process of the minimum voltage selector, and allow the load, which is crucial for the stability and reliability of the lowest voltage power supply in a multi-power system.

[0042] Embodiments of the present disclosure also provide a multi-power chip. The chip includes a minimum power supply voltage selection circuit according to embodiments of the present disclosure, and in addition, the multi-power chip can also include a maximum power supply voltage selection circuit.

[0043] Embodiments of the present disclosure also provide an electronic device. The electronic device includes a multi-power chip according to embodiments of the present disclosure. The electronic device is, for example, a mobile device, an embedded system, a communication device, etc.

[0044] In summary, the minimum power supply voltage selection circuit according to embodiments of the present disclosure not only avoids the inconsistency problem of the threshold voltage of the NMOS at different process corners, but also improves the problem caused by the complete closing characteristics of the switch tube, avoids the problem of mismatch between the ideal selected minimum power supply voltage and the actually selected minimum power supply voltage due to the change of the threshold voltage, and can ensure that the circuit can work stably under different process and temperature conditions, so that the minimum output voltage maintains a relatively stable output. Through accurate control of the conduction state of the switch tube and current matching, it can avoid unnecessary large current through regions in the comparison process of the minimum voltage selection circuit, thereby improving the efficiency and stability of the circuit. By dynamically selecting the minimum voltage, the circuit can work stably at the lowest possible voltage, thereby minimizing power consumption and being suitable for devices in low-power and low-voltage working environments.

[0045] The singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a" or "the" element is

[0046] Further aspects and ranges of adaptation will become apparent from the description provided herein. It should be understood that the various aspects of the application can be practiced separately or in combination with one or more other aspects. It should also be understood that the description and specific examples herein are intended to be illustrative only and are not intended to limit the scope of the application.

[0047] The above detailed description of several embodiments of the disclosure has been presented for the purposes of illustration and description. It is not intended to be exhaustive or limiting to the precise form described. Many modifications and variations are possible in light of this disclosure. It is intended to cover all modifications and variations as long as they fall within the scope of the disclosure. The disclosure was chosen and disclosed in order to best explain the principles and the practical application of the disclosure to others skilled in the art.

Claims

1. A minimum power supply voltage selection circuit, characterized in that: include: a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, and a fifth switching transistor; a first voltage is input to the source of the first switching transistor, and a second voltage is input to the drain of the fourth switching transistor; a gate of the first switching transistor is connected to the gate and drain of the second switching transistor, the drain of the first switching transistor is connected to the gate of the fourth switching transistor, and the source of the fourth switching transistor is connected to the source of the second switching transistor, and a minimum output voltage is drawn and input into the internal circuit; A bias voltage is input to the gate of the third switching tube and the gate of the fifth switching tube. The gates of the third switching tube and the fifth switching tube are connected, the sources are grounded, the drain of the third switching tube is connected to the drain of the first switching tube, and the drain of the fifth switching tube is connected to the drain of the second switching tube.

2. The minimum power supply voltage selection circuit according to claim 1, wherein: The width-to-length ratios of the third switching transistor and the fifth switching transistor are proportional, and they constitute a bias current source for providing a reference current for the first switching transistor and the second switching transistor.

3. The minimum power supply voltage selection circuit according to claim 1 or 2, characterized in that: The width-to-length ratio of the first switching transistor and the second switching transistor is proportional to the width-to-length ratio of the third switching transistor and the fifth switching transistor.

4. The minimum power supply voltage selection circuit according to claim 1, wherein: When the first voltage is higher than the second voltage, the first switch tube is turned on, the drain voltage of the first switch tube is equal to the first voltage, the fourth switch tube is turned on, and the minimum output voltage is equal to the second voltage.

5. The minimum power supply voltage selection circuit according to claim 1, wherein: When the second voltage is higher than the first voltage, the first switch is turned on, V min =V1-V gsMp1 +V gsMp2 , where V min is the minimum output voltage, V1 is the first voltage, V gsMp1 is the gate-source voltage of the first switch tube, V gsMp2 is the gate-source voltage of the second switching tube.

6. The minimum power supply voltage selection circuit according to claim 5, wherein: The gate-source voltages of the first switching tube and the second switching tube are equal, and the minimum output voltage is equal to the first voltage.

7. The minimum power supply voltage selection circuit according to claim 2, wherein: The minimum output voltage port is connected to an internal circuit. When the first voltage is greater than a second voltage, the second voltage is used as the power supply potential of the internal circuit. When the first voltage is less than the second voltage, the first voltage is used as the power supply potential of the internal circuit.

8. The minimum power supply voltage selection circuit according to claim 1, wherein: The first switch tube and the second switch tube are PMOS tubes.

9. The minimum power supply voltage selection circuit according to claim 1, wherein: The third switch tube, the fourth switch tube and the fifth switch tube are NMOS tubes.

10. A multi-power chip, characterized in that: The method comprises the minimum power supply voltage selection circuit according to any one of claims 1 to 9.

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