Long distance multipath synchronous clock transmission device

Abstract

The application discloses a long-distance multi-path synchronous clock transmission device and relates to the technical field of electronic communication. The device comprises a main power distribution circuit and two clock transmission modules connected with the main power distribution circuit; the clock transmission module comprises a sub power distribution circuit and n output branches connected with the sub power distribution circuit, wherein n is a positive integer; and the output branch comprises at least one low-noise amplifier, a filter circuit and a matching adjustment circuit connected in sequence. Thus, the synchronous transmission of long-distance and high-power multi-path clock signals is realized.

Description

Technical Field

[0001] The present application relates to the field of electronic communication technology, and in particular to a long-distance multi-channel synchronous clock transmission device. Background Art

[0002] In modern digital circuit systems, clock signals play a crucial role. They not only provide a synchronization reference for various components within the system but are also essential for ensuring the correct transmission and processing of data. Currently, well-known clock signal transmission methods include LVDS (low-voltage differential signaling), LVPECL (low-voltage positive emitter-coupled logic), CML (current-mode logic), and LVCMOS (low-voltage complementary metal-oxide semiconductor). While these clock signal transmission methods offer low power consumption, strong anti-interference capabilities, simple interfaces, and high-speed transmission, they also have some significant drawbacks.

[0003] First, while these clock signal transmission methods can achieve low-power output, their output power is limited. Furthermore, over long distances, the power attenuates during transmission, resulting in the transmitted power failing to meet the input level requirements of subsequent circuits. Furthermore, the frequency of the output clock signal is limited by the operating frequency of the clock driver chip, and currently available clock driver chips have a relatively low operating frequency, making high-frequency clock drive impossible.

[0004] Secondly, the output of high-frequency clock signals is often in the form of differential signals. Since differential signals are double-ended outputs, they are more inconvenient to transmit over long distances.

[0005] Finally, although the interfaces of these clock signal transmission methods are simple, the clock signal transmission process of digital circuit systems usually involves the synchronous transmission of multiple clock signals. The number of channels for clock signal transmission currently depends on the number of output channels of the clock driver chip, so the number of output channels is limited. Summary of the Invention

[0006] The main purpose of this application is to provide a long-distance multi-channel synchronous clock transmission device to achieve long-distance, high-power synchronous transmission of multi-channel clock signals.

[0007] To achieve the above-mentioned object, the present application provides a long-distance multi-channel synchronous clock transmission device, comprising a main power division circuit and two clock transmission modules connected to the main power division circuit;

[0008] The clock transmission module includes a sub-power division circuit and n output branches connected to the sub-power division circuit, where n is a positive integer;

[0009] The output branch includes at least one low noise amplifier, a filtering circuit and a matching adjustment circuit connected in sequence.

[0010] Optionally, the two clock transmission modules are respectively a low-frequency clock transmission module and a high-frequency clock transmission module, the sub-power division circuit of the low-frequency clock transmission module is a low-frequency power division circuit, and the sub-power division circuit of the high-frequency clock transmission module is a high-frequency power division circuit.

[0011] Optionally, the high-frequency clock transmission module further includes a PLL phase-locked loop, one end of the PLL phase-locked loop is connected to the main power division circuit, and the other end of the PLL phase-locked loop is connected to the high-frequency power division circuit.

[0012] Optionally, n is a multiple of 2, and the low-frequency power division circuit includes n / 2 low-frequency sub-power division units, and the low-frequency sub-power division unit includes a first capacitor, a first inductor, a second inductor, a first resistor, a second capacitor and a third capacitor; one end of the first capacitor is connected to the output end of the main power division circuit to form a first node, and the other end of the first capacitor is grounded; one end of the first inductor is connected to the first node, and the other end of the first inductor is connected to one end of the first resistor to form a second node, one end of the second capacitor is connected to the second node, and the other end of the second capacitor is grounded; one end of the second inductor is connected to the first node, and the other end of the second inductor is connected to the other end of the first resistor to form a third node, one end of the third capacitor is connected to the third node, and the other end of the third capacitor is grounded.

[0013] Optionally, the inductance values ​​of the first inductor and the second inductor are set according to a target frequency, where the target frequency is a required frequency of a load.

[0014] Optionally, the high-frequency power division circuit includes a plurality of cascaded power dividers.

[0015] Optionally, the matching adjustment circuit includes a second resistor, a third resistor, a fourth resistor and a fourth capacitor; one end of the second resistor is connected to the filter circuit to form a fourth node, the other end of the second resistor is connected to one end of the fourth capacitor to form a fifth node, and the other end of the fourth capacitor is connected to the output interface; one end of the third resistor is connected to the fourth node, the other end of the third resistor is grounded to form a sixth node; one end of the fourth resistor is connected to the fifth node, and the other end of the fourth resistor is connected to the sixth node.

[0016] Optionally, the resistance values ​​of the second resistor, the third resistor, and the fourth resistor are determined according to the gain and target power of the low noise amplifier, where the target power is the required power of the load.

[0017] Optionally, the number and gain of the low noise amplifiers are determined according to the length and attenuation of the transmission cable of the long-distance multi-path synchronous clock transmission device.

[0018] Optionally, the low noise amplifiers, the PLL, the low frequency power dividing circuit and the high frequency power dividing circuit are single-port.

[0019] The long-distance multi-path synchronous clock transmission device of the present application replaces the traditional clock driving chip with the main power dividing circuit, the sub power dividing circuit and the low noise amplifier, so that the clock signal is amplified by the low noise amplifier during long-distance transmission, preventing power attenuation of the clock signal and realizing stable long-distance transmission. Secondly, the main power dividing circuit, the sub power dividing circuit and the n output branches of the two clock transmission modules realize multi-path synchronous transmission of the clock signal. Finally, the matching adjustment circuit adjusts the power of the finally output clock signal, so that the power of the clock signal meets the requirements of the input level of the subsequent circuit, realizing high-power transmission of the clock signal. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 is a schematic diagram of the long-distance multi-path synchronous clock transmission device of the embodiment of the present application;

[0021] Figure 2 is a structural schematic diagram of the low frequency sub power dividing unit of the embodiment of the present application;

[0022] Figure 3 is a structural schematic diagram of the high frequency power dividing circuit of one example of the present application;

[0023] Figure 4 is a structural schematic diagram of the high frequency power dividing circuit of the embodiment of the present application.

[0024] The implementation, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solutions and advantages of the present application more clear, the technical solutions of the present application will be described clearly and completely below with reference to the drawings in the present application. Obviously, the described embodiments are some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0026] Clock signals play a crucial role in modern digital circuit systems. They not only provide a synchronization reference for various components within the system but are also essential for ensuring the correct transmission and processing of data. With the increasing complexity and performance demands of electronic devices, the quality of clock signals directly impacts the stability and efficiency of the entire system. Therefore, designing efficient and reliable clock signal transmission devices has become a key challenge.

[0027] Currently, several standard clock signal output types are widely used in the industry, including LVDS (Low Voltage Differential Signaling), LVPECL (Low Voltage Positive Emitter Coupled Logic), CML (Current Mode Logic), and LVCMOS (Low Voltage Complementary Metal Oxide Semiconductor). These technologies, to varying degrees, offer advantages such as low power consumption, strong anti-interference capabilities, simplified interface design, and high-speed data transmission. However, they also have inherent limitations that restrict their application in broader or higher-level scenarios.

[0028] The above-mentioned clock signal transmission methods are mainly achieved through clock driver chips. While these clock signal output methods achieve low power consumption, their output power is fixed and single. In some long-distance transmission scenarios, the power of the clock signal is attenuated during transmission, resulting in the output clock signal power being unable to meet the input level requirements of the subsequent circuit. In addition, the output frequency of these clock signal output methods is generally low because it is limited by the operating frequency of the clock driver chip, and therefore overly dependent on the performance of the clock driver chip. The operating frequency of the clock driver chips currently available on the market is relatively low, resulting in the above-mentioned clock signal output methods being unable to achieve high-frequency clock drive in some system circuits.

[0029] Secondly, high-frequency clock signals are often output as differential signals. Compared to single-ended signals, differential signals require an additional trace, increasing the PCB area. The routing requirements on the PCB are more stringent, requiring high symmetry between the two traces, otherwise the noise suppression effect will be reduced. Testing is also more complex than testing single-ended signals. Furthermore, the differential, dual-ended output of high-frequency clock signals makes it difficult to transmit the clock signal over long distances via RF cables during system assembly.

[0030] Finally, while output methods like LVDS, LVPECL, CML, and LVCMOS offer simple interfaces, a complete digital circuit system typically involves multiple clock signals. The number of output channels for these output methods is entirely dependent on the number of output channels in the clock driver chip, limiting the number of clock signal output channels. Furthermore, since the clock driver chip outputs a square wave, it generates significant harmonic components, resulting in severe nonlinear distortion of the clock signal, which can even disrupt system operation.

[0031] In summary, traditional clock signal transmission devices have certain limitations in design. With the advancement of electronic technology, traditional clock circuits are no longer able to meet the working requirements of some digital circuit systems.

[0032] Based on this, an embodiment of the present application provides a long-distance multi-channel synchronous clock transmission device. By replacing the traditional clock driver chip with a main power division circuit, a sub-power division circuit and a low-noise amplifier, the inherent disadvantages of the transmission method with a clock driver chip are solved. The main power division circuit and the sub-power division circuit are used to realize the transmission of multi-channel clock signals, and the number of transmission channels can be determined by the sub-power division circuit, and the number of transmission channels will not be limited; by setting a low-noise amplifier on each output branch, long-distance transmission of the clock signal is realized; by setting a high-frequency clock transmission module, high-frequency clock signal transmission can be realized; by setting a matching adjustment circuit on each output branch, the power of the final output clock signal is made more in line with the input level requirements of the subsequent circuit.

[0033] Figure 1 Schematic diagram of a long-distance multi-channel synchronous clock transmission device according to an embodiment of the present application. Figure 1 As shown, the long-distance multi-channel synchronous clock transmission device may include a main power division circuit 100 and two clock transmission modules connected to the main power division circuit 100; the clock transmission module includes a sub-power division circuit and n output branches connected to the sub-power division circuit, where n is a positive integer; the output branch includes at least one low-noise amplifier, a filtering circuit, and a matching adjustment circuit connected in sequence.

[0034] In this embodiment, a clock signal is input into a long-distance, multi-channel synchronous clock transmission device. First, the main power splitter circuit 100 employs a symmetrical design, splitting the clock signal into two clock signals of equal power. These two clock signals are then input into two clock transmission modules. Taking one clock transmission module as an example, the clock signal is further split into n clock signals of equal power by the sub-power splitter circuit of the clock transmission module. After the clock signal is split into n clock signals of equal power by the sub-power splitter circuit, each clock signal passes through an amplifier, a low-noise device, a filter circuit, and a matching adjustment circuit.

[0035] The low-noise amplifier amplifies the clock signal to compensate for the power attenuation during transmission. The filter circuit removes harmonics, spurious signals, and broadband noise from the clock signal, optimizing the output quality and ensuring high-performance clock signal output. Finally, the matching adjustment circuit amplifies or attenuates the clock signal output power to meet the varying power requirements of the load. The output of any clock transmission module can be selected as the final output of the entire long-distance, multi-channel synchronous clock transmission device.

[0036] It should be noted that the number of low noise amplifiers can be determined according to the length of the transmission distance. If the transmission distance is long, more low noise amplifiers can be set; if the transmission distance is short, the number of low noise amplifiers can be appropriately reduced.

[0037] In some embodiments, the two clock transmission modules are a low-frequency clock transmission module 200 and a high-frequency clock transmission module 300, respectively. The sub-power division circuit of the low-frequency clock transmission module 200 is a low-frequency power division circuit, and the sub-power division circuit of the high-frequency clock transmission module 300 is a high-frequency power division circuit.

[0038] In this embodiment, the low-frequency clock transmission module 200 is used to transmit a low-frequency clock signal, that is, the low-frequency clock transmission module 200 ultimately outputs a low-frequency clock signal. The high-frequency clock transmission module 300 is used to transmit a high-frequency clock signal, that is, the high-frequency clock transmission module 300 ultimately outputs a high-frequency clock signal. Specifically, after the clock signal is input, the main power division circuit 100 divides the clock signal into two parts, and the main power division circuit 100 directly divides the clock signal into two parts. Figure 1 The low-frequency clock transmission module 200 shown in the figure directly divides, amplifies, filters, and matches the clock signal to output it as a high-stability, low-noise low-frequency reference clock. Figure 1 The high-frequency clock transmission module 300 shown in the figure directly splits, amplifies, filters, and matches the clock signal for output. Conventional clock signals are mostly low-frequency, such as 10 MHz, 100 MHz, 200 MHz, and 500 MHz. However, this high-frequency clock transmission module 300 can generate high-frequency clock signals ranging from 10 MHz to over 10 GHz, covering a wider range of application scenarios.

[0039] Similarly, the sub-power division circuit of the low-frequency clock transmission module 200 can be a low-frequency power division circuit, which can be composed of simple components. The sub-power division circuit of the high-frequency clock transmission module 300 can be a high-frequency power division circuit, which can be composed of multiple high-frequency power dividers.

[0040] In practical applications, it can be determined whether the downstream load requires a low-frequency clock signal or a high-frequency clock signal. If the downstream load requires a low-frequency clock signal, the output of the low-frequency clock transmission module 200 is used as the output of the entire device; if the downstream load requires a high-frequency clock signal, the output of the high-frequency clock transmission module 300 is used as the output of the entire device.

[0041] In some embodiments, the high-frequency clock transmission module 300 further includes a PLL phase-locked loop, one end of the PLL phase-locked loop is connected to the main power division circuit, and the other end of the PLL phase-locked loop is connected to the high-frequency power division circuit.

[0042] Continue to refer Figure 1 In this embodiment, the high-frequency clock transmission module 300 also includes a PLL (phase-locked loop) connected between the main power divider circuit and the high-frequency power divider circuit. The PLL can be controlled by a VCO oscillator and an FPGA chip. The high-frequency clock transmission module 300 serves as the reference frequency for the PLL. Through the VCO oscillator and the FPGA chip's control of the PLL chip's configuration, it can convert a low-frequency clock signal into a high-frequency clock signal.

[0043] It's important to note that a PLL (phase-locked loop) is a feedback control system that synchronizes the output signal with a reference signal by adjusting its frequency and phase. The process for converting a low-frequency clock signal to a high-frequency clock signal is as follows: First, a suitable division ratio is set. A programmable divider is implemented within the PLL. This divider divides the low-frequency clock signal output by the VCO into a higher-frequency clock signal, which is then fed back to the phase detector. For example, if a 10MHz reference clock is to be converted to a 100MHz output clock, a divider with a division ratio of 1 / 10 can be implemented in the feedback path. Initially, the VCO output frequency may differ from the target frequency. The phase detector continuously monitors the phase difference between the feedback signal (the divided VCO output) and the reference signal. Using a charge pump and loop filter, it adjusts the VCO control voltage until the two signals achieve phase and frequency alignment. At this point, the PLL is considered "locked." Once locked, the VCO operates at a higher frequency than the reference frequency by the ratio set by the divider. Continuing with the above example, if the division ratio is 1 / 10, the actual output frequency of the VCO will be 10 times the reference frequency, which means that the frequency is doubled from 10MHz to 100MHz.

[0044] The following is a detailed introduction to the low-frequency power division circuit, high-frequency power division circuit, low-noise amplifier, filter circuit and matching adjustment circuit.

[0045] In some implementations, n is a multiple of 2, and the low-frequency power division circuit includes n / 2 low-frequency sub-power division units. Figure 2 Schematic diagram of the structure of the low-frequency sub-power division unit of the embodiment of the present application. Figure 2 As shown, the low-frequency sub-power division unit includes a first capacitor C1, a first inductor L1, a second inductor L2, a first resistor R1, a second capacitor C2 and a third capacitor C3.

[0046] Among them, one end of the first capacitor C1 is connected to the output end of the main power division circuit 100 to form a first node N1, and the other end of the first capacitor C1 is grounded; one end of the first inductor L1 is connected to the first node N1, and the other end of the first inductor L1 is connected to one end of the first resistor R1 to form a second node N2, one end of the second capacitor C2 is connected to the second node N2, and the other end of the second capacitor C2 is grounded; one end of the second inductor L2 is connected to the first node N1, and the other end of the second inductor L2 is connected to the other end of the first resistor R1 to form a third node N3, one end of the third capacitor C3 is connected to the third node N3, and the other end of the third capacitor C3 is grounded.

[0047] In this embodiment, the low-frequency power splitter circuit is composed of n / 2 low-frequency sub-power splitter units. Because each low-frequency sub-power splitter unit can split the clock signal into two clock signals of equal power, if there are n output branches, then there are n / 2 low-frequency sub-power splitter units, and each low-frequency sub-power splitter unit is connected in a cascade connection. For example, if there are four output branches, then there are two low-frequency sub-power splitter units. Thus, by cascading the low-frequency sub-power splitter units, rapid expansion is achieved to meet the required number of channels.

[0048] This embodiment utilizes common LC resistor-capacitor-inductor (RCI) components to construct a low-frequency sub-power splitter. The input clock signal passes through two identical inductors (i.e., first inductor L1 and second inductor L2), combined with differential matching of first resistor R1 and filtering of second capacitor C2 and third capacitor C3 to split the clock signal. The low-frequency sub-power splitter employs a symmetrical design, outputting two clock signals of equal power, achieving a one-to-two split. This low-frequency sub-power splitter circuit is a 100 MHz clock signal power splitter circuit characterized by its simple implementation, low cost, and excellent economical performance.

[0049] In some embodiments, the inductance values ​​of the first inductor L1 and the second inductor L2 can be set according to a target frequency, which is a required frequency of the load. Specifically, the inductance values ​​of the first inductor L1 and the second inductor L2 can be adjusted according to the target frequency required by the subsequent load.

[0050] Figure 3 This is a schematic diagram of the structure of a high-frequency power splitter circuit of an example of this application. Figure 3 As shown, in some embodiments, the high-frequency power division circuit includes a plurality of cascaded power dividers.

[0051] Specifically, the power divider in the high-frequency power splitting circuit can be selected based on the frequency. The power divider with the corresponding frequency can be selected according to the target frequency required by the downstream load. If it is necessary to transmit multiple high-frequency clock signals, these power dividers can be cascaded.

[0052] The power divider can support high-frequency clock signals to pass through. Figure 3 The high-frequency power dividing circuit composed of the power divider in the example can support the transmission of clock signals in the 2.8GHz-7.4GHz frequency band, and has good amplitude balance and phase balance performance. The multi-channel clock signals after power division by the high-frequency power dividing circuit have high amplitude and phase consistency.

[0053] High-frequency clock signals utilize a PLL (phase-locked loop) design. Combined with current PLL technology, this design can achieve output frequencies ranging from low to tens of GHz and beyond. Based on actual needs, a PLL with the appropriate frequency band is selected, and the PLL integrates a frequency divider, enabling both high- and low-frequency clock output. This solution enables simultaneous output of high- and low-frequency clock signals, and even multiple frequencies.

[0054] It can be understood that since the power of the clock signal will gradually decrease as the number of output channels increases after the power splitter, in order to ensure that multiple clock signal outputs can be achieved while also ensuring that the power of the output clock signal is not affected, a low-noise amplifier is provided in each output branch in the embodiment of the present application, and the low-noise amplifier is provided after the power splitter.

[0055] In this embodiment, the low noise amplifier can be a currently available low noise amplifier. The structure of the low noise amplifier can be composed of an input matching network, a noise suppression network, an amplifier stage, an output matching network, a bias circuit, a package, and a shield, etc., which will not be described in detail here.

[0056] In some embodiments, the number and gain of low-noise amplifiers are determined based on the length and attenuation of the transmission cables in a long-distance, multi-channel synchronous clock transmission device. Specifically, as the transmission distance increases, the clock signal experiences more attenuation, which not only reduces the amplitude of the clock signal but also may introduce additional noise, thereby affecting the clock signal quality.

[0057] To maintain the stability and integrity of the clock signal during transmission, the number of low-noise amplifiers (LNAs) should be adjusted based on actual conditions. Generally, if the clock signal level drops to near the noise floor after traveling a certain length of cable, adding a LNA should be considered. For particularly long transmission paths, a segmented amplification approach can be used. This divides the entire transmission path into several shorter segments, with a LNA placed between each segment for signal amplification. This approach not only effectively compensates for cable attenuation but also avoids nonlinear distortion caused by over-amplification by a single LNA.

[0058] The clock signal can be amplified through the low-noise amplifier. The low-noise amplifier with a corresponding frequency band and a corresponding gain is designed on each channel to improve the power and performance of the clock signal. The gain and the number of the low-noise amplifier can be selected according to the length and the attenuation of the transmission cable. If the transmission attenuation is large, a larger gain or multiple low-noise amplifiers can be used to achieve a larger gain. The design of the low-noise amplifier can output multiple channels at the same time and ensure a large clock signal output power, which is convenient for long-distance transmission and can easily meet the input power requirements of the subsequent circuit.

[0059] Further, the clock signal output by the low-noise amplifier is filtered by the single-point filter circuit. The filter circuit can select a suitable filter according to the frequency type and power size of the clock signal, so as to filter out the harmonics, spurs and wideband noise of the clock signal, optimize the quality of the output clock signal, and ensure that the clock signal can still have high performance output under high power.

[0060] Further, after the filtered clock signal is output by the filter circuit, the power of the clock signal is adjusted by using the matching adjustment circuit, so that the power of the output clock signal can be flexibly adjusted according to the demand of the subsequent load end, and the long-distance multi-channel synchronous clock transmission device of the embodiment of the present application has a wider application range. The matching adjustment circuit can use a digital attenuator or use a resistor to design a pi-type or T-type attenuator to attenuate and adjust the power of the clock signal.

[0061] Figure 4 is a structural schematic diagram of the high-frequency power dividing circuit of the embodiment of the present application. As shown in Figure 4 In some embodiments, the matching adjustment circuit includes a second resistor R2, a third resistor R3, a fourth resistor R4, and a fourth capacitor C4.

[0062] The one end of the second resistor R2 is connected with the filter circuit and forms a fourth node N4. The other end of the second resistor R2 is connected with one end of the fourth capacitor C4 and forms a fifth node N5. The other end of the fourth capacitor C4 is connected with an output interface J10. The one end of the third resistor R3 is connected with the fourth node N4. The other end of the third resistor R3 is grounded and forms a sixth node N6. The one end of the fourth resistor R4 is connected with the fifth node N5. The other end of the fourth resistor R4 is connected with the sixth node N6.

[0063] In some embodiments, the resistance values of the second resistor R2, the third resistor R3, and the fourth resistor R4 are determined according to the gain of the low-noise amplifier and the target power. The target power is the demand power of the load.

[0064] In this embodiment, a matching adjustment circuit is introduced into each output branch, and a π-type network is constructed by using discrete components such as resistors and capacitors. By selecting appropriate resistance values ​​for the second resistor R2, the third resistor R3, and the fourth resistor R4, impedance matching and amplitude attenuation adjustment can be achieved. The attenuation value and impedance matching value can be calculated by connecting resistors in series and in parallel. Combined with the gain of the low-noise amplifier, the clock output power can be amplified or attenuated, which can meet the design requirements of different power requirements at the load end.

[0065] Specifically, assume the input impedance is Zin, the output impedance is Zout, and the goal is to match Zin to Zout. For a π-type network, impedance matching can be achieved by selecting appropriate resistor values. For a π-type network, the input impedance Zin can be calculated using the following formula:

[0066]

[0067] Where jw is the angular frequency expressed as a complex number.

[0068] The matching adjustment circuit works by selecting the appropriate second resistor R2 and fourth resistor R4 to ensure that the input impedance Zin approaches the desired value (e.g., 50Ω). The parallel-connected fourth capacitor C4 compensates for impedance variations at high frequencies, ensuring good matching across a wide frequency band. Adjusting the resistance of the third resistor R3 controls the degree of output voltage attenuation. For example, if the desired output voltage of the output branch is half the input voltage, the resistance of the third resistor R3 can be adjusted to the same value as the fourth resistor R4.

[0069] Furthermore, in some embodiments, the low noise amplifier, the PLL phase-locked loop, the low-frequency power division circuit, and the high-frequency power division circuit are single-port.

[0070] It is understandable that in traditional circuits, clock signals generally exist in the form of differential signals. The reason is that differential signals transmit signals using two lines, and transmit two signals with opposite phases at the same time. This can largely eliminate the impact of external noise on the signal, reduce common-mode interference, and improve the stability and accuracy of the clock signal. In addition, differential signals can more accurately control the timing relationship between various circuit modules. Since differential signals can reduce errors and delays during signal transmission, the overall performance of the entire system can be improved. However, differential signals require symmetrical and equal lengths, and the winding is complex. They are easily interfered with during long-distance transmission, making them inconvenient for long-distance transmission. PCB differential cable transmission has certain advantages in short-distance single-module transmission, but its disadvantages are more obvious in scenarios of system-level inter-board transmission or long-distance transmission.

[0071] Therefore, in each output branch, the low-noise amplifier, PLL, phase-locked loop, and power divider that can be selected are all single-port. Therefore, the clock signal is designed for single-ended input and single-ended output. This design not only simplifies the PCB circuitry but also facilitates transmission via RF cables. RF cables have excellent impedance characteristics and shielding effectiveness. Using RF cables to transmit clocks allows for higher transmission frequencies than PCB differential transmission, easily achieving low-loss transmission of signals above tens of GHz. It also achieves the anti-interference advantages of differential transmission on PCBs while eliminating some of the shortcomings of differential transmission. This reduces the drawbacks of excessive power attenuation caused by long-distance PCB wiring and transmission, while also taking into account electromagnetic shielding. Using RF cables for transmission significantly reduces the transmission link's exposure to external interference and the generation of external radiated interference.

[0072] Thus, by replacing the traditional clock driver chip with the main power division circuit 100, the sub-power division circuit, and the low-noise amplifier, the inherent drawbacks of the transmission method with a clock driver chip are resolved. The main power division circuit 100 and the sub-power division circuit enable the transmission of multiple clock signals, and the number of transmission channels can be determined by the sub-power division circuit, so the number of transmission channels is not limited. By providing a low-noise amplifier on each output branch, long-distance transmission of the clock signal is achieved. By providing a high-frequency clock transmission module, high-frequency clock signal transmission can be achieved. By providing a matching adjustment circuit on each output branch, the power of the final output clock signal is made to better meet the input level requirements of the subsequent circuit.

[0073] The long-distance, multi-channel synchronous clock transmission device of the present invention overcomes the drawbacks of traditional clocks, such as limited output channels, low frequency, high harmonic spurious signals, fixed power, high transmission attenuation, and difficult PCB trace design. With the rapid development of modern electronic technology, signal bandwidth and sampling rates are increasing, and the demand for high-frequency, high-bandwidth acquisition clocks is increasing. The present invention overcomes the limitations of traditional clock driver chips and can be widely used in homologous frequency conversion, high-speed acquisition, radar, communications, electronic countermeasures, and other fields.

[0074] Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented using software plus a necessary general-purpose hardware platform, or of course, hardware. Based on this understanding, the essence of the above technical solution, or the portion that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, or an optical disk, and includes a number of instructions for causing a computer device (such as a personal computer, server, or network device) to execute the methods described in each embodiment or certain portions of the embodiments.

[0075] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A long-distance multi-channel synchronous clock transmission device, characterized in that: It includes a main power division circuit and two clock transmission modules connected to the main power division circuit; The clock transmission module includes a sub-power division circuit and n output branches connected to the sub-power division circuit, where n is a positive integer; The output branch includes at least one low noise amplifier, a filter circuit and a matching adjustment circuit connected in sequence; The two clock transmission modules are respectively a low-frequency clock transmission module and a high-frequency clock transmission module, the sub-power division circuit of the low-frequency clock transmission module is a low-frequency power division circuit, and the sub-power division circuit of the high-frequency clock transmission module is a high-frequency power division circuit; The high-frequency clock transmission module further includes a PLL phase-locked loop, one end of the PLL phase-locked loop is connected to the main power division circuit, and the other end of the PLL phase-locked loop is connected to the high-frequency power division circuit.

2. The long-distance multi-channel synchronous clock transmission device according to claim 1, characterized in that: The n is a multiple of 2, the low-frequency power division circuit includes n / 2 low-frequency sub-power division units, and the low-frequency sub-power division units include a first capacitor, a first inductor, a second inductor, a first resistor, a second capacitor, and a third capacitor; One end of the first capacitor is connected to the output end of the main power dividing circuit to form a first node, and the other end of the first capacitor is grounded; One end of the first inductor is connected to the first node, the other end of the first inductor is connected to one end of the first resistor to form a second node, one end of the second capacitor is connected to the second node, and the other end of the second capacitor is grounded; One end of the second inductor is connected to the first node, the other end of the second inductor is connected to the other end of the first resistor to form a third node, one end of the third capacitor is connected to the third node, and the other end of the third capacitor is grounded.

3. The long-distance multi-channel synchronous clock transmission device according to claim 2, characterized in that: The inductance values ​​of the first inductor and the second inductor are set according to a target frequency, and the target frequency is a required frequency of a load.

4. The long-distance multi-channel synchronous clock transmission device according to claim 1, characterized in that: The high-frequency power dividing circuit includes a plurality of cascaded power dividers.

5. The long-distance multi-channel synchronous clock transmission device according to claim 1, characterized in that: The matching adjustment circuit includes a second resistor, a third resistor, a fourth resistor and a fourth capacitor; One end of the second resistor is connected to the filter circuit to form a fourth node, the other end of the second resistor is connected to one end of the fourth capacitor to form a fifth node, and the other end of the fourth capacitor is connected to the output interface; One end of the third resistor is connected to the fourth node, and the other end of the third resistor is grounded to form a sixth node; One end of the fourth resistor is connected to the fifth node, and the other end of the fourth resistor is connected to the sixth node.

6. The long-distance multi-channel synchronous clock transmission device according to claim 5, characterized in that: The resistance values ​​of the second resistor, the third resistor, and the fourth resistor are determined according to the gain and target power of the low noise amplifier, where the target power is the required power of the load.

7. The long-distance multi-channel synchronous clock transmission device according to any one of claims 1 to 6, characterized in that: The number and gain of the low noise amplifiers are determined according to the length and attenuation of the transmission cables of the long-distance multi-channel synchronous clock transmission device.

8. The long-distance multi-channel synchronous clock transmission device according to claim 1, characterized in that: The low noise amplifier, the PLL phase-locked loop, the low-frequency power division circuit and the high-frequency power division circuit are single-port.

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