Multi-phase power converter with external phase circuit

Abstract

The invention relates to a multi-phase power converter with an external phase circuit. A power management circuit included in a computer system stabilizes a voltage level of a power node used by other circuits in the computer system. The power management circuit includes a control circuit and a plurality of phase circuits coupled to a regulated power supply node via corresponding inductors. The control circuit selectively activates particular phase circuits of the plurality of phase circuits, allowing them to provide respective currents to the regulated power supply node. The control circuit also selectively activates a particular one of the other phase circuits located external to the power management circuit and coupled to the regulated power supply node via its corresponding inductor. Once activated, the external phase circuit provides a respective current to the regulated power supply node via its corresponding inductor.

Description

[0001] This application is a divisional application of the Chinese invention patent application whose international application date is June 3, 2022, national application number is 202280041140.6, and invention name is "Multi-phase power converter with external phase circuit" which has entered the Chinese national phase. Technical Field

[0002] The present disclosure relates to power management in computer systems, and more particularly to voltage regulator circuit operation.

[0003] Description of Related Technology

[0004] Modern computer systems may include multiple circuit blocks designed to perform various functions. For example, such circuit blocks may include a processor, or a processor core configured to execute software or program instructions. In addition, circuit blocks may include memory circuits, mixed signal or analog circuits, etc.

[0005] In some computer systems, circuit blocks may be designed to operate using different supply voltage levels. For example, in some computer systems, power management circuits (also referred to as "power management units") may generate and monitor various power signals.

[0006] The power management circuit generally includes one or more power converter circuits configured to generate a regulator voltage level on a corresponding power signal line using the voltage level of an input power signal. Such converter circuits may employ a plurality of reactive circuit elements, such as inductors, capacitors, etc. Summary of the invention

[0007] Various embodiments for generating a voltage level on a regulated power supply node are disclosed. In general, a power management unit includes a control circuit and a first phase circuit. The control circuit is configured to generate an external demand current and an internal demand current using the voltage level of the regulated power supply node. The first phase circuit is coupled to the regulated power supply node via a first inductor and is configured to provide a first current to the regulated power supply node via the first inductor during a first conduction time period based on the internal demand current. A second phase circuit external to the power management unit is coupled to the regulated power supply node via a second inductor and is configured to provide a second current to the regulated power supply node via the second inductor during a second conduction time period based on the external demand current. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A block diagram of an embodiment of a power converter system for a computer system is shown.

[0009] Figure 2 A block diagram of another embodiment of a power converter system is shown.

[0010] Figure 3 A block diagram of an embodiment of an internal / external phase circuit for a power converter circuit is shown.

[0011] Figure 4 A block diagram of an embodiment of an internal driver circuit is shown.

[0012] Figure 5 A block diagram of an embodiment of an external phase circuit for a power converter circuit is shown.

[0013] Figure 6 A block diagram of an embodiment of an external driver circuit for a power converter circuit is shown.

[0014] Figure 7 A block diagram of a control circuit for a power converter phase circuit is shown.

[0015] Figure 8 A block diagram of a main control circuit for a power converter circuit is shown.

[0016] Fig. 9 A block diagram of a power management system using an external phase circuit is shown.

[0017] Fig.10 A block diagram of a phase circuit for use with a power management circuit is shown.

[0018] Fig.11 A block diagram of a control circuit for use with a power management circuit is shown.

[0019] Fig.12 A block diagram of a power management system with a shared phase circuit is shown.

[0020] Fig.13 A flow chart depicting an embodiment of a method for operating a power converter system is shown.

[0021] Fig.14 A flow chart depicting an embodiment of a method for operating a power management circuit is shown.

[0022] Fig.15 It is a block diagram of the system on chip.

[0023] Fig.16 is a block diagram of an embodiment of a computer system.

[0024] Fig.17 An example of a non-transitory computer-readable storage medium storing circuit design information is shown. DETAILED DESCRIPTION

[0025] A computer system may include multiple circuit blocks configured to perform specific functions. Such circuit blocks may be fabricated on a common substrate and may employ different supply voltage levels. A power management unit (commonly referred to as a "PMU") may include multiple power converter circuits or regulator circuits configured to generate regulated voltage levels for various power supply signals. Such regulator circuits may employ both passive circuit elements (e.g., inductors, capacitors, etc.) and active circuit elements (e.g., transistors, diodes, etc.).

[0026] Different types of voltage regulator circuits may be employed based on the power requirements of the load circuit, available circuit area, etc. One common type of voltage regulator circuit is a buck converter circuit. Such a converter circuit includes a plurality of switches (also referred to as "power switches") and a switch node, which is coupled to a regulated power supply node via an inductor. One switch is coupled between the input power supply node and the switch node and is referred to as a "high-side switch". Another switch is coupled between the switch node and the ground power supply node and is referred to as a "low-side switch".

[0027] When the high-side switch is closed (known as the “on-time”), energy is applied to the inductor, causing the current through the inductor to increase. During this time, the inductor stores energy in the form of a magnetic field. When the high-side switch is open and the low-side switch is closed (known as the “off-time”), energy is no longer applied to the inductor and the voltage across the inductor reverses, which causes the inductor to act as a current source, where the energy stored in the inductor’s magnetic field supports the current flowing into the load. The process of closing and opening the high-side switch and the low-side switch is performed periodically to maintain the desired voltage level on the power supply node.

[0028] The power converter circuit can use different voltage regulation modes to determine the periodicity and duration of the on-time and off-time. As used herein, the voltage regulation mode refers to a specific method of detecting operating conditions to determine the frequency and duration of the on-time and off-time used by the power converter circuit. For example, the power converter can detect the maximum current flowing through its inductor to determine the end of the on-time period. This type of voltage regulation mode is called "peak current regulation mode". Alternatively, the power converter can detect the minimum current flowing through its inductor to determine the end of the off-time period. This type of voltage regulation mode is called "valley current regulation mode".

[0029] As the level of integration increases, power converters need to provide an increased amount of current to the load circuit. For example, in some cases, the power converter needs to be able to provide 100A or more to the load circuit. Existing power converter solutions are limited by thermal budget and packaging requirements. Therefore, the scalability of current power converter designs is restrictive and inefficient for high current applications. In addition, the efficiency of the power converter circuit must be maintained at smaller loads, and the design of the power converter circuit must be flexible to allow for changes in current requirements later in the design process.

[0030] The techniques described in the present disclosure allow for power converter circuits that employ a combination of external phases and drive circuits that may be located on different integrated circuits. Such external phases and drive circuits may be manufactured to have different physical properties that allow for the use of higher input voltages, thereby allowing the power converter to more easily support high current requirements. Where the external phases and drive circuits are located on different integrated circuits, the heat generated by the power converter circuit is not located on a single integrated circuit, thereby improving thermal management. Furthermore, additional external phases and drive circuits may be added later in the design process to more easily accommodate changes in load current as the computer system design evolves.

[0031] Go to Figure 1 , depicts a block diagram of a power converter system. As shown, the power converter system 100 includes a main control circuit 101, a phase circuit 102, a phase circuit 103, and a drive circuit 105. In various embodiments, the main control circuit 101 and the phase circuits 102 and 103 are located on an integrated circuit 109, while the drive circuit 105 is located on an integrated circuit 110. It should be noted that although only two phase circuits are depicted as being included on the integrated circuit 109, in other embodiments, any suitable number of phase circuits may be included on the integrated circuit 109.

[0032] The master control circuit 101 is configured to selectively activate either of the phase circuits 102 and 103. As described below, the master control circuit 101 can be configured to generate a phase clock signal 111 and other control signals, reference signals, and enable signals (all not shown) used by the phase circuits 102 and 103. In various embodiments, the master control circuit 101 can be configured to support additional phase circuits. The number of phase circuits managed by the master control circuit 101 can be controlled by control bits stored in registers, one-time programmable memory, or other suitable storage locations.

[0033] As used herein, when a signal is activated, it is set to a logic or voltage level that activates a load circuit or device. Depending on the load circuit, the logic level can be a high logic level or a low logic level. For example, the active state of a signal coupled to a p-channel MOSFET is a low logic level (referred to as an "active low signal"), while the active state of a signal coupled to an n-channel MOSFET is a high logic level (referred to as an "active high signal").

[0034] Phase circuit 102 includes driver circuit 104 and is configured to use a first phase clock signal of phase clock signals 111 to activate driver circuit 104, which is coupled to regulated supply node 108 via inductor 106. Driver circuit 104 is configured to provide current 112 to regulated supply node 108 during a first on-time period.

[0035] Phase circuit 103 is configured to use the second phase clock signal of phase clock signal 111 to activate driver circuit 105, which is coupled to regulated power supply node 108 via inductor 107. Driver circuit 105 is configured to provide current 113 to regulated power supply node 108 during the second conduction time period. It should be noted that the first conduction time period and the second conduction time period can be different, or they can overlap. The respective timing and duration of the first conduction time period and the second conduction time period can be based on currents 112 and 113, the first phase clock and the second phase clock, and the voltage level of regulated power supply node 108.

[0036] In various embodiments, inductors 106 and 107 may be located on integrated circuit 109. Alternatively, inductors 106 and 107 may be located on integrated circuit 110, or on an integrated circuit different from integrated circuit 109 or integrated circuit 110. In various embodiments, inductors 106 and 107 may be implemented as chip inductors coupled to integrated circuits 109 and 110. In other embodiments, inductors 106 and 107 may be fabricated as planar spirals or other suitable structures on either integrated circuit 109 or 110.

[0037] exist Figure 1 In the embodiment of the present invention, the drive circuit 105 outside the integrated circuit 109 is controlled by the phase circuit 103. As shown, the phase circuit 103 does not have an internal drive circuit and is configured to control only the external drive circuit. However, in some cases, a phase circuit including an internal drive circuit such as the phase circuit 102 can also be configured to control the external drive circuit. Figure 2 Another embodiment of a power converter system including a phase circuit capable of driving both internal and external drive circuits is depicted in FIG.

[0038] As shown in the figure, the power converter system 200 includes a main control circuit 101, a phase circuit 102, a phase circuit 201 and a drive circuit 105. The main control circuit 101, the phase circuit 102 and the drive circuit 105 are configured to Figure 1 The method operates in a similar manner to that described in the embodiment of the present invention.

[0039] Phase circuit 201 includes driver circuit 202 and is configured to activate driver circuit 105, which is coupled to regulated power supply node 108 via inductor 106, using a phase clock signal in phase clock signal 111. As described below, phase circuit 201 can deactivate driver circuit 202 based on the value of enable signal 203. In various embodiments, the value of enable signal 203 can be set during initialization or as part of a power-up sequence. Alternatively, the value of enable signal 203 can be stored in a non-volatile memory circuit, a one-time programmable memory circuit, or any other suitable storage circuit.

[0040] Please note that Figure 2 The embodiments depicted in are examples only. In other embodiments, additional phase circuits may be included on integrated circuit 109, including phase circuits that do not have internal drive circuits.

[0041] As described above, different types of phase circuits may be employed in a power converter circuit. Some phase circuits may be dedicated to external drive circuits (referred to as "external phase circuits"), while other phase circuits may be used for both internal and external drive circuits (referred to as "internal / external phase circuits").

[0042] exist Figure 3 A block diagram of an embodiment of an internal / external phase circuit is depicted in FIG. As shown, the internal / external phase circuit 300 includes a control circuit 301, an internal drive circuit 302, and a buffer circuit 303. In various embodiments, the internal / external phase circuit 300 may correspond to Figure 1 The phase circuit 102 depicted in FIG.

[0043] The control circuit 301 is configured to generate a control signal 310 and a control signal 311 using a phase enable signal 307, a driver enable signal 308, and a reference voltage 309. In some embodiments, the phase enable signal 307 may be a phase clock signal whose frequency is used to determine the duration of an on-time or an off-time associated with the driver circuit. In various embodiments, the reference voltage 309 may indicate a desired voltage level of the regulated power supply node 108.

[0044] In various embodiments, control circuit 301 may be configured to generate control signal 310 for a particular value of driver enable signal 308, and to generate control signal 311 for a different value of driver enable signal 308. For example, in response to determining that driver enable signal 308 is at a high logic level, control circuit 301 may activate control signal 311 based on the values ​​of phase enable signal 307 and reference voltage 309.

[0045] As described below, the control circuit 301 can be configured to generate a control signal 310 to determine the on-time and off-time of the high-side switch and the low-side switch in the drive circuit (e.g., the internal drive circuit 302). The control circuit 301 can be configured to control the on-time and the off-time according to pulse width modulation or pulse frequency modulation. In various embodiments, the control circuit 301 can use peak current regulation or valley current regulation.

[0046] The control circuit 301 may be implemented using any suitable combination of combinatorial logic circuits and sequential logic circuits.In various embodiments, the control circuit 301 may include one or more comparator circuits or amplifier circuits.

[0047] The internal drive circuit 302 is configured to drive the output node 304 based on the control signal 310. In various embodiments, when the driver enable signal 308 is set to a value that causes the internal / external phase circuit 300 to operate using the internal drive circuit 302 rather than the external drive circuit, the output node 304 may be coupled to an inductor (e.g., inductor 106). As described below, the internal drive circuit 302 may include a plurality of high-side switches that can couple the output node 304 to the power supply node 305, thereby allowing current to flow from the power supply node 305 through the output node 304 into the inductor. The internal drive circuit 302 may also include a plurality of low-side switches that can couple the output node 304 to the ground power supply node, thereby allowing the inductor to act as a current source when its magnetic field collapses. The number of high-side switches and low-side switches may vary based on the operating mode. For example, when the internal / external phase circuit 300 operates as an internal phase circuit, the internal drive circuit 302 can employ all available high-side and low-side switches, and when the internal / external phase circuit 300 operates as an external phase circuit, the internal drive circuit 302 can be all available high-side and low-side switches or any suitable portion thereof.

[0048] Buffer circuit 303 is coupled to power supply node 306 and is configured to buffer control signal 311 and drive the signal onto output node 304. Note that in various embodiments, the voltage level of power supply node 306 is greater than the voltage level of power supply node 305. In various embodiments, when buffer circuit 303 is inactive, it can enter a high output impedance state (referred to as "tri-state") to avoid loading the output of internal driver circuit 302. In some embodiments, buffer circuit 303 can be implemented as a non-inverting amplifier circuit, two inverter logic gates coupled in series, or any other suitable circuit.

[0049] Go to Figure 4 , depicts a block diagram of an internal driver circuit. As shown, internal driver circuit 400 includes gate control circuit 401, buffer circuits 402A-C, buffer circuits 403A-C, and slices 414A-C. Slice 414A includes devices 404A and 405A, and slice 414B includes devices 404B and 405B. In a similar manner, slice 414C includes devices 404C and 405C. In various embodiments, internal driver circuit 400 may correspond to Figure 3 The internal driving circuit 302 is depicted in FIG.

[0050] The gate control circuit 401 is configured to generate signals 410 and 411 using a control signal 408 and an enable signal 409. In various embodiments, the enable signal 409 may correspond to the driver enable signal 308, and the control signal 408 may correspond to the phase enable signal 307, such as Figure 3 4. It is noted that in various embodiments, different signals in signals 410 and 411 can be activated to activate different slices in slices 414A-C. By adjusting the number of slices 414A-C that are active, the strength with which output node 406 is driven can be adjusted, thereby allowing internal drive circuit 400 to drive an inductor or an external drive circuit. In some embodiments, gate control circuit 401 is configured to deactivate signals 410 and 411 in response to determining that enable signal 409 is deactivated.

[0051] When the enable signal 409 is valid, the gate control circuit 401 is configured to activate the signals 410 and 411 based on the control signal 408. For example, the gate control circuit 401 may be configured to activate a particular one of the signals 410 and deactivate a particular one of the signals 411 in response to determining that the control signal 408 is valid. In some cases, the gate control circuit 401 may be configured to activate one or more of the signals 410 and deactivate one or more of the signals 411 during an on-time of a phase circuit (e.g., the internal / external phase circuit 300). The gate control circuit 401 may also be configured to deactivate one or more of the signals 410 and activate one or more of the signals 411 during an off-time of the phase circuit.

[0052] To avoid shoot-through current from power supply node 305 to ground power supply node 306 when devices 404A-C and 405A-C are both active, in some embodiments, gate control circuit 401 can be configured to generate signals 410 and 411 such that specific ones of signals 410 and 411 are not active at the same time. In various embodiments, gate control circuit 401 can be implemented using any suitable combination of combinational logic circuits and sequential logic circuits.

[0053] Buffer circuit 402A is configured to generate signal 412A using one of signals 410, and buffer circuit 402B is configured to generate signal 412B using a different one of signals 410. In a similar manner, buffer circuit 402C is configured to generate signal 412C using a corresponding one of signals 410. Buffer circuit 403A is configured to generate signal 413A using one of signals 411, and buffer circuit 403B is configured to generate signal 413B using a different one of signals 411. In a similar manner, buffer circuit 403C is configured to generate signal 413C using a corresponding one of signals 411. In some embodiments, buffer circuits 402A-C and 403A-C can provide additional drive to drive control terminals of devices 404A-C and 405A-C, respectively. In various embodiments, buffer circuits 402A-C and 403A-C can be implemented as non-inverting amplifier circuits, inverter gates connected in series, or any other suitable circuit.

[0054] Devices 404A-C are coupled between power supply node 305 and output node 406 and are controlled by corresponding signals in signals 412A-C. For example, in response to determining that signal 412A is valid, device 404A is configured to couple power supply node 305 to output node 406, thereby allowing current to flow from power supply node 305 into output node 406. Note that output node 406 may be coupled to an inductor (e.g., inductor 106), in which case devices 404A-C may collectively act as a high-side switch for the inductor. Alternatively, output node 406 may be coupled to an external drive circuit, such as drive circuit 105. In various embodiments, devices 404A-C may be implemented as p-channel metal oxide semiconductor field effect transistors (MOSFETs), fin field effect transistors (FinFETs), or gate-all-around field effect transistors (GAAFETs).

[0055] Devices 405A-C are coupled between output node 406 and ground power supply node 306 and are configured to couple output node 406 to ground power supply node 306 based on corresponding signals in signals 413A-C. When output node 406 is coupled to an inductor, devices 405A-C collectively act as a low-side switch for the inductor, thereby allowing the inductor to demagnetize during an off cycle. In various embodiments, devices 405A-C can be implemented as n-channel MOSFETs, FinFETs, or GAAFETs.

[0056] As described above, some phase circuits do not include an internal drive circuit and are configured to drive an external drive circuit. Figure 5 A block diagram of an embodiment of such a phase circuit is depicted in FIG. As shown, the external phase circuit 500 includes a control circuit 501 and a buffer 502. In various embodiments, the external phase circuit 500 may correspond to Figure 1 Phase circuit 103 is depicted.

[0057] The control circuit 501 is configured to generate a control signal 504 using a phase enable signal 503 and a reference voltage 309. In some embodiments, the phase enable signal 503 may be a phase clock signal whose frequency is used to determine the duration of an on-time or off-time associated with the driver circuit. In various embodiments, the reference voltage 309 may indicate a desired voltage level of the regulated power supply node 108.

[0058] As described below, the control circuit 501 can be configured to generate a control signal 504 to determine the on-time and off-time of the high-side switch and the low-side switch in the driver circuit (e.g., the driver circuit 105). The control circuit 501 can be configured to control the on-time and the off-time according to pulse width modulation or pulse frequency modulation. In various embodiments, the control circuit 501 can use peak current regulation or valley current regulation.

[0059] The control circuit 501 may be implemented using any suitable combination of combinatorial logic circuits and sequential logic circuits.In various embodiments, the control circuit 501 may include one or more comparator circuits or amplifier circuits.

[0060] Buffer circuit 502 is coupled to power supply node 306 and is configured to buffer control signal 504 to generate buffered control signal 505. Note that in various embodiments, the voltage level of power supply node 306 is greater than the voltage level of power supply node 305. In some embodiments, buffer circuit 502 can be implemented as a non-inverting amplifier circuit, two inverter logic gates coupled in series, or any other suitable circuit.

[0061] Go to Figure 6 , depicts a block diagram of an external driver circuit. As shown, the internal driver circuit 600 includes a logic circuit 601, a buffer circuit 602, a buffer circuit 603, and devices 604 and 605. In various embodiments, the external driver circuit 600 may correspond to Figure 1 The driving circuit 105 is depicted.

[0062] Logic circuit 601 is configured to generate signals 610 and 611 using control signal 607. In various embodiments, control signal 607 may correspond to Figure 1 . The logic circuit 601 is configured to activate the signals 610 and 611 based on the control signal 607. For example, the logic circuit 601 may be configured to activate the signal 610 and deactivate the signal 611 in response to determining that the control signal 607 is valid. In some cases, the logic circuit 601 may be configured to activate the signal 610 and deactivate the signal 611 during the on-time of the phase circuit (e.g., the phase circuit 103). The logic circuit 601 may also be configured to deactivate the signal 610 and activate the signal 611 during the off-time of the phase circuit.

[0063] To avoid shoot-through current from power supply node 608 to ground power supply node 609 when both devices 604 and 605 are active, in some embodiments, logic circuit 601 can be configured to generate signals 610 and 611 so that the two signals are not valid at the same time. In various embodiments, logic circuit 601 can be implemented using any suitable combination of combinational logic circuits and sequential logic circuits.

[0064] Buffer circuit 602 is configured to use signal 610 to generate signal 612, and buffer circuit 603 is configured to use signal 611 to generate signal 613. In some embodiments, buffer circuits 602 and 603 can provide additional drive to respectively drive control terminals of devices 604 and 605. In various embodiments, buffer circuits 602 and 603 can be implemented as non-inverting amplifier circuits, inverter gates connected in series, or any other suitable circuits.

[0065] Device 604 is coupled between power supply node 608 and output node 606 and is controlled by signal 612. In response to determining that signal 612 is valid, device 604 is configured to couple power supply node 608 to output node 606, thereby allowing current to flow from power supply node 608 into output node 606. Note that output node 606 may be coupled to an inductor (e.g., inductor 107), in which case device 604 may act as a high-side switch for the inductor. In various embodiments, device 604 may be implemented as a p-channel MOSFET, FinFET, or GAAFET.

[0066] Device 605 is coupled between output node 606 and ground power node 609 and is configured to couple output node 606 to ground power node 609 based on signal 613. When output node 606 is coupled to the inductor, device 605 acts as a low-side switch of the inductor, thereby allowing the inductor to demagnetize during the off cycle. In various embodiments, device 605 can be implemented as an n-channel MOSFET, FinFET, or GAAFET. It should be noted that devices 604 and 605 may have different physical properties (e.g., oxide thickness) than devices 404 and 405, thereby allowing devices 604 and 605 to operate at a higher voltage than devices 404 and 405.

[0067] Go to Figure 7 , depicts a block diagram of an embodiment of a control circuit. As shown, the control circuit 700 includes a latch circuit 702, a current sensor circuit 703, an error amplifier circuit 704, a slope compensation circuit 705, and a comparator circuit 706. In various embodiments, the control circuit 700 may correspond to the control circuit 301 or the control circuit 501.

[0068] The latch circuit 702 is configured to deactivate the control signal 717 using the reset signal 712 and the set signal 718. In various embodiments, the reset signal 712 may correspond to one of the phase clock signals 111. In some embodiments, the latch circuit 702 is configured to activate the control signal 717 in response to activation of the set signal 718 and to deactivate the control signal 717 in response to activation of the reset signal 712. In various embodiments, the latch circuit 702 may be implemented as a set-reset (SR) latch circuit including any suitable combination of logic gates.

[0069] The current sensor circuit 703 is coupled to the sensor node 707 and is configured to generate the inductor current 716. In some embodiments, the sensor node 707 may be coupled to a switch node of a power converter circuit, or to a terminal of a device in a drive circuit (e.g., drive circuit 105). In various embodiments, the current sensor circuit 703 may measure the voltage drop across the device in the drive circuit. And the measured voltage drop is used to generate the inductor current 716. The current sensor circuit 703 may include any suitable combination of a reference circuit and an amplifier circuit.

[0070] The error amplifier circuit 704 is configured to generate a demand current 714 using a reference voltage 713 and the voltage level of the regulated power supply node 108. In various embodiments, the error amplifier circuit 704 can be configured to generate the demand current 714 such that the value of the demand current 714 is proportional to the difference between the reference voltage 713 and the voltage level of the regulated power supply node 108. In some embodiments, the error amplifier circuit 704 can be implemented as a differential amplifier circuit or any other suitable comparator circuit.

[0071] The slope compensation circuit 705 is configured to modify the inductor current 716. In various embodiments, the slope compensation circuit 705 can be configured to combine a periodic current ramp with the inductor current 716 in a process referred to as "slope compensation." It is noted that slope compensation is used to improve the stability of a phase circuit (e.g., phase circuit 102) by increasing the frequency at which the regulator feedback loop can operate, thereby reducing the time it takes for the phase circuit to recover from transients.

[0072] The comparator circuit 706 is configured to generate a set signal 718 using the demand current 714 and the inductor current 716. In some embodiments, the comparator circuit 706 can be configured to compare the demand current 714 to the inductor current 716 and activate the set signal 718 in response to determining that the demand current 714 is less than the inductor current 716. In various embodiments, the comparator circuit 706 can be implemented using a differential amplifier circuit, a Schmitt trigger circuit, or any other suitable comparator circuit.

[0073] Go to Figure 8 , depicts a block diagram of an embodiment of the master control circuit 101. As shown, the master control circuit 101 includes a reference generator circuit 801 and a clock generator circuit 802.

[0074] Reference generator circuit 801 is coupled to power supply node 305 and is configured to generate reference voltage 309. In various embodiments, reference generator circuit 801 may be implemented as a bandgap reference circuit or any other suitable power supply temperature independent reference circuit. In some cases, reference generator circuit 801 may include a startup circuit configured to drive reference generator circuit 801 into a known state during a power-up operation.

[0075] The clock generator circuit 802 is configured to generate the phase clock signal 111 using the clock signal 803. In various embodiments, the clock generator circuit 802 can be configured to generate the phase clock signal 111 so that the respective phase clock signals in the phase clock signal 111 are out of phase with each other. In some cases, the respective frequencies of the phase clock signal 111 can be the same as the frequency of the clock signal 803, while in other cases, the respective frequencies of the phase clock signal 111 can be greater than or less than the frequency of the clock signal 803.

[0076] The clock generator circuit 802 can be implemented using any suitable combination of combinational logic circuits and sequential logic circuits. In some cases, the clock generator circuit 802 can include a phase-locked loop or a delay-locked loop circuit. Although the clock generator circuit 802 is depicted as generating a single set of phase clock signals, in other embodiments, the clock generator circuit 802 can generate multiple sets of phase clock signals for controlling different sets of phase circuits coupled to corresponding regulated power supply nodes.

[0077] As described above, some power converter circuits use external drive circuits to allow better thermal management while providing higher load currents. In other cases, a combination of an internal phase circuit and an external phase circuit having similar beneficial effects may be used. By using both internal phase and external phase, the power converter may have an improved load transient response. The internal phase circuit can operate at a higher switching frequency, thereby allowing them to respond to changes in the load faster before the external phase circuit can respond. Using both the internal phase circuit and the external phase circuit may reduce undershoot and overshoot on the regulated power supply node. A block diagram of an embodiment of a power management system using both internal phase circuits and external phase circuits is depicted. As shown, the power management system 900 includes an external phase circuit 903, inductors 904 and 905, and a power management unit 911, which includes a control circuit 901 and an internal phase circuit 902.

[0078] Control circuit 901 is configured to use the voltage level of regulated power supply node 108 to generate external demand current 910 , internal demand current 908 , and enable signal 909 . In some embodiments, control circuit 901 may be further configured to generate a plurality of enable signals including enable signal 909 .

[0079] The internal phase circuit 902 is coupled to the regulated power supply node 108 via the inductor 904 and is configured to provide a current 906 to the regulated power supply node 108 via the inductor 904 during a first on-time period based on the internal demand current 908. In some embodiments, the internal phase circuit 902 may also provide the current 906 in response to determining that a corresponding enable signal of the plurality of enable signals is valid.

[0080] The external phase circuit 903 is coupled to the regulated power supply node 108 via the inductor 905 and is configured to provide a current 907 to the regulated power supply node 108 via the inductor 905 during a second on-time period based on the external demand current 910 and the enable signal 909. In some embodiments, the external phase circuit 903 is further configured to provide the current 907 in response to determining that the enable signal 909 is valid.

[0081] Despite Fig. 9 In the embodiment of FIG. 1 , only a single internal phase circuit and a single external phase circuit are depicted, but in other embodiments, any suitable number of internal phase circuits and external phase circuits may be employed. In some embodiments, the respective number of internal phase circuits and external phase circuits included in power management system 900 may be based on the expected maximum load current that can be drawn from regulated power supply node 108.

[0082] Go to Fig.10 , depicts a block diagram of an embodiment of a phase circuit. As shown, the phase circuit 1000 includes a drive circuit 1001, a device 1008, a device 1009, a latch circuit 1002, a comparator circuit 1006, a slope compensation circuit 1005, and a current sensor circuit 1003.

[0083] Device 1008 is coupled between input power supply node 1010 and switch node 1007, and is controlled by control signal 1020. In a similar manner, device 1009 is coupled between switch node 1007 and ground power supply node 1011, and is controlled by control signal 1021. In various embodiments, switch node 1007 may also be coupled to an inductor, which in turn is coupled to a regulated power supply node.

[0084] In response to activation of control signal 1020, device 1008 is configured to couple input power node 1010 to switch node 1007, thereby allowing current to flow into the inductor, thereby magnetizing the inductor. In response to activation of control signal 1021, device 1009 is configured to couple switch node 1007 to ground power node 1011. When switch node 1007 is coupled to ground power node 1011, energy is no longer supplied to the inductor, thereby causing the magnetic field of the inductor to collapse. When the magnetic field collapses, the inductor acts as a current source, thereby providing current to the regulated power node.

[0085] In various embodiments, device 1008 can be implemented as a p-channel MOSFET, FinFET, GAAFET, or any other suitable transconductance device. In some embodiments, device 1009 can be implemented as an n-channel MOSFET, FinFET, GAAFET, or other suitable transconductance device.

[0086] The driver circuit 1001 is configured to generate a control signal 1020 and a control signal 1021 using the control signal 1017. In various embodiments, the driver circuit 1001 can be configured to activate the control signal 1020 and deactivate the control signal 1021 in response to activation of the control signal 1017. The driver circuit 1001 can also be configured to deactivate the control signal 1020 and activate the control signal 1021 in response to deactivation of the control signal 1017. In some embodiments, the driver circuit 1001 can include any suitable combination of logic gates, sequential logic circuit elements, MOSFETs, FinFETs, GAAFETs, or any other suitable transconductance devices.

[0087] The latch circuit 1002 is configured to deactivate the control signal 1017 using the reset signal 1012, the set signal 1018, and the enable signal 1022. In some embodiments, the latch circuit 1002 is configured to activate the control signal 1017 in response to activation of the set signal 1018 when the enable signal 1022 is valid, and to deactivate the control signal 1017 in response to activation of the reset signal 1012 when the enable signal 1022 is valid. The latch circuit 1002 is configured to deactivate the control signal 1017 in response to determining that the enable signal 1022 is invalid. In various embodiments, the latch circuit 1002 can be implemented as a set-reset (SR) latch circuit including any suitable combination of logic gates.

[0088] The current sensor circuit 1003 is configured to generate an inductor current 1016. In various embodiments, the current sensor circuit 1003 can measure the voltage drop across the device 1009 and use the measured voltage drop to generate the inductor current 1016. The current sensor circuit 1003 can include any suitable combination of reference circuits and amplifier circuits.

[0089] The slope compensation circuit 1005 is configured to modify the inductor current 1016. In various embodiments, the slope compensation circuit 1005 can be configured to combine a periodic current ramp with the inductor current 1016 in a process referred to as "slope compensation." Note that slope compensation is used to improve the stability of the phase circuit 1000 by increasing the frequency at which the regulator feedback loop can operate, thereby reducing the time for the phase circuit 1000 to recover from transients.

[0090] The comparator circuit 1006 is configured to generate a set signal 1018 using the demand current 1014 and the inductor current 1016. In some embodiments, the comparator circuit 1006 can be configured to compare the demand current 1014 to the inductor current 1016 and activate the set signal 1018 in response to determining that the demand current 1014 is less than the inductor current 1016. In various embodiments, the comparator circuit 1006 can be implemented using a differential amplifier circuit, a Schmitt trigger circuit, or any other suitable comparator circuit.

[0091] Go to Fig.11 , depicts a block diagram of an embodiment of the control circuit 901. As shown, the control circuit 901 includes an error amplifier 1101, a management circuit 1102, a current comparison circuit 1103, and a logic circuit 1111.

[0092] The error amplifier 1101 is configured to generate a demand current 1106 using a reference voltage 1104 and a feedback signal 1105. In various embodiments, the value of the feedback signal 1105 can be based on the voltage level of the regulated power supply node 108. In various embodiments, the error amplifier 1101 can be configured to generate the demand current 1106 such that the value of the demand current 1106 is proportional to the difference between the reference voltage 1104 and the feedback signal 1105. In some embodiments, the error amplifier 1101 can be implemented using a differential amplifier circuit or any other suitable comparator circuit.

[0093] Management circuit 1102 is configured to generate external demand current 910 and internal demand current 908 using demand current 1106. Fig.11In the embodiment of FIG. 1 , a single external demand current and a single internal demand current are depicted, but in other embodiments, the management circuit 1102 can be configured to generate any suitable number of internal demand currents and external demand currents. In some embodiments, the management circuit 1102 can be configured to scale the demand current 1106 to generate the external demand current 910 and the internal demand current 908. In various embodiments, the management circuit 1102 can include any suitable combination of current mirror circuits, amplifier circuits, and bias circuits.

[0094] The current comparison circuit 1103 is configured to generate a comparison signal 1109 using the sensed current 1108 and the current threshold 1107. Note that the sensed current 1108 may correspond to an inductor current of an inductor coupled to an internal phase circuit such as the internal phase circuit 902. In various embodiments, the current comparison circuit 1103 may be configured to compare a given sensed current in the sensed current 1108 with a corresponding threshold in the current threshold 1107 to generate a specific comparison signal in the comparison signal 1109.

[0095] In various implementations, the current comparison circuit 1103 can be implemented using a plurality of differential amplifier circuits or other comparator circuits with resistors coupled to their respective inputs to convert the current threshold 1107 and the sensed current 1108 into voltages for comparison. In some implementations, additional circuitry (e.g., a Schmitt trigger circuit) can be used to convert the output of the differential amplifier circuit into a digital value for the comparison signal 1109.

[0096] The logic circuit 1111 is configured to generate an enable signal 1110 using the comparison signal 1109. In various embodiments, the logic circuit 1111 may be configured to activate a given one of the enable signals in response to determining that the number of comparison signals 1109 has exceeded a threshold. For example, if two enable signals are valid, and the comparison signals of the two phase circuits coupled to the valid enable signals are valid, then the current limits of the two phase circuits have been reached, and the logic circuit 1111 may activate a third enable signal to activate the third phase circuit. By generating the enable signal 1110 in this manner, an increase or decrease in the load current drawn from the regulated power supply node 108 results in a corresponding increase or decrease in the number of active phase circuits. Adjusting the number of active phase circuits can ensure that a sufficient number of phase circuits are active to supply the required current and prevent an undesirable drop in the voltage level of the regulated power supply node 108.

[0097] In various embodiments, logic circuit 1111 may be implemented using any suitable combination of combinatorial logic circuits and sequential logic circuits. In some cases, logic circuit 1111 may be implemented as a microcontroller or general purpose processor circuit configured to execute software or program instructions.

[0098] In some computer systems, different groups of functional circuits may require different supply voltage levels. To accommodate such functional circuit blocks, a power management system may be configured to generate voltage levels on multiple regulated power supply nodes. Fig.12 A block diagram of an embodiment of a power management system configured to generate voltage levels of multiple regulated power supply nodes is depicted in As shown, power management system 1200 includes controller circuits 1201 and 1202 and external phase circuits 1204-1206.

[0099] Controller circuit 1201 is configured to manage the voltage level of regulated power supply node 1213 by generating control signals 1216-1218. Control signal 1216 is used to control a specific phase within external phase circuit 1204, while control signal 1217 is used to control external phase circuit 1205. Control signal 1218 is used to control a given phase circuit within external phase circuit 1206. As described below, external phase circuit 1206 is shared between controller circuit 1201 and controller circuit 1202.

[0100] The controller circuit 1202 includes an internal phase circuit 1203 and is configured to manage a voltage level of a regulated power supply node 1214. The controller circuit 1202 is configured to control the operation of the internal phase circuit 1203, which is configured to provide current to the regulated power supply node via the inductor 1212. In addition, the controller circuit 1202 is further configured to generate a control signal 1219 that is used to control a specific phase of the external phase circuit 1206. In various embodiments, the control signal 1219 may include a demand current used by a specific phase of the external phase circuit 1206 to determine the on-time of the supply current through the inductor 1211 to the regulated power supply node 1214.

[0101] The external phase circuit 1204 includes a multi-phase circuit (e.g., Fig.10 1200) and is coupled to a power supply node 1220 and inductors 1207 and 1208, which are further coupled to a regulated power supply node 1213. In various embodiments, the external phase circuit 1204 is configured to provide a corresponding current through the inductors 1207 and 1208. In some embodiments, the external phase circuit 1204 can be configured to determine the on-time of the current through the inductors 1207 and 1208 using the control signal 1216. In other embodiments, the external phase circuit 1204 can be configured to determine when to start the on-time of the current based on the demand current included in the control signal 1216.

[0102] The external phase circuit 1205 includes a single-phase circuit (e.g., Fig.10 1200) and is coupled to a power supply node 1221. In various embodiments, the voltage level of the power supply node 1221 can be greater than the voltage level of the power supply node 1220. The external phase circuit 1205 is further coupled to an inductor 1209, which in turn is coupled to a regulated power supply node 1213. In some embodiments, the external phase circuit 1205 is configured to provide current to the regulated power supply node 1213 via the inductor 1209. In some embodiments, by using a power supply node with a high voltage level, the external phase circuit 1205 is allowed to provide additional current to the regulated power supply node 1213 during high load periods.

[0103] The external phase circuit 1206 includes a plurality of phases and is coupled to the power supply node 1220 and the inductors 1210 and 1211. The inductor 1210 is further coupled to the regulated power supply node 1213, and the inductor 1211 is coupled to the regulated power supply node 1214. By using different phases of the plurality of phases for different power supply nodes 1214. The external phase circuit 1206 is shared between the controller circuit 1201 and the controller circuit 1202, and each controller circuit controls one phase within the external phase circuit 1206 to provide current to the regulated power supply nodes 1213 and 1214. This sharing allows current supply capabilities to be provided to different regulated power supply nodes while minimizing the impact on area.

[0104] Note that in some embodiments, controller circuits 1201 and 1202 may be included on a first integrated circuit, and external phase circuits 1204-1206 may be located on a second integrated circuit. Inductors 1207-1212 may be located on the first integrated circuit, the second integrated circuit, a third integrated circuit, or elsewhere within a computer system that includes the first integrated circuit and the second integrated circuit. Fig.12 In the embodiment of FIG. 1 , only three controller circuits and three external phase circuits are depicted, but in other embodiments, any suitable number of controller circuits, external phase circuits, and power supply nodes for the external phase circuits may be employed.

[0105] Go to Fig.13 , a flow chart depicting an embodiment of a method for operating a power converter system is shown. The method applicable to the power converter system 100 begins in block 1301 .

[0106] The method includes activating a first driver circuit using a first phase enable signal by a first phase circuit of a plurality of phase circuits, wherein the plurality of phase circuits and the first driver circuit are included on a first integrated circuit (block 1302). The method also includes activating a second driver circuit using a second phase enable signal by a second phase circuit of the plurality of phase circuits, wherein the second driver circuit is included on a second integrated circuit (block 1303).

[0107] In some embodiments, the second phase circuit may be further coupled to a third driver circuit included on the first integrated circuit. In this case, the method may further include deactivating the third driver circuit by the second phase circuit based on the driver enable signal.

[0108] In various embodiments, the method may further include generating, by a master control circuit, a first phase enable signal and a second phase enable signal, wherein the master control circuit is included on the first integrated circuit. In other embodiments, the method may include generating, by the master control circuit, a driver enable signal based on a load current drawn from a regulated power supply node, and generating, by the master control circuit, a reference voltage level using a voltage level of the first power supply node.

[0109] In various embodiments, the first driver circuit is coupled to the first power supply node, and the second driver circuit is coupled to the second power supply node. In some embodiments, multiple phase circuits are coupled to the first power supply node. In various embodiments, the voltage level of the second power supply node can be greater than the voltage level of the first power supply node.

[0110] The method also includes providing a first current to a regulated power supply node by the first driver circuit during a first on-time period in response to being activated (block 1304). In various embodiments, providing the first current to the regulated power supply node may include comparing a reference voltage to a voltage level of the regulated power supply node.

[0111] The method also includes providing a second current to the regulated power supply node by the second driver circuit during a second on-time period in response to being activated (block 1305). In various embodiments, the duration of the second on-time period can be based on the value of the second current or based on the clock signal. The method ends in block 1306.

[0112] Go to Fig.14 , a flow chart depicting an embodiment of a method for operating a power management system is shown. The method applicable to the power management system 900 begins in block 1401 .

[0113] The method includes generating, by a control circuit in a power management unit, an external demand current and an internal demand current (block 1402). In various embodiments, generating, by the control circuit, the external demand current and the internal demand current includes comparing a feedback signal to a threshold, wherein a value of the feedback signal is based on a voltage level of a regulated power supply node.

[0114] The method also includes providing a first current to a regulated power supply node via a first inductor using an internal demand current by a first phase circuit during a first on-time period, wherein the first phase circuit is included in a power management unit (block 1403). In some embodiments, providing the first current includes determining a current flowing in the first inductor and comparing the internal demand current to the current flowing in the first inductor.

[0115] The method also includes providing a second current to the regulated power supply node via a second inductor using the external demand current by a second phase circuit during a second on-time period, wherein the second phase circuit is external to the power management unit (block 1404). In some embodiments, providing the second current includes determining a current flowing in the second inductor and comparing the external demand current to the current flowing in the second inductor.

[0116] Note that in some cases, the power management unit can be located on the first integrated circuit and the second phase circuit can be located on the second integrated circuit. In some embodiments, the first inductor and the second inductor can be located on a third integrated circuit or attached to an interposer or other substrate that is also attached to the first integrated circuit and the second integrated circuit.

[0117] In various embodiments, the method may further include generating, by the control circuit, a plurality of enable signals. The method may further include: providing, by the first phase circuit, a first current in response to determining that a first enable signal in the plurality of enable signals is valid; and providing, by the second phase circuit, a second current in response to determining that a second enable signal in the plurality of enable signals is valid. In some embodiments, the plurality of valid enable signals are based on values ​​of a load current drawn from a regulated power supply node. The method ends in block 1405.

[0118] exist Fig.15 1500. In the illustrated embodiment, SoC 1500 includes a power management unit 1501, a processor circuit 1502, a memory circuit 1503, and an input / output circuit 1504, each of which is coupled to a power supply node 1505. In various embodiments, SoC 1500 may be configured for use in a desktop computer, a server, or in a mobile computing application such as, for example, a tablet computer, a laptop computer, or a wearable computing device.

[0119] The power management unit 1501 is configured to generate a regulated voltage level on a power node 1505 to provide power to the processor circuit 1502, the memory circuit 1503, and the input / output circuit 1504. In various embodiments, the power management unit 1501 may be implemented as follows: Figure 6 The external drive circuit 600 depicted in FIG. Fig. 9 . Although the power management unit 1501 is depicted as generating a voltage level for a single power supply node, in other embodiments, the power management unit 1501 may be configured to generate multiple voltage levels on corresponding power supply nodes.

[0120] In various embodiments, processor circuit 1502 may represent a general purpose processor that performs computing operations. For example, processor circuit 1502 may be a central processing unit (CPU) such as a microprocessor, microcontroller, application specific integrated circuit (ASIC), or field programmable gate array (FPGA).

[0121] In various embodiments, memory circuit 1503 may include any suitable type of memory, such as, for example, dynamic random access memory (DRAM), static random access memory (SRAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or non-volatile memory. Fig.15 A single memory circuit is shown in FIG. 1 , but in other embodiments, any suitable number of memory circuits may be employed.

[0122] Input / output circuitry 1504 may be configured to coordinate data transfers between SoC 1500 and one or more peripheral devices. Such peripheral devices may include, but are not limited to, storage devices (e.g., storage devices based on magnetic or optical media, including hard drives, tape drives, CD drives, DVD drives, etc.), audio processing subsystems, or any other suitable type of peripheral device. In some embodiments, input / output circuitry 1504 may be configured to implement a universal serial bus (USB) protocol or an IEEE 1394 The version of the protocol.

[0123] Input / output circuitry 1504 may also be configured to coordinate data transfers between SoC 1500 and one or more devices (e.g., other computing systems or integrated circuits) coupled to SoC 1500 via a network. In one embodiment, input / output circuitry 1504 may be configured to perform data processing required to implement an Ethernet (IEEE 802.3) networking standard such as, for example, Gigabit Ethernet or 10 Gigabit Ethernet, but it is contemplated that any suitable networking standard may be implemented. In some embodiments, input / output circuitry 1504 may be configured to implement multiple discrete network interface ports.

[0124] Now go to Fig.16 , various types of systems that may include any of the circuits, devices, or systems described above are shown. The system or device 1600, which may combine or otherwise utilize one or more of the techniques described herein, may be used in a wide range of fields. For example, the system or device 1600 may be used as part of the hardware of a system such as a desktop computer 1610, a laptop computer 1620, a tablet computer 1630, a cellular or mobile phone 1640, or a television 1650 (or a set-top box coupled to a television).

[0125] Similarly, the disclosed elements can be used in a wearable device 1660, such as a smart watch or a health monitoring device. In many embodiments, a smart watch can implement a variety of different functions—for example, access to email, cellular service, calendar, health monitoring, etc. A wearable device can also be designed to perform only health monitoring functions, such as monitoring a user's vital signs, performing epidemiological functions such as contact tracing, providing communications to emergency medical services, etc. Other types of devices are also contemplated, including devices worn around the neck, devices implantable in the human body, glasses or helmets designed to provide computer-generated reality experiences, such as those based on augmented reality and / or virtual reality, etc.

[0126] The system or device 1600 may also be used in various other environments. For example, the system or device 1600 may be used in the context of a server computer system (such as a dedicated server) or on shared hardware that implements a cloud-based service 1670. Further, the system or device 1600 may be implemented in a wide range of dedicated everyday devices, including devices 1680 common in the home, such as refrigerators, thermostats, security cameras, etc. The interconnection of such devices is generally referred to as the "Internet of Things" (IoT). Elements may also be implemented in various modes of transportation. For example, the system or device 1600 may be used for control systems, guidance systems, entertainment systems, etc. of various types of vehicles 1690.

[0127] Fig.16 The applications shown in are merely exemplary and are not intended to limit potential future applications of the disclosed system or device. Other exemplary applications include, but are not limited to: portable gaming devices, music players, data storage devices, unmanned aerial vehicles, etc.

[0128] Fig.17 17 is a block diagram illustrating an example of a non-transitory computer-readable storage medium storing circuit design information according to some embodiments. In the illustrated embodiment, a semiconductor manufacturing system 1720 is configured to process design information 1715 stored on a non-transitory computer-readable storage medium 1710 and manufacture an integrated circuit 1730 based on the design information 1715.

[0129] The non-transitory computer-readable storage medium 1710 may include any of a variety of suitable types of memory devices or storage devices. The non-transitory computer-readable storage medium 1710 may be an installation medium, such as a CD-ROM, a floppy disk, or a tape device; a computer system memory or random access memory such as DRAM, DDR RAM, SRAM, EDO RAM, Rambus RAM, etc.; a non-volatile memory such as flash memory, a magnetic medium, for example, a hard drive or an optical storage device; a register or other similar type of memory element, etc. The non-transitory computer-readable storage medium 1710 may also include other types of non-transitory memories or combinations thereof. The non-transitory computer-readable storage medium 1710 may include two or more memory media that may reside in different locations, such as different computer systems connected by a network.

[0130] Design information 1715 may be specified using any of a variety of suitable computer languages, including hardware description languages ​​such as, but not limited to, VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, etc. Design information 1715 can be used by semiconductor manufacturing system 1720 to manufacture at least a portion of integrated circuit 1730. The format of design information 1715 can be recognized by at least one semiconductor manufacturing system such as, for example, semiconductor manufacturing system 1720. In some embodiments, design information 1715 may include a netlist specifying elements of a cell library and their connectivity. One or more cell libraries used during logic synthesis of circuits included in integrated circuit 1730 may also be included in design information 1715. Such cell libraries may include information indicating device or transistor level netlists, mask design data, characterization data, etc. of cells included in the cell library.

[0131] In various embodiments, integrated circuit 1730 may include one or more custom macrocells, such as memory, analog or mixed signal circuits, etc. In this case, design information 1715 may include information related to the included macrocells. Such information may include, but is not limited to, a schematic capture database, mask design data, behavioral models, and device or transistor level netlists. As used herein, mask design data may be formatted according to a graphic data system (GDSII) or any other suitable format.

[0132] Semiconductor manufacturing system 1720 may include any of a variety of suitable elements configured to manufacture integrated circuits. This may include, for example, elements for depositing semiconductor material (e.g., on a wafer that may include a mask), removing material, changing the shape of deposited material, modifying material (e.g., by doping the material or using ultraviolet treatment to modify the dielectric constant), etc. Semiconductor manufacturing system 1720 may also be configured to perform various tests of the manufactured circuits for proper operation.

[0133] In various embodiments, integrated circuit 1730 is configured to operate according to the circuit design specified by design information 1715, which may include performing any of the functions described herein. For example, integrated circuit 1730 may include any of the various elements shown or described herein. In addition, integrated circuit 1730 may be configured to perform various functions described herein in conjunction with other components. In addition, the functionality described herein may be performed by multiple connected integrated circuits.

[0134] As used herein, a phrase of the form "design information specifying a design of a circuit configured to..." does not imply that the circuit under consideration must be manufactured to satisfy the element. Rather, the phrase indicates that the design information describes a circuit that, when manufactured, will be configured to perform the indicated actions or will include the specified components.

[0135] ***

[0136] The present disclosure includes references to "embodiments," which are non-limiting, specific implementations of the disclosed concepts. References to "an embodiment," "one embodiment," "a specific embodiment," "some embodiments," "various embodiments," etc., do not necessarily refer to the same embodiment. A large number of possible embodiments are contemplated, including the specific embodiments described in detail, as well as modifications or alternatives that fall within the spirit or scope of the present disclosure. Not all of these embodiments will necessarily exhibit any or all of the potential advantages described herein.

[0137] Unless otherwise stated, the specific embodiments are not intended to limit the scope of the claims drafted based on the disclosure of the disclosed form, even if only a single example is described for a particular feature. Therefore, the embodiments disclosed by the present invention are intended to be illustrative rather than restrictive, without any contrary statement. This patent application is intended to cover such alternatives, modifications and equivalent forms, which will be obvious to those skilled in the art who benefit from this disclosure.

[0138] The particular features, structures or characteristics may be combined in any suitable manner consistent with the present disclosure. Accordingly, the present disclosure is intended to include any feature or combination of such features disclosed herein (explicitly or implicitly), or any generalization thereof. Accordingly, new claims may be made during the prosecution of this patent application (or a patent application claiming priority thereto) for any such combination of features. In particular, with reference to the appended claims, features of the dependent claims may be combined with features of the independent claims, and features from the corresponding independent claims may be combined in any suitable manner rather than merely by the specific combinations listed in the appended claims.

[0139] For example, although the appended dependent claims are drafted so that each dependent claim is dependent on a single other claim, additional dependencies are also contemplated. It is also contemplated that a claim drafted in one legal type (e.g., apparatus) may inspire a corresponding claim of another legal type (e.g., method), where appropriate.

[0140] ***

[0141] Because this disclosure is a legal document, various terms and phrases may be subject to regulatory and judicial interpretation. Notice is hereby given that the definitions provided in the following paragraphs and throughout this disclosure will be used to determine how to interpret claims drafted based on this disclosure.

[0142] Unless the context clearly dictates otherwise, references to singular forms such as “a,” “an,” and “the” are intended to mean “one or more.” Thus, reference to “an item” in a claim does not exclude additional instances of that item.

[0143] The word "may" is used herein in a permissive sense (ie, having the potential to, being able to), rather than the mandatory sense (ie, must).

[0144] The terms "including" and "comprising" and forms thereof are open ended and mean "including, but not limited to."

[0145] When the term "or" is used in this disclosure with respect to a list of options, it will generally be understood to be used in an inclusive sense unless the context provides otherwise. Thus, the expression "x or y" is equivalent to "x or y, or both," covering x but not y, y but not x, and both x and y. On the other hand, phrases such as "either, but not both, x or y" make it clear that "or" is used in an exclusive sense.

[0146] The expressions "w, x, y, or z, or any combination thereof" or "... at least one of w, x, y, and z" are intended to cover all possibilities involving a single element, up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. Thus, the phrase "... at least one of w, x, y, and z" refers to at least one element of the elements in the set [w, x, y, z], thereby covering all possible combinations in the list of options. The phrase should not be interpreted as requiring the presence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0147] In this disclosure, various "labels" may precede a noun. Unless the context provides otherwise, different labels used for a feature (e.g., "a first circuit," "a second circuit," "a particular circuit," "a given circuit," etc.) refer to different instances of the feature. Unless otherwise specified, the labels "first," "second," and "third" do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) when applied to a particular feature.

[0148] Within the present disclosure, different entities (which may be variously referred to as "units," "circuits," other components, etc.) may be described or claimed as being "configured to" perform one or more tasks or operations. This expression—[an entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a physical thing). More specifically, this expression is used to indicate that this structure is arranged to perform one or more tasks during operation. A structure may be said to be "configured to" perform a task even if the structure is not currently being operated. Thus, an entity described or stated as "configured to" perform a task refers to a physical thing used to implement the task, such as a device, a circuit, a memory storing executable program instructions, and the like. The phrase is not used herein to refer to an intangible thing.

[0149] The term "configured to" is not intended to mean "configurable to." For example, an unprogrammed FPGA would not be considered "configured to" perform a particular function. However, the unprogrammed FPGA may be "configurable to" perform that function.

[0150] The phrase "configured to" perform one or more tasks in the appended claims is expressly intended not to invoke 35 U.S.C. §112(f) for that claim element. If the applicant wishes to invoke section 112(f) during prosecution, it will use the phrase "means for [performing the function]" to describe the claim element.

[0151] The phrase "based on" is used to describe one or more factors that influence a determination. This term does not exclude that there may be additional factors that may influence the determination. That is, the determination may be based only on the specified factors or on the specified factors and other unspecified factors. Consider the phrase "A is determined based on B." This phrase specifies that B is a factor used to determine A or that B influences the determination of A. This phrase does not exclude that the determination of A may also be based on some other factor such as C. This phrase is also intended to cover embodiments in which A is determined based only on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0152] The phrase "in response to" describes one or more factors that trigger an effect. The phrase does not exclude the possibility that other factors may influence or otherwise trigger the effect. That is, the effect may be responsive only to those factors, or may be responsive to the specified factors as well as other unspecified factors. Consider the phrase "in response to B, A is performed." The phrase specifies that B is the factor that triggers the performance of A. The phrase does not exclude that the performance of A may also be responsive to some other factor, such as C. The phrase is also intended to cover embodiments in which A is performed only in response to B.

Claims

1. A device, comprising: a first phase circuit included on a first integrated circuit, wherein the first phase circuit is configured to activate a first driver circuit coupled to a regulated power supply node via a first inductor using a first phase clock signal, wherein the first driver circuit is included on the first integrated circuit, and wherein the first driver circuit is configured to provide a first current to the regulated power supply node during a first on-time period; and a second phase circuit included on the first integrated circuit, wherein the second phase circuit is configured to activate a second drive circuit coupled to the regulated power supply node via a second inductor using a second phase clock signal, wherein the second drive circuit is included on the second integrated circuit, and wherein the second drive circuit is configured to provide a second current to the regulated power supply node during a second on-time period. 2 . The apparatus of claim 1 , further comprising a master control circuit included on the first integrated circuit and configured to generate the first phase clock signal and the second phase clock signal.

3. The apparatus according to claim 1, further comprising: The second driver circuit is included on the second integrated circuit.

4. The apparatus of claim 1 , further comprising a third driver circuit included on the first integrated circuit and coupled to the second phase circuit, wherein the second phase circuit is further configured to disable at least a portion of the third driver circuit based on an enable signal. 5 . The apparatus of claim 4 , wherein the second phase circuit is configured to activate the second drive circuit via the third drive circuit. 6 . The apparatus of claim 4 , further comprising a master control circuit included on the first integrated circuit and configured to generate the first phase clock signal, the second phase clock signal, and the enable signal.

7. A method comprising: selecting, by a first phase circuit and based on a driver enable signal, between a first driver circuit and a second driver circuit for providing a first current to a regulated power supply node, wherein the first phase circuit and the first driver circuit are included on a first integrated circuit and the second driver circuit is included on a second integrated circuit; activating the selected first drive circuit or the second drive circuit using a first phase enable signal by the first phase circuit to provide the first current to the regulated power supply node during a first on-time period; as well as A third driver circuit is activated by a second phase circuit using a second phase enable signal to provide a second current to the regulated power supply node during a second on-time period, wherein the second phase circuit and the third driver circuit are included on the first integrated circuit.

8. The method according to claim 7, wherein: The driver enable signal has a first value; and Selecting between the first drive circuit and the second drive circuit includes generating a first control signal to activate the first drive circuit.

9. The method according to claim 7, wherein: The driver enable signal has a second value; and Selecting between the first drive circuit and the second drive circuit includes generating a second control signal to activate the second drive circuit.

10. The method according to claim 7, further comprising: The first phase enable signal, the second phase enable signal, and the driver enable signal are generated by a main control circuit included on the first integrated circuit.

11. The method according to claim 9, wherein: Activating the selected first drive circuit or the second drive circuit includes activating the second drive circuit; and Activating the second drive circuit includes buffering the second control signal using a buffer circuit. 12 . The method of claim 7 , wherein selecting between the first driver circuit and the second driver circuit comprises using a selection control circuit to generate a first control signal or a second control signal based on the driver enable signal.

13. The method according to claim 7, wherein: activating the first drive circuit to provide the first current and activating the third drive circuit to provide the second current includes using a first power supply node; as well as Activating the second drive circuit to provide the first current includes using a second power supply node.

14. A device, comprising: a main control circuit configured to selectively activate a plurality of phase circuits, wherein the main control circuit and the plurality of phase circuits are included on a first integrated circuit, and wherein the plurality of phase circuits include: a first phase circuit configured to activate a first driver circuit coupled to a regulated power supply node via a first inductor using a first phase clock signal, wherein the first driver circuit is included on the first integrated circuit, and wherein the first drive circuit is configured to provide a first current to the regulated power supply node during a first on-time period; and a second phase circuit configured to activate a second driver circuit coupled to the regulated power supply node via a second inductor using a second phase clock signal, wherein the second driver circuit is included on a second integrated circuit, And wherein the second drive circuit is configured to provide a second current to the regulated power supply node during a second on-time period.

15. The apparatus of claim 14, wherein the first drive circuit is coupled to a first power supply node, and wherein the second drive circuit is coupled to a second power supply node.

16. The apparatus of claim 15, wherein the main control circuit and the plurality of phase circuits are coupled to the first power supply node. 17 . The apparatus of claim 15 , wherein a voltage level of the second power supply node is greater than a voltage level of the first power supply node.

18. The apparatus of claim 15, wherein the second phase circuit is further coupled to a second internal driver circuit included on the first integrated circuit, and wherein the second phase circuit is further configured to disable the second internal driver circuit based on an enable signal.

19. The apparatus according to claim 15, wherein the main control circuit is configured to: generating a plurality of phase clock signals using a clock signal, the plurality of phase clock signals including the first phase clock signal and the second phase clock signal; and A reference voltage level is generated using the voltage level of the first power supply node.

20. A method comprising: activating a first driver circuit using a first phase enable signal by a first phase circuit of a plurality of phase circuits, wherein the plurality of phase circuits and the first driver circuit are included on a first integrated circuit; activating a second driver circuit using a second phase enable signal by a second phase circuit of the plurality of phase circuits, wherein the second driver circuit is included on a second integrated circuit; In response to being activated, providing a first current to a regulated power supply node by the first drive circuit during a first on-time period; as well as In response to being activated, a second current is provided by the second drive circuit to the regulated power supply node during a second on-time period.

21. The method of claim 20, wherein the first driver circuit is coupled to a first power supply node, and wherein the second driver circuit is coupled to a second power supply node.

22. The method of claim 21, wherein the plurality of phase circuits are coupled to the first power supply node.

23. The method of claim 21, wherein a voltage level of the second power supply node is greater than a voltage level of the first power supply node.

24. The method of claim 21, wherein the second phase circuit is further coupled to a third driver circuit included on the first integrated circuit, and further comprising disabling, by the second phase circuit, the third driver circuit based on a driver enable signal.

25. The method according to claim 24, further comprising: generating the first phase enable signal and the second phase enable signal by a main control circuit, wherein the main control circuit is included on the first integrated circuit; generating, by the master control circuit, the driver enable signal based on a load current drawn from the regulated power supply node; as well as A reference voltage level is generated by the main control circuit using the voltage level of the first power supply node.

26. The method of claim 25, wherein providing the first current to the regulated power supply node comprises comparing the reference voltage level to a voltage level of the regulated power supply node.

27. An apparatus, comprising: a first integrated circuit, the first integrated circuit comprising a first plurality of driver circuits, the first plurality of driver circuits comprising a first driver circuit coupled to a regulated power supply node via a first inductor, wherein the first driver circuit is configured to provide a first current to the regulated power supply node during a first on-time period; and A second integrated circuit, the second integrated circuit comprising: a second plurality of driver circuits, the second plurality of driver circuits comprising a second driver circuit coupled to the regulated supply node via a second inductor, wherein the second driver circuit is configured to provide a second current to the regulated supply node during a second on-time period; a first phase circuit configured to activate the first drive circuit using a first phase enable signal; and A second phase circuit is configured to activate the second drive circuit using a second phase enable signal.

28. The apparatus of claim 27, wherein the first drive circuit is coupled to a first power supply node, and wherein the second drive circuit is coupled to a second power supply node.

29. The apparatus of claim 28, wherein the first phase circuit and the second phase circuit are coupled to the second power supply node.

30. The apparatus of claim 28, wherein a voltage level of the first power supply node is greater than a voltage level of the second power supply node.

31. The apparatus of claim 28, wherein the second integrated circuit further comprises a third phase circuit coupled to a third driver circuit of the first plurality of driver circuits and a fourth driver circuit of the second plurality of driver circuits, and wherein the third phase circuit is configured to disable the fourth driver circuit based on a driver enable signal.

32. The apparatus of claim 28, wherein the first inductor is included on the first integrated circuit, and wherein the second inductor is included on the second integrated circuit.

33. The apparatus of claim 28, wherein the second integrated circuit further comprises a main control circuit, the main control circuit being configured to: generating the first phase enable signal and the second phase enable signal using a clock signal; and A reference voltage level is generated using the voltage level of the second power supply node.

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