Instruction set processor for integer-to-floating-point number transmission and conversion fusion

Abstract

The invention relates to an instruction set processor for integer-to-floating-point number transmission and conversion fusion, and the processor comprises an instruction transmission control part which is used for transmitting instruction control information; the memory access execution component is used for generating target register write port information according to the instruction control information, generating instruction execution completion information and transmitting the information to the instruction submission component; the integer execution component is used for decoding the instruction control information to obtain first instruction execution control information and further reading an integer source operand from an integer register file; the floating point execution component is used for decoding the first instruction execution control information to obtain second instruction execution control information, converting the integer source operand into a floating point number according to the second instruction execution control information, and writing the floating point number into a floating point register file, and abnormal coding information is generated according to the abnormal state generated in the conversion process and is transmitted to the instruction submitting component. According to the invention, the processing efficiency of the processor on integer-to-floating-point number transmission and conversion can be improved.

Description

Technical Field

[0001] The invention relates to the field of processor design, and in particular to an instruction set processor for integrating transmission and conversion from integer to floating point. Background Art

[0002] In a processor, integers are usually stored in a memory or integer registers, and floating-point numbers are usually stored in a memory or floating-point registers. When a modern processor microstructure is implemented, an independent integer register file and a floating-point register file are usually set. Integer operations mainly operate on integer registers, and floating-point operations mainly operate on floating-point registers. In order to save the number of read and write ports of the register file, a direct read and write transmission path between the integer and floating-point register files is usually not directly provided, but is implemented by borrowing other data paths. If a floating-point operation instruction needs to use an integer in an integer register, multiple instructions are required to implement it. Usually, an integer-to-floating-point transmission instruction is required to first transfer the integer in the integer register to the floating-point register, and then an integer-to-floating-point instruction is used to convert the integer stored in the floating-point register into a floating-point number. In such a transmission and conversion method, at least two instructions are required to realize the transmission and conversion between floating-point numbers and integers, which not only wastes the instruction processing resources of the instruction component in the processor and reduces the instruction processing efficiency, but also requires reading the register twice and writing the register twice, which significantly increases the execution delay of data transmission and conversion, which is not conducive to the improvement of the processor's computing performance. In order to improve processor performance, it is necessary to explore a method to speed up the transmission and conversion of integers to floating-point numbers. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide an instruction set processor that integrates integer-to-floating-point number transmission and conversion, which can improve the processing efficiency of the processor for integer-to-floating-point number transmission and conversion.

[0004] The technical solution adopted by the present invention to solve the technical problem is: to provide an instruction set processor for integrating transmission and conversion of integers to floating points, including:

[0005] An instruction transmission control component, used for sending instruction control information of the integer-to-floating-point transmission conversion instruction to a corresponding execution component;

[0006] A memory access execution unit, used to generate target register write port information according to the instruction control information, generate instruction execution completion information and pass it to the instruction submission unit;

[0007] an integer execution unit, configured to decode the instruction control information to obtain first instruction execution control information, and read an integer source operand from an integer register file according to the first instruction execution control information;

[0008] A floating-point execution unit is used to decode the first instruction execution control information to obtain the second instruction execution control information, and then convert the integer source operand into a floating-point number according to the second instruction execution control information, and generate exception coding information according to the exception state generated during the conversion process, and then write the converted floating-point number result into a floating-point register file according to the write port control information, and pass the exception coding information to the instruction submission unit.

[0009] Furthermore, the integer execution component includes:

[0010] A first decoder, used for decoding the instruction control information to obtain the first instruction execution control information;

[0011] The read integer register control module is used to generate read port control information of the integer register file according to the first instruction execution control information, and read the integer source operand from the integer register file according to the read port control information.

[0012] Furthermore, the floating-point execution unit includes:

[0013] A second decoder, used for decoding the first instruction execution control information to obtain second instruction execution control information;

[0014] A floating point control status register, used to set a floating point exception trap control bit, a rounding mode control bit, and a floating point exception status bit according to an exception status during the conversion process from an integer to a floating point number;

[0015] an integer to floating point transmission conversion subcomponent, configured to convert the integer source operand into a floating point number according to the second instruction execution control information, the floating point exception trap control bit and the rounding mode control bit to obtain the floating point result, and to generate exception coding information according to an exception state in the conversion process and transmit it to the instruction submission component;

[0016] The floating-point register write control module is used to write the floating-point number result into the floating-point register file according to the write port control information.

[0017] Furthermore, the floating-point exception trap control bit is used to set a processing strategy when an exception occurs during the integer-to-floating-point conversion process, the rounding mode control bit is used to set the result rounding mode of the integer-to-floating-point conversion, and the floating-point exception status bit is used to record the exception status that occurs during the integer-to-floating-point conversion process.

[0018] Further, the integer to floating point number transmission conversion subcomponent includes:

[0019] A third decoder, configured to decode the second instruction execution control information to obtain third instruction execution control information, wherein the third instruction execution control information includes an instruction type, an integer format to be converted, a floating point format after conversion, and a result rounding mode;

[0020] A complementer for converting a negative signed integer to be converted into a positive number;

[0021] A selector, for selecting the data generated by the complementer when the signed integer to be converted is a negative number, and otherwise selecting the integer to be converted whose data bit width is extended to a set bit width as data for subsequent operations;

[0022] A leading zero detector, used to detect the number of leading zeros of the data generated by the selector and determine the initial exponent value of the floating point number after transmission conversion;

[0023] A shifter, used for performing a left shift operation on the data generated by the selector according to the number of leading zeros, so as to form an initial value of the mantissa of the floating-point number after transmission conversion;

[0024] A rounding module, which performs a rounding operation on the mantissa initial value generated by the shifter according to the converted floating-point format and the result rounding mode, corrects the exponent initial value generated by the leading zero detector, generates a converted floating-point result, and detects abnormal coding information in the conversion process;

[0025] A result selector is configured to select and output the floating point result or the exception coding information according to the third instruction execution control information.

[0026] Furthermore, the abnormal coding information includes:

[0027] An inexact result exception is used to indicate that the true values ​​of the to-be-transmitted conversion integer and the floating-point result are not equal;

[0028] A floating point overflow exception is used to indicate that the value of the converted integer to be transmitted exceeds the representation range of the converted floating point format.

[0029] Furthermore, the conversion integers to be transmitted include 64-bit unsigned longword integers, 32-bit unsigned word integers, 16-bit unsigned halfword integers, and 64-bit signed longword integers, 32-bit signed word integers and 16-bit signed halfword integers represented in complement code; the integer register file includes a plurality of 64-bit integer registers, each of which stores one of the conversion integers to be transmitted as a 64-bit integer source operand, wherein the unsigned word integer is stored in the lower 32 bits of the integer register and the upper 32 bits are padded with zeros, the signed word integer is stored in the lower 32 bits of the integer register and the upper 32 bits are extended according to the sign bit, the unsigned halfword integer is stored in the lower 16 bits of the integer register and the upper 48 bits are padded with zeros, and the signed halfword integer is stored in the lower 16 bits of the integer register and the upper 48 bits are extended according to the sign bit.

[0030] Furthermore, the instruction control information of the integer-to-floating-point transfer conversion instruction is sent by the integer storage instruction data transmitting port STD.

[0031] Furthermore, the integer-to-floating-point transfer conversion instruction reuses the same integer storage instruction data emission port STD of the instruction emission control unit, the same load instruction completion port of the instruction submission unit, and the same read port, data line and address line of the integer register file with the integer-to-floating-point transfer instruction and the integer storage data instruction; the integer-to-floating-point transfer conversion instruction reuses the data path from the integer execution unit to the floating-point execution unit with the integer-to-floating-point transfer instruction; the integer-to-floating-point transfer conversion instruction reuses the same write port, data line and address line of the floating-point register file with the integer-to-floating-point transfer instruction and the floating-point load instruction.

[0032] Furthermore, the floating-point register file includes a plurality of 64-bit floating-point registers, each of which stores a double-precision floating-point number, two single-precision floating-point numbers, or four half-precision floating-point numbers, and each of the double-precision floating-point number, the single-precision floating-point number, and the half-precision floating-point number can be used separately, and the half-precision floating-point number includes FP16 half-precision floating-point number and BF16 half-precision floating-point number.

[0033] Beneficial Effects

[0034] Due to the adoption of the above technical solution, the present invention has the following advantages and positive effects compared with the prior art:

[0035] (1) The present invention integrates the functions of the original integer-to-floating-point transmission instruction and the integer-to-floating-point conversion instruction, without adding new data paths, integer register read ports, and floating-point register write ports. The transmission and conversion of integers to floating-point numbers can be realized with one instruction, thereby expanding the functions of a single instruction, accelerating the execution speed of the transmission and conversion of integers to floating-point numbers in the processor, and thus improving the processor performance;

[0036] (2) The integer-to-floating-point transfer conversion instruction proposed by the present invention saves processor instruction processing resources, increases instruction processing efficiency, and does not require reading and writing registers twice, so that the execution delay of the transfer conversion operation is less than the sum of the execution delays of the original transfer instruction and the conversion instruction, which is conducive to speeding up the execution speed and thus improving the computing performance of the processor;

[0037] (3) The present invention not only supports the transmission and conversion of long-word integers and word integers into double-precision floating-point numbers and single-precision floating-point numbers, but also supports the transmission and conversion of word integers and half-word integers into half-precision floating-point numbers. The same conversion circuit is reused for the conversion of different data formats, which not only saves hardware overhead, but also helps to improve the applicability of the processor in emerging fields such as artificial intelligence. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a schematic structural diagram of an embodiment of the present invention;

[0039] Figure 2 It is a structural schematic diagram of an integer-to-floating-point number transmission conversion subcomponent according to an embodiment of the present invention. DETAILED DESCRIPTION

[0040] The present invention will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention. In addition, it should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms fall within the scope limited by the appended claims of the application equally.

[0041] The embodiment of the present invention relates to an instruction set processor for fusion of integer to floating point number transfer and conversion, such as Figure 1 As shown, including:

[0042] The instruction unit (101) includes an internal first-level instruction cache and its access control, which is used to obtain instructions from the instruction cache or the next-level cache or even the main memory, and decode the obtained instructions;

[0043] An instruction emission control unit (102), including register renaming and emission control, is used to implement mapping of all instruction logic registers to physical registers, correlation detection and emission control, and multiple emission ports are set for different instruction types, corresponding to different execution units;

[0044] An integer storage instruction data emission queue (103) is used to control and emit integer storage (Store) instruction data and integer to floating point number transmission conversion instructions, wherein the storage (Store) instruction address and data emission are separated, the storage (Store) instruction address is emitted and executed through the memory access instruction address calculation emission queue, and the storage (Store) instruction data is emitted and executed through a special data emission queue;

[0045] An integer register file (104) is used to store integer source operands and operation results. A plurality of read ports are set to provide source operands for integer operations; a plurality of write ports are set to allow integer operations or integer load instructions to write back register results; the component comprises 32 integer registers, each of which has a bit width of 64 bits. Unsigned word integers are stored in the lower 32 bits of the integer register, and the upper 32 bits are padded with zeros for extension; signed word integers are stored in the lower 32 bits of the integer register, and the upper 32 bits are extended according to the sign bit; unsigned half-word integers are stored in the lower 16 bits of the integer register, and the upper 48 bits are padded with zeros for extension; signed half-word integers are stored in the lower 16 bits of the integer register, and the upper 48 bits are extended according to the sign bit;

[0046] The integer execution unit (105) is used to receive instruction execution requests, read source operands from the integer register file (104) or receive data input from other units, perform operations according to the instructions, obtain execution results and write them back to the integer register file (104) or output them to other units, and pass instruction execution completion information to the instruction submission unit (115). The instruction submission unit (115) is often called ROB (Reorder Buffer);

[0047] A first decoder (106), configured to decode the received instruction and generate control information for executing the instruction;

[0048] A read integer register control module (107), used to generate read port control information of the integer register file (104) according to the instruction execution control information, including read enable and read register number, and bypass selection control signal, etc.;

[0049] The memory access execution unit (108) is used to process the memory access instruction from the instruction emission control unit (102), complete the memory access address calculation, access the internal first-level data cache, determine whether the data cache is hit, and if it is not hit, further generate a request to access the next-level cache or main memory, and submit the instruction execution completion information to the instruction submission unit (115); for the integer to floating-point transmission instruction, the transmission and conversion fusion instruction, it is not necessary to perform address calculation or access the data cache, but only to receive the instruction execution request, receive the data input by other components or read the source operand from the floating-point register file (114), perform the operation according to the instruction, obtain the execution result and write it back to the floating-point register file (114) or output it to other components, and pass the instruction execution completion information to the instruction submission unit (115); wherein, the instruction submission and the register file write back are completed by borrowing the memory access instruction execution completion interface and the Load instruction write floating-point register file write port;

[0050] A floating point execution unit (109), used to receive instruction execution requests, receive data input from other units or read source operands from a floating point register file (114), perform calculation operations according to the instructions, obtain execution results and write them back to the floating point register file (114) or output them to other units, and pass instruction execution completion information to an instruction submission unit (115);

[0051] A second decoder (110) is used to further decode the received floating-point operation instruction and generate control information required for executing the floating-point instruction;

[0052] A floating-point control status register (111), including information such as a floating-point exception status bit, a rounding mode bit, a floating-point exception self-trap control bit, and a control bit of special data, is also called FPCR (Floating-Point Control Register); when converting an integer to a floating-point number, the result needs to be rounded according to the floating-point rounding mode bit; if an exception occurs during the conversion from an integer to a floating-point number, exception coding information needs to be generated, the exception status bit of the FPCR needs to be registered, and whether an arithmetic self-trap is generated is determined according to the floating-point exception self-trap control bit, and software processing is entered;

[0053] The integer to floating point transmission conversion subunit (112) is used to convert the integer transmitted by the integer execution unit (105) into a floating point output according to the instruction execution control information generated by the second decoder (110) and the status information of the floating point control status register (111), and to process the exception information and generate the exception code of the execution result; wherein, if the real value of the integer to be transmitted and converted is not equal to the real value of the floating point number after the transmission conversion, the instruction of the integer to floating point transmission conversion will generate an inexact result exception; if the value of the integer to be converted exceeds the representable range of the floating point format after the conversion, the instruction of the integer to floating point transmission conversion will generate a floating point overflow exception;

[0054] A floating-point register writing control module (113) is used to select, according to the instruction control information, to write the execution result of the integer-to-floating-point number transfer conversion instruction, the integer-to-floating-point number transfer instruction or the floating-point loading instruction into the floating-point register file (114);

[0055] A floating-point register file (114) is used to store floating-point source operands and operation results. A plurality of read ports are provided to provide source operands for floating-point operations, and a plurality of write ports are provided to allow floating-point operations or floating-point load instructions to write back register results. The component includes 32 floating-point registers, each of which has a bit width of 64 bits and can store a double-precision floating-point number, two single-precision floating-point numbers, or four half-precision floating-point numbers. An instruction can also use only one single-precision floating-point number (lower 32 bits) or one half-precision floating-point number (lower 16 bits) each time.

[0056] The instruction submitting unit (115) is used to receive instruction completion information submitted by the integer, floating point or memory access execution unit, and complete the exit of the instruction according to the program sequence.

[0057] The instruction set processor supports the instruction set of integer to floating point transfer and conversion fusion, which is used to implement the transfer of integers in integer registers and convert them into floating point numbers in floating point registers. The source register of this instruction set is an integer register, the source operand is an integer, the target register is a floating point register, and the execution result is a floating point number.

[0058] The specific instructions are shown in Table 1:

[0059] Table 1 An instruction set for fusion of integer to floating point transfer and conversion

[0060] Serial number Instruction mnemonics Instruction Description Instruction Format 1 CMOVLD Signed longword integer transfer to double precision floating point instruction CMOVLDRa.rl,Fb.wd 2 CMOVLS Signed longword integer transfer conversion to single-precision floating-point instruction CMOVLSRa.rl,Fb.ws 3 CMOVULD Unsigned longword integer transfer to double precision floating point instruction CMOVULDRa.rl,Fb.wd 4 CMOVULS Unsigned longword integer transfer conversion to single-precision floating point instruction CMOVULSRa.rl,Fb.ws 5 CMOVWD Signed integer transfer to double precision floating point instruction CMOVWDRa.rw,Fb.wd 6 CMOVWS Signed integer transfer to single precision floating point instruction CMOVWSRa.rw,Fb.ws 7 CMOVUWD Unsigned integer word transfer to double precision floating point instruction CMOVUWDRa.rw,Fb.wd 8 CMOVUWS Unsigned integer word transfer to single precision floating point instruction CMOVUWSRa.rw,Fb.ws 9 CMOVWHF Signed integer transfer conversion to half-precision floating point instruction CMOVWHFRa.rw,Fb.wh 10 CMOVUWHF Unsigned integer word transfer conversion to half-precision floating point instruction CMOVUWHFRa.rw,Fb.wh 11 CMOVHHF Signed half-word integer transfers are converted to half-precision floating-point instructions CMOVHHFRa.rh,Fb.wh 12 CMOVUHHF Unsigned half-word integer transfer converted to half-precision floating point instruction CMOVUHHFRa.rh,Fb.wh

[0061] Among them, signed integers are represented and stored in 2's complement, and unsigned integers are represented in original code. The integers to be converted include unsigned long word integers, unsigned word integers, unsigned half word integers, and signed long word integers, signed word integers, and signed half word integers represented in 2's complement; the floating point numbers to be generated include double-precision floating point numbers, single-precision floating point numbers, FP16 half-precision floating point numbers, and BF16 half-precision floating point numbers, wherein the double-precision floating point number includes 1 sign bit (S), 11-bit exponent (E), and 52-bit mantissa (F), the single-precision floating point number includes 1 sign bit (S), 8-bit exponent (E), and 23-bit mantissa (F), the FP16 half-precision floating point number includes 1 sign bit (S), 5-bit exponent (E), and 10-bit mantissa (F), and the BF16 half-precision floating point number includes 1 sign bit (S), 8-bit exponent (E), and 7-bit mantissa (F).

[0062] The instructions for fusion of integer to floating point transfer and conversion support the four rounding modes defined by the IEEE-754 floating point standard: round to nearest, round to zero, round to positive infinity, and round to negative infinity. The rounding mode can be directly determined by the instruction encoding or dynamically controlled by the rounding mode control bit in the FPCR.

[0063] Integer to floating point transfer conversion instructions are performed by the following components:

[0064] The integer storage instruction transmission port of the integer storage instruction data transmission queue (103) in the instruction transmission control unit (102) transmits the integer to floating point number transmission conversion instruction, and the instruction control information is sent to the memory access execution unit (108) and the integer execution unit (105) at the same time;

[0065] The memory access execution unit (108) generates execution completion information of the integer to floating point transfer conversion instruction according to the instruction control information, and transmits it to the instruction submission unit (115), and at the same time generates target register write port control information, and transmits it to the floating point execution unit (109);

[0066] The integer execution unit (105) reads the source operand in the integer register file (104) according to the instruction control information, and transmits the read data and the instruction control information to the floating point execution unit (109);

[0067] The integer-to-floating-point transmission conversion subunit (112) in the floating-point execution unit (109) completes integer-to-floating-point conversion and exception processing under the control of instruction control information and a floating-point control status register (111), generates a converted floating-point result and an exception code, and passes the exception code to an instruction submission unit (115); the floating-point register write control module (113) selects to write the execution result of the integer-to-floating-point transmission conversion instruction, the integer-to-floating-point transmission instruction or the floating-point load instruction into a floating-point register file (114) according to the instruction control information.

[0068] The integer-to-floating-point transfer conversion instruction, the integer-to-floating-point transfer instruction, and the integer storage instruction reuse the same instruction issuance port of the instruction issuance control unit (102), and the same instruction completion port of the multiplexing instruction submission unit (115); the integer-to-floating-point transfer conversion instruction, the integer-to-floating-point transfer instruction, and the integer storage instruction reuse the same read port, data line, and address line of the integer register file (104); the integer-to-floating-point transfer conversion instruction and the integer-to-floating-point transfer instruction reuse the data transmission line from the integer execution unit (105) to the floating-point execution unit (109); the integer-to-floating-point transfer conversion instruction, the integer-to-floating-point transfer instruction, and the floating-point load instruction reuse the same write port, data line, and address line of the floating-point register file (114).

[0069] Considering that the representation ranges of signed half-word integers and signed word integers are both subsets of signed long-word integers, the signed half-word integers and signed word integers can be expanded into signed long-word integers according to the sign bit during the conversion process, and then the conversion circuit of the signed long-word integer can be reused to implement it; similarly, the representation ranges of unsigned half-word integers and unsigned word integers are both subsets of unsigned long-word integers, and the unsigned half-word integers and unsigned word integers can be expanded into unsigned long-word integers during the conversion process, and then the conversion circuit of the unsigned long-word integer can be reused to implement it; and because the conversion of signed long-word integers into floating-point numbers is mainly compared with the conversion of unsigned long-word integers into floating-point numbers, there is only one more process of calculating the absolute value, therefore, the instructions for the transfer and conversion of integers to floating-point numbers can reuse the same set of conversion circuits, such as Figure 2 As shown, the integer to floating point transfer conversion subcomponent (112) includes:

[0070] A decoder (201) decodes the instruction execution control information to determine the instruction type, the integer data format to be transmitted and converted, the data format after the transmission conversion, and the rounding mode encoding;

[0071] A complementer (202) performs a complement operation by taking the inversion and then adding 1, thereby converting the signed negative integer to be converted into a positive number, and the bit width of the complementer (202) is 64 bits;

[0072] A selector (203) selects the data generated by the complementer (202) if the signed integer to be converted is a negative number, and otherwise selects the integer to be converted with a data bit width extended to 64 bits as data for subsequent operations;

[0073] A leading zero detector (204) detects the number of leading zeros of the data generated by the selector (203) and determines the initial exponent value of the floating point result after transmission conversion;

[0074] A shifter (205) performs a left shift operation on the data generated by the selector (203) according to the number of leading zeros generated by the leading zero detector (204) to form an initial value of the mantissa of the floating point number after transmission conversion, and the bit width of the shifter (205) is 64 bits;

[0075] A rounding module (206) performs a rounding operation on the mantissa initial value generated by the shifter (205) according to the data format and rounding mode code after the transmission conversion generated by the decoder (201), corrects the exponent initial value generated by the leading zero detector (204), detects abnormal conversion results, and generates a floating point number result after conversion and abnormal result information;

[0076] The result selector (207) selects the converted floating point number or the abnormal result to be output as a result according to the instruction execution control information generated by the decoder (201), and outputs the corresponding abnormal code.

[0077] With reference to this embodiment, the present invention can be used in various types of processors, which may be a general-purpose CPU, a GPU, or a dedicated processor.

Claims

1. An instruction set processor for fusion of integer to floating point number transfer and conversion, characterized in that: include: An instruction transmission control component, used for sending instruction control information of the integer-to-floating-point transmission conversion instruction to a corresponding execution component; A memory access execution unit, used to generate target register write port information according to the instruction control information, generate instruction execution completion information and pass it to the instruction submission unit; an integer execution unit, configured to decode the instruction control information to obtain first instruction execution control information, and read an integer source operand from an integer register file according to the first instruction execution control information; A floating-point execution unit is used to decode the first instruction execution control information to obtain the second instruction execution control information, and then convert the integer source operand into a floating-point number according to the second instruction execution control information, and generate exception coding information according to the exception state generated during the conversion process, and then write the converted floating-point number result into a floating-point register file according to the write port control information, and pass the exception coding information to the instruction submission unit.

2. The processor according to claim 1, characterized in that The integer execution unit comprises: A first decoder, used for decoding the instruction control information to obtain the first instruction execution control information; The read integer register control module is used to generate read port control information of the integer register file according to the first instruction execution control information, and read the integer source operand from the integer register file according to the read port control information.

3. The processor according to claim 1, wherein: The floating point execution unit comprises: A second decoder, used for decoding the first instruction execution control information to obtain second instruction execution control information; A floating point control status register, used to set a floating point exception trap control bit, a rounding mode control bit, and a floating point exception status bit according to an exception status during the conversion process from an integer to a floating point number; an integer to floating point transmission conversion subcomponent, configured to convert the integer source operand into a floating point number according to the second instruction execution control information, the floating point exception trap control bit and the rounding mode control bit to obtain the floating point result, and to generate exception coding information according to an exception state in the conversion process and transmit it to the instruction submission component; The floating-point register write control module is used to write the floating-point number result into the floating-point register file according to the write port control information.

4. The processor according to claim 3, characterized in that The floating point exception trap control bit is used to set a processing strategy when an exception occurs during the integer to floating point conversion process, the rounding mode control bit is used to set the result rounding mode of the integer to floating point conversion, and the floating point exception status bit is used to record the exception status that occurs during the integer to floating point conversion process.

5. The processor according to claim 3, characterized in that The integer to floating point transmission conversion subcomponent includes: a third decoder, used for decoding the second instruction execution control information to obtain third instruction execution control information, wherein the third instruction execution control information includes an instruction type, an integer format to be converted, a floating point format after conversion, and the result rounding mode; A complementer for converting a negative signed integer to be converted into a positive number; A selector, for selecting the data generated by the complementer when the signed integer to be converted is a negative number, and otherwise selecting the integer to be converted whose data bit width is extended to a set bit width as data for subsequent operations; A leading zero detector, used to detect the number of leading zeros of the data generated by the selector and determine the initial exponent value of the floating point number after transmission conversion; A shifter, used for performing a left shift operation on the data generated by the selector according to the number of leading zeros, so as to form an initial value of the mantissa of the floating-point number after transmission conversion; A rounding module, which performs a rounding operation on the mantissa initial value generated by the shifter according to the converted floating-point format and the result rounding mode, corrects the exponent initial value generated by the leading zero detector, generates a converted floating-point result, and detects abnormal coding information in the conversion process; A result selector is configured to select and output the floating point result or the exception coding information according to the third instruction execution control information.

6. The processor according to claim 5, characterized in that The abnormal coding information includes: An inexact result exception is used to indicate that the true values ​​of the to-be-transmitted conversion integer and the floating-point result are not equal; a floating-point overflow exception is used to indicate that the value of the to-be-transmitted conversion integer exceeds the representation range of the converted floating-point format.

7. The processor according to claim 1, characterized in that The conversion integers to be transmitted include 64-bit unsigned long word integers, 32-bit unsigned word integers, 16-bit unsigned half word integers, and 64-bit signed long word integers, 32-bit signed word integers and 16-bit signed half word integers represented in complement code; the integer register file includes a plurality of 64-bit integer registers, each of which stores one conversion integer to be transmitted as a 64-bit integer source operand, wherein the unsigned word integer is stored in the lower 32 bits of the integer register and the upper 32 bits are padded with zeros and extended, the signed word integer is stored in the lower 32 bits of the integer register and the upper 32 bits are extended according to the sign bit, the unsigned half word integer is stored in the lower 16 bits of the integer register and the upper 48 bits are padded with zeros and extended, and the signed half word integer is stored in the lower 16 bits of the integer register and the upper 48 bits are extended according to the sign bit.

8. The processor according to claim 1, wherein: The instruction control information of the integer-to-floating-point transfer conversion instruction is sent by the integer storage instruction data transmitting port STD.

9. The processor according to claim 1, wherein: The integer-to-floating-point transfer conversion instruction, the integer-to-floating-point transfer instruction and the integer storage data instruction reuse the same integer storage instruction data emission port STD of the instruction emission control unit, the same load instruction completion port of the instruction submission unit, and the same read port, data line and address line of the integer register file; the integer-to-floating-point transfer conversion instruction and the integer-to-floating-point transfer instruction reuse the data path from the integer execution unit to the floating-point execution unit; the integer-to-floating-point transfer conversion instruction, the integer-to-floating-point transfer instruction and the floating-point load instruction reuse the same write port, data line and address line of the floating-point register file.

10. The processor according to claim 1, wherein: The floating-point register file includes a plurality of 64-bit floating-point registers, each of which stores a double-precision floating-point number, two single-precision floating-point numbers, or four half-precision floating-point numbers, and each of the double-precision floating-point number, the single-precision floating-point number, and the half-precision floating-point number can be used separately, and the half-precision floating-point number includes FP16 half-precision floating-point number and BF16 half-precision floating-point number.

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