Processor core, instruction processing method, electronic device and storage medium

Abstract

The embodiment of the invention relates to a processor core comprising a front end, an instruction processing method, equipment and a medium. The processor core front end comprises N fetch decoding assembly lines, at least one instruction cache and at least one microinstruction cache, wherein N is an integer greater than or equal to 2. Each fetch decoding pipeline comprises fetch selection logic, an instruction cache port, a microinstruction cache port, a decoder and a first microinstruction queue. And the prediction information is processed by the instruction decoding assembly line or the micro instruction assembly line in the N instruction fetching decoding assembly lines to enter the first micro instruction queue for distribution. The processor core has a larger average front-end bandwidth and has improved processing performance.

Description

Technical Field

[0001] The present disclosure relates to a processor core, an instruction processing method, an electronic device, and a computer-readable storage medium. Background Art

[0002] The CPU core front-end typically includes branch prediction (BP), instruction fetch (IF), instruction decoder (DE), and instruction dispatch (DI) modules. In some high-performance processors, the instruction decode module also includes a micro-op cache (u-op cache). The micro-op cache stores the microinstructions obtained from instruction decoding. When the address of these microinstructions is accessed a second time, the processor directly accesses the micro-op cache and no longer accesses the instruction cache to decode the instructions. In some processor architectures, instruction decoding increases latency, reduces bandwidth, and increases power consumption. If a micro-op cache is used, the negative effects of these decoding operations are significantly reduced in a large number of programs. The logic for selecting between the instruction cache and the micro-op cache is located between the branch prediction stage and the instruction fetch stage. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a processor core, including a front end, wherein the front end includes N instruction fetch and decode pipelines, at least one instruction cache and at least one microinstruction cache, where N is an integer greater than or equal to 2; each of the instruction fetch and decode pipelines includes instruction fetch selection logic, an instruction cache port, a microinstruction cache port, a decoder, and a first microinstruction queue; the instruction cache port is configured to read and write the instruction cache, and provide instructions obtained from the instruction cache to the decoder; the microinstruction cache port is configured to read and write the microinstruction cache, and provide the first microinstruction obtained from the microinstruction cache to the first microinstruction queue; the decoder is configured to decode the instruction obtained from the instruction cache port into a second microinstruction and provide the decoded second microinstruction to the first microinstruction queue; the instruction fetch selection logic is configured to select the instruction cache port and the decoder to perform an instruction fetch and decode operation, or to select the microinstruction cache port to perform an instruction fetch and decode operation.

[0004] For example, at least one embodiment of the present disclosure provides a processor core, wherein the front end further includes: an instruction distribution unit configured to distribute microinstructions received from a first microinstruction queue of one of the N instruction fetch and decode pipelines for execution.

[0005] For example, at least one embodiment of the present disclosure provides a processor core, wherein the instruction cache is configured to be coupled to the instruction cache ports of the N instruction fetch and decode pipelines through memory interleaving technology or multi-port technology, so that the N instruction fetch and decode pipelines access the instruction cache; and / or the microinstruction cache is configured to be coupled to the microinstruction cache ports of the N instruction fetch and decode pipelines through memory interleaving technology or multi-port technology, so that the N instruction fetch and decode pipelines access the microinstruction cache.

[0006] For example, in at least one embodiment of the present disclosure, the processor core provided by the front end further includes: a branch prediction unit configured to generate a prediction result based on a received instruction address for use in the N instruction fetch and decode pipelines.

[0007] For example, at least one embodiment of the present disclosure provides a processor core, wherein the front end further includes: a boundary information determination unit, configured to generate boundary information based on the prediction result, and generate at least one information stream based on the prediction result; wherein the type of the boundary information includes the last byte of the jump branch instruction, the last byte of the prediction result, or the last byte of the intermediate instruction in the prediction result.

[0008] For example, in a processor core provided by at least one embodiment of the present disclosure, the front end further includes: a window selection unit configured to allocate the at least one information stream to the N instruction fetch and decoding pipelines to process the at least one information stream, wherein the allocation strategy of the window selection unit includes any one of the number of prediction results, the number of bytes of the prediction results, the blocking degree of the N instruction fetch and decoding pipelines, and the window switching frequency under different modes.

[0009] For example, in a processor core provided by at least one embodiment of the present disclosure, the front end further includes: reordering logic configured to reorder the microinstructions obtained by the N instruction fetch and decoding pipelines processing the at least one information stream and send them to the instruction distribution unit.

[0010] For example, at least one embodiment of the present disclosure provides a processor core, wherein the front end further includes: a first arbitration logic and a second arbitration logic, wherein the prediction results include prediction results for M threads, wherein M is an integer greater than or equal to 2; the first arbitration logic is configured to assign the prediction results in the M threads to the N instruction fetch and decode pipelines for processing; and the second arbitration logic is configured to sequentially select and send microinstructions corresponding to the M threads obtained by processing the N instruction fetch and decode pipelines to the instruction dispatch unit.

[0011] For example, at least one embodiment of the present disclosure provides a processor core, wherein each of the instruction fetch and decode pipelines further includes a second microinstruction queue, and the second microinstruction queue is configured to receive microinstructions from the decoder and / or the microinstruction cache port in each of the instruction fetch and decode pipelines.

[0012] At least one embodiment of the present disclosure also provides an instruction processing method, comprising: in response to an instruction processing request, selecting a target instruction fetch decoding pipeline from the N instruction fetch decoding pipelines included in the front end of the processor core to respond to the instruction processing request, wherein N is an integer greater than or equal to 2; in the target instruction fetch decoding pipeline, selecting to perform an instruction fetch decoding operation through an instruction cache port and a decoder, or selecting to perform an instruction fetch decoding operation through a microinstruction cache port to respond to the instruction processing request, wherein, in response to selecting the microinstruction cache port, performing an instruction fetch decoding operation to respond to the instruction processing request comprises: obtaining a first microinstruction from a microinstruction cache through the microinstruction cache port and providing the first microinstruction to a first microinstruction queue, or in response to selecting to perform an instruction fetch decoding operation through the instruction cache port and the decoder to respond to the instruction processing request comprises: obtaining an instruction from an instruction cache through the instruction cache port and providing the instruction to the decoder, and the decoder decodes the instruction into a second microinstruction and provides the second microinstruction to the first microinstruction queue.

[0013] For example, the instruction processing method provided by at least one embodiment of the present disclosure further includes: distributing microinstructions received from a first microinstruction queue of one of the target instruction fetch and decode pipelines in the N instruction fetch and decode pipelines for execution.

[0014] For example, at least one embodiment of the present disclosure provides an instruction processing method, wherein the instruction cache is coupled to the instruction cache port of the target instruction fetch decoding pipeline among the N instruction fetch decoding pipelines through memory interleaving technology or multi-port technology, so that the target instruction fetch decoding pipeline among the N instruction fetch decoding pipelines accesses the instruction cache; and / or the microinstruction cache is coupled to the microinstruction cache port of the target instruction fetch decoding pipeline among the N instruction fetch decoding pipelines through memory interleaving technology or multi-port technology, so that the target instruction fetch decoding pipeline among the N instruction fetch decoding pipelines accesses the microinstruction cache.

[0015] For example, the instruction processing method provided by at least one embodiment of the present disclosure further includes: generating a prediction result based on the received instruction address to generate the instruction processing request for a target instruction fetch decoding pipeline among the N instruction fetch decoding pipelines.

[0016] For example, the instruction processing method provided by at least one embodiment of the present disclosure further includes: generating boundary information based on the prediction result corresponding to the instruction processing request, and generating at least one information stream based on the prediction result, wherein the type of the boundary information includes the last byte of the jump branch instruction, the last byte of the prediction result, or the last byte of the intermediate instruction in the prediction result.

[0017] For example, the instruction processing method provided by at least one embodiment of the present disclosure further includes: allocating the at least one information stream to the target instruction fetch decoding pipeline among the N instruction fetch decoding pipelines through window selection logic to process the at least one information stream, wherein the window selection logic includes any one of the number of prediction results, the number of bytes of the prediction results, the blocking degree of the target instruction fetch decoding pipeline among the N instruction fetch decoding pipelines, and the window switching frequency under different modes.

[0018] For example, the instruction processing method provided by at least one embodiment of the present disclosure further includes: reordering the microinstructions obtained by processing the at least one information stream by the target instruction fetch decoding pipeline among the N instruction fetch decoding pipelines for distribution.

[0019] For example, at least one embodiment of the present disclosure provides an instruction processing method, wherein the prediction result includes prediction results for M threads, wherein M is an integer greater than or equal to 2, and the method further includes: allocating the prediction results corresponding to the instruction processing request in the M threads to the target instruction fetch decoding pipeline in the N instruction fetch decoding pipelines for processing; and selecting the microinstructions corresponding to the M threads obtained by processing the target instruction fetch decoding pipeline in the N instruction fetch decoding pipelines in sequence for distribution.

[0020] For example, at least one embodiment of the present disclosure provides an instruction processing method, wherein the response to selecting the microinstruction cache port to perform an instruction fetch decoding operation to respond to the instruction processing request includes: obtaining a third microinstruction from the microinstruction cache through the microinstruction cache port and providing the third microinstruction to the second microinstruction queue; and the response to selecting the instruction cache port and the decoder to perform an instruction fetch decoding operation to respond to the instruction processing request includes: obtaining an instruction from the instruction cache through the instruction cache port and providing the instruction to the decoder, and the decoder decodes the instruction into a fourth microinstruction and provides the fourth microinstruction to the second microinstruction queue.

[0021] At least one embodiment of the present disclosure further provides an electronic device, comprising the processor core described in any of the above embodiments.

[0022] At least one embodiment of the present disclosure further provides an electronic device, comprising: a processor; and a memory, comprising one or more computer program instructions; wherein the one or more computer program instructions, when executed by the processor, execute the instruction processing method provided in any of the above embodiments.

[0023] At least one embodiment of the present disclosure provides a computer-readable storage medium that non-temporarily stores computer-readable instructions, wherein when the computer-readable instructions are executed by a processor, the instruction processing method provided by any embodiment of the present disclosure is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0025] Figure 1 A schematic diagram of a pipeline of a processor core is shown;

[0026] Figure 2 A schematic diagram showing the basic structural division of a processor is shown;

[0027] Figure 3 A schematic diagram showing an example of a front-end structure of a CPU core;

[0028] Figure 4 A schematic diagram of a branch prediction module is shown;

[0029] Figure 5 A schematic diagram illustrating the operation of decoding instructions in a processor core;

[0030] Figure 6 A schematic diagram showing the structure of a processor core according to at least one embodiment of the present disclosure is shown;

[0031] Figure 7 A schematic flow chart illustrating an instruction processing method according to at least one embodiment of the present disclosure is shown;

[0032] Figure 8 A specific flow chart of the instruction processing method according to at least one embodiment of the present disclosure is shown;

[0033] Figure 9 An example of the structure of a processor core according to at least one embodiment of the present disclosure is shown;

[0034] Figure 10 An example of the structure of a processor core according to at least another embodiment of the present disclosure is shown;

[0035] Figure 11 An example of the structure of a processor core according to at least another embodiment of the present disclosure is shown;

[0036] Figure 12 A schematic block diagram of an electronic device according to at least one embodiment of the present disclosure is shown;

[0037] Figure 13 A schematic diagram showing the structure of a computer-readable storage medium according to at least one embodiment of the present disclosure; and

[0038] Figure 14 A schematic block diagram of an electronic device according to at least another embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0039] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0040] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by persons of ordinary skill in the field to which the present disclosure pertains. The terms "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are merely used to distinguish between different components. Similarly, terms such as "include" or "comprise" and the like mean that the elements or objects preceding the term encompass the elements or objects listed following the term and their equivalents, without excluding other elements or objects. Terms such as "connect" or "connected" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "upper", "lower", "left", and "right" are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0041] The processor cores (CPU cores) of single-core or multi-core processors use pipelining to improve instruction execution efficiency. Pipelining divides the complete operation steps of the CPU core into multiple sub-steps and executes these sub-steps in a pipelined manner to improve efficiency.

[0042] Figure 1 FIG. 1 shows an exemplary scalar central processing unit (CPU) instruction pipeline comprising a five-stage pipeline. Figure 1As shown, each instruction can be issued every clock cycle and executed within a fixed time (e.g., five clock cycles). The execution of each instruction is divided into five steps: instruction fetch (IF) stage 1001, decode (ID) stage 1002, execute (EX) stage 1003, memory access (MEM) stage 1004, and writeback (WB) stage 1005. In IF stage 1001, a specified instruction is retrieved from the instruction cache. A portion of the retrieved instruction specifies the source register that can be used for instruction execution. In ID stage 1002, the instruction is decoded and control logic is generated to retrieve the contents of the specified source register. Based on the control logic, an arithmetic or logical operation is performed on the retrieved contents in EX stage 1003. In MEM stage 1004, the executed instruction can read or write to the memory in the data cache. Finally, in WB stage 1005, the value obtained by executing the instruction can be written back to a register.

[0043] Usually, the earlier pipeline steps in the CPU are classified as the front end. For example, taking a five-stage pipeline as an example, the modules used for the instruction fetch stage and the decoding stage are classified as the CPU front end. Correspondingly, the later pipeline steps in the CPU are classified as the back end. For example, taking a five-stage pipeline as an example, the modules used for the execution stage, memory access stage and write-back stage are classified as the CPU back end.

[0044] In order to support high operating frequencies, each pipeline stage may contain multiple (sub) pipeline stages (clock cycles). Although each pipeline stage performs limited operations, each clock can be kept to a minimum, thereby improving the performance of the CPU core by increasing the operating frequency of the CPU. Each pipeline stage can also further improve the performance of the processor core by accommodating more instructions (i.e., superscalar technology). Superscalar refers to a method of executing multiple instructions in parallel within one cycle. A processor with increased instruction-level parallelism that can process multiple instructions within one cycle is called a superscalar processor. For example, a superscalar processor can further support out-of-order execution. Out-of-order execution refers to the technology used by the CPU to allow multiple instructions to be sent separately to the corresponding circuit units for processing, not in the order specified by the program.

[0045] Within the microarchitecture, the processor core translates each architectural instruction ("instruction") into one or more microinstructions. Each microinstruction performs only a limited number of operations, which keeps each pipeline stage short and increases the processor core's operating frequency. For example, a memory read instruction (load) can be translated into an address generation microinstruction and a memory read microinstruction. The second microinstruction depends on the result of the first microinstruction, so the second microinstruction will not begin execution until the first microinstruction is completed. Microinstructions contain multiple microarchitecture-related fields that are used to pass relevant information between pipeline stages.

[0046] Speculative execution is another technique for improving processor performance. This technique executes the instructions following an instruction before it has completed execution. One speculative execution technique is branch prediction. As mentioned above, the instruction fetch unit is responsible for providing the processor with the next instruction to execute. During the instruction fetch stage, in addition to fetching multiple instructions, the address for the next instruction fetch must also be determined. Therefore, this stage determines whether a conditional branch instruction exists, if so, whether the branch will be taken (in which direction), and the target address. The instruction fetch unit includes a branch prediction unit (branch predictor) to perform branch prediction. The branch prediction unit (branch predictor) at the front end of the processor core predicts the direction of the conditional branch instruction, prefetches, and executes instructions in that direction. Another speculative execution technique is executing a memory read instruction before the addresses of all previous memory write instructions are known.

[0047] Speculative execution further increases inter-instruction parallelism, significantly improving processor core performance. When a speculative execution error occurs, such as a branch prediction error or a write instruction preceding a memory read instruction overwriting the same address, all instructions in the pipeline following the erroneous instruction must be flushed (or "cleared"), and the program then jumps to the error point and re-executes to ensure correct execution.

[0048] Figure 2 A schematic diagram of the basic structure of a processor is shown. Processor 200 includes at least one CPU core (processor core) and at least one level of cache. For example, the CPU core includes a front end 201 and a back end 202. For example, the at least one level of cache includes a level 1 cache (not shown) provided within the CPU core and a level 2 cache 203 provided outside the CPU core. Here, the level 2 cache 203 is a separate structure.

[0049] Figure 3A schematic diagram of an example of the front-end structure of a CPU core is shown. The front-end 201 of the CPU core includes an instruction fetch unit, a decoding unit and a firing unit. The instruction fetch unit includes a branch prediction 301 and a selection logic 302; the decoding unit includes an instruction cache 303, an instruction decode 304, a microinstruction cache 305 and a microinstruction queue 306; and the firing unit 307 is connected to the microinstruction queue 306. The CPU core has both an instruction cache and a microinstruction cache, so it has micro-architecture optimization. The instruction address obtained by the instruction fetch unit (which can be a program counter address, referred to as a PC address) is predicted through a branch prediction 301 to obtain the instruction address to be executed next. At the same time, the instruction address passes through the selection logic 302 to determine whether the instruction corresponding to the instruction address needs to be decoded. If "yes", then go to step 1. Figure 3 The left path in the middle needs to decode the instruction; if "no", then go to Figure 3 The path on the right does not need to decode the instruction, but accesses the microinstruction cache to obtain the corresponding microinstruction group data.

[0050] Figure 4 A schematic diagram of a branch prediction module is shown. Figure 3 , the instruction address that is about to enter the processor pipeline first enters the branch prediction 301 module, and accesses the branch predictor 3011 and other functional modules 3012 respectively. The purpose of accessing the branch predictor 301 is to determine whether there is a branch instruction within an interval starting from the instruction address (for example, it can be the range from the instruction address to the first subsequent alignment address, for example, the processor alignment address can be 64 bytes), the branch direction and jump address when there is a branch instruction. The purpose of accessing other functional modules is to obtain some key information to facilitate access to subsequent modules. Other functional modules may include, for example, a micro-tag cache of microinstructions and a micro-tag cache of instructions. If a branch that can be jumped is predicted, the next instruction address is the jump address of the branch. If no branch that can be jumped is predicted, the next instruction address is the starting address of the next alignment address.

[0051] Figure 5 A schematic diagram showing the operation of decoding instructions in a processor core is shown. Figure 3Based on instruction address A, the instruction cache 303 is queried to obtain the undecoded instruction data (e.g., one or more instructions) corresponding to instruction address A. The instruction data is then decoded into multiple microinstructions (these microinstructions may be referred to as microinstruction groups, e.g., microinstruction 1, microinstruction 2, microinstruction 3, etc.) by instruction decoding 304. The obtained microinstruction group is sent to the microinstruction queue 306 to wait for the issue unit 307 to allocate and issue it to the corresponding execution unit in the backend of the CPU core for execution. On the other hand, if certain conditions are met (e.g., the microinstruction group is a commonly used group of microinstructions), it is saved to the microinstruction cache 305 to await possible access again in the future.

[0052] In one embodiment, the processor core may update the micro tag cache of the micro instructions in other functional modules 3012 while saving the micro instruction group into the micro instruction cache 305 .

[0053] The inventors of the present disclosure noticed that the above-mentioned processor has only one pipeline including branch prediction, instruction fetch, decoding and microinstruction cache. With the development trend of increasing instruction distribution bandwidth (distributing more instructions per unit time) and memory access bandwidth and increasing the number of various execution units, the front end of the processor core is gradually unable to meet the demand of the back end of the processor core to execute more instructions. Therefore, how to increase the front-end bandwidth has become a problem that mainstream processors need to solve.

[0054] Simultaneous Multithreading (SMT) technology is a key technology for improving overall CPU performance. It leverages the multi-issue and out-of-order execution mechanisms of high-performance CPU cores to simultaneously execute instructions from multiple threads. This allows a single physical CPU core to appear to software and the operating system as multiple virtual CPU cores. When executing a single thread, the multiple execution units and hardware resources within a modern, multi-issue, high-performance CPU core are often underutilized. When the thread stalls due to certain reasons (such as an L2 cache miss), the hardware execution units are forced to idle, wasting hardware resources and reducing performance-to-power ratio. In SMT modes, such as dual-thread mode (SMT2), when one thread stalls, other threads can continue to run. This improves hardware resource utilization, thereby enhancing the CPU core's multithreaded throughput, overall performance, and performance-to-power ratio. However, due to sharing CPU core resources with other threads, the performance of a single thread running under SMT is often lower than its performance in single-threaded mode.

[0055] In SMT mode, at least one pipeline stage in a processor core is time-shared. This means that if a thread occupies a pipeline stage at a given moment, other threads cannot occupy that stage at that moment. However, if there are two pipelines, each thread can exclusively occupy one. This significantly improves overall SMT performance.

[0056] The inventors of the present disclosure also noticed that for a multi-threaded processor core, it can only allow multiple threads to use partially expanded multiple pipelines in one of the modes: instruction decoding mode or microinstruction mode, and cannot fully and effectively utilize the advantages of multiple pipelines.

[0057] At least one embodiment of the present disclosure provides a processor core, an instruction processing method, an electronic device, and a storage medium. The processor core of the embodiment of the present disclosure includes a front end, which includes N instruction fetch and decode pipelines, at least one instruction cache, and at least one microinstruction cache, where N is an integer greater than or equal to 2. Each of the above-mentioned instruction fetch and decode pipelines includes instruction fetch selection logic, an instruction cache port, a microinstruction cache port, a decoder, and a first microinstruction queue. The instruction cache port is configured to read and write the instruction cache, and provides the instruction obtained from the instruction cache to the decoder; the microinstruction cache port is configured to read and write the microinstruction cache, and provides the first microinstruction obtained from the microinstruction cache to the first microinstruction queue; the decoder is configured to decode the instruction obtained from the instruction cache port into a second microinstruction and provide the decoded second microinstruction to the first microinstruction queue; the instruction fetch selection logic is configured to select the instruction cache port and the decoder to perform an instruction fetch and decode operation, or select the microinstruction cache port to perform an instruction fetch and decode operation. The first microinstruction and the second microinstruction here are respectively used to refer to the microinstructions described in the two processing methods.

[0058] At least one embodiment of the present disclosure further provides an instruction processing method corresponding to the above-mentioned processor core.

[0059] The processor core provided by at least one embodiment of the present disclosure can, on the one hand, be designed with multiple instruction fetch and decode pipelines, each of which can operate in instruction decoding mode and microinstruction cache mode. Regardless of whether one pipeline in either instruction decoding mode or microinstruction cache mode is blocked, another pipeline can be used to take over the prediction information, so that more microinstructions can be accumulated in the microinstruction queue for execution by the processor core backend, providing a larger processor front-end bandwidth and improving the performance of the processor. On the other hand, the processor core provided by at least one embodiment of the present disclosure can allow multiple threads to use multiple pipelines regardless of whether it is in instruction decoding mode or microinstruction cache mode, and each thread can generate a larger average front-end bandwidth, thereby greatly improving the multi-threaded performance.

[0060] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0061] Figure 6 A schematic structural diagram of a processor core according to at least one embodiment of the present disclosure is shown.

[0062] like Figure 6 As shown, the processor core 600 includes a front end 601, which includes N instruction fetch and decode pipelines (e.g., N=2, i.e., instruction fetch and decode pipeline 1 and instruction fetch and decode pipeline 2 as shown in the figure), at least one instruction cache 6031-603n, and at least one microinstruction cache 6041-604n. It should be noted that the number of instruction fetch and decode pipelines can be determined based on the specific design performance of the processor core front end and is not limited in this disclosure.

[0063] The following description uses instruction fetch and decode pipeline 1 as an example. Instruction fetch and decode pipeline 1 includes selection logic 6021, instruction cache port 6051, microinstruction cache port 6061, instruction decoder 6071, and first microinstruction queue 6081. For example, instruction cache port 6051, instruction cache (e.g., instruction cache 6031), and instruction decoder 6071 constitute an instruction decode pipeline (used in instruction decode mode); for example, microinstruction cache port 6061 and microinstruction cache (e.g., microinstruction cache 6041) constitute a microinstruction pipeline (used in microinstruction cache mode). The internal structure of the remaining N-1 instruction fetch and decode pipelines is the same as that of instruction fetch and decode pipeline 1 and will not be repeated here.

[0064] In the above embodiment, for example, there is only one instruction cache (eg, instruction cache 6031 ) and one microinstruction cache (eg, microinstruction cache 6041 ), and thus N instruction fetch and decode pipelines share the instruction cache and microinstruction cache.

[0065] For example, unless otherwise specified, all the following descriptions are based on the instruction fetch and decode pipeline 1.

[0066] For example, in one possible implementation, the front end 601 further includes an instruction dispatch unit configured to dispatch microinstructions received from a first microinstruction queue of one of the N instruction fetch and decode pipelines for execution.

[0067] For example, the instruction dispatch unit (not shown in the figure) is configured after the first microinstruction queue 6081, receives the processed microinstructions in the instruction fetch and decode pipeline 1 and dispatches them to subsequent execution units for execution.

[0068] For example, the instruction cache (e.g., instruction cache 6031) is coupled to the instruction cache ports 6051-605n via bank-interleaving technology, so that the instruction cache ports 6051-605n access the instruction cache 6031; the microinstruction cache (e.g., microinstruction cache 6041) is coupled to the microinstruction cache ports 6061-606n via bank-interleaving technology, so that the microinstruction cache ports 6061-606n access the instruction cache 6041.

[0069] Memory interleaving technology divides memory modules into multiple independent channels and allocates data blocks to different channels alternately, so that multiple channels can be operated simultaneously when accessing memory, thereby reducing waiting time and increasing data transmission rate.

[0070] For example, the instruction cache (e.g., instruction cache 6031) is coupled to the instruction cache ports 6051-605n via multi-port technology, so that the instruction cache ports 6051-605n access the instruction cache 6031; the microinstruction cache (e.g., microinstruction cache 6041) is coupled to the microinstruction cache ports 6061-606n via multi-port technology, so that the microinstruction cache ports 6061-606n access the instruction cache 6041.

[0071] Each of the multiple ports provided by the multi-port technology can perform read and write operations independently, which allows multiple requests to be processed at the same time, thereby reducing waiting time and improving the overall performance of the system.

[0072] The above-mentioned instruction cache 6031 and microinstruction cache 6041 are merely exemplary and are not limited in this disclosure. For example, if two ports (e.g., instruction cache port 6051 and instruction cache port 6052) are accessed simultaneously and encounter an address conflict, the access to one of them (e.g., instruction cache port 6052) can be delayed to wait until the access to the non-delayed port is completed.

[0073] For example, in a possible implementation, the front end 601 further includes a branch prediction unit, which is configured to generate a prediction result based on a received instruction address for use in the N instruction fetch and decode pipelines.

[0074] For example, a branch prediction unit (not shown) is configured before instruction fetch and decode pipelines 1 to N. The branch prediction unit is used in the processor to optimize the program execution process, especially the performance of processing conditional branch statements. For example, the branch prediction unit can generate a prediction result based on the instruction address of the instruction (e.g., a jump instruction) entering the instruction pipeline for use in the above-mentioned instruction fetch and decode pipelines 1 to N. For example, the branch prediction method of the branch prediction unit can include any one or more of static branch prediction, dynamic branch prediction, and indirect branch prediction.

[0075] For example, in one possible embodiment, the front end 601 further includes a boundary information determination unit, which is configured to generate boundary information based on the prediction result and generate at least one information stream based on the prediction result. For example, depending on the type of the branch prediction unit, the type of the boundary information includes the last byte of the jump branch instruction, the last byte of the prediction result, or the last byte of the intermediate instruction in the prediction result. For example, in one type of branch prediction unit, when a branch target buffer (BTB) hits, even if the branch instruction does not jump, the prediction information will be forcibly ended at the last byte of a branch instruction, rather than at the last byte of the cache basic block (or prediction window), thereby resulting in "the last byte of the prediction result."

[0076] For example, the boundary information determination unit (not shown) is configured after the branch prediction unit and before the instruction fetch and decoding pipeline. For example, the number of generated information flows is determined based on the number of boundary information, and this disclosure does not limit this.

[0077] For example, the boundary information can be stored in a new cache structure or in an existing cache structure. When the boundary information is the last byte of the intermediate instruction in the above prediction result, the boundary information is first decoded and then stored in any of the above cache structures.

[0078] For example, in one possible embodiment, the front end 601 further includes a window selection unit, which is configured to allocate the at least one information stream to the N finger fetch and decoding pipelines for processing the at least one information stream. For example, the allocation strategy of the window selection unit includes any one of the number of prediction results, the number of bytes of the prediction results, the blocking degree of the N finger fetch and decoding pipelines, and the window switching frequency under different modes.

[0079] For example, a window selection unit (not shown in the figure) is configured after the above-mentioned boundary information determination unit and before the finger fetch decoding pipeline. For example, at least one information stream (for example, 3) is sent to finger fetch decoding pipeline 1 and finger fetch decoding pipeline 2 through the window selection unit. For example, the at least one information stream may be sent to one pipeline or to different pipelines. For example, two information streams are sent to finger fetch decoding pipeline 1, and the remaining one is sent to finger fetch decoding pipeline 2. The specific number of allocated streams can be dynamically adjusted based on the execution status (for example, the degree of congestion) of finger fetch decoding pipeline 1 to finger fetch decoding pipeline n, and the present disclosure does not impose any restrictions on this.

[0080] For example, in one possible implementation, the front end 601 further includes reordering logic, which is configured to reorder the microinstructions obtained by the N instruction fetch and decode pipelines processing the at least one information stream and send them to the instruction dispatch unit.

[0081] For example, the reorder logic (not shown) is configured after the instruction fetch and decode pipeline and before the instruction dispatch unit. For example, because instruction fetch and decode pipelines 1 to n (e.g., instruction fetch and decode pipelines 1 and 2) receive prediction results corresponding to a single thread, the instruction data processed by the boundary information determination unit and distributed by the window selection unit is in an out-of-order state. This means that the information flows processed in instruction fetch and decode pipelines 1 and 2 are in an out-of-order state. For example, based on the first-in-first-out (FIFO) principle, the microinstructions processed in instruction fetch and decode pipeline 1 and accumulated in the first microinstruction queues 6081-608n need to be reordered in the reorder logic to restore their order before entering the instruction fetch and decode pipeline. This allows the microinstructions processed by the instructions that are ranked higher in the information flow to be dispatched in a timely manner, thereby facilitating efficient and correct processing of the instruction sequence.

[0082] It should be noted that the boundary information unit, window selection unit, and reordering logic mentioned in the above embodiments are applicable to the single-threaded mode.

[0083] The processor core provided by at least one embodiment of the present disclosure is suitable for single-threaded mode, and multiple instruction fetch and decode pipelines are designed. Each instruction fetch and decode pipeline can operate in instruction decoding mode and microinstruction cache mode. No matter whether one pipeline in either instruction decoding mode or microinstruction cache mode is blocked, another pipeline can be used to take over the prediction information, so that more microinstructions can be accumulated in the microinstruction queue for execution by the processor core back end, providing a larger processor front-end bandwidth and improving the performance of the processor.

[0084] For example, in one possible embodiment, the front end 601 further includes a first arbitration logic and a second arbitration logic, wherein the prediction results include prediction results for M hardware threads (hereinafter referred to as "threads"), where M is an integer greater than or equal to 2 (for example, M = 2, 4 or 8, etc.); the first arbitration logic is configured to assign the prediction results of the M threads to the N instruction fetch and decode pipelines for processing; the second arbitration logic is configured to sequentially select and send the microinstructions corresponding to the M threads obtained after processing by the N instruction fetch and decode pipelines to the instruction dispatch unit.

[0085] For example, the first arbitration logic (not shown) is configured after the branch prediction unit and before the instruction fetch and decode pipeline. The second arbitration logic (not shown) is configured after the instruction fetch and decode pipeline and before the instruction dispatch unit. Since this embodiment is applicable to multi-threaded mode, it does not include a boundary information determination unit, a window selection unit, and a reordering logic.

[0086] For example, the above prediction results include prediction results for two (M=2) threads (e.g., thread 1 and thread 2). The first arbitration logic assigns the prediction results of the two threads to N instruction fetch and decode pipelines (e.g., two, namely, instruction fetch and decode pipeline 1 and instruction fetch and decode pipeline 2) for processing. For example, the prediction result of thread 1 can be assigned to instruction fetch and decode pipeline 1 or instruction fetch and decode pipeline 2. The specific allocation rules are not limited in this disclosure. For example, the second arbitration logic selects the microinstructions corresponding to the two threads obtained by processing through instruction fetch and decode pipeline 1 and instruction fetch and decode pipeline 2 in sequence and sends them to the instruction dispatch unit.

[0087] For example, in one possible embodiment, each of the N instruction fetch and decode pipelines further includes a second microinstruction queue, which is configured to receive microinstructions from the instruction decoder and / or microinstruction cache port in each of the above-mentioned instruction fetch and decode pipelines.

[0088] For example, in one possible embodiment, the second microinstruction queue (not shown in the figure) is parallel (and equivalent) to the first microinstruction queue (for example, the first microinstruction queue 6081), and is configured after the instruction decoder 6071 and the microinstruction cache port 6061 and before the above-mentioned second arbitration logic.

[0089] Exemplarily, the above prediction results include prediction results for four (M=4) threads (e.g., threads 1 through 4). The first arbitration logic distributes the prediction results for these four threads to N instruction fetch and decode pipelines (e.g., two, namely, instruction fetch and decode pipeline 1 and instruction fetch and decode pipeline 2). For example, the prediction results from threads 1 and 2 are distributed to instruction fetch and decode pipeline 1, and the prediction results from threads 3 and 4 are distributed to instruction fetch and decode pipeline 2 for processing. It should be noted that the above thread distribution results are merely exemplary and are not limited in this disclosure.

[0090] Taking the above allocation results as an example, for example, in the instruction fetch decoding pipeline 1, the microinstructions obtained by thread 1 through the instruction decoding pipeline or the microinstruction pipeline can be sent to the first microinstruction queue 6081, and the microinstructions obtained by thread 2 through the instruction decoding pipeline or the microinstruction pipeline can be sent to the second microinstruction queue.

[0091] For example, the microinstructions obtained by thread 1 through the instruction decoding pipeline or microinstruction pipeline can be sent to the second microinstruction queue, and the microinstructions obtained by thread 2 through the instruction decoding pipeline or microinstruction pipeline can be sent to the first microinstruction queue 6081.

[0092] For example, part of the microinstructions obtained by processing the instruction decoding pipeline or the microinstruction pipeline of thread 1 can be sent to the first microinstruction queue 6081, and the remaining part of the microinstructions obtained by processing the instruction decoding pipeline or the microinstruction pipeline of thread 1 can be sent to the second microinstruction queue, and the same is true for thread 2.

[0093] It should be noted that the allocation method of microinstructions for the instruction fetch and decode pipeline 2 for processing threads 3 and 4 is similar to that of the instruction fetch and decode pipeline 1, and will not be repeated here.

[0094] The processor core provided in at least one embodiment of the present disclosure is suitable for multi-threaded mode, and can allow multiple threads to use multiple pipelines regardless of instruction decoding mode or microinstruction cache mode. Each thread can generate a larger average front-end bandwidth, thereby greatly improving multi-threaded performance.

[0095] In addition to the above-mentioned front end, the processor core of the embodiment of the present disclosure also includes a back end. For example, the back end includes various execution units (such as arithmetic logic unit (ALU), floating point unit (FPU), load / store unit (LSU), etc.), reorder cache (ROB), end unit, etc., which will not be repeated here.

[0096] The processor core of the embodiment of the present disclosure can be based on the X86 microarchitecture, ARM microarchitecture, RISC-V microarchitecture, MIPS microarchitecture, etc., and the present disclosure does not impose any restrictions on this.

[0097] At least one embodiment of the present disclosure further provides an instruction processing method, the instruction processing method comprising: in response to an instruction processing request, selecting a target instruction fetch decoding pipeline from N instruction fetch decoding pipelines included in the front end of a processor core to respond to the instruction processing request, wherein N is an integer greater than or equal to 2; in the target instruction fetch decoding pipeline, selecting to perform an instruction fetch decoding operation in response to the instruction processing request through an instruction cache port and a decoder, or selecting to perform an instruction fetch decoding operation through a microinstruction cache port. In response to selecting to perform an instruction fetch decoding operation in response to the instruction processing request through the microinstruction cache port, the method comprises: obtaining a first microinstruction from a microinstruction cache through the microinstruction cache port and providing the first microinstruction to a first microinstruction queue. Alternatively, in response to selecting to perform an instruction fetch decoding operation in response to the instruction processing request through the instruction cache port and the decoder, the method comprises: obtaining an instruction from the instruction cache through the instruction cache port and providing the instruction to the decoder, wherein the decoder decodes the instruction into a second microinstruction and provides the second microinstruction to the first microinstruction queue.

[0098] Figure 7 A schematic flow chart of an instruction processing method according to at least one embodiment of the present disclosure is shown. Figure 7 As shown, the instruction processing method includes step S710 and step S720.

[0099] Step S710: In response to an instruction processing request, selecting a target instruction fetch and decode pipeline from N instruction fetch and decode pipelines included in the front end of the processor core to respond to the instruction processing request, where N is an integer greater than or equal to 2;

[0100] Step S720: In the target instruction fetch and decode pipeline, select to perform an instruction fetch and decode operation through the instruction cache port and the decoder, or select to perform an instruction fetch and decode operation through the microinstruction cache port to respond to the instruction processing request.

[0101] For example, the above instruction processing method corresponds to Figure 6 The processor core is shown.

[0102] For example, in one possible implementation, before responding to an instruction processing request, the instruction processing method includes generating a prediction result based on a received instruction address for use in a target instruction fetch decode pipeline among the N instruction fetch decode pipelines. For example, the prediction result is issued by a branch prediction unit. The specific function of the branch prediction unit has been described above and will not be repeated here.

[0103] For example, in the above instruction processing method, the prediction result includes a prediction result for a single thread or multiple threads (ie, multiple hardware threads in a multi-thread processor).

[0104] For example, in one possible embodiment, boundary information is generated based on the prediction result, and at least one information stream is generated based on the prediction result. For example, the type of boundary information includes the last byte of a jump branch instruction, the last byte of a prediction result, or the last byte of an intermediate instruction in the prediction result. For example, the number of information streams is based on the number of boundary information. For example, if the last byte of an intermediate instruction in the prediction result is regarded as boundary information, it is generated by decoding and then saved in a cache structure. For example, the cache structure can be a newly added cache, or it can reuse an existing cache, and the present disclosure does not limit this.

[0105] For example, in one possible implementation, at least one information stream is assigned to a target instruction fetch and decode pipeline among N instruction fetch and decode pipelines via window selection logic for processing. For example, the window selection logic may be based on any one of the following: the number of prediction results, the number of bytes of the prediction results, the degree of congestion of the target instruction fetch and decode pipeline among the N instruction fetch and decode pipelines, and the frequency of window switching in different modes, etc., which is not limited by the present disclosure. For example, the aforementioned multiple information streams can be sent to a single instruction fetch and decode pipeline or to different instruction fetch and decode pipelines.

[0106] For example, in response to selecting to perform an instruction fetch and decode operation through the microinstruction cache port to respond to the instruction processing request, the method includes: obtaining a first microinstruction from the microinstruction cache through the microinstruction cache port and providing the first microinstruction to a first microinstruction queue.

[0107] For another example, in response to selecting to perform an instruction fetch and decode operation through an instruction cache port and a decoder to respond to an instruction processing request, the process includes: obtaining an instruction from the instruction cache through the instruction cache port and providing the instruction to the decoder, the decoder decoding the instruction into a second microinstruction and providing the second microinstruction to the first microinstruction queue.

[0108] As described above, the microinstruction cache port and the microinstruction cache constitute a microinstruction pipeline (i.e., used in microinstruction cache mode), and the instruction cache port, instruction decoder, and instruction cache constitute an instruction decode pipeline (i.e., used in instruction decode mode). For example, a first microinstruction refers to a microinstruction processed by the microinstruction pipeline; a second microinstruction refers to a microinstruction processed by the instruction decode pipeline.

[0109] For example, in one possible implementation, the instruction cache is coupled to the instruction cache port of a target instruction fetch and decode pipeline among N instruction fetch and decode pipelines via memory interleaving technology or multi-port technology, so that the target instruction fetch and decode pipeline among the N instruction fetch and decode pipelines can access the instruction cache; or, the microinstruction cache is coupled to the microinstruction cache port of a target instruction fetch and decode pipeline among N instruction fetch and decode pipelines via memory interleaving technology or multi-port technology, so that the target instruction fetch and decode pipeline among the N instruction fetch and decode pipelines can access the microinstruction cache. This disclosure does not limit the cache technology that can achieve multi-port access; the specific cache technology is determined based on the actual design.

[0110] For example, the microinstruction cache ports of the target instruction fetch decode pipeline in N instruction fetch decode pipelines access the same microinstruction cache, and the instruction cache ports of the target instruction fetch decode pipeline in N instruction fetch decode pipelines access the same instruction cache. It should be noted that if multiple ports (for example, two instruction cache ports accessing the instruction cache) access simultaneously and encounter an address conflict, the accesses are processed sequentially.

[0111] For example, in one possible implementation, the instruction processing method further includes reordering the microinstructions obtained by processing at least one information stream by a target instruction fetch and decode pipeline among the N instruction fetch and decode pipelines for distribution. For example, because two information streams exist in a target instruction fetch and decode pipeline, the operating states of the two information streams in their respective instruction fetch and decode pipelines are determined by their respective pipelines, and it is possible that the information stream that enters first will exit the pipeline later. Since the order of the information streams must be maintained at this stage, the microinstructions need to be reordered for distribution.

[0112] For example, in one possible implementation, the instruction processing method further includes: distributing the microinstructions received from the first microinstruction queue of one of the target instruction fetch and decode pipelines among the N instruction fetch and decode pipelines for execution.

[0113] The instruction processing method provided by at least one embodiment of the present disclosure is achieved by designing multiple target instruction fetch and decoding pipelines. Each target instruction fetch and decoding pipeline can operate in instruction decoding mode and microinstruction cache mode. No matter whether one pipeline in either instruction decoding mode or microinstruction cache mode is blocked, another pipeline can be used to take over the prediction information, so that more microinstructions can be accumulated in the microinstruction queue for execution by the processor core back end, providing a larger processor front-end bandwidth and improving the performance of the processor.

[0114] For example, in one possible embodiment, the prediction results include prediction results for M threads, where M is an integer greater than or equal to 2, and the instruction processing method further includes: allocating the prediction results in the M threads to the target instruction fetch decoding pipeline in the N instruction fetch decoding pipelines for processing; and selecting the microinstructions corresponding to the M threads obtained by processing the target instruction fetch decoding pipeline in the N instruction fetch decoding pipelines in sequence for distribution.

[0115] For example, if M<N (e.g., M=3, N=4), each thread is sent to its own instruction fetch and decode pipeline (e.g., thread 1 corresponds to pipeline 1, and so on in sequence), where there are remaining instruction fetch and decode pipelines (e.g., remaining pipeline 4).

[0116] For example, if M=N (eg, M=N=4), each thread is sent to its own instruction fetch and decode pipeline (eg, thread 1 corresponds to pipeline 1, and so on in sequence), wherein there are no remaining instruction fetch and decode pipelines.

[0117] For example, if M>N (for example, M=5, N=4), in addition to the threads assigned to each pipeline (for example, thread 1 corresponds to pipeline 1, and so on in sequence), the remaining threads (for example, the remaining thread 5) are collectively assigned to the existing pipelines for processing based on the execution status of all pipelines (for example, blocking status).

[0118] It should be noted that the allocation order of the above threads is only exemplary and may be determined based on actual design, and this disclosure does not impose any restrictions on this.

[0119] For example, the microinstructions corresponding to M threads (e.g., thread 1 to thread 4) processed by the target instruction fetch decoding pipeline among N instruction fetch decoding pipelines (e.g., instruction fetch decoding pipeline 1-instruction fetch decoding pipeline 4) are selected in sequence for distribution (e.g., instruction fetch decoding pipeline 1 corresponds to thread 1, and so on).

[0120] For example, in one possible embodiment, in response to selecting a microinstruction cache port to perform an instruction fetch and decode operation in response to an instruction processing request, the method further includes: obtaining a first microinstruction from the microinstruction cache through the microinstruction cache port and providing the first microinstruction to a second microinstruction queue; and in response to selecting an instruction cache port and a decoder to perform an instruction fetch and decode operation in response to an instruction processing request, the method further includes: obtaining an instruction from the instruction cache through the instruction cache port and providing the instruction to the decoder, and the decoder decodes the instruction into a second microinstruction and provides the second microinstruction to the second microinstruction queue.

[0121] For example, the first microinstruction and the second microinstruction may come from the same thread or different threads. For example, instruction data from thread 1 and thread 2 are processed in instruction fetch and decode pipeline 1. Exemplarily, the first microinstruction and the second microinstruction obtained from thread 1 through instruction fetch and decode pipeline 1 may be provided to the first microinstruction queue or the second microinstruction queue separately, or part of the first microinstruction and the second microinstruction obtained from thread 1 through instruction fetch and decode pipeline 1 may be provided to the first microinstruction queue, and the remaining part may be provided to the second microinstruction queue. The same applies to the microinstructions of thread 2.

[0122] The instruction processing method provided by at least one embodiment of the present disclosure can allow multiple threads to use multiple pipelines regardless of instruction decoding mode or microinstruction cache mode. Each thread can generate a larger average front-end bandwidth, thereby greatly improving multi-threading performance.

[0123] Figure 8 The specific flow chart of the instruction processing method of at least one embodiment of the present disclosure is shown, which is applicable to the single-threaded mode. Figure 8 As shown, the instruction processing method includes steps S801-S812.

[0124] Steps S801 - S804 , S806 - S808 , S810 and S812 have been described above and will not be repeated here.

[0125] Step S805: Whether to enter the instruction decoding mode.

[0126] For example, based on the cache hit or cache miss information provided by the microinstruction cache, it is determined whether to enable the microinstruction cache mode. For example, when the microinstruction cache provides cache hit information indicating that several consecutive microinstruction groups are present in the microinstruction cache, the microinstruction cache fetch mode is enabled; otherwise, the prediction result continues to be processed in the instruction cache mode.

[0127] Step S809: Check whether the microinstruction has become the head of the queue.

[0128] For example, if the microinstructions of the currently processed information stream become the head of the microinstruction queue (FIFO queue), it means that the microinstructions of the previous information stream have been distributed (emitted), and thus there are no longer microinstructions of the previous information stream in the current microinstruction queue. Therefore, the microinstructions from different instruction fetch and decode pipelines can be reordered to restore the order before entering the N instruction fetch and decode pipelines.

[0129] Step S811: Whether it is possible to enter instruction distribution.

[0130] For example, in one possible implementation, instruction dispatch is determined based on one or more factors of resource availability, data dependency, scheduling policy, and branch prediction and prefetching.

[0131] For example, each execution unit (such as the arithmetic logic unit (ALU), floating point unit (FPU), load / store unit (LSU), etc.) has a certain throughput limit. If there is an idle execution unit, the corresponding instruction can be dispatched. Otherwise, the instruction needs to wait until the required resources become available.

[0132] For example, to ensure program correctness, instruction dispatch needs to consider data dependencies. For example, if the result of one instruction is the input of another instruction, the latter cannot be executed before the result of the other instruction. The reordering logic tracks these dependencies to ensure that instructions are dispatched only when all preconditions are met.

[0133] For example, complex scheduling algorithms are often used to decide which instructions should be dispatched first. Common scheduling algorithms include:

[0134] Oldest First: Select the instruction that arrived at the reservation station earliest and has no unresolved dependencies.

[0135] Least Delay: Prioritizes dispatching instructions with the shortest expected execution time to reduce the possibility of pipeline stalls.

[0136] Maximize resource utilization: Try to balance the workload of each execution unit to avoid overloading some units while others are idle.

[0137] The instruction processing method provided by at least one embodiment of the present disclosure is applicable to single-threaded processor cores or multi-threaded processor cores. Regardless of which of the multiple instruction fetch and decode pipelines is blocked, a backup pipeline is available to take over the prediction information, allowing more microinstructions to be accumulated in the microinstruction queue for back-end consumption, providing greater front-end bandwidth, and thus further improving processor performance. Moreover, regardless of whether the processor is in instruction decoding mode or microinstruction mode, the processor has two pipelines to consume the increased branch prediction bandwidth, thereby making better use of the increased branch prediction bandwidth.

[0138] Figure 9 The present invention shows a structural example of a processor core according to at least one embodiment of the present disclosure, where the processor core is suitable for single-threaded mode.

[0139] like Figure 9As shown, the front end of the processor core includes two instruction fetch and decode pipelines (for example, instruction fetch and decode pipeline 1 and instruction fetch and decode pipeline 2). It should be noted that, in other examples, the number of instruction fetch and decode pipelines can be determined based on the specific design performance of the processor core front end, and can include two or more instruction fetch and decode pipelines.

[0140] The processor core front end specifically includes a branch prediction unit 901, selection logic 9021 / 9022, an instruction cache 903, instruction cache ports 9031 / 9032, an instruction decoder 9041 / 9042, a microinstruction cache 905, microinstruction cache ports 9051 / 9052, microinstruction queues 9061 / 9063 (an example of a "first microinstruction queue"), an instruction dispatch unit 907, a boundary information determination unit 908, a window selection unit 909, and a reordering logic 910. These components or logics may be implemented in hardware, firmware, software, or any combination thereof, and their functional descriptions are described above and will not be repeated here.

[0141] The following describes one of the two instruction fetch and decode pipelines (e.g., instruction fetch and decode pipeline 1) as an example. Instruction fetch and decode pipeline 1 includes selection logic 9021, instruction cache 903, instruction cache port 9031, instruction decoder 9041, microinstruction cache 905, microinstruction cache port 9051, and microinstruction queue 9061. The instruction cache 903, instruction cache port 9031, and instruction decoder 9041 constitute instruction decode pipeline 1; the microinstruction cache 905 and microinstruction cache port 9051 constitute microinstruction pipeline 1. The structure of instruction fetch and decode pipeline 2 is similar to that of instruction fetch and decode pipeline 1 and will not be further described here.

[0142] The instruction cache port 9031 and the instruction cache port 9032 in the two instruction fetch and decode pipelines access the same instruction cache 903 ; the microinstruction cache port 9051 and the microinstruction cache port 9052 in the two instruction fetch and decode pipelines access the same microinstruction cache 905 .

[0143] The instruction cache 903 is configured to be coupled to the instruction cache ports (e.g., instruction cache port 9031 and instruction cache port 9032) of the two instruction fetch and decode pipelines through memory interleaving technology or multi-port technology to achieve non-blocking multi-port access, so that the two instruction fetch and decode pipelines access the instruction cache; the microinstruction cache 905 is configured to be coupled to the microinstruction cache ports (e.g., microinstruction cache port 9051 and microinstruction cache port 9052) of the two instruction fetch and decode pipelines through memory interleaving technology or multi-port technology to achieve non-blocking multi-port access, so that the two instruction fetch and decode pipelines access the microinstruction cache.

[0144] For example, if the above-mentioned instruction cache ports (e.g., instruction cache port 9031 and instruction cache port 9032) simultaneously access instruction cache 903 and encounter an address conflict, the access is performed in sequence. This disclosure does not restrict the access order. For the microinstruction cache, the processing method is consistent with the instruction cache and will not be repeated here.

[0145] Figure 9 The processor core shown is suitable for single-threaded mode and is designed with two instruction fetch and decode pipelines, including an instruction decode pipeline and a microinstruction pipeline. No matter which pipeline is blocked, there is a spare pipeline to take over the instructions to be processed, providing greater front-end bandwidth, thereby further improving processor performance.

[0146] Figure 10 A structural example of a processor core according to at least another embodiment of the present disclosure is shown. The processor core is suitable for a dual-thread mode, that is, the processor core is an SMT2 processor core.

[0147] like Figure 10 As shown, the front end of the processor core also includes two instruction fetch and decode pipelines. Figure 9 The processor core structure of the illustrated embodiment does not include the boundary information confirmation unit 908 , the window selection unit 909 and the reordering logic 910 , but includes the first arbitration logic 911 and the second arbitration logic 912 .

[0148] The prediction results from the branch prediction unit include prediction results for two threads. The first arbitration logic 911 is configured to distribute the prediction results of the two threads to the two instruction fetch and decode pipelines for processing.

[0149] The microinstruction queues 9061 / 9063 of the processor core respectively receive the microinstructions obtained by processing the prediction results of their respective threads, and the second arbitration logic 912 is configured to select the microinstructions corresponding to the two threads obtained by the two instruction fetch and decode pipelines in sequence and send them to the instruction dispatch unit.

[0150] Figure 10 The processor core shown is suitable for dual-thread mode, allowing dual threads to use two instruction fetch and decode pipelines regardless of instruction decoding or micro-instruction mode, so that each thread can generate a larger average front-end bandwidth, thereby improving multi-thread performance.

[0151] Figure 11 A structural example of a processor core according to at least another embodiment of the present disclosure is shown. The processor core is suitable for a four-thread mode, that is, the processor core is an SMT4 processor core.

[0152] like Figure 11 As shown, the front end of the processor core also includes two instruction fetch and decode pipelines. Figure 10 The processor core of the illustrated embodiment has microinstruction queues 9062 / 9064 (an example of a "second microinstruction queue") added to the two instruction fetch and decode pipelines, respectively.

[0153] The microinstruction queue 9062 / 9064 is configured to receive microinstructions from the decoder and / or microinstruction cache port in each corresponding instruction fetch and decode pipeline.

[0154] exist Figure 11 In the embodiment, the prediction results include prediction results for four threads (e.g., threads 1 through 4), while there are two instruction fetch decode pipelines (e.g., instruction fetch decode pipeline 1 and instruction fetch decode pipeline 2). After arbitration by the first arbitration logic 911, for example, the prediction results from threads 1 and 2 may be assigned to instruction fetch decode pipeline 1 for processing, while the prediction results from threads 3 and 4 may be assigned to instruction fetch decode pipeline 2 for processing.

[0155] For example, in instruction fetch and decode pipeline 1, all microinstructions obtained by thread 1 through the instruction decode pipeline or microinstruction pipeline can be sent to microinstruction queue 9061 or microinstruction queue 9062; for example, some microinstructions obtained by thread 1 through the instruction decode pipeline or microinstruction pipeline can be sent to microinstruction queue 9061, and the remaining microinstructions can be sent to microinstruction queue 9062. The allocation method for microinstructions from thread 2 in instruction fetch and decode pipeline 1 is the same as that for microinstructions from thread 1 described above, and will not be repeated here. The second arbitration logic 912 is configured to sequentially select the microinstructions corresponding to the four threads obtained through the two instruction fetch and decode pipelines and send them to the instruction dispatch unit.

[0156] Figure 11 The processor core shown is suitable for four-thread mode, allowing four threads to use two instruction fetch and decode pipelines regardless of instruction decoding or microinstruction mode. This can increase the number of instructions received by the front end of the processor core, thereby improving multi-threading performance.

[0157] At least one embodiment of the present disclosure further provides an electronic device. Figure 12 A schematic block diagram of an electronic device according to at least one embodiment of the present disclosure is shown.

[0158] For example, Figure 12As shown, the electronic device 1200 includes a processor 1210 and a memory 1220. The memory 1220 is used to store non-transitory computer-readable instructions (e.g., one or more computer program modules). The processor 1210 is used to execute the computer program instructions, which, when executed by the processor 1210, execute the instruction processing method provided by any embodiment of the present disclosure. The memory 1220 and the processor 1210 can be interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0159] The processor 1210 may be a device with data processing and / or program execution capabilities, such as a central processing unit (CPU), a tensor processing unit (TPU), a network processor (NP), or a graphics processing unit (GPU). It may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. For example, the central processing unit (CPU) may be an X86 or ARM architecture. The processor 1210 may be a general-purpose processor or a dedicated processor, and may control other components in the electronic device 1200 to perform desired functions.

[0160] For example, the memory 1220 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), a hard disk, an erasable programmable read-only memory (EPROM), a portable compact disk read-only memory (CD-ROM), a USB memory, a flash memory, etc. One or more computer program modules may be stored on the computer-readable storage medium, and the processor 1210 may execute one or more computer program modules to implement various functions of the electronic device 1200. Various applications and various data, as well as various data used and / or generated by the applications, may also be stored in the computer-readable storage medium.

[0161] It should be noted that, in the embodiment of the present disclosure, the specific functions and technical effects of the electronic device 1200 can be referred to the above description of the instruction processing method, which will not be repeated here.

[0162] At least one embodiment of the present disclosure further provides a non-transitory storage medium. Figure 13 A schematic diagram of a computer-readable storage medium provided for at least one embodiment of the present disclosure. Figure 13As shown, the storage medium 1300 non-transitorily stores computer-executable instructions 1310 . When the non-transitory computer-executable instructions 1310 are executed by a computer (including a processor), the instruction processing method of any embodiment of the present disclosure can be executed.

[0163] For example, one or more computer instructions may be stored on the storage medium 1300. Some of the computer instructions stored on the storage medium 1300 may be, for example, instructions for implementing one or more steps in the above-mentioned instruction processing method.

[0164] For example, the storage medium may include a tablet computer storage component, a personal computer hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), compact disc read-only memory (CD-ROM), flash memory, or any combination thereof, or other applicable storage media. For example, the storage medium 1300 may include the memory 1220 in the aforementioned electronic device 1200.

[0165] The technical effects of the storage medium provided by the embodiments of the present disclosure can be referred to the corresponding description of the instruction processing method in the above embodiments, which will not be repeated here.

[0166] At least one embodiment of the present disclosure further provides an electronic device, which includes the processor core of any of the above embodiments.

[0167] Figure 14 A schematic block diagram of an electronic device according to at least another embodiment of the present disclosure is shown. Figure 14 The electronic device 1400 shown is merely an example and should not limit the functions and scope of use of the embodiments of the present disclosure.

[0168] like Figure 14 As shown, in some examples, the electronic device 1400 includes a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 1401, which may include a processor core of any of the above-mentioned embodiments, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1402 or a program loaded from a storage device 1408 into a random access memory (RAM) 1403. Various programs and data required for the operation of the computer system are also stored in the RAM 1403. The processor 1301, ROM 1402, and RAM 1403 are connected to each other via a bus 1404. An input / output (I / O) interface 1305 is also connected to the bus 1404.

[0169] For example, the following components may be connected to the I / O interface 1405: an input device 1406 including, for example, a touch screen, touchpad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; an output device 1407 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; a storage device 1408 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1409, which may also include, for example, a network interface card such as a LAN card or modem. The communication device 1409 may allow the electronic device 1400 to communicate with other devices wirelessly or wired to exchange data, performing communication processing via a network such as the Internet. A drive 1410 is also connected to the I / O interface 1405 as needed. Removable media 1411, such as a magnetic disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed in the drive 1410 as needed, so that computer programs read therefrom can be installed into the storage device 1408 as needed.

[0170] Although Figure 14 The electronic device 1400 is shown as including various devices, but it should be understood that it is not required to implement or include all of the devices shown. More or fewer devices may be implemented or included instead.

[0171] For example, the electronic device 1400 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device 1409 may communicate with a network and other devices through wireless communication, such as the Internet, an intranet and / or a wireless network such as a cellular phone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communications may use any of a variety of communication standards, protocols, and technologies, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0172] For example, the electronic device 1400 may include any device such as a mobile phone, a tablet computer, a laptop computer, an e-book, a game console, a television, a digital photo frame, a navigator, a server, etc., or may be a combination of any data processing device and hardware, and the embodiments of the present disclosure do not limit this.

[0173] Regarding this disclosure, the following points need to be explained:

[0174] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to conventional designs.

[0175] (2) Unless there is any conflict, the features of the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0176] The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A processor core, comprising a front end, wherein: The front end includes N instruction fetch and decode pipelines, at least one instruction cache and at least one microinstruction cache, where N is an integer greater than or equal to 2. Each of the instruction fetch and decode pipelines includes an instruction fetch selection logic, an instruction cache port, a microinstruction cache port, a decoder, and a first microinstruction queue. The instruction cache port is configured to read and write the instruction cache and provide instructions obtained from the instruction cache to the decoder, The microinstruction cache port is configured to read and write the microinstruction cache, and provide the first microinstruction obtained from the microinstruction cache to the first microinstruction queue, The decoder is configured to decode the instruction obtained from the instruction cache port into a second microinstruction and provide the decoded second microinstruction to the first microinstruction queue, The instruction fetch selection logic is configured to select the instruction cache port and the decoder to perform instruction fetch decoding operations, or to select the microinstruction cache port to perform instruction fetch decoding operations.

2. The processor core according to claim 1, wherein: The front end also includes: The instruction dispatch unit is configured to dispatch the microinstructions received from the first microinstruction queue of one of the N instruction fetch and decode pipelines for execution.

3. The processor core according to claim 1, wherein: The instruction cache is configured to be coupled to the instruction cache ports of the N instruction fetch and decode pipelines through a memory interleaving technology or a multi-port technology, so that the N instruction fetch and decode pipelines access the instruction cache; and / or The microinstruction cache is configured to be coupled to the microinstruction cache ports of the N instruction fetch and decode pipelines through memory interleaving technology or multi-port technology, so that the N instruction fetch and decode pipelines access the microinstruction cache.

4. The processor core according to claim 2 or 3, wherein: The front end also includes: The branch prediction unit is configured to generate a prediction result according to the received instruction address for use in the N instruction fetch and decode pipelines.

5. The processor core according to claim 4, wherein: The front end also includes: a boundary information determining unit, configured to generate boundary information according to the prediction result, and to generate at least one information flow according to the prediction result, The type of the boundary information includes the last byte of the jump branch instruction, the last byte of the prediction result, or the last byte of the intermediate instruction in the prediction result.

6. The processor core according to claim 5, wherein: The front end also includes: A window selection unit is configured to allocate the at least one information stream to the N instruction fetch and decode pipelines to process the at least one information stream, wherein the allocation strategy of the window selection unit includes any one of the number of the prediction results, the number of bytes of the prediction results, the blocking degree of the N instruction fetch and decode pipelines, and the window switching frequency in different modes.

7. The processor core according to claim 5, wherein: The front end also includes: The reordering logic is configured to reorder the microinstructions obtained by the N instruction fetch and decode pipelines processing the at least one information stream and send them to the instruction distribution unit.

8. The processor core according to claim 4, wherein: The front end also includes: The first arbitration logic and the second arbitration logic, wherein: The prediction result includes prediction results for M threads, where M is an integer greater than or equal to 2; The first arbitration logic is configured to distribute the prediction results in the M threads to the N instruction fetch and decode pipelines for processing; and The second arbitration logic is configured to sequentially select and send microinstructions corresponding to the M threads obtained through the N instruction fetch and decode pipelines to the instruction distribution unit.

9. The processor core according to claim 8, wherein: Each of the instruction fetch and decode pipelines also includes a second microinstruction queue, The second microinstruction queue is configured to receive microinstructions from the decoder and / or the microinstruction cache port in each of the instruction fetch and decode pipelines.

10. A method for processing an instruction, comprising: In response to the instruction processing request, selecting a target instruction fetch decoding pipeline from N instruction fetch decoding pipelines included in the front end of the processor core to respond to the instruction processing request, wherein N is an integer greater than or equal to 2; In the target instruction fetch and decode pipeline, selecting to perform an instruction fetch and decode operation through an instruction cache port and a decoder, or selecting to perform an instruction fetch and decode operation through a microinstruction cache port to respond to the instruction processing request, wherein in response to selecting to perform an instruction fetch and decode operation through the microinstruction cache port to respond to the instruction processing request, the steps include: obtaining a first microinstruction from a microinstruction cache through the microinstruction cache port and providing the first microinstruction to a first microinstruction queue, or In response to selecting to perform an instruction fetch and decode operation through the instruction cache port and the decoder to respond to the instruction processing request, the method includes: obtaining an instruction from the instruction cache through the instruction cache port and providing the instruction to the decoder, and the decoder decodes the instruction into a second microinstruction and provides the second microinstruction to the first microinstruction queue.

11. The instruction processing method according to claim 10, further comprising: The microinstructions received from the first microinstruction queue of one of the target instruction fetch decode pipelines among the N instruction fetch decode pipelines are dispatched for execution.

12. The instruction processing method according to claim 10, wherein: The instruction cache is coupled to an instruction cache port of a target instruction fetch and decode pipeline among the N instruction fetch and decode pipelines through a memory interleaving technology or a multi-port technology, so that the target instruction fetch and decode pipeline among the N instruction fetch and decode pipelines accesses the instruction cache; and / or The microinstruction cache is coupled to a microinstruction cache port of a target instruction fetch decoding pipeline among the N instruction fetch decoding pipelines through memory interleaving technology or multi-port technology, so that the target instruction fetch decoding pipeline among the N instruction fetch decoding pipelines can access the microinstruction cache.

13. The instruction processing method according to claim 11 or 12, further comprising: A prediction result is generated according to the received instruction address to generate the instruction processing request for a target instruction fetch decoding pipeline among the N instruction fetch decoding pipelines.

14. The instruction processing method according to claim 13, further comprising: generating boundary information according to the prediction result corresponding to the instruction processing request, and generating at least one information flow according to the prediction result, The type of the boundary information includes the last byte of the jump branch instruction, the last byte of the prediction result, or the last byte of the intermediate instruction in the prediction result.

15. The instruction processing method according to claim 14, further comprising: Allocating the at least one information stream to a target instruction fetch decoding pipeline among the N instruction fetch decoding pipelines through a window selection logic to process the at least one information stream, The window selection logic includes any one of the number of the prediction results, the number of bytes of the prediction results, the blocking degree of the target instruction fetch and decode pipeline in the N instruction fetch and decode pipelines, and the window switching frequency in different modes.

16. The instruction processing method according to claim 15, further comprising: The microinstructions obtained by processing the at least one information stream by a target instruction fetch decoding pipeline among the N instruction fetch decoding pipelines are reordered for distribution.

17. The instruction processing method according to claim 13, wherein: The prediction result includes prediction results for M threads, where M is an integer greater than or equal to 2, and the method further includes: Allocating the prediction results corresponding to the instruction processing request in the M threads to a target instruction fetch decoding pipeline in the N instruction fetch decoding pipelines for processing; and The microinstructions corresponding to the M threads obtained by processing the target instruction fetch decoding pipeline in the N instruction fetch decoding pipelines are selected in sequence for distribution.

18. The instruction processing method according to claim 17, wherein: The step of performing an instruction fetch and decode operation in response to the instruction processing request by selecting the microinstruction cache port comprises: Retrieving a first microinstruction from a microinstruction cache through the microinstruction cache port and providing the first microinstruction to a second microinstruction queue; and The step of performing an instruction fetch and decode operation in response to the instruction processing request by selecting the instruction cache port and the decoder comprises: An instruction is obtained from the instruction cache through the instruction cache port and provided to the decoder, and the decoder decodes the instruction into a second microinstruction and provides the second microinstruction to the second microinstruction queue.

19. An electronic device, comprising the processor core according to any one of claims 1 to 9.

20. An electronic device, comprising: processor; as well as a memory including one or more computer program instructions; The one or more computer program instructions are executed by the processor when executed by the processor. The instruction processing method according to any one of claims 10-18.

21. A computer-readable storage medium that non-transitorily stores computer-readable instructions, wherein: When the computer-readable instructions are executed by a processor, the instruction processing method according to any one of claims 10 to 18 is implemented.

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