Test case generation method, test device, electronic equipment and storage medium

Abstract

The invention provides a test case generation method, a test device, electronic equipment and a storage medium. The test case generation method comprises the following steps: acquiring a reference file according to a reference identifier in a test vector file; secondly, reading text contents of a plurality of subfiles referenced in the test vector file according to a start identifier and an end identifier in the reference file; then, combining the text contents of the plurality of sub-files and the test vector file into an intermediate file; and finally, compiling the intermediate file into a test case file. By means of the mode, the whole reference file and the test vector file do not need to be packaged into the intermediate file, the line number of the intermediate file is reduced, and therefore the compiling efficiency is improved while the compiling failure problem is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a test case generation method, a test device, an electronic device, and a storage medium. Background Art

[0002] At present, when it is necessary to test the memory, the corresponding test case file can be generated by an automatic test equipment (ATE). Among them, the test vector (pattern) file in the algorithmic pattern generator (ALPG) in the ATE is mainly used to load into the pattern generator (pattern generator) to generate the corresponding test case file, so as to test the memory for operations such as stimulation and reading. However, in the algorithmic pattern generator, the current file-based compilation system is prone to compilation failure when generating test case files according to the pattern file. Summary of the invention

[0003] The embodiments of the present disclosure provide a test case generation method, a test device, an electronic device and a storage medium, which are intended to solve the problem of compilation failure that is likely to occur when compiling test cases according to test vector files, while improving compilation efficiency.

[0004] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0005] In the first aspect, a test case generation method is provided. When the method is executed, the algorithm pattern generator in the integrated circuit automatic test machine can first obtain the test vector file to be compiled. The test vector file includes a reference identifier of the reference file and a description of the calling relationship between multiple sub-files in the reference file. Then, the text content of the multiple sub-files is obtained according to the reference identifier. Then, the text content of the multiple sub-files and the test vector file are merged into an intermediate file according to the above calling relationship. Finally, a test case file is generated according to the intermediate file. In the above manner, the algorithm pattern generator can directly obtain the required multiple sub-files from the reference file according to the reference identifier, and generate corresponding test case files according to the multiple sub-files and the test vector file, without packaging the entire reference file and the test vector file into an intermediate file, reducing the number of lines in the intermediate file, thereby reducing the compilation failure problem and improving the compilation efficiency.

[0006] In a possible implementation, when obtaining the text contents of multiple sub-files according to the reference identifier, the reference file can be read according to the reference identifier first. Then, the text contents of the multiple sub-files can be obtained according to the start identifier and the end identifier of each sub-file in the reference file. Based on this, the text contents of the multiple sub-files can be accurately read.

[0007] In a possible implementation, the reference identifier is a file reference function in a programming language corresponding to the test vector file. Based on this, it is possible to obtain the reference file more conveniently without constructing an additional reference identifier.

[0008] In a possible implementation, the calling relationship between multiple sub-files in the reference file is described by a calling identifier. The calling identifier is a calling function in the programming language corresponding to the test vector file. Based on this, the calling relationship between multiple sub-files in the reference file can be directly confirmed by calling the function, without the need to additionally configure the calling relationship between multiple sub-files, thereby improving the efficiency of confirming the calling relationship between multiple sub-files.

[0009] In a possible implementation, the calling relationship between multiple sub-files in the reference file is described by a calling table. The calling table includes the calling sub-files and the called sub-files in the multiple sub-files. By describing the calling relationship between multiple sub-files by means of a calling table, there is no need to create multiple calling functions, and the calling relationship between multiple sub-files can be configured more conveniently according to actual needs.

[0010] In a possible implementation, when generating a test case file according to an intermediate file, the intermediate file can be compiled into a binary format to generate a corresponding test case file. Because data is usually stored in a binary format, the above method eliminates the need to perform binary conversion on the test case file, thereby improving the access efficiency of the test case file.

[0011] In a possible implementation, the test case file includes a read instruction, a programming instruction and a pulse control instruction of the memory. In this way, multiple functions of the memory can be tested through one test case file, thereby improving the test efficiency.

[0012] In a second aspect, a test device is provided, which includes an acquisition unit, a reading unit, a merging unit and a compiling unit. The acquisition unit is used to acquire a test vector file to be compiled. The test vector file includes a reference identifier of a reference file and a description of a calling relationship between multiple subfiles in the reference file. The reading unit is used to acquire the text content of multiple subfiles according to the reference identifier. The merging unit is used to merge the text content of multiple subfiles with the test vector file into an intermediate file according to the calling relationship. The compiling unit is used to generate a test case file according to the intermediate file.

[0013] In a possible implementation, the reading unit is specifically configured to: read the reference file according to the reference identifier, and obtain text contents of the plurality of sub-files according to the start identifier and the end identifier of each sub-file in the reference file.

[0014] In a possible implementation, the reference identifier is a file reference function in a programming language corresponding to the test vector file.

[0015] In a possible implementation, the calling relationship between multiple sub-files in the reference file is described by a calling identifier, wherein the calling identifier is a calling function in the programming language corresponding to the test vector file.

[0016] In a possible implementation, the calling relationship between multiple sub-files in the reference file is described by a calling table, wherein the calling table includes a calling sub-file and a called sub-file in the multiple sub-files.

[0017] In a possible implementation, the compilation unit is specifically used to perform binary compilation on the intermediate file to generate a test case file.

[0018] In a possible implementation, the test case file includes a memory read instruction, a memory programming instruction, and a pulse control instruction.

[0019] In a third aspect, an electronic device is provided, which includes a memory and a processor coupled to the memory; the memory stores computer program instructions; when the computer program instructions are executed by the processor, the method in any possible implementation manner of the above-mentioned first aspect is implemented.

[0020] In a fourth aspect, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer program instructions. When the computer program instructions are executed by a processor, the method in any possible implementation of the first aspect is implemented.

[0021] In a fifth aspect, a computer program product is provided, which, when executed by a processor, implements a method in any possible implementation of the first aspect.

[0022] The beneficial effects that can be achieved in the second to fifth aspects mentioned above can refer to the beneficial effects of the first aspect and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic diagram of a compiling method of a test vector file in some implementation modes;

[0024] Figure 2 A flowchart of a test case generation method provided in an embodiment of the present application;

[0025] Figure 3 A schematic diagram of a calling relationship between sub-files provided in an embodiment of the present application;

[0026] Figure 4 A schematic diagram of a test vector file compilation method provided in an embodiment of the present application;

[0027] Figure 5 A schematic diagram of another test vector file compilation method provided in an embodiment of the present application;

[0028] Figure 6 A schematic diagram of the structure of a testing device provided in an embodiment of the present application;

[0029] Figure 7 A schematic diagram of the structure of a storage system provided in an embodiment of the present application;

[0030] Figure 8 A schematic diagram of the structure of another storage system provided in an embodiment of the present application;

[0031] Fig. 9 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0032] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0033] In the description of the present disclosure, unless the context requires otherwise, throughout the specification and claims, the term "including" is interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics described may be included in any one or more embodiments or examples in any appropriate manner.

[0034] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0035] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0036] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0037] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0038] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0039] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0040] Before a memory product is put into practical use, it is usually debugged. When testing the memory, the corresponding test case file can be generated by an automatic test equipment (ATE). The test vector (pattern) file in the algorithmic pattern generator (ALPG) in the ATE is mainly used to load into the pattern generator (pattern generator) to generate the corresponding test case file, so as to test the memory for operations such as stimulation and reading. The Pattern file is used to provide test instructions, test data, level and timing setting selections. It consists of a large number of test vector rows and generates stimulation signals. Usually, the Pattern file exists in text form and needs to be compiled by the compilation system to generate an executable target format for ATE (machine code recognizable by the device). For example Figure 1As shown, when compiling a pattern file, the current compilation system (such as a pattern generator) usually packages the pattern file and the reference file containing the sub-file (subpattern) into an intermediate file. Then, the corresponding test case file is compiled according to the intermediate file. Among them, the reference file (or subpattern file) includes multiple sub-files (subpattern). Each subpattern is used to indicate any one of the test instructions, test data, level and timing. However, the file-based compilation system will package all the sub-files in the pattern file and the reference file for compilation. In this way, a large number of useless subpatterns will be added to the intermediate file, resulting in the number of lines exceeding the limit, thereby causing the problem of compilation failure. In addition, from the perspective of code reuse, the underlying public subpattern is usually encapsulated for upper-level calls. The more functions the underlying subpattern covers, the more lines it occupies. If it is split into a file containing a subpattern, it will bring serious file organization and usage efficiency problems. In addition, as more and more functions need to be tested, the underlying public subpattern has occupied more than 1,400 lines (limited to 2,048 lines), resulting in the test pattern file of a certain functional group in the upper layer having to be split into multiple files to avoid compilation failure. However, if the pattern file and the reference files containing subpatterns are all packaged into an intermediate file, there will inevitably be a problem that a complex test pattern file cannot be compiled due to too many lines in the subpattern file. At present, in order to solve this problem, the pattern file is usually split into multiple files of the same family, or the reference file of the pattern file is split into multiple files. However, splitting files will increase the difficulty of file organization and reduce compilation efficiency.

[0041] In order to solve the above problems, Figure 2 As shown, an embodiment of the present application provides a test case generation method, and the specific execution process of the test case generation method is as follows.

[0042] S201. The processor obtains a test vector file to be compiled.

[0043] The test vector file includes a reference identifier of the reference file and a description of the calling relationship between multiple sub-files in the reference file.

[0044] In one example, the reference identifier is a file reference function in the programming language corresponding to the test vector file. The file reference function includes but is not limited to file reference functions commonly used in the field of computer technology such as include function and require function. The specific type can be determined according to the programming language actually used, and the embodiment of the present application does not impose specific restrictions on this.

[0045] In some embodiments, the calling relationship between multiple sub-files in the reference file can be described by a calling identifier. The calling identifier can be a calling function and a jump function in a programming language. For example, the text content of the first subpattern called in the reference file can be obtained by calling a function (CALL). Then, the subsequent subpatterns are obtained by jumping (JUMP) functions. By parsing the above instructions, the calling relationship (also called calling order) between multiple sub-files in the pattern file can be confirmed according to the order of calling.

[0046] Of course, the call instructions and jump instructions in the above implementation scheme are just examples given in the embodiments of the present application. When used, they can be configured according to the call instructions and jump instructions in the programming language actually used.

[0047] In some embodiments, the calling relationship between multiple subfiles in a reference file can be described by a calling table. Among them, the calling table may include calling subfiles and called subfiles in multiple subfiles. Exemplarily, assume that a certain reference file includes 13 subfiles such as subfile 1 to subfile 13, and there are currently three test vector files (test vector file 1 to test vector file 3) that need to be compiled. Among them, test vector file 1 first references subfile 1 and subfile 3, subfile 1 references subfile 9 and subfile 13, and subfile 3 references subfile 9. Test vector file 2 is first referenced as subfile 1, and subfile 1 references subfile 9 and subfile 13. Test vector file 3 is first referenced as subfile 4, and subfile 4 references subfile 9. The corresponding calling relationship is as follows Figure 3 As shown. The call table constructed according to the above call relationship is shown in Table 1. The call table can be pre-configured by the tester according to the test requirements and stored in the memory. The call table can also be read in the test vector file by setting the call instruction, and the call relationship between multiple sub-files can be parsed according to the call table.

[0048] Table 1

[0049]

[0050] Of course, the above-mentioned call table is only an example given in the embodiment of the present application. When used specifically, the tester can perform it according to various conventional settings in the field, and the embodiment of the present application does not make specific restrictions on this.

[0051] S202. The processor obtains text contents of multiple sub-files according to the reference identifier.

[0052] In some embodiments, the processor may first read the reference file according to the reference identifier. The processor may parse the test vector file to obtain the reference identifier, and read the reference file from the corresponding storage address through the reference identifier. Then, the text content of the multiple sub-files is obtained according to the start identifier and the end identifier of each sub-file in the reference file. Figure 1 Take the reference file in as an example. The start mark of each sub-file is SUB PAT START, and the end mark is SUB PAT END. Therefore, after obtaining the reference file, the text content of each sub-file can be obtained according to the above start mark and end mark to accurately separate each sub-file from the reference file.

[0053] In the above implementation process, the start mark and end mark of the above sub-file are only an example given in the embodiment of the present application. During actual testing, the tester can customize it according to actual needs.

[0054] S203. The processor merges the text contents of the multiple sub-files and the test vector file into an intermediate file according to the calling relationship.

[0055] After the text contents of multiple sub-files are obtained, the text contents of the multiple sub-files and the test vector file can be merged into an intermediate file according to the calling relationship between the multiple sub-files.

[0056] S204. Generate a test case file based on the intermediate file.

[0057] The test case file includes various control instructions such as read instructions, programming instructions and pulse control instructions of the memory to be tested, as well as voltage and timing when executing the above control instructions. The specific content can be adjusted according to actual test requirements.

[0058] In some implementation schemes, when generating a test case file from an intermediate file, the intermediate file may be compiled into a binary format to generate a binary test case file. Because data in the computer field is usually stored in a binary format, the above method eliminates the need to perform binary conversion on the test case file, thereby improving the access efficiency of the test case file.

[0059] Of course, when compiling the intermediate file, octal, hexadecimal, etc. compilation methods may also be used, and the present application embodiment does not impose specific restrictions on this. When testing the memory, if octal, hexadecimal, etc. are used for compilation, the obtained test case file can be converted into a binary file before testing the memory.

[0060] In order to more clearly understand the technical solution of the present application, the present application provides the following two embodiments to illustrate the above test case generation method.

[0061] Embodiment 1

[0062] like Figure 4 As shown, it is assumed that a subfile SUB_AAA is referenced by a call instruction (CALL) in a test vector file. The reference file includes subfile SUB_AAA, subfile SUB_BBB and subfile SUB_CCC, then the text content from the start mark to the end mark of the test vector file and subfile SUB_AAA can be merged into an intermediate file. Then, binary compilation is performed based on the intermediate file to obtain the corresponding test case file. In the above manner, the intermediate file does not need to include the text content corresponding to the subfile SUB_CCC and the subfile SUB_BBB, which reduces the number of compiled lines, thereby reducing the probability of compilation failure and improving compilation efficiency.

[0063] Embodiment 2

[0064] like Figure 5 As shown, it is assumed that a test vector file references a subfile SUB_AAA through a call instruction (CALL). The subfile SUB_AAA references the subfile SUB_CCC through a jump instruction (JUMP). The reference file includes subfile SUB_AAA, subfile SUB_BBB and subfile SUB_CCC. Then, the text content from the start mark to the end mark of the test vector file and the subfile SUB_AAA, and the text content from the start mark to the end mark of the subfile SUB_CCC can be merged into an intermediate file. Then, binary compilation is performed according to the intermediate file to obtain the corresponding test case file. In the above manner, the intermediate file does not need to include the text content corresponding to the subfile SUB_BBB, and the number of compiled lines is reduced, thereby reducing the probability of compilation failure and improving compilation efficiency.

[0065] The above embodiments are only used to illustrate the situation that a plurality of subfiles are included in the reference file. The number of subfiles quoted by the test vector file and the total number of subfiles in the reference file can be adjusted according to actual needs, and the embodiments of the present application do not make specific restrictions on this. In addition, since there are more and more functions to be tested, the underlying public subpattern has occupied more than 1400 lines at present. If the test case generation method provided by the embodiments of the present application is adopted, the useless subfiles in the reference file (subpattern file) can be eliminated before compiling, so that only the subfiles actually quoted by the test vector file are included in the intermediate file. Based on this, the number of compiled lines of the intermediate file will be greatly reduced during compilation, which can better solve the problem of compilation failure caused by too many compiled lines of the intermediate file, and even if the subfiles in the reference file continue to increase with the increase of functions in the subsequent period, the problem of compilation failure will not be caused.

[0066] In some embodiments, such as Figure 6 As shown, an embodiment of the present application also provides a test device 600, which includes an acquisition unit 610, a reading unit 620, a merging unit 630 and a compiling unit 640. The acquisition unit 610 is used to obtain a test vector file to be compiled. The test vector file includes a reference identifier of a reference file and a description of a calling relationship between multiple sub-files in the reference file. The reading unit 620 is used to obtain the text content of multiple sub-files according to the reference identifier. The merging unit 630 is used to merge the text content of multiple sub-files with the test vector file into an intermediate file according to the calling relationship. The compiling unit 640 is used to generate a test case file based on the intermediate file.

[0067] In some embodiments, the reading unit 620 is specifically used to read the reference file according to the reference identifier, and then obtain the text content of multiple sub-files according to the start identifier and the end identifier of each sub-file in the reference file.

[0068] In some embodiments, the reference identifier is a file reference function in the programming language corresponding to the test vector file, wherein the file reference function includes but is not limited to the include function, require function and other file reference functions commonly used in the field of computer technology.

[0069] In some embodiments, the calling relationship between multiple sub-files in the reference file is described by a calling identifier. The calling identifier is a calling function in the programming language corresponding to the test vector file. For example, the calling function includes but is not limited to the calling functions commonly used in the field of computer technology such as CALL function and JUMP function.

[0070] In some embodiments, the calling relationship between multiple sub-files in the reference file is described by a calling table, wherein the calling table includes the calling sub-file and the called sub-file in the multiple sub-files.

[0071] In some implementation schemes, the compiling unit 640 is specifically used to perform binary compilation on the intermediate file to generate a test case file, wherein the test case file includes a memory read instruction, a programming instruction, a pulse control instruction, and the like.

[0072] In some implementation schemes, the test case file generated by the test case generation method described above can be used to test the storage system to be tested. Figure 7 As shown, the storage system 700 may include a controller 710 and a memory 720 , and the storage system 700 may be integrated into a memory card.

[0073] Among them, the memory card includes any one of PC card (PCMCIA, Personal Computer Memory Card International Association), compact flash (CF) card, smart media (SM) card, memory stick, multimedia card (MMC), secure digital (SD) card, and UFS.

[0074] In other embodiments, Figure 8 As shown, the storage system 700 includes a controller 710 and a plurality of memories 720, and the storage system 700 is integrated into a solid state drive (SSD). In some embodiments, the controller 710 is configured to operate in a low duty cycle environment, for example, an SD card, a CF card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones. In other embodiments, the controller 710 is configured to operate in a high duty cycle environment SSD or eMMC, which is used for data storage in mobile devices such as smart phones, tablets, and laptops, as well as enterprise storage arrays.

[0075] In some embodiments, the controller 710 may be configured to manage data stored in the memory 720 and communicate with an external device (e.g., a host). In some embodiments, the controller 710 may also be configured to control operations of the memory 720, such as read, erase, and program operations. In some embodiments, the controller 710 may also be configured to manage various functions regarding data stored or to be stored in the memory 720, including at least one of bad block management, garbage collection, logical to physical address conversion, and wear leveling. In some embodiments, the controller 710 is also configured to process error correction codes regarding data read from or written to the memory 720. In order to ensure that the controller 710 can correctly perform the above-mentioned various operations, the test case file may include instructions (e.g., read instructions, programming instructions, and pulse control instructions) when the controller 710 performs the above-mentioned series of operations, signal timing, level, etc., so that the various functions of the memory 720 or the memory system 700 can be tested.

[0076] Of course, the controller may also perform any other suitable functions, such as formatting a memory; for example, the controller may communicate with an external device (eg, a host) via at least one of various interface protocols.

[0077] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer interface (SCSI) protocol, enhanced minidisk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, and Firewire protocol.

[0078] like Fig. 9 As shown, some embodiments of the present application also provide an electronic device 900. The electronic device 900 includes a processor 910 (e.g., a central processing unit (CPU)) and a memory 920. The processor 910 can be coupled to the storage system 700 described above. The memory 920 can be used to store program instructions. When the processor 910 executes the program instructions, the above-mentioned test case generation method can be implemented to obtain a corresponding test case file. The test case file can be sent to a controller in the storage system 700 for execution. The electronic device 900 can be an automated testing machine or other processing device with the same or similar functions as an automated testing machine.

[0079] The embodiment of the present application also provides a computer-readable storage medium, which includes instructions; when the instructions are executed on the processor described in the above embodiment, the processor executes the test case generation method described in the above embodiment. When the instructions are executed on the electronic device described in the above embodiment, the electronic device executes the test case generation method described in the above embodiment.

[0080] The embodiment of the present application also provides a computer program product, when the computer program product is run on the processor described in the above embodiment, the processor is caused to execute the test case generation method described in the above embodiment. When the computer program product is run on a computer, the computer is caused to execute the test case generation method described in the above embodiment.

[0081] The processor involved in the embodiments of the present application may be a chip. For example, it may be a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on chip (SoC), a central processor unit (CPU), a network processor (NP), a digital signal processor (DSP), a microcontroller unit (MCU), a programmable logic device (PLD), or other integrated chips.

[0082] The memory involved in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct RAM (DR RAM). It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0083] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0084] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0085] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0086] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0087] The units described as separate components may or may not be physically separated, and the components shown may or may not be physical modules, that is, they may be located in one device or distributed on multiple devices. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0088] In addition, each functional unit in each embodiment of the present application may be integrated into one device, or each unit may exist physically separately, or two or more units may be integrated into one device.

[0089] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using a software program, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium may be any available medium that a computer can access or may contain one or more servers, data centers and other data storage devices that can be integrated with the medium. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (eg, a solid state disk (SSD)).

[0090] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A test case generation method, characterized in that: The method comprises: Obtaining a test vector file to be compiled; the test vector file includes a reference identifier of a reference file and a description of a calling relationship between multiple subfiles in the reference file; Acquire the text contents of the plurality of sub-files according to the reference identifiers; Merging the text contents of the plurality of sub-files and the test vector file into an intermediate file according to the calling relationship; Generate a test case file according to the intermediate file.

2. The method according to claim 1, characterized in that Acquiring text contents of the plurality of sub-files according to the reference identifiers includes: Read the reference file according to the reference identifier; The text contents of the plurality of sub-files are acquired according to the start identifier and the end identifier of each sub-file in the reference file.

3. The method according to claim 1, characterized in that The reference identifier is a file reference function in the programming language corresponding to the test vector file.

4. The method according to any one of claims 1 to 3, characterized in that: The calling relationship between the multiple sub-files in the reference file is described by a calling identifier; the calling identifier is a calling function in the programming language corresponding to the test vector file.

5. The method according to any one of claims 1 to 3, characterized in that: The calling relationship between the multiple sub-files in the reference file is described by a calling table; the calling table includes the calling sub-file and the called sub-file in the multiple sub-files.

6. The method according to claim 1, characterized in that Generating a test case file according to the intermediate file includes: The intermediate file is binary compiled to generate the test case file.

7. The method according to claim 1, characterized in that The test case file includes memory read instructions, programming instructions and pulse control instructions.

8. A testing device, characterized in that: include: An acquisition unit, used for acquiring a test vector file to be compiled; wherein the test vector file includes a reference identifier of a reference file and a description of a calling relationship between multiple subfiles in the reference file; A reading unit, configured to obtain text contents of the plurality of sub-files according to the reference identifiers; A merging unit, used for merging the text contents of the plurality of sub-files and the test vector file into an intermediate file according to the calling relationship; The compiling unit is used to generate a test case file according to the intermediate file.

9. The testing device according to claim 8, characterized in that: The reading unit is specifically used for: Read the reference file according to the reference identifier; The text contents of the plurality of sub-files are acquired according to the start identifier and the end identifier of each sub-file in the reference file.

10. The testing device according to claim 8, characterized in that: The reference identifier is a file reference function in the programming language corresponding to the test vector file.

11. The testing device according to any one of claims 8 to 10, characterized in that: The calling relationship between the multiple sub-files in the reference file is described by a calling identifier; the calling identifier is a calling function in the programming language corresponding to the test vector file.

12. The testing device according to any one of claims 8 to 10, characterized in that: The calling relationship between the multiple sub-files in the reference file is described by a calling table; the calling table includes the calling sub-file and the called sub-file in the multiple sub-files.

13. The testing device according to claim 8, characterized in that: The compilation unit is specifically used for: The intermediate file is binary compiled to generate the test case file.

14. The testing device according to claim 8, characterized in that: The test case file includes memory read instructions, programming instructions and pulse control instructions.

15. An electronic device, characterized in that: The method comprises a memory and a processor coupled to the memory; the memory stores computer program instructions; and when the computer program instructions are executed by the processor, the method according to any one of claims 1 to 7 is implemented.

16. A computer-readable storage medium, characterized in that: Computer program instructions are stored; when the computer program instructions are executed by the processor, the method according to any one of claims 1 to 7 is implemented.

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