Command bus training method, electronic equipment, medium and command bus training device

Abstract

The invention relates to the technical field of computers and provides a command bus training method, electronic equipment, a medium and a command bus training device. Through optimization on hardware, a command address remapping module, a data remapping module and a delay training module are provided, and through optimization on software, time delay of command address signals is adjusted based on a central point algorithm through the delay training module, so that alignment between the command address signals and data signals is realized; not only can the requirements of low-power fifth-generation double rate and related memory technical specifications in the aspects of state alignment and synchronization be met, but also the adverse effects of pin layout and wiring after chip packaging can be effectively overcome, and the adverse effects caused by existence of a metastable state interval can be effectively overcome; the alignment relation is quickly and reliably determined, the optimal center position is positioned, the training effect is improved, the overall training delay is reduced, and quick response and equipment adaptation are facilitated.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a command bus training method, electronic equipment, medium and command bus training device. Background Art

[0002] Double Data Rate 5 (DDR5) is a memory technology specification used to improve data flow channels and data transmission efficiency. Low Power Double Data Rate 5 (LPDDR5), or LPDDR5, adds low power (LP) to DDR5, which means lower power consumption and smaller size. LPDDR5 has the characteristics of DDR, that is, double data rate, which means that data is transmitted on both the rising and falling edges of the signal, that is, each clock cycle completes twice the amount of data transmission of synchronous dynamic random access memory (SDRAM). LPDDR5 is used in mobile devices such as smartphones and smart watches or in-vehicle intelligence and other application fields that are sensitive to power consumption and size. The clock scheme of LPDDR5 adopts a dual clock signal design, which is different from the single clock signal design adopted by the clock scheme of DDR5. It can help improve the effective rate of the data bus, but it also brings challenges in state alignment and synchronization. In order to meet the requirements of the clock scheme of LPDDR5 for state alignment and synchronization, command bus training (CBT) is used to achieve alignment between signals. However, the command bus training scheme in the prior art is affected by the pin layout and routing after chip packaging, and relies on asynchronous signal feedback to determine the alignment relationship during the training process. In addition, due to the existence of the metastable interval, there is a deviation in position determination, resulting in poor training results and high overall training delay, which is not conducive to rapid response and device adaptation.

[0003] To this end, the present application provides a command bus training method, electronic device, medium and command bus training device, which can not only meet the requirements of low-power fifth-generation double-rate and related memory technical specifications in terms of state alignment and synchronization, but also effectively overcome the adverse effects of pin layout and routing after chip packaging, effectively overcome the adverse effects of the existence of metastable intervals, quickly and reliably determine the alignment relationship and locate the optimal center position, improve training effects and reduce overall training delays, and facilitate rapid response and device adaptation. Summary of the invention

[0004] In a first aspect, the present application provides a command bus training method. The command bus training method comprises: mapping multiple command address bus pins of a storage module to be trained to standard command address bus pins of a standard storage module one by one through a command address remapping module; mapping multiple data bus pins of the storage module to be trained to standard data bus pins of the standard storage module one by one through a data remapping module, wherein a first connection relationship is satisfied between the multiple command address bus pins of the storage module to be trained and the multiple data bus pins of the storage module to be trained, and a second connection relationship is satisfied between the standard command address bus pins of the standard storage module and the standard data bus pins of the standard storage module; determining the asynchronous signal feedback source corresponding to each of the multiple command address bus pins of the storage module to be trained when each is called based on the first connection relationship and the second connection relationship through a delay training module, and then adjusting the delay of each of the command address signals corresponding to each of the multiple command address bus pins of the storage module to be trained based on a center point algorithm, thereby achieving alignment between the command address signals corresponding to each of the multiple command address bus pins of the storage module to be trained and the data signals corresponding to each of the multiple data bus pins of the storage module to be trained.

[0005] Through the first aspect of the present application, not only can the requirements of the low-power fifth-generation double-rate and related memory technical specifications in terms of state alignment and synchronization be met, but also the adverse effects of the pin layout and routing after chip packaging can be effectively overcome, and the adverse effects of the existence of the metastable interval can be effectively overcome. The alignment relationship and the optimal center position can be quickly and reliably determined, the training effect can be improved, and the overall training delay can be reduced, which is conducive to rapid response and device adaptation.

[0006] In a possible implementation of the first aspect of the present application, the multiple command address bus pins of the storage module to be trained include a first command address bus pin, and the first command address bus pin is connected to a first data bus pin among the multiple data bus pins of the storage module to be trained based on the first connection relationship. The delay training module adjusts the delay of the first command address signal corresponding to the first command address bus pin based on the center point algorithm, thereby achieving alignment between the first command address signal corresponding to the first command address bus pin and the first data signal corresponding to the first data bus pin.

[0007] In a possible implementation of the first aspect of the present application, the delay training module adjusts the delay of the first command address signal corresponding to the first command address bus pin based on the center point algorithm, thereby achieving alignment between the first command address signal corresponding to the first command address bus pin and the first data signal corresponding to the first data bus pin, including: the delay training module determines the left boundary of the first command address signal using the first function of the center point algorithm, and determines the right boundary of the first command address signal using the second function of the center point algorithm, and then determines the center point position of the first command address signal based on the determined left boundary of the first command address signal and the determined right boundary of the first command address signal, and then adjusts the delay of the first command address signal based on the determined center point position of the first command address signal.

[0008] In a possible implementation of the first aspect of the present application, the first function of the center point algorithm is used to sequentially scan the error position of the left boundary of the first command address signal, the metastable position of the left boundary of the first command address signal, and the steady-state position of the left boundary of the first command address signal, and the second function of the center point algorithm is used to sequentially scan the error position of the right boundary of the first command address signal, the metastable position of the right boundary of the first command address signal, and the steady-state position of the right boundary of the first command address signal.

[0009] In a possible implementation of the first aspect of the present application, the delay training module uses the first function of the center point algorithm to determine the left boundary of the first command address signal, including: when the first data signal is fed back as a low level and the clock signal does not collect the first command address signal, increasing the delay of the first command address signal; when the first data signal is fed back as a high level and the clock signal collects the first command address signal, maintaining the delay of the first command address signal.

[0010] In a possible implementation of the first aspect of the present application, the delay training module uses the second function of the center point algorithm to determine the right boundary of the first command address signal, including: when the first data signal is fed back as a low level and the clock signal does not collect the first command address signal, reducing the delay of the first command address signal; when the first data signal is fed back as a high level and the clock signal collects the first command address signal, maintaining the delay of the first command address signal.

[0011] In a possible implementation of the first aspect of the present application, the delay training module uses the first function of the center point algorithm to determine the left boundary of the first command address signal, and also includes: initially setting the delay of the first command address signal to a first initial delay, and then using the first function of the center point algorithm to perform a first number of loop searches; the delay training module uses the second function of the center point algorithm to determine the right boundary of the first command address signal, and also includes: initially setting the delay of the first command address signal to a second initial delay, and then using the first function of the center point algorithm to perform a second number of loop searches, wherein the first initial delay is less than the second initial delay.

[0012] In a possible implementation of the first aspect of the present application, the first loop search number and the second loop search number are both determined based on the maximum frequency of the clock signal, the first initial delay corresponds to a single step unit, the step unit is determined based on the maximum frequency of the clock signal, and the second initial delay corresponds to multiple step units.

[0013] In a possible implementation of the first aspect of the present application, the multiple command address bus pins of the storage module to be trained include command address bus pins for a first data channel and command address bus pins for a second data channel, and the standard command address bus pins of the standard storage module corresponding to the command address bus pins for the first data channel are different from the standard command address bus pins of the standard storage module corresponding to the command address bus pins for the second data channel.

[0014] In a possible implementation of the first aspect of the present application, the multiple data bus pins of the storage module to be trained include paired data bus pins, the paired data bus pins are used for differential signal transmission, and the standard data bus pins of the standard storage module corresponding to the paired data bus pins are used for differential signal transmission.

[0015] In a possible implementation manner of the first aspect of the present application, the first connection relationship and the second connection relationship are determined based on a computer memory specification associated with the storage module to be trained.

[0016] In a possible implementation of the first aspect of the present application, the computer memory specification is a low power fifth generation double rate, Internet Protocol version 4, a design specification of a data processing unit, or a design specification of an image processing unit.

[0017] In a second aspect, an embodiment of the present application further provides a computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements a method according to any one of the implementation modes of any of the above aspects when executing the computer program.

[0018] In a third aspect, an embodiment of the present application further provides a computer-readable storage medium, which stores computer instructions. When the computer instructions are executed on a computer device, the computer device executes a method according to any one of the implementation methods of any of the above aspects.

[0019] In a fourth aspect, an embodiment of the present application further provides a computer program product, which includes instructions stored on a computer-readable storage medium, and when the instructions are executed on a computer device, the computer device executes a method according to any one of the implementation methods of any of the above aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 A flowchart of a command bus training method provided in an embodiment of the present application;

[0022] Figure 2 A schematic diagram of a command bus training device provided in an embodiment of the present application;

[0023] Figure 3 A schematic diagram of the structure of a computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0024] The embodiments of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0025] It should be understood that, in the description of this application, "at least one" means one or more, and "a plurality of" means two or more. In addition, unless otherwise specified, the words "first", "second", etc. are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying an order.

[0026] Figure 1 A flowchart of a command bus training method provided in an embodiment of the present application. Figure 1As shown, the command bus training method includes the following steps.

[0027] Step S101: Mapping a plurality of command address bus pins of a storage module to be trained to standard command address bus pins of a standard storage module one by one through a command address remapping module.

[0028] Step S103: Mapping the multiple data bus pins of the storage module to be trained to the standard data bus pins of the standard storage module one by one through the data remapping module, wherein a first connection relationship is satisfied between the multiple command address bus pins of the storage module to be trained and the multiple data bus pins of the storage module to be trained, and a second connection relationship is satisfied between the standard command address bus pins of the standard storage module and the standard data bus pins of the standard storage module.

[0029] Step S105: Determine, through the delay training module, based on the first connection relationship and the second connection relationship, the asynchronous signal feedback sources corresponding to the multiple command address bus pins of the storage module to be trained when each is called, and then adjust the delay of the command address signal corresponding to each of the multiple command address bus pins of the storage module to be trained based on the center point algorithm, so as to achieve alignment between the command address signal corresponding to each of the multiple command address bus pins of the storage module to be trained and the data signal corresponding to each of the multiple data bus pins of the storage module to be trained.

[0030] Figure 1The command bus training method shown can be applied to memory technology specifications such as LowPower Double Data Rate 5 (LPDDR5). LPDDR5 is based on the fifth generation double data rate (Double Data Rate 5, DDR5) and adds low power (LP), which means lower power consumption and smaller size. LPDDR5 has the characteristics of DDR, that is, double data rate, which means that data transmission is performed on both the rising edge and the falling edge of the signal, that is, each clock cycle completes twice the amount of data transmission of synchronous dynamic random access memory (SDRAM). LPDDR5 is used in mobile devices such as smartphones and smart watches or in-vehicle intelligence and other application fields that are sensitive to power consumption and volume. The clock scheme of LPDDR5 adopts a dual clock signal design, which is different from the single clock signal design adopted by the clock scheme of DDR5, which can help improve the effective rate of the data bus, but also brings challenges in state alignment and synchronization. Specifically, LPDDR5 defines a command address (CA) bus and a clock (CK) signal. The command address bus is used to transfer from the host to the device, and the clock signal is used to set the transfer rate from the host's central processor to the DDR. Before LPDDR5, a single clock signal was used, and the command address bus was a single data rate SDR bus. Therefore, in the clock scheme before LPDDR5, the clock signal and the data strobe (DQS) signal had the same frequency, and the maximum transfer rate of the command address bus corresponded to the maximum rate operation of the clock signal and the DQS signal at the highest frequency. The maximum transfer rate of the data (Data, DQ) bus is twice the maximum transfer rate of the command address bus (the DDR bus transmits two data packets in the next clock cycle). For example, the maximum frequency of the clock signal is 2133 megahertz (MHz), the maximum frequency of the DQS signal is 2133MHz, the maximum effective rate of the command address bus is 2133 megabits per second (Mbps), and the maximum effective rate of the data bus is 4266Mbps. LPDDR5 introduces a dual clock signal design, providing two signals, one is the write clock (WCK) signal from the host to the device, and the other is the read data (Read DQS, RDQS) signal from the device to the host. The clock scheme of LPDDR5 realizes the decoupling between the data selection signal, that is, the RDQS signal, and the clock signal, which allows the frequency of the clock signal to be significantly lower than the frequency of the RDQS signal.For example, the maximum frequency of the clock signal is 800MHz, the maximum frequency of the RDQS signal is 3200MHz, the maximum effective rate of the command address bus is 1600Mbps, and the maximum effective rate of the data bus is 6400Mbps. Therefore, the clock scheme used in the low-power fifth-generation double-rate and related memory technology specifications decouples the clock signal and the data selection signal, and also decouples the clock signal and the write clock signal. The frequency of the write clock signal can be twice or four times the frequency of the clock signal, but it also brings challenges in state alignment and synchronization. In addition, the routing between memory particles, such as dynamic random access memory (dynamic RAM, DRAM) particles and the command address bus and data bus of the system chip may not correspond one to one. Therefore, it is necessary to consider the impact of the pin layout and routing on the command bus training after the chip is packaged. Figure 1 The command bus training method shown, through hardware optimization, provides a command address remapping module, a data remapping module and a delay training module, and through software optimization, adjusts the delay of the command address signal based on the center point algorithm through the delay training module, thereby realizing the alignment between the command address signal and the data signal. It can not only meet the requirements of the low-power fifth-generation double rate and related memory technical specifications in terms of state alignment and synchronization, but also effectively overcome the adverse effects of the pin layout and routing after chip packaging, effectively overcome the adverse effects of the existence of the metastable interval, quickly and reliably determine the alignment relationship and locate the best center position, improve the training effect and reduce the overall training delay, and facilitate rapid response and device adaptation. The following is combined with Figure 1 Further details are given.

[0031] refer to Figure 1In step S101, a command address remapping module is used to map multiple command address bus pins of the storage module to be trained to standard command address bus pins of the standard storage module. In step S103, a data remapping module is used to map multiple data bus pins of the storage module to be trained to standard data bus pins of the standard storage module. A first connection relationship is satisfied between multiple command address bus pins of the storage module to be trained and multiple data bus pins of the storage module to be trained, and a second connection relationship is satisfied between standard command address bus pins of the standard storage module and standard data bus pins of the standard storage module. In the command bus training process, when it is necessary to determine the delay of a certain command address bus, it is necessary to determine which data signal line the feedback result comes from, so as to adjust the circuit delay of the command address bus according to the feedback result, and when finding the boundary of the address bus signal, it is necessary to consider the uncertainty of the electronic circuit signal in the boundary delay sampling, for example, when the clock signal is used to sample the command address signal, there is a metastable interval on the left boundary and the right boundary, which will lead to inaccurate positioning of the left and right boundaries, and thus may lead to deviation in the positioning of the optimal center point position. In addition, the storage module to be trained may adopt various memory technology specifications, have different product models and packaging specifications, so the number and distribution of pins on the storage module to be trained may be complex and changeable. For example, LPDDR5 generally specifies 7 command address bus pins, and Internet Protocol Version 4 (IPV4) generally specifies 8 command address bus pins. For another example, a dedicated processor may have customized requirements for the pin distribution and bus design on its storage module, such as a graphics processing unit (GPU) and a data processing unit (DPU). To this end, through hardware optimization, a command address remapping module and a data remapping module are provided, which are equivalent to any pin distribution and packaging design specifications on the storage module to be trained, and are mapped to a hypothetical standard storage module, including mapping multiple command address bus pins of the storage module to be trained to the standard command address bus pins of the standard storage module one by one through the command address remapping module, and including mapping multiple data bus pins of the storage module to be trained to the standard data bus pins of the standard storage module one by one through the data remapping module. In this way, the signal transmission and alignment problems to be solved by the storage module to be trained through command bus training are transformed into signal transmission and alignment problems of the standard storage module. In this way, through software optimization, the delay training module can be used to adjust the delay of the command address signal based on the center point algorithm, thereby achieving alignment between the command address signal and the data signal.In the face of the inconsistency problem between the command address bus pin and the data bus pin, the above-mentioned command address remapping module and data remapping module can be used to overcome the inconsistency problem through the first connection relationship and the second connection relationship. For example, for a specific command address bus CA0, first determine that the specific command address bus CA0 is connected to a standard command address bus pin (such as CAX) of the standard storage module through the command address remapping module, and the standard command address bus pin (CAX) is fed back through the standard data bus pin (such as DQX), and the standard data bus pin (DQX) is remapped by the data remapping module, and finally, DQ0 or DQ5 actually provides asynchronous signal feedback. Through the command address remapping module and the data remapping module, the first connection relationship can be flexibly adapted, and the subsequent center point algorithm can be optimized in combination with the second connection relationship. Therefore, it is not only conducive to adapting to the product models and packaging specifications of various storage modules to be trained, but also simplifies the difficulty of hardware and software collaborative design, so that software-level optimization can be carried out for the second connection relationship and the standard storage module, and various sampling optimization algorithms such as the center point algorithm are used to improve the training effect of the standard storage module. In addition, the delay training module can be implemented using a programmable device, firmware, or a circuit algorithm.

[0032] Continue to refer Figure 1In step S105, the asynchronous signal feedback sources corresponding to the multiple command address bus pins of the storage module to be trained are determined based on the first connection relationship and the second connection relationship through the delay training module, and then the delay of the command address signals corresponding to the multiple command address bus pins of the storage module to be trained is adjusted based on the center point algorithm, so as to achieve the alignment between the command address signals corresponding to the multiple command address bus pins of the storage module to be trained and the data signals corresponding to the multiple data bus pins of the storage module to be trained. In this way, on the basis of the above-mentioned construction of the assumed standard storage module through the command address remapping module and the data remapping module, the command bus training result of the standard storage module can be used for the signal transmission and alignment of the storage module to be trained, that is, the first connection relationship of the actual storage module to be trained is converted into the second connection relationship of the standard storage module, and then, based on the first connection relationship and the second connection relationship, the asynchronous signal feedback sources corresponding to the multiple command address bus pins of the storage module to be trained can be conveniently determined when they are called. For example, for a specific command address bus CA0, first determine that the specific command address bus CA0 is connected to a standard command address bus pin (such as CAX) of the standard storage module through the command address remapping module, and the standard command address bus pin (CAX) is fed back through the standard data bus pin (such as DQX), and the standard data bus pin (DQX) is remapped by the data remapping module, and finally it is DQ0 that actually provides asynchronous signal feedback, or it may be DQ5. This means that through the command address remapping module and the data remapping module, the first connection relationship can be flexibly adapted, and the subsequent center point algorithm can be optimized in combination with the second connection relationship. Therefore, it is not only conducive to adapting to the product models and packaging specifications of various storage modules to be trained, but also simplifies the difficulty of hardware and software collaborative design, so that software-level optimization can be performed for the second connection relationship and the standard storage module. In this way, the center point algorithm can better optimize the deviation of the optimal center point position caused by the existence of the metastable interval, which helps to improve the timeliness and accuracy of training. In this way, through hardware optimization, a command address remapping module, a data remapping module and a delay training module are provided. Through software optimization, the delay of the command address signal is adjusted based on the center point algorithm through the delay training module, thereby realizing the alignment between the command address signal and the data signal. This can not only meet the requirements of the low-power fifth-generation double rate and related memory technical specifications in terms of state alignment and synchronization, but also effectively overcome the adverse effects of the pin layout and routing after chip packaging, and effectively overcome the adverse effects of the existence of the metastable interval, quickly and reliably determine the alignment relationship and locate the optimal center position, improve the training effect and reduce the overall training delay, and contribute to rapid response and device adaptation.

[0033] Figure 2 A schematic diagram of a command bus training device provided in an embodiment of the present application. Figure 2 As shown, the command bus training device 200 is applied to the storage module 201 to be trained. The command bus training device 200 includes a command address remapping module 211, a data remapping module 213 and a delay training module 215. The command bus training method associated with the storage module 201 to be trained by the command bus training device 200 includes: mapping multiple command address bus pins of the storage module 201 to be trained to standard command address bus pins of a standard storage module one by one by the command address remapping module 211; mapping multiple data bus pins of the storage module 201 to standard data bus pins of the standard storage module one by one by the data remapping module 213, wherein the multiple command address bus pins of the storage module 201 to be trained and the multiple data bus pins of the storage module 201 to be trained satisfy a first connection relationship, and the standard command address bus pins of the standard storage module Make the address bus pins and the standard data bus pins of the standard storage module satisfy the second connection relationship; through the delay training module 215, based on the first connection relationship and the second connection relationship, determine the asynchronous signal feedback sources corresponding to the multiple command address bus pins of the storage module to be trained 201 when they are each called, and then adjust the delay of the command address signal corresponding to the multiple command address bus pins of the storage module to be trained 201 based on the center point algorithm, so as to achieve alignment between the command address signals corresponding to the multiple command address bus pins of the storage module to be trained 201 and the data signals corresponding to the multiple data bus pins of the storage module to be trained 201.

[0034] Figure 2 The command bus training device 200 shown, through hardware optimization, provides a command address remapping module 211, a data remapping module 213 and a delay training module 215, and through software optimization, through the delay training module 215, adjusts the delay of the command address signal based on the center point algorithm, thereby realizing the alignment between the command address signal and the data signal, which can not only meet the requirements of the low-power fifth-generation double rate and related memory technical specifications in terms of state alignment and synchronization, but also effectively overcome the adverse effects of the pin layout and routing after chip packaging, effectively overcome the adverse effects brought by the existence of the metastable interval, quickly and reliably determine the alignment relationship and locate the optimal center position, improve the training effect and reduce the overall training delay, and contribute to rapid response and device adaptation.

[0035] refer to Figure 1 and Figure 2In a possible implementation, the plurality of command address bus pins of the storage module to be trained include a first command address bus pin, the first command address bus pin is connected to a first data bus pin among the plurality of data bus pins of the storage module to be trained based on the first connection relationship, and the delay training module adjusts the delay of the first command address signal corresponding to the first command address bus pin based on the center point algorithm, thereby realizing alignment between the first command address signal corresponding to the first command address bus pin and the first data signal corresponding to the first data bus pin. Here, the first command address bus pin is any command address bus among the plurality of command address bus pins of the storage module to be trained. On the basis of constituting an assumed standard storage module through the command address remapping module and the data remapping module, the result of command bus training of the standard storage module can be used for signal transmission and alignment of the storage module to be trained, that is, the first connection relationship of the actual storage module to be trained is converted into the second connection relationship of the standard storage module, and then, based on the first connection relationship and the second connection relationship, the asynchronous signal feedback source corresponding to each of the plurality of command address bus pins of the storage module to be trained when they are called can be conveniently determined. For example, for a specific command address bus CA0, first determine that the specific command address bus CA0 is connected to a standard command address bus pin (such as CAX) of the standard storage module through the command address remapping module, and the standard command address bus pin (CAX) is fed back through the standard data bus pin (such as DQX), and the standard data bus pin (DQX) is remapped by the data remapping module, and finally it is DQ0 that actually provides asynchronous signal feedback, or it may be DQ5. This means that through the command address remapping module and the data remapping module, the first connection relationship can be flexibly adapted, and the subsequent center point algorithm can be optimized in combination with the second connection relationship. Therefore, it is not only conducive to adapting to the product models and packaging specifications of various storage modules to be trained, but also simplifies the difficulty of hardware and software collaborative design, so that software-level optimization can be performed for the second connection relationship and the standard storage module. In this way, the center point algorithm can better optimize the deviation of the optimal center point position caused by the existence of the metastable interval, which helps to improve the timeliness and accuracy of training.

[0036] In some embodiments, the delay training module adjusts the delay of the first command address signal corresponding to the first command address bus pin based on the center point algorithm, so as to achieve alignment between the first command address signal corresponding to the first command address bus pin and the first data signal corresponding to the first data bus pin, including: the delay training module determines the left boundary of the first command address signal using the first function of the center point algorithm, and determines the right boundary of the first command address signal using the second function of the center point algorithm, and then determines the center point position of the first command address signal based on the determined left boundary of the first command address signal and the determined right boundary of the first command address signal, and then adjusts the delay of the first command address signal based on the determined center point position of the first command address signal. In this way, by providing the first function and the second function, optimization can be performed for the left and right boundary situations respectively, so as to better determine the stable boundary and then determine the optimal center point position, thereby improving the training effect.

[0037] In some embodiments, the first function of the center point algorithm is used to sequentially scan the error position of the left boundary of the first command address signal, the metastable position of the left boundary of the first command address signal, and the steady-state position of the left boundary of the first command address signal, and the second function of the center point algorithm is used to sequentially scan the error position of the right boundary of the first command address signal, the metastable position of the right boundary of the first command address signal, and the steady-state position of the right boundary of the first command address signal. In this way, by scanning in order from the error position to the metastable position and then to the steady-state position, it means starting from the left and right sides, looking for the steady-state positions of the left and right boundaries towards the stable state of the best center point position, so that the steady-state positions of the left and right boundaries found and the further determined center point position are accurate. Therefore, the stable boundary is better determined and then the best center point position is determined, thereby improving the training effect.

[0038] In some embodiments, the delay training module uses the first function of the center point algorithm to determine the left boundary of the first command address signal, including: when the first data signal is fed back as a low level and the clock signal does not collect the first command address signal, increase the delay of the first command address signal, and when the first data signal is fed back as a high level and the clock signal collects the first command address signal, maintain the delay of the first command address signal. In this way, the scanning order from the error position to the metastable position and then to the stable position is realized, which means starting from the left and right sides, the stable positions of the left and right boundaries are searched towards the stable state of the optimal center point position, so that the stable positions of the left and right boundaries found and the further determined center point position are accurate. Therefore, through the delay training module, the algorithm for finding the steady-state position of the left boundary increases or maintains the circuit delay according to the asynchronous feedback result, so as to better determine the stable boundary and then the optimal center point position, thereby improving the training effect.

[0039] In some embodiments, the delay training module uses the second function of the center point algorithm to determine the right boundary of the first command address signal, including: when the first data signal is fed back as a low level and the clock signal does not collect the first command address signal, reducing the delay of the first command address signal, and when the first data signal is fed back as a high level and the clock signal collects the first command address signal, maintaining the delay of the first command address signal. In this way, the scanning order from the error position to the metastable position and then to the stable position is realized, which means starting from the left and right sides, the stable positions of the left and right boundaries are searched towards the stable state of the optimal center point position, so that the stable positions of the left and right boundaries found and the further determined center point position are accurate. Therefore, through the delay training module, the algorithm for finding the steady-state position of the right boundary is used to reduce or maintain the circuit delay according to the asynchronous feedback result, so as to better determine the stable boundary and then the optimal center point position, thereby improving the training effect.

[0040] In some embodiments, the delay training module determines the left boundary of the first command address signal using the first function of the center point algorithm, and further includes: initially setting the delay of the first command address signal to the first initial delay, and then performing a first number of loop searches using the first function of the center point algorithm; the delay training module determines the right boundary of the first command address signal using the second function of the center point algorithm, and further includes: initially setting the delay of the first command address signal to the second initial delay, and then performing a second number of loop searches using the first function of the center point algorithm, wherein the first initial delay is less than the second initial delay. In this way, by distinguishing the search algorithm for the steady-state positions of the left and right boundaries, the first initial delay is set as the smaller circuit delay, and the second initial delay is set as the larger circuit delay, so as to better determine the stable boundary and thus determine the optimal center point position, thereby improving the training effect.

[0041] In some embodiments, the first number of loop searches and the second number of loop searches are both determined based on the maximum frequency of the clock signal, the first initial delay corresponds to a single step unit, the step unit is determined based on the maximum frequency of the clock signal, and the second initial delay corresponds to multiple step units. Here, the maximum frequency of the clock signal determines the number of loop searches. The higher the maximum frequency of the clock signal, the more loop searches, because the step becomes smaller, but the delay of the address bus signal relative to the clock signal does not become smaller. In addition, the maximum rate of the command address bus corresponds to the frequency of the command address signal, and the protocol generally stipulates that the frequency of the command address signal is consistent with the maximum frequency of the clock signal. Regarding the initial delay, the first initial delay is set as a smaller circuit delay, and the second initial delay is set as a larger circuit delay. The first initial delay is used in the algorithm for finding the steady-state position of the left boundary, and the smaller value of the first initial delay corresponds to the step unit, such as 1 unit interval (UI) or 0.1 UI. The second initial delay is used in the algorithm for finding the steady-state position of the right boundary, and the larger value of the second initial delay corresponds to multiple step units, such as 7 UI. Here, the UI is determined based on the maximum frequency of the clock signal, and a step size equal to 64 UI or 32 UI can be set. In addition, if the clock skew of the command address signal relative to the clock signal is large, a larger scanning range is required. The scanning range is determined by the initial delay. Therefore, in some embodiments, when the clock skew of the command address signal relative to the clock signal is large, a larger scanning range can be obtained by setting a first initial delay and a second initial delay to offset the adverse effects of the larger clock skew. In this way, the stable boundary is better determined and the optimal center point position is determined, thereby improving the training effect.

[0042] In a possible implementation, the plurality of command address bus pins of the storage module to be trained include command address bus pins for a first data channel and command address bus pins for a second data channel, and the standard command address bus pins of the standard storage module corresponding to the command address bus pins for the first data channel are different from the standard command address bus pins of the standard storage module corresponding to the command address bus pins for the second data channel. Thus, through hardware optimization, a command address remapping module, a data remapping module and a delay training module are provided, and through software optimization, the delay of the command address signal is adjusted based on the center point algorithm through the delay training module, so that the alignment between the command address signal and the data signal is achieved, which can not only meet the requirements of the low-power fifth-generation double rate and related memory technical specifications in terms of state alignment and synchronization, but also effectively overcome the adverse effects of the pin layout and routing after chip packaging, effectively overcome the adverse effects caused by the existence of the metastable interval, quickly and reliably determine the alignment relationship and locate the best center position, improve the training effect and reduce the overall training delay, and contribute to fast response and device adaptation.

[0043] In a possible implementation, the multiple data bus pins of the storage module to be trained include paired data bus pins, the paired data bus pins are used for differential signal transmission, and the standard data bus pins of the standard storage module corresponding to the paired data bus pins are used for differential signal transmission. In this way, through hardware optimization, a command address remapping module, a data remapping module and a delay training module are provided, and through software optimization, the delay of the command address signal is adjusted based on the center point algorithm through the delay training module, so that the alignment between the command address signal and the data signal is achieved, which can not only meet the requirements of the low-power fifth-generation double rate and related memory technical specifications in terms of state alignment and synchronization, but also effectively overcome the adverse effects of pin layout and routing after chip packaging, effectively overcome the adverse effects caused by the existence of metastable intervals, quickly and reliably determine the alignment relationship and locate the best center position, improve the training effect and reduce the overall training delay, and contribute to rapid response and device adaptation.

[0044] In a possible implementation, the first connection relationship and the second connection relationship are determined based on the computer memory specification associated with the storage module to be trained. The number and distribution of pins on the storage module to be trained may be complex and variable. For example, LPDDR5 generally specifies 7 command address bus pins, and Internet Protocol Version 4 (IPV4) generally specifies 8 command address bus pins. For another example, a dedicated processor may have customized requirements for the pin distribution and bus design on its storage module, such as a graphics processing unit (GPU) and a data processing unit (DPU). To this end, through hardware optimization, a command address remapping module and a data remapping module are provided, which are equivalent to any pin distribution and packaging design specifications on the storage module to be trained, and are mapped to an assumed standard storage module, including mapping multiple command address bus pins of the storage module to be trained to the standard command address bus pins of the standard storage module one by one through the command address remapping module, and including mapping multiple data bus pins of the storage module to be trained to the standard data bus pins of the standard storage module one by one through the data remapping module. In this way, the signal transmission and alignment problems to be solved by the storage module to be trained through command bus training are transformed into signal transmission and alignment problems of the standard storage module. In this way, through software optimization, the delay training module can be used to adjust the delay of the command address signal based on the center point algorithm, thereby achieving alignment between the command address signal and the data signal.

[0045] In some embodiments, the computer memory specification is low power fifth generation double rate, Internet Protocol version 4, data processing unit design specification, or image processing unit design specification. In this way, through the command address remapping module and the data remapping module, the first connection relationship can be flexibly adapted, and the subsequent center point algorithm can be optimized in combination with the second connection relationship. Therefore, it is not only conducive to adapting the product models and packaging specifications of various storage modules to be trained, but also simplifies the difficulty of hardware and software collaborative design, so that software level optimization can be carried out for the second connection relationship and the standard storage module, and various sampling optimization algorithms such as the center point algorithm are used to improve the training effect of the standard storage module.

[0046] Figure 33 is a schematic diagram of the structure of a computing device provided in an embodiment of the present application, and the computing device 300 includes: one or more processors 310, a communication interface 320 and a memory 330. The processor 310, the communication interface 320 and the memory 330 are interconnected via a bus 340. Optionally, the computing device 300 may also include an input / output interface 350, and the input / output interface 350 is connected to an input / output device for receiving parameters set by a user, etc. The computing device 300 can be used to implement some or all of the functions of the device embodiment or system embodiment in the above-mentioned embodiment of the present application; the processor 310 can also be used to implement some or all of the operating steps of the method embodiment in the above-mentioned embodiment of the present application. For example, the specific implementation of the various operations performed by the computing device 300 can refer to the specific details in the above-mentioned embodiments, such as the processor 310 is used to perform some or all of the steps in the above-mentioned method embodiment or some or all of the operations in the above-mentioned method embodiment. For another example, in an embodiment of the present application, the computing device 300 may be used to implement part or all of the functions of one or more components in the above-mentioned apparatus embodiment. In addition, the communication interface 320 may be specifically used to perform the communication functions necessary to implement the functions of these apparatuses and components, and the processor 310 may be specifically used to perform the processing functions necessary to implement the functions of these apparatuses and components.

[0047] It should be understood that Figure 3 The computing device 300 may include one or more processors 310, and the multiple processors 310 may provide processing capabilities in a parallel connection mode, a serial connection mode, a serial-parallel connection mode, or any connection mode, or the multiple processors 310 may form a processor sequence or a processor array, or the multiple processors 310 may be divided into a main processor and an auxiliary processor, or the multiple processors 310 may have different architectures such as a heterogeneous computing architecture. In addition, Figure 3 The computing device 300 shown in the figure, and the related structural description and functional description are exemplary and non-limiting. In some exemplary embodiments, the computing device 300 may include Figure 3 More or fewer components may be shown, or some components may be combined or separated, or may have a different arrangement of components.

[0048] The processor 310 may have a variety of specific implementation forms. For example, the processor 310 may include a central processing unit (CPU), a graphic processing unit (GPU), a neural-network processing unit (NPU), a tensor processing unit (TPU) or a data processing unit (DPU), etc., and the embodiment of the present application does not specifically limit it. The processor 310 may also be a single-core processor or a multi-core processor. The processor 310 may be a combination of a CPU and a hardware chip. The above-mentioned hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof. The above-mentioned PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof. The processor 310 may also be implemented using a logic device with built-in processing logic alone, such as an FPGA or a digital signal processor (DSP). The communication interface 320 may be a wired interface or a wireless interface for communicating with other modules or devices. The wired interface may be an Ethernet interface, a local interconnect network (LIN), etc., and the wireless interface may be a cellular network interface or a wireless local area network interface, etc.

[0049] The memory 330 may be a non-volatile memory, such as a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The memory 330 may also be a volatile memory, which may be a random access memory (RAM) used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM). The memory 330 may also be used to store program codes and data, so that the processor 310 calls the program codes stored in the memory 330 to execute some or all of the operation steps in the above method embodiment, or to execute the corresponding functions in the above device embodiment. Figure 3 Show more or fewer components, or have different component configurations.

[0050] The bus 340 may be a peripheral component interconnect express (PCIe) bus, an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a compute express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc. The bus 340 may be divided into an address bus, a data bus, a control bus, etc. In addition to the data bus, the bus 340 may also include a power bus, a control bus, and a status signal bus, etc. However, for the sake of clarity, Figure 3 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0051] The method and device provided in the embodiments of the present application are based on the same inventive concept. Since the principles of solving the problems in the methods and devices are similar, the embodiments, implementation methods, examples or implementation methods of the methods and devices can refer to each other, and the repeated parts will not be repeated. The embodiments of the present application also provide a system, which includes multiple computing devices, and the structure of each computing device can refer to the structure of the computing device described above. The functions or operations that can be implemented by the system can refer to the specific implementation steps in the above method embodiments and / or the specific functions described in the above device embodiments, which will not be repeated here.

[0052] The present application also provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, and when the computer instructions are executed on a computer device (such as one or more processors), the method steps in the above method embodiment can be implemented. The specific implementation of the processor of the computer-readable storage medium in executing the above method steps can refer to the specific operations described in the above method embodiment and / or the specific functions described in the above device embodiment, which will not be repeated here.

[0053] It should be understood by those skilled in the art that the embodiments of the present application may be provided as methods, systems, or computer program products. The present application may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. The embodiments of the present application may be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented using software, the above embodiments may be implemented in whole or in part in the form of a computer program product. The present application may take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program codes. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the process or function described in the embodiments of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, computer instructions may be transmitted from one website site, computer, server, or data center to another website site, computer, server, or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. Computer-readable storage media can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media. Available media can be magnetic media (such as floppy disks, hard disks, tapes), optical media, or semiconductor media. Semiconductor media can be solid-state hard disks, random access memory, flash memory, read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, or any other form of suitable storage media.

[0054] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. Each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the functions specified in the process. Figure 1A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide for implementing the process in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0055] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. The steps in the method of the embodiment of the present application can be adjusted in order, merged or deleted according to actual needs; the modules in the system of the embodiment of the present application can be divided, merged or deleted according to actual needs. If these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

1. A command bus training method, characterized in that: The command bus training method comprises: Mapping multiple command address bus pins of the storage module to be trained to standard command address bus pins of the standard storage module one by one through the command address remapping module; Through a data remapping module, multiple data bus pins of the storage module to be trained are mapped one by one to the standard data bus pins of the standard storage module, wherein a first connection relationship is satisfied between multiple command address bus pins of the storage module to be trained and multiple data bus pins of the storage module to be trained, and a second connection relationship is satisfied between standard command address bus pins of the standard storage module and standard data bus pins of the standard storage module; Through the delay training module, based on the first connection relationship and the second connection relationship, the asynchronous signal feedback sources corresponding to the multiple command address bus pins of the storage module to be trained when they are each called are determined, and then, based on the center point algorithm, the delay of the command address signal corresponding to each of the multiple command address bus pins of the storage module to be trained is adjusted, so as to achieve alignment between the command address signal corresponding to each of the multiple command address bus pins of the storage module to be trained and the data signal corresponding to each of the multiple data bus pins of the storage module to be trained.

2. The command bus training method according to claim 1, characterized in that: The multiple command address bus pins of the storage module to be trained include a first command address bus pin, and the first command address bus pin is connected to a first data bus pin among the multiple data bus pins of the storage module to be trained based on the first connection relationship. The delay training module adjusts the delay of the first command address signal corresponding to the first command address bus pin based on the center point algorithm, thereby achieving alignment between the first command address signal corresponding to the first command address bus pin and the first data signal corresponding to the first data bus pin.

3. The command bus training method according to claim 2, characterized in that: The delay training module adjusts the delay of the first command address signal corresponding to the first command address bus pin based on the center point algorithm, thereby achieving alignment between the first command address signal corresponding to the first command address bus pin and the first data signal corresponding to the first data bus pin, including: The delay training module uses the first function of the center point algorithm to determine the left boundary of the first command address signal, and uses the second function of the center point algorithm to determine the right boundary of the first command address signal, and then determines the center point position of the first command address signal based on the determined left boundary of the first command address signal and the determined right boundary of the first command address signal, and then adjusts the delay of the first command address signal based on the determined center point position of the first command address signal.

4. The command bus training method according to claim 3, characterized in that: The first function of the center point algorithm is used to sequentially scan the error position of the left boundary of the first command address signal, the metastable position of the left boundary of the first command address signal, and the stable position of the left boundary of the first command address signal, and the second function of the center point algorithm is used to sequentially scan the error position of the right boundary of the first command address signal, the metastable position of the right boundary of the first command address signal, and the stable position of the right boundary of the first command address signal.

5. The command bus training method according to claim 3, characterized in that: The delay training module determines the left boundary of the first command address signal by using the first function of the center point algorithm, including: When the first data signal is fed back as a low level and the clock signal does not collect the first command address signal, the delay of the first command address signal is increased; when the first data signal is fed back as a high level and the clock signal collects the first command address signal, the delay of the first command address signal is maintained.

6. The command bus training method according to claim 5, characterized in that: The delay training module determines the right boundary of the first command address signal by using the second function of the center point algorithm, including: When the first data signal is fed back as a low level and the clock signal does not collect the first command address signal, the delay of the first command address signal is reduced; when the first data signal is fed back as a high level and the clock signal collects the first command address signal, the delay of the first command address signal is maintained.

7. The command bus training method according to claim 6, characterized in that: The delay training module uses the first function of the center point algorithm to determine the left boundary of the first command address signal, and also includes: initially setting the delay of the first command address signal to a first initial delay, and then using the first function of the center point algorithm to perform a first number of loop searches; the delay training module uses the second function of the center point algorithm to determine the right boundary of the first command address signal, and also includes: initially setting the delay of the first command address signal to a second initial delay, and then using the first function of the center point algorithm to perform a second number of loop searches, wherein the first initial delay is less than the second initial delay.

8. The command bus training method according to claim 7, characterized in that: The first loop search number and the second loop search number are both determined based on the maximum frequency of the clock signal, the first initial delay corresponds to a single step unit, the step unit is determined based on the maximum frequency of the clock signal, and the second initial delay corresponds to multiple step units.

9. The command bus training method according to claim 1, characterized in that: The multiple command address bus pins of the storage module to be trained include command address bus pins for a first data channel and command address bus pins for a second data channel, and the standard command address bus pins of the standard storage module corresponding to the command address bus pins for the first data channel are different from the standard command address bus pins of the standard storage module corresponding to the command address bus pins for the second data channel.

10. The command bus training method according to claim 1, characterized in that: The multiple data bus pins of the storage module to be trained include paired data bus pins, the paired data bus pins are used for differential signal transmission, and the standard data bus pins of the standard storage module corresponding to the paired data bus pins are used for differential signal transmission.

11. The command bus training method according to claim 1, characterized in that: The first connection relationship and the second connection relationship are determined based on a computer memory specification associated with the storage module to be trained.

12. The command bus training method according to claim 11, characterized in that: The computer memory specification is low power fifth generation double data rate, Internet Protocol version 4, a design specification for a data processing unit, or a design specification for an image processing unit.

13. An electronic device, characterized in that: The electronic device comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method according to any one of claims 1 to 12 when executing the computer program.

14. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, which, when executed on a computer device, cause the computer device to perform the method according to any one of claims 1 to 12.

15. A command bus training device, characterized in that: The command bus training device is applied to the storage module to be trained, and the command bus training device includes a command address remapping module, a data remapping module and a delay training module. The command bus training method associated with the storage module to be trained by the command bus training device includes: Mapping the plurality of command address bus pins of the storage module to be trained to the standard command address bus pins of the standard storage module one by one through the command address remapping module; Through the data remapping module, the multiple data bus pins of the storage module to be trained are mapped one by one to the standard data bus pins of the standard storage module, wherein the multiple command address bus pins of the storage module to be trained and the multiple data bus pins of the storage module to be trained satisfy a first connection relationship, and the standard command address bus pins of the standard storage module and the standard data bus pins of the standard storage module satisfy a second connection relationship; Through the delay training module, based on the first connection relationship and the second connection relationship, the asynchronous signal feedback sources corresponding to the multiple command address bus pins of the storage module to be trained when they are each called are determined, and then, based on the center point algorithm, the delays of the command address signals corresponding to the multiple command address bus pins of the storage module to be trained are adjusted, thereby achieving alignment between the command address signals corresponding to the multiple command address bus pins of the storage module to be trained and the data signals corresponding to the multiple data bus pins of the storage module to be trained.

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