A computable storage core fabric and tile unit and system for data compression storage

Abstract

The application discloses a kind of computable storage core structure and slice unit and system for data compression storage.NVM cross array is used as the basic structure of the storage computing core, the array is divided into computing part and storage part, and the peripheral circuit for computing and storage is integrated around the array.The compression / decompression algorithm is mapped in the device of array computing part, and the original data is compressed by using in-memory computing method, and the compressed data is programmed and stored in the device of array storage part in situ.When data is taken out, the data is restored by the computing part.A plurality of computable storage cores constitute a computable storage slice unit, which further constitutes a computable storage system to realize large-scale in-memory computing and in-situ storage of data.Compared with the existing data compression storage system, the application reduces data handling, increases energy efficiency, greatly improves the density of data storage, and is more efficient in processing multi-source and unstructured data.

Description

Technical Field

[0001] The present invention relates to semiconductor technology, and in particular to a computable storage unit based on non-volatile memory (NVM) for performing in-memory calculations and data compression. Background Art

[0002] With the development of the Internet, the amount of data generated by data centers and end-side devices has increased day by day, and has already reached ZB (1 ZB = 10 21 B) The majority of this data is unstructured. This data contains valuable information that needs to be analyzed and stored. However, the development of mainstream storage technologies such as FLASH faces challenges in terms of cost and technology, and the growth rate of storage device capacity has gradually slowed. Another development direction is to adopt more efficient data storage methods to reduce the total amount of data stored, that is, to use data compression technology to process data.

[0003] Data compression technology refers to the use of data redundancy to reduce the space or bandwidth required for data storage and transmission. It is mainly divided into two categories: lossless compression and lossy compression. For most data generated on the Internet, lossy compression is usually used to compress the data when it needs to be stored, in exchange for a higher compression ratio than lossless compression. Lossy compression mainly includes algorithms such as JPEG and JPEG2000 for processing image data, algorithms such as MP3 for processing audio data, and the H.264 algorithm for processing video information. Most of these algorithms use domain transformations and experience-based quantization matrices to process raw data. In recent years, researchers have also discovered the application of deep learning algorithms in the field of data compression. Training deep learning algorithms such as convolutional autoencoders based on partial data samples can better improve the compression and decompression effects of complex data.

[0004] Current data compression technologies typically use CPUs and GPUs as computing cores, processing the raw data and transferring it to a hard drive for storage. This method requires transferring the compressed data when storing it, and reading it from external storage when retrieving it, resulting in significant energy consumption during data transfer. Some ASIC chips are designed to accelerate the data compression calculation process, but they also face overhead issues such as energy consumption and latency associated with transferring compressed data from the computing unit to the storage unit. According to statistics, in systems where storage and computing are separated, the energy consumed to transfer data is several times the energy required to calculate the data. Therefore, it is particularly necessary to design a data compression storage system that can significantly reduce data transfer overhead. Summary of the Invention

[0005] The purpose of the present application is to solve the problem that a large amount of data needs to be frequently transported between a computing unit and a storage unit in the current data compression storage system based on traditional computing cores such as CPU, GPU, and ASIC for compression algorithm acceleration, resulting in poor energy efficiency of compression storage, low data storage density, and difficulty in effectively processing complex data of multiple sources and unstructured.

[0006] To solve the above problems, the present application provides a computable storage core with non-volatile memory as the main storage medium for implementing data compression, storage and decompression, and a corresponding larger system, and a corresponding data compression, storage and decompression operation method.

[0007] The computable storage core in the present application is composed of an NVM cross array, a computing peripheral circuit, a storage peripheral circuit, etc. Compared with other hardware circuits for data compression, the present application integrates the computing part for data compression and decompression and the storage part for storing compressed data in the same NVM cross array, and integrates the peripheral circuits for computing and storage around the NVM cross array. The close integration of the computing peripheral circuit and the storage peripheral circuit greatly reduces the large overhead caused by data transportation, and improves the energy efficiency of the data compression storage and restoration process. At the same time, part of the NVM device has the characteristic of multi-value storage, and at the same time adopts the method of in-memory computing of cross array to compress and decompress the data. Compared with the traditional system with CPU as the computing core, the present application has higher storage density. At the same time, the in-memory computing part of the present application is suitable for matrix operation, and can flexibly arrange various data compression algorithms, especially the algorithms based on deep learning, which can have better compression effect when compressing and restoring the data of multiple sources and unstructured.

[0008] Specifically, the computable storage core proposed by the present application includes an NVM cross array, a computing peripheral circuit, and a storage peripheral circuit. The NVM cross array is composed of non-volatile storage units connected by vertically crossed bit lines, word lines and source lines, and is used to store matrix operators in the data compression algorithm and compressed data. The computing peripheral circuit is composed of input registers, multiplexing circuits, sample and hold circuits, analog-to-digital conversion circuits (ADC), shift and addition circuits, etc., and is used for data transmission in the in-memory data compression and decompression computing process. The storage peripheral circuit is composed of input data registers, driving circuits, comparators, etc., and is used for storing and reading out the compressed data.

[0009] In the face of larger scale storage data and compression algorithm, multiple computable storage cores can be integrated to form a computable storage tile unit. The computable storage cores inside the tile unit are connected through a certain topological relationship, and data exchange is performed with the outside of the tile unit through an L1 cache. Meanwhile, the computable storage tile unit can also integrate more complex addition tree circuits, special functional units such as activation function calculation modules, and part of control logic circuits to realize larger scale compression algorithms.

[0010] On the basis of the computable storage tile unit, multiple tile units are connected through a routing module to build an on-chip network, forming a complete computable storage system. L2 cache, IO interface, etc. can be integrated to communicate with the outside of the chip, and the integration of MCU and other chips with stronger functional control logic circuits can enable the chip to perform more complex control on internal and external data communication, data programming storage, etc.

[0011] The operation method of the computable storage core of the present application is as follows: the compression / decompression algorithm is mapped to the device of the NVM cross array calculation part of the computable storage core; then the original data is input into the calculation part of the computable storage core to perform compression processing through the storage calculation method, and the obtained compressed data is programmed and stored in situ in the device of the NVM cross array storage part of the computable storage core for saving. When the compressed data needs to be taken out, the corresponding data is first read out from the storage part, then the read data is input into the calculation part of the computable storage core for decompression, and finally the restored data result is output externally.

[0012] The above operation method can specifically include the following steps:

[0013] 1) training the compression and decompression algorithm based on deep learning using sample data;

[0014] 2) programming and mapping the algorithm weight to the device of the NVM cross array calculation part of the computable storage core;

[0015] 3) performing compression processing on the original data through the calculation part of the computable storage core;

[0016] 4) programming and storing the compressed data to the device of the NVM cross array storage part of the computable storage core;

[0017] 5) reading out the compressed data stored in the storage part of the computable storage core and temporarily storing it in the cache;

[0018] 6) decompressing the compressed data through the calculation part of the computable storage core and temporarily storing it in the cache;

[0019] 7) outputting the decompressed and restored data through an external communication interface.

[0020] The beneficial technical effects of the present application are:

[0021] 1. The structure of the computing and storage functions integrated in the array proposed by the present application can eliminate the data transfer between the separated computing unit and the storage unit in the data compression and storage process, thereby greatly improving the energy efficiency of the data compression and storage process.

[0022] 2. Through the multi-value storage characteristics of the non-volatile memory, the storage density of the present application can be greatly improved.

[0023] 3. Through the use of data compression algorithms mapped in the computing storage unit composed of non-volatile memory, such as compression algorithms based on deep learning, the present application can have better data compression and recovery effects when facing multi-source and unstructured data. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 It is a schematic diagram of the computable storage core structure of the embodiment of the present application.

[0025] Figure 2 It is a schematic diagram of the computable storage chip unit and system of the embodiment of the present application, wherein (a) is a structural schematic diagram of the computable storage chip unit, and (b) is a structural schematic diagram of the computable storage system.

[0026] Figure 3 It is an example diagram of the system operation method flow of the embodiment of the present application.

[0027] Figure 4 It is a data flow schematic diagram of the system data compression storage and restoration reading process of the embodiment of the present application.

[0028] Figure 5 It shows the technical effects of the embodiment of the present application: compared with CPU, GPU, ASIC and other systems, the computable storage system of the present application can greatly improve the energy efficiency of the data compression and storage process. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical scheme and advantages of the present application more clear and obvious, the present application is further described in detail below in combination with specific embodiments and with reference to the drawings.

[0030] In this embodiment, the non-volatile storage medium for storing compressed data and mapping the weights of the compression / decompression algorithm is a resistive random access memory (RRAM), which can perform 4-bit storage per device. The RRAM array size of the computational storage core is 4k (256x16), the connection line topology is bit line || source line perpendicular to word line, and the ADC is connected to the source line end. The data required for compression storage is RGB image data with a resolution of 32x32, and the compression / decompression algorithm used is a convolutional autoencoder algorithm based on deep learning.

[0031] The basic hardware unit of the present application is a computational storage core ( Figure 1 ), which is composed of an RRAM array and peripheral circuits. The peripheral circuits include: related peripheral circuits for in-memory computing, such as bit line / word line / source line multiplexing circuit, sample and hold circuit, ADC, shift-add circuit, input / output register, etc.; and related peripheral circuits for data storage, such as input / output register, bit line / word line / source line driving circuit, multiplexing circuit, comparator, etc. The RRAM array is divided into a computing part and a storage part. The computing part is used for data compression / decompression, and the storage part is used for compressed data storage, so that the data processing and storage modules can be tightly integrated. The positions and proportions of the array computing part and the storage part can be dynamically divided according to the required computing load and storage load of different tasks and data to obtain the optimal performance. The peripheral circuits for computing are located around the array, and the input register for data input and the sample and hold circuit, ADC, etc. for data output are connected to the array through the multiplexing circuit. The output result of the ADC enters the shift-add circuit for processing, and then is output to the outside of the core. The peripheral circuits for storage are also located around the array and are tightly integrated with the circuits for computing, which are located in different positions. The bit line / word line / source line driving circuit for data storage and the comparator for data readout are connected to the array through the multiplexing circuit. The compressed data stored in the array is read out through the comparator and then output to the outside.

[0032] Based on the above computational storage core, when facing larger scale storage data and compression algorithms, multiple computational storage cores can be integrated ( Figure 2 ). The multiple computational storage cores constitute a computational storage chip unit. The internal computational storage cores are connected through a certain topology, exchange data with the outside of the chip unit through L1 cache, and at the same time, in order to realize larger scale compression algorithms, more complex addition tree circuits, special functional units such as activation function calculation modules, and part of the control logic circuit can also be integrated.

[0033] On the basis of the computable storage tile unit, a plurality of tile units are connected through a routing module to build an on-chip network, which can constitute a complete computable storage system, integrated with L2 cache, IO interface and other communication with the outside of the chip, and the integration of MCU and other chips with stronger function control logic circuit can also enable the chip to control the internal and external data communication, data programming storage and other functions more complex.

[0034] The operation mode of the computable storage core and system in the embodiment is generally introduced as follows Figure 3 ):

[0035] Step 110: a convolutional autoencoder algorithm based on deep learning is selected to compress and decompress the data, and part of the data in the data set to be compressed and stored is sampled to train the algorithm.

[0036] Step 120: mapping the weight data in the convolutional autoencoder. The weight in the algorithm is programmed and mapped to the device for in-memory computing in the computable storage core, i.e. the array computing part.

[0037] Step 130: after quantizing the data to be compressed and stored, the peripheral circuit module for in-memory computing is used to input from the word line, and the calculation result is obtained from the corresponding ADC of the source line, and the output register is obtained by post-processing through the shift addition circuit. The compressed data required for storage is temporarily stored in the output register.

[0038] Step 140: the compressed data in the cache is taken out and programmed and stored in the device for data storage in the computable storage core, i.e. the array storage part.

[0039] Step 150: the compressed data stored in the RRAM array is read out through the peripheral circuit for data storage in the computable storage core, and is temporarily stored in the output register after quantization.

[0040] Step 160: the quantized compressed data in the cache is input from the word line through the peripheral circuit module for in-memory computing, and is calculated with the part of the RRAM array that maps the decompression algorithm. After being read out by the ADC, the decompressed data is obtained by post-processing through the shift addition module and is temporarily stored in the output register.

[0041] Step 170: the restored data temporarily stored in the cache is output through the IO interface for external communication.

[0042] The data flow of the original data compression and storage of the compressed data, and the data flow of the restored data output to the outside Figure 4 )indicates that the data flow in the compression / decompression process does not need to interact frequently with the external storage, and the data can be stored in situ.

[0043] Experiments show that the computable storage system can reduce the overhead of data transfer by integrating the in-memory computing array and the data storage array in the same NVM cross array, and closely integrating the peripheral circuit, compared with the traditional CPU and GPU-based data compression system and the ASIC chip only used for accelerating the data compression algorithm, the energy consumption of the data compression, storage and decompression process can be greatly reduced. Figure 5 )。

[0044] Experiments show that, due to the high density of the storage array, the multi-value storage characteristics of the RRAM and the close integration of the peripheral circuit, compared with the traditional hardware implementation of data compression by CPU, the application has higher storage density.

[0045] In addition, since the computable storage core can configure data compression algorithms of different scales and sizes, compared with the traditional data compression method using fixed mode transformation and empirical quantization matrix, the embodiment adopts a compression algorithm based on deep learning, and can obtain better compression effect on multi-source and unstructured data such as text, image, audio and video.

[0046] So far, the embodiments of the present disclosure have been described in detail with reference to the accompanying drawings.

[0047] The above specific embodiments further illustrate the purpose, technical solutions and advantages of the present application. It should be understood that the above description is only a specific embodiment of the present application and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A compute storage core comprising an NVM crossbar, a compute periphery, and a storage periphery, the compute periphery and the storage periphery both integrated around the NVM crossbar, the NVM crossbar divided into a compute portion and a storage portion, wherein, The computing part is connected with a computing peripheral circuit for data compression and decompression, and the storage part is connected with a storage peripheral circuit for compressed data storage. The NVM cross array dynamically divides the computing part and the storage part according to different tasks and data requirements.

2. The computable storage core of claim 1, wherein, The device constituting the NVM cross array is RRAM.

3. The computational storage core of claim 1, wherein, The computing peripheral circuit is used for data transmission in the data compression and decompression computing process, and includes a multiplexing circuit of bit lines, source lines and word lines, a sample and hold circuit, an ADC, a shift and addition circuit, an input register and an output register; the storage peripheral circuit is used for storage and reading of compressed data, and includes an input register, an output register, a driving circuit of bit lines, source lines and word lines, a multiplexing circuit and a comparator.

4. A computable storage tile unit integrated with a plurality of the computable storage cores according to any one of claims 1 to 3, the computable storage cores in the tile unit being connected through a certain topological relationship and exchanging data with the outside of the tile unit through an L1 cache.

5. The compute storage tile unit of claim 4, wherein, The computable storage tile unit is further integrated with an addition tree circuit, a special function unit and a control logic circuit.

6. A computable storage system comprising a plurality of the computable storage tile units according to claim 4, the computable storage tile units being connected through an on-chip network constructed by a routing module.

7. The computer storage system of claim 6, wherein, The computable storage system is further integrated with an L2 cache, an external communication interface and a chip control logic circuit.

8. A method of operation using the computer storage core of any of claims 1 to 3, comprising: Mapping the compression and decompression algorithm to the device of the computing part of the computable storage core NVM cross array; Inputting the original data into the computing part of the computable storage core for compression processing through in-memory computing, and storing the obtained compressed data in situ into the device of the storage part of the computable storage core NVM cross array; When compressed data needs to be taken out, first read out the data from the storage part, then input the read-out data into the computing part of the computable storage core for decompression, and finally output the decompressed data to the outside.

9. The operating method of claim 8, wherein, The method comprises the following steps: 1) training the compression and decompression algorithm based on deep learning using sample data; 2) programming and mapping the algorithm weight to the device of the computing part of the computable storage core NVM cross array; 3) compressing the original data through the computing part of the computable storage core and temporarily storing in the cache; 4) programming and storing the compressed data into the device of the storage part of the computable storage core NVM cross array; 5) reading out the compressed data stored in the storage part of the computable storage core and temporarily storing in the cache; 6) decompressing the compressed data through the computing part of the computable storage core and temporarily storing in the cache; 7) outputting the decompressed data to the outside through the external communication interface.

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