Calculation circuit and calculation device

Abstract

The invention relates to an operational circuit and a computing device. The operation circuit comprises a multiple operation module, which is configured to calculate a preset multiple of a first operand so as to generate a corresponding second operand; and the inner product operation module is in communication connection with the multiple operation module, and the inner product operation module is configured to calculate a dot product of the first vector and the second vector at least according to a second operand from the multiple operation module and a second coefficient multiplied by the second operand.

Description

Technical Field

[0001] The present disclosure relates to the technical field of electronic circuits, and more specifically, to an operation circuit and a computing device. Background Art

[0002] In the process of data processing, dot product operations between vectors are often involved. However, the circuits currently used to perform vector dot product operations have problems such as complex structure, large circuit area, long critical path, difficulty in timing convergence and high circuit power consumption, which need to be improved. Summary of the invention

[0003] One of the objectives of the present disclosure is to provide an operation circuit and a computing device.

[0004] According to a first aspect of the present disclosure, a computing circuit is provided, the computing circuit being at least used to calculate a dot product of a first vector and a second vector, wherein the first vector is a pre-known coefficient vector, and the computing circuit comprises: a multiple operation module, the multiple operation module being configured to calculate a preset multiple of a first operand to generate a corresponding second operand, wherein the first operand is generated according to at least one target element in the second vector, and in a dot product calculation, an absolute value of a first coefficient in the first vector multiplied by the target element is greater than or equal to an absolute value of a preset multiple, and the preset multiple is greater than 1; and, An inner product operation module, the inner product operation module is communicatively connected to the multiple operation module, and the inner product operation module is configured to calculate the dot product of the first vector and the second vector based on at least a second operand from the multiple operation module and a second coefficient multiplied by the second operand, wherein for each first operand and corresponding second operand, the product of the second coefficient and the preset multiple is less than or equal to the first coefficient.

[0005] In some embodiments, the preset multiple is determined according to the first vector; or, The preset multiple includes at least one of 3 times, 5 times and 7 times.

[0006] In some embodiments, the multiple calculation module includes one or more multiple calculation units, and the multiple calculation unit includes: A first shifter is configured to shift the fourth operand to the left by m bits to generate a fifth operand, wherein the fifth operand is 2 m times the fourth operand, the fourth operand is a positive integer multiple of the first operand, and m is a positive integer; and, A first adding unit is configured to add a sixth operand and a seventh operand to generate an eighth operand, wherein the sixth operand is a positive integer multiple of the first operand, and the seventh operand is a positive integer multiple of the first operand.

[0007] In some embodiments, the multiple operation module further includes: A first register is communicatively connected to at least one multiple calculation unit, and the first register is configured to register a fifth operand or an eighth operand from the multiple calculation unit.

[0008] In some embodiments, the inner product operation module is further configured to calculate the dot product of the first vector and the second vector according to the first operand corresponding to the second operand and the third coefficient multiplied by the first operand, wherein, for each first operand and the corresponding second operand, the sum of the product of the second coefficient and the preset multiple plus the third coefficient is equal to the first coefficient; and / or, The inner product operation module is also configured to calculate the dot product of the first vector and the second vector based on a third operand and a first coefficient in the first vector multiplied by the third operand, wherein the third operand is generated based on at least one element in the second vector except the element used to generate the first operand.

[0009] In some embodiments, the inner product operation module includes at least one of the following: A second shifter is configured to shift the ninth operand to the left by n bits to generate a tenth operand, wherein the tenth operand is 2 n times the ninth operand, the ninth operand is the second operand, the first operand or the third operand, and n is a positive integer; and, A second adding unit is configured to calculate a sum of at least a portion of a product of the second operand and the second coefficient, a product of the first operand and the third coefficient, and a product of the third operand and the first coefficient.

[0010] In some embodiments, the inner product operation module further includes: A second register is communicatively connected to the second shifter or the second adding unit, and the second register is configured to register a tenth operand from the second shifter or a sum of products from the second adding unit.

[0011] In some embodiments, the operation circuit further includes a bitwise inversion module, wherein the bitwise inversion module is configured to, when the first coefficient in the first vector is a negative number, bitwise invert the first operand or the third operand multiplied by the first coefficient, or the second operand generated according to the first operand multiplied by the first coefficient; The second adding unit is configured to calculate the sum of at least a portion of the product of the second operand and the second coefficient, the product of the first operand and the third coefficient, and the product of the third operand and the first coefficient and a preset constant, wherein the preset constant is determined based on the first coefficient in the first vector that is at least partially negative.

[0012] In some embodiments, the inner product operation module includes: a third adding unit configured to add at least a product of the first operand and the third coefficient and a product of the third operand and the first coefficient to generate an eleventh operand and a twelfth operand, wherein the third adding unit and the multiple operation module operate in the same clock cycle; and, A fourth adding unit is communicatively connected to the third adding unit and is configured to add at least the product of the eleventh operand, the twelfth operand, and the second operand from the third adding unit and the second coefficient to generate a thirteenth operand and a fourteenth operand.

[0013] In some embodiments, the inner product operation module further includes: a third register, the third register being communicatively connected to the third adding unit and configured to register an eleventh operand from the third adding unit; a fourth register, the fourth register being communicatively connected to the third adding unit and the fourth register being configured to register a twelfth operand from the third adding unit; a fifth register, the fifth register being communicatively connected to the fourth adding unit and configured to register a thirteenth operand from the fourth adding unit; and, A sixth register is communicatively connected to the fourth adding unit and is configured to register a fourteenth operand from the fourth adding unit.

[0014] In some embodiments, the inner product operation module further includes: A fifth adding unit is communicatively connected to the fourth adding unit and is configured to add the thirteenth operand and the fourteenth operand to generate a dot product of the first vector and the second vector.

[0015] In some embodiments, the inner product operation module further includes: A seventh register is communicatively connected to the fifth adding unit and is configured to register a dot product of the first vector and the second vector from the fifth adding unit.

[0016] In some embodiments, the operation circuit is configured to perform an image interpolation operation, and the first vector is a coefficient vector for image interpolation.

[0017] According to a second aspect of the present disclosure, a computing device is provided, comprising one or more computing circuits as described above.

[0018] In some embodiments, when the computing device includes a plurality of computing circuits, at least two computing circuits operate in parallel.

[0019] Other features and advantages of the present disclosure will become more apparent from the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings, which constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0021] The present disclosure may be more clearly understood from the following detailed description with reference to the accompanying drawings, in which: Figure 1 A schematic diagram showing a computing device performing image interpolation; Figure 2 Shows Figure 1 A schematic diagram of a computing circuit in a computing device; Figure 3 A block diagram of a computing device according to an exemplary embodiment of the present disclosure is shown; Figure 4 A block diagram of an operation circuit according to an exemplary embodiment of the present disclosure is shown; Figure 5 A block diagram of a multiple operation module in an operation circuit according to a specific embodiment of the present disclosure is shown; Figure 6 A block diagram of a multiple operation module in an operation circuit according to another specific embodiment of the present disclosure is shown; Figure 7 A block diagram of a multiple operation module in an operation circuit according to another specific embodiment of the present disclosure is shown; Figure 8 A block diagram of an inner product operation module in an operation circuit according to a specific embodiment of the present disclosure is shown; Fig. 9 A block diagram of an operation circuit according to another exemplary embodiment of the present disclosure is shown; Fig.10 A schematic diagram showing a computing device performing image interpolation according to a specific embodiment of the present disclosure is shown; Fig.11 Shows Fig.10A schematic diagram of a computing circuit in a computing device; Fig.12 A schematic diagram of the structure of an operation circuit according to a specific embodiment of the present disclosure is shown.

[0022] Note that in the embodiments described below, the same reference numerals are sometimes used in common between different drawings to represent the same parts or parts with the same functions, and their repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to represent similar items, so once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0023] For ease of understanding, the positions, sizes, and ranges of various structures shown in the drawings and the like sometimes do not represent actual positions, sizes, and ranges, etc. Therefore, the disclosed invention is not limited to the positions, sizes, and ranges, etc. disclosed in the drawings and the like. In addition, the drawings are not necessarily drawn to scale, and some features may be exaggerated to show details of specific components. DETAILED DESCRIPTION

[0024] Various exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that unless otherwise specifically stated, the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure.

[0025] The following description of at least one exemplary embodiment is in fact merely illustrative and is in no way intended to limit the present disclosure and its application or use. That is, the structures and methods herein are shown in an exemplary manner to illustrate different embodiments of the structures and methods in the present disclosure. However, those skilled in the art will appreciate that they merely illustrate exemplary ways of the present disclosure that can be implemented, rather than exhaustive ways. In addition, the drawings need not be drawn to scale, and some features may be enlarged to illustrate the details of specific components.

[0026] In addition, technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0027] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0028] In various data processing processes, the dot product operation of vectors is a common operation form. For example, the dot product P between a first vector A and a second vector B, each with a dimension of I d It can be expressed as: (1) in, represents the i-th component of the first vector A, represents the i-th component of the second vector B, where i is an integer and (Those skilled in the art will appreciate that the value of i may also be an integer greater than or equal to 1, which does not affect the essence of the operation. Therefore, in this article, the value of i starting from zero will be used as an example for detailed explanation).

[0029] In some examples, dot product operations of vectors can be used in image interpolation. Specifically, image interpolation is the process of inferring the values ​​of new pixels from the values ​​of known pixels. The new pixels may not be at the integer coordinates of the original image. In this case, the values ​​of these new pixels can be obtained through image interpolation algorithms. When the size, shape or position of the image changes, or in the process of video processing, in order to fill in missing frames or generate smooth slow motion effects, etc., image interpolation related to images or video frames may be required.

[0030] Depending on the image interpolation algorithm used, a corresponding coefficient vector may be determined, which may be used as the first vector in the vector dot product operation process. In a specific example, in Advanced Video Coding (AVC, H.264), a pixel value at a half-pixel position may be generated based on a coefficient vector (0, 1, -5, 20, 20, -5, 1, 0). In another specific example, in High Efficiency Video Coding (HEVC, H.265), a pixel value at a half-pixel position may be generated based on a coefficient vector (-1, 4, -11, 40, 40, -11,4, -1), a pixel value at a quarter-pixel position may be generated based on a coefficient vector (-1, 4, -10, 58, 17, -5, 1, 0), or a pixel value at a three-quarter-pixel position may be generated based on a coefficient vector (0, 1, -5, 17, 58, -10, 4, -1). In some specific embodiments below, the coefficient vector (-1, 4, -11, 40, 40, -11, 4, -1) in H.265 is taken as the first vector, and the second vector formed by the pixel values ​​of eight pixels to be processed in the image is taken as an example to explain the technical solution of the present disclosure in detail. However, it can be understood that the operation circuit and the computing device of the present disclosure can also be used to calculate the dot product between other types of vectors, or used in application scenarios other than image interpolation, which is not limited here.

[0031] like Figure 1 and Figure 2As shown, a computing device 200' may include a plurality of computing circuits 100', and the plurality of computing circuits 100' may run in parallel to process image interpolation operations associated with a plurality of groups of pixels 910 in an image 900 in parallel. Figure 1 In the image 900 shown in FIG. 1 , in the current clock cycle, the pixel values ​​(p0, p1, . . . , p10) of the pixel point 910 in the rightmost column among the pixel points that have not yet participated in the interpolation operation can be calculated. n+7 ) is input into the computing device 200' to perform image interpolation operation related to the column; and in the next clock cycle, the pixel values ​​of a column of pixel points 910 located on the left side of the column can be input into the computing device 200' to continue the image interpolation operation until the interpolation of the entire image 900 is completed. For each column of pixel points 910, each computing circuit 100' can be used to perform interpolation related to one group of pixel points 910, for example Figure 1 The respective operation circuits 100′ shown in the figure can be used to respectively execute the pixel group including the pixel points p0 to p7, the pixel group including the pixel points p1 to p8, and the pixel group including the pixel points p1 to p8. n ~p n+7 In other specific examples, the pixel values ​​of the corresponding pixels may be input into the corresponding operation circuit 100' in the computing device 200' according to the pixel rows in the image or the diagonal lines in the image, etc., to achieve the desired image interpolation operation, which is not limited here. For example, each operation circuit 100' may be responsible for the image interpolation operation associated with the pixel points 910 in a row or a column in the image 900. Each operation circuit 100' may include eight input terminals (d0, d1, d2, d3, d4, d5, d6, d7) to receive the pixel values ​​of a corresponding pixel point and an output terminal (dout) to output the dot product of the first vector and the second vector or the calculation result of the image interpolation. According to the above formula (1), a large number of multiplication and addition operations are usually involved in the vector dot product or image interpolation operation. In order to simplify the operation, the multiplication operation in the dot product calculation can be converted into shift and addition operations according to the first vector inside each operation circuit 100'. Taking the first vector A=(-1, 4, -11, 40, 40, -11, 4, -1) and the second vector B=(p0, p1, p2,p3, p4, p5, p6, p7) as examples, each element in the first vector can be converted into the sum of integer powers of 2, that is: A=(-1, 4, -8-2-1, 32+8, 32+8, -8-2-1, 4, -1). Furthermore, the dot product of the first vector A and the second vector B can be expressed as: (2) In this way, by setting a shifter in the operation circuit 100', p1 and p6 are shifted to the left by 2 bits respectively to obtain 4p1 and 4p6, p2 (or ~p2, i.e., the bit-by-bit inversion of p2), p3, p4 and p5 (or ~p5) are shifted to the left by 3 bits respectively to obtain 8p2 (or ~8p2), 8p3, 8p4 and 8p5 (or ~8p5), p2 (or ~p2) and p5 (or ~p5) are shifted to the left by 1 bit respectively to obtain 2p2 (or ~2p2) and 2p5 (or ~2p5), p3 and p4 are shifted to the left by 5 bits respectively to obtain 32p3 and 32p4, and then the dot product of the first vector A and the second vector B is obtained by setting an addition unit (or, if necessary, a subtraction unit) in the operation circuit 100'. However, according to the above formula (2), such operation mode will introduce a large number of addition (or subtraction) operations, resulting in defects such as complex structure, large circuit area, long critical path, difficulty in timing convergence and high circuit power consumption inside the operation circuit 100 ′.

[0032] In order to solve the above problems, the present disclosure provides an operation circuit and a computing device including the same. In an exemplary embodiment of the present disclosure, Figure 3 As shown, the computing device 200 may include one or more computing circuits 100, wherein the computing circuit 100 may be used to calculate the dot product of the first vector and the second vector. In an embodiment of the present disclosure, the first vector may be a pre-known coefficient vector, so that the specific setting mode of various components in the computing circuit 100 is determined according to the pre-known first coefficient in the first vector. Compared with the case where both the first vector and the second vector are uncertain, the computing circuit 100 of the present disclosure only needs to consider the uncertain second vector, which helps to simplify the circuit structure of the computing circuit 100 and the computing device 200. Further, in the case where the computing device 200 includes multiple computing circuits 100, at least two computing circuits 100 can run in parallel to improve the computing efficiency.

[0033] In some embodiments, the operation circuit 100 and the computing device 200 including the same may be configured to perform image interpolation operations. Figure 1 Similar to the description, in a specific example, for Fig.10 In the image 900 shown in FIG. 1 , in the current clock cycle, the pixel values ​​(p0, p1, . . . , p10) of the pixel point 910 in the rightmost column among the pixel points that have not yet participated in the interpolation operation can be calculated. n+7 ) and preset multiples of pixel values ​​(5p0, 5p1, ..., 5p n+7) is input into the computing device 200 to perform image interpolation operation related to the column (the operation process will be described in detail later); and in the next clock cycle, the pixel values ​​of a column of pixel points 910 located on the left side of the column and the pixel values ​​of the preset multiples can be input into the computing device 200 to continue the image interpolation operation until the interpolation of the entire image 900 is completed. For each column of pixel points 910, each operation circuit 100 can be used to perform interpolation related to one group of pixel points 910, for example Fig.10 The respective operation circuits 100 shown in the figure can be used to respectively execute the pixel group including the pixel points p0 to p7, the pixel group including the pixel points p1 to p8, and the pixel group including the pixel points p1 to p8. n ~p n+7 In other specific examples, the pixel values ​​of corresponding pixels may be input into the corresponding operation circuit 100 in the computing device 200 according to the pixel rows in the image, or according to the diagonal lines in the image, etc., to achieve the desired image interpolation operation, which is not limited here. For example, each operation circuit 100 may be responsible for the image interpolation operation associated with the pixel points in a row or a column in the image. Accordingly, the first vector may be a coefficient vector for image interpolation. It is to be understood that in other embodiments, the computing device 200 and the operation circuit 100 of the present disclosure may also be used for vector dot product operations involved in other application scenarios, etc., which are not limited here.

[0034] In the present disclosure, examples of computing device 200 may include, but are not limited to, video encoders, consumer electronics, components of consumer electronics, electronic testing equipment, image processing equipment, cellular communication infrastructure such as base stations, etc. Examples of computing device 200 may include, but are not limited to, mobile phones such as smart phones, wearable computing devices such as smart watches or headphones, phones, televisions, computer monitors, computers, modems, handheld computers, laptop computers, tablet computers, personal digital assistants (PDAs), in-vehicle electronic systems such as automotive electronic systems, stereo systems, DVD players, portable cameras, cameras such as digital cameras, portable memory chips, peripheral devices, clocks, etc. In addition, computing device 200 may include incomplete products.

[0035] In an exemplary embodiment of the present disclosure, Figure 4As shown, the operation circuit 100 may include a multiple operation module 110 and an inner product operation module 120, wherein the inner product operation module 120 is communicatively connected to the multiple operation module 110, for example, the input end of the inner product operation module 120 may be communicatively connected to the output end of the multiple operation module 110 to obtain data from the multiple operation module 110 for further calculation. It should be noted that in some first vectors, there may be a first coefficient that is a negative number, and the negative first coefficient can be reflected by subtraction, or the subtraction can be converted into addition by bit-by-bit inversion of the corresponding operands, etc., so as to perform calculation. In the following text, if a negative coefficient is involved, then depending on the specific processing method of the negative number, the negative number itself or its absolute value may be used in the specific calculation process, so the negative coefficient will be represented in the form of a (or -a).

[0036] The multiple operation module 110 can be configured to calculate a preset multiple of the first operand to generate a corresponding second operand, that is, the second operand is equal to the product of the first operand and the preset multiple. The first operand can be generated according to at least one target element in the second vector. The target element in the second vector can refer to an element that satisfies the following conditions: in the dot product calculation, the absolute value of the first coefficient multiplied by the target element in the first vector is greater than or equal to the absolute value of the preset multiple, and the preset multiple is greater than 1. In this way, by calculating the preset multiples of at least some of the target elements in the second vector in advance, the number of shifts and / or addition and subtraction calculations required to be performed during the dot product operation can be reduced, thereby simplifying the structure of the operation circuit 100.

[0037] In some specific examples, the first operand may be generated according to a single target element in the second vector. For example, the first operand may be a target element in the second vector itself. Alternatively, the first operand may be equal to the bitwise inversion of a target element in the second vector, especially when the first coefficient corresponding to the target element in the first vector is a negative number, the subtraction calculation in the dot product operation may be converted into an addition calculation by the bitwise inversion operation, thereby further simplifying the structure of the operation circuit 100.

[0038] In some other specific examples, the first operand may be generated based on at least two target elements in the second vector. For example, in the dot product operation, if the first coefficients in the first vector multiplied by two or more target elements in the second vector have absolute values ​​equal to each other, then the sum or difference of the two or more target elements in the second vector may be calculated first, and then the product of the obtained sum or difference and the coefficients may be calculated. For example, when the first vector is A=(-1, 4,-11, 40, 40, -11, 4, -1) and the second vector is B=(p0, p1, p2, p3, p4, p5, p6, p7), the values ​​of p0+p7, p1+p6, p2+p5 or p3+p4 may be calculated first, and then their products with the corresponding coefficients may be calculated. That is, as required, the first operand may be the sum or difference of two or more target elements, or may be equal to the bitwise inversion of the above-mentioned sum or difference. It can be understood that, as required, the first operand may also be obtained by calculating one or more target elements in the second vector in other ways, which is not limited here.

[0039] In addition, it should be noted that, in the second vector, there may be multiple target elements that meet the above conditions, but in some embodiments of the present disclosure, it is not necessarily necessary to ultimately convert all target elements into the form of a second operand. For example, if a first coefficient in the first vector is 6 and the preset multiple is 5, then for the element p in the second vector multiplied by the first coefficient 6, the multiple operation module 110 can be used to calculate 5p, so that 6p is expressed in the form of 5p+p for further calculation, or 5 times of this element can be not calculated, but 6p can be expressed in the form of 4p+2p for further calculation, and the number of addition operations brought about by these two methods is the same. In general, it is possible to reduce the number of required shifts and / or addition calculations by only generating the corresponding second operand based on a portion of the target elements, thereby simplifying the operation circuit 100 to a certain extent.

[0040] In some embodiments, the operation circuit 100 may include one or more multiple operation modules 110 to convert the corresponding first operand into the second operand. In addition, in the case where there are multiple multiple operation modules 110, these multiple operation modules 110 can be used to calculate the product of the corresponding first operand and the same preset multiple. Alternatively, multiple preset multiples can also be set as needed. In this case, these multiple operation modules 110 can also be used to calculate the product of the same first operand and multiple preset multiples, which is not limited here.

[0041] In some embodiments, the preset multiple can be determined according to the first vector. Generally speaking, the larger the preset multiple is, the more likely it is to convert the multiplication calculation related to the first coefficient with a larger absolute value in the first vector into less shift and / or addition calculation, but at the same time, for the first coefficient with a smaller absolute value in the first vector, it generally cannot be rewritten into a form related to the preset multiple, but can only use the original shift and addition calculation method. Therefore, the specific value of the preset multiple can be weighed according to the specific first vector. In order to simplify the operation, the preset multiple can be an integer. Further, in some embodiments, considering that the multiples of integer powers of 2 can be realized by shift operations, the preset multiple can be set to an odd number or a prime number to simplify the operation as much as possible. For example, the preset multiple can include at least one of 3 times, 5 times and 7 times. In some specific examples below, the technical solution of the present disclosure will be described in detail by taking the preset multiple of 5 times as an example.

[0042] In some embodiments, Figures 5 to 7 As shown, the multiple operation module 110 may include one or more multiple calculation units, wherein the multiple calculation unit may include a first shifter 111 or a first adding unit 112 .

[0043] exist Figure 5 In the specific example shown, the multiple calculation unit may include a first shifter 111, which may be configured to shift the fourth operand to the left by m bits to generate a fifth operand, that is, the fifth operand is 2 m The fourth operand may be a positive integer multiple of the first operand, wherein the fourth operand may be a positive integer multiple of the first operand, and m is a positive integer. For example, the value of m may be 1, and depending on the specific value of the fourth operand, the first shifter 111 may be configured to generate various even multiples of the first operand.

[0044] exist Figure 6 In the specific example shown, the multiple calculation unit may include a first addition unit 112, and the first addition unit 112 may be configured to add the sixth operand and the seventh operand to generate an eighth operand, that is, the eighth operand is the sum of the sixth operand and the seventh operand, wherein the sixth operand may be a positive integer multiple of the first operand, and the seventh operand may be a positive integer multiple of the first operand. It can be seen that, depending on the specific values ​​of the sixth operand and the seventh operand, the first addition unit 112 may be configured to generate various integer multiples of the first operand. In some specific examples, the first addition unit 112 may include an adder to perform the addition of two operands.

[0045] In addition, various multiple calculation units can also be used in combination, which is not limited here. Figure 7In the specific example shown, the first adding unit 112 may be connected to the output end of the first shifter 111 to conveniently generate the required second operand.

[0046] Furthermore, in some embodiments, Figures 5 to 7 As shown, the multiple operation module 110 may further include a first register 113, the first register 113 may be communicatively connected to at least one multiple calculation unit, and the first register 113 may be configured to register the fifth operand or the eighth operand from the multiple calculation unit. Figures 5 to 7 In the specific example shown, the first register 113 can be connected to the output end of the last stage multiple calculation unit in the multiple operation module 110, so as to reduce the burrs in the signal, help control the timing in the operation circuit 100, and ensure the correct operation.

[0047] return Figure 4 As described above, the inner product operation module 120 can be communicatively connected to the multiple operation module 110, and the inner product operation module 120 can be configured to calculate the dot product of the first vector and the second vector based on at least the second operand from the multiple operation module 110 and the second coefficient multiplied by the second operand. Wherein, for each first operand and the corresponding second operand, the product of the second coefficient and the preset multiple is less than or equal to the first coefficient. For example, if the first vector A=(5, 15, -10, 5, 5, -10, 15, 5) and the second vector B=(p0, p1, p2, p3, p4, p5, p6, p7), and the preset multiple is 5, then the inner product operation module 120 can be configured to calculate: (3) 5p0-5p7 in the above formula (3) can be pre-calculated by the multiple operation module 110, and other multiplication and addition and subtraction calculations involved can be implemented by the inner product operation module 120. The second coefficients corresponding to the second operands 5p0-5p7 are 1, 3, 2 (or -2), 1, 1, 2 (or -2), 3, 1 respectively.

[0048] In some embodiments, depending on the specific value of the first coefficient in the first vector, a target element in the second vector may be converted into the form of the sum of the product of the second operand and the target element and an integer power of 2. In this case, in order to correctly calculate the dot product of the first vector and the second vector, the inner product operation module 120 can also be configured to calculate the dot product of the first vector and the second vector according to the first operand corresponding to the second operand and the third coefficient multiplied by the first operand, wherein for each first operand and the corresponding second operand, the product of the second coefficient and the preset multiple plus the sum of the third coefficient is equal to the first coefficient. For example, if the first vector A=(6, 15, -10, 5, 5, -10, 15, 5) and the second vector B=(p0, p1, p2, p3, p4, p5, p6, p7), and the preset multiple is 5, then the inner product operation module 120 can be configured to calculate: (4) 5p0~5p7 in the above formula (4) can be pre-calculated by the multiple operation module 110. In addition, for the term related to the first operand p0, its second coefficient is 1 and the third coefficient is 1, that is, 6p0=1*5p0+1*p0. The related multiplication and addition and subtraction calculations can be implemented by the inner product operation module 120.

[0049] In some embodiments, depending on the specific value of the first coefficient in the first vector, a certain element in the second vector may not be converted into a form containing the second operand. In this case, in order to correctly calculate the dot product of the first vector and the second vector, the inner product operation module 120 can also be configured to calculate the dot product of the first vector and the second vector according to the third operand and the first coefficient in the first vector multiplied by the third operand. Wherein, the third operand is generated according to at least one element in the second vector other than the element used to generate the first operand. In some specific examples, the third operand can be generated according to a single element in the second vector. For example, the third operand can be an element in the second vector itself. Alternatively, the third operand can be equal to the bitwise inversion of a certain element in the second vector, especially when the first coefficient corresponding to this element in the first vector is a negative number, the subtraction calculation in the dot product operation can be converted into an addition calculation by the bitwise inversion operation, thereby further simplifying the structure of the operation circuit 100. In other specific examples, the third operand can be generated according to at least two elements in the second vector. For example, during the dot product operation, if the first coefficients in the first vector multiplied by two or more elements in the second vector have equal absolute values, then the sum or difference of the two or more elements in the second vector can be calculated first, and then the product of the obtained sum or difference and the coefficient can be calculated, similar to the above explanation of the first operand. As needed, the third operand can be the sum or difference of two or more elements in the second vector, or it can also be equal to the bitwise inversion of the above sum or difference. It can be understood that, as needed, the third operand can also be obtained by calculating one or more elements in the second vector in other ways, which is not limited here. For example, if the first vector A=(-1, 4, -11, 40, 40, -11, 4, -1), the second vector B=(p0, p1, p2, p3, p4, p5, p6, p7), and the preset multiple is 5, then the inner product operation module 120 can be configured to calculate: (5) 5p2~5p5 in the above formula (5) can be pre-calculated by the multiple operation module 110, and the corresponding second coefficients of these items are 2 (or -2), 8, 8 and 2 (or -2), respectively, and for the items related to the first operands p2 and p5, their third coefficients are 1 (or -1) respectively. In addition, for the items related to the third operands p0, p1, p6 and p7, their first coefficients are 1 (or -1), 4, 4, 1 (or -1) respectively. As described above, the related multiplication and addition and subtraction calculations can be implemented by the inner product operation module 120.

[0050] In some embodiments, Figure 8As shown, the inner product operation module 120 may include at least one of a second shifter 121 a and a second adding unit 122 a .

[0051] The second shifter 121a may be configured to shift the ninth operand to the left by n bits to generate a tenth operand, that is, the tenth operand is 2 n times the ninth operand, wherein the ninth operand may be the second operand, the first operand or the third operand (depending on the specific dot product operation), and n is a positive integer. In a special case, if the dot product of the first vector A and the second vector B can be written in the form of a product of a single operand and an integer power of 2, then the inner product operation module 120 may only include the second shifter 121a.

[0052] The second addition unit 122a may be configured to calculate the sum of at least a portion of the products of the second operand and the second coefficient, the first operand and the third coefficient, and the third operand and the first coefficient (depending on the specific dot product operation). In some specific examples, the second addition unit 122a may be implemented by a compression tree. The compression tree can efficiently compress multiple data into the form of the sum of two or three data. In addition, as needed, the shift operation of the relevant data can also be implemented inside the compression tree, thereby realizing the shift and addition operations involved in the dot product operation, and shifting and compressing multiple numbers into the sum of two or three numbers. Common compression trees may include compression trees with two output ends such as 4:2 compression trees and 3:2 compression trees, and may also include compression trees with three output ends such as 5:3 compression trees, 6:3 compression trees, and 7:3 compression trees. The compression tree here may be a compression tree with any number of input ends and output ends that is currently available or developed later, or a compression tree module with any number of input ends and output ends that is implemented by a combination of multiple currently available compression trees. In some other specific examples, the second adding unit 122a may also be implemented as a full adder or a combination of a full adder and a half adder. In this case, it may be necessary to use the second shifter 121a and the second adding unit 122a in combination to implement the shift and addition calculations in the dot product operation. In some other specific examples, the second adding unit 122a may include a compression tree and a full adder or a combination of a full adder and a half adder. For example, for simplicity, a compression tree with two output ends may be used in an embodiment of the present disclosure, and the two output data of the compression tree are added by an adder to obtain the final dot product operation result, as will be described in detail later.

[0053] In some embodiments, Figure 8As shown, the inner product operation module 120 may further include a second register 123a, which may be communicatively connected to the second shifter 121a or the second adding unit 122a, and the second register 123a may be configured to store the tenth operand from the second shifter 121a or the sum of the products from the second adding unit 122a, thereby reducing glitches in the signal, helping to control the timing in the operation circuit 100, and ensuring the correct execution of the operation.

[0054] It is understandable that the second shifter 121a, the second adding unit 122a or the second register 123a may be set in a variety of ways. According to the needs, their respective numbers may be one or more, and they may have various arrangements, as long as the shift and addition calculations involved in the dot product operation can be implemented, and there is no limitation here.

[0055] As mentioned above, when the first vector includes negative coefficients, in order to simplify the operation, the subtraction in the dot product operation can be converted into addition by a bit-by-bit inversion operation. For example, when a negative number is represented by a two's complement code, (-1)*b=~b+1, where ~b is the bit-by-bit inversion of b. It can be seen that the product of a negative coefficient and an element in the second vector can be expressed as the sum of the product of the absolute value of the coefficient and the element and a constant term, where the constant term is determined according to the specific value of the coefficient, and the constant term can be extracted for subsequent processing. Accordingly, in some embodiments, such as Fig. 9As shown, the operation circuit 100 may also include a bitwise inversion module 130, which may be configured to invert the first operand or the third operand multiplied by the first coefficient in the first vector when the first coefficient is a negative number, or the bitwise inversion module 130 may be configured to invert the second operand generated according to the first operand multiplied by the first coefficient. The bitwise inversion module 130 may be connected to the input end of the multiple operation module 110, that is, the elements whose corresponding first coefficients in the second vector are negative numbers are inverted bit by bit in advance for subsequent calculations, and the constant term extracted in this process may be compensated in the inner product operation module 120, or may be compensated in other appropriate positions, which is not limited here. Alternatively, the bitwise inversion module 130 may be connected between the multiple operation module 110 and the inner product operation module 120, that is, before the inner product operation module 120, to convert the subtraction that may be involved in the dot product operation into addition. Similarly, the constant term separated out in this process can be compensated in the inner product operation module 120, or can also be compensated in other appropriate positions, which is not limited here. In some embodiments, the bit-by-bit inversion module 130 can be formed by multiple inverters. Alternatively, the bit-by-bit inversion module 130 can also be formed in other ways, which is not limited here. In some embodiments, especially when the compensation of the constant term is performed in the inner product operation module 120, the second addition unit 122a can be configured to calculate the sum of at least a portion of the product of the second operand and the second coefficient, the product of the first operand and the third coefficient, and the product of the third operand and the first coefficient and a preset constant, wherein the preset constant can be determined based on the first coefficient that is at least partially negative in the first vector, that is, the preset constant and the above-mentioned constant term can be closely related.

[0056] In a specific embodiment of the present disclosure, in order to simplify the structure of the operation circuit, reduce the delay of the critical path, and correctly converge the timing, the inner product operation module 120 can be designed in the form of a three-stage pipeline. Figures 10 to 12As shown, the inner product operation module 120 may include a third addition unit 122b and a fourth addition unit 122c connected to the third addition unit 122b in communication. Wherein, the third addition unit 122b may be configured to add at least the product of the first operand and the third coefficient and the product of the third operand and the first coefficient to generate the eleventh operand and the twelfth operand. Here, the third addition unit 122b may only process the calculation related to the first operand and the third operand, so as to effectively reduce the propagation of the burr. Wherein, the third addition unit 122b and the multiple operation module 110 may run in the same clock cycle. For example, the first addition unit 112 in the multiple operation module 110 and the third addition unit 122b in the inner product operation module 120 may run in the same clock cycle to generate the second operand, and the sum of the product of the first operand and the third coefficient and the product of the third operand and the first coefficient, respectively. Then, the above operation result can be provided to the fourth addition unit 122c in the inner product operation module 120, and the fourth addition unit 122c can be configured to add at least the product of the eleventh operand, the twelfth operand and the second operand from the third addition unit 122b and the second coefficient to generate the thirteenth operand and the fourteenth operand. Here, the fourth addition unit 122c can be operated in a clock cycle after the operation clock cycle of the third addition unit 122b, so that the fourth addition unit 122c can obtain all the required data for calculation. In some specific examples, the first addition unit 112 can be in the form of a compression tree and / or an adder, and the third addition unit 122b and the fourth addition unit 122c can each be in the form of a compression tree.

[0057] Furthermore, if Fig.12 As shown, the inner product operation module 120 may further include a fifth adding unit 122d, which may be communicatively connected to the fourth adding unit 122c, and the fifth adding unit 122d may be configured to add the thirteenth operand and the fourteenth operand to generate a dot product of the first vector and the second vector. In some specific examples, the fifth adding unit 122d may be in the form of an adder.

[0058] Furthermore, in some embodiments, in order to reduce the burrs in the signal and help achieve the correct timing in the operation circuit 100, as shown in FIG. Fig.12As shown, the inner product operation module 120 may also include a third register 123b, a fourth register 123c, a fifth register 123d and a sixth register 123e. The third register 123b and the fourth register 123c may each be connected to the third adding unit 122b in a communication manner, and the third register 123b may be configured to store the eleventh operand from the third adding unit 122b, and the fourth register 123c may be configured to store the twelfth operand from the third adding unit 122b. The fifth register 123d and the sixth register 123e may each be connected to the fourth adding unit 122c in a communication manner, and the fifth register 123d may be configured to store the thirteenth operand from the fourth adding unit 122c, and the sixth register 123e may be configured to store the fourteenth operand from the fourth adding unit 122c. Under the action of the first register 113, the third register 123b and the fourth register 123c, the fourth adding unit 122c can synchronously or substantially synchronously obtain the data it needs so as to calculate the dot product of the first vector and the second vector.

[0059] Furthermore, if Fig.12 As shown, the inner product operation module 120 may further include a seventh register 123f, which may be communicatively connected to the fifth adding unit 122d, and the seventh register 123f may be configured to store the dot product of the first vector and the second vector from the fifth adding unit 122d.

[0060] like Figures 10 to 12As shown, taking the first vector A=(-1, 4, -11, 40, 40, -11, 4, -1) and the second vector B=(d0, d1, d2, d3, d4, d5, d6, d7) as examples, the first adding unit 112 can be used to calculate the values ​​of 5d2 (or ~5d2), 5d3, 5d4 and 5d5 (or ~5d5), and the first register 113 can be used to store the above values. While the first adding unit 112 is calculating, the third adding unit 122b can be used to calculate the value of (~d0)+4d1+(~d2)+(~d5)+4d6+(~d7), and the obtained two operands reg_s1 and reg_c1 ​​can be stored in the third register 123b and the fourth register 123c respectively. Then, the fourth adding unit 122c can be used to calculate the value of 2*(~5d2)+8*(5d3)+8*(5d4)+2*(~5d5)+reg_s1+reg_c1+K, where the preset constant K is generated in the process of processing the negative coefficient in the manner described above, and the fourth adding unit 122c can store the two generated operands in the fifth register 123d and the sixth register 123e respectively. Finally, the fifth adding unit 122d can add the operands stored in the fifth register 123d and the sixth register 123e to obtain the final dot product operation result, which can be stored in the seventh register 123f. By comparing Fig.11 and Figure 2 It can be seen that by adopting the technical solution of the present disclosure, the addition of 14 numbers involved in the dot product operation can be reduced to the addition of 10 numbers.

[0061] In the technical solution of the present disclosure, by pre-calculating the preset multiples of certain vector elements involved in the vector dot product operation, the number of shift and / or addition calculations required in the subsequent calculation is effectively reduced, thereby reducing the number of shifters and / or addition units required in the operation circuit, making the structure of the operation circuit simpler, reducing the circuit area, shortening the critical path, making the timing easier to converge, reducing the delay in the circuit, and reducing the power consumption of the circuit, thereby improving the performance of the operation circuit and the computing device containing it. In some examples, the operation circuit and computing device of the present disclosure can be used in the field of image interpolation, thereby effectively improving the efficiency and effect of image processing.

[0062] The words "left", "right", "front", "back", "top", "bottom", "up", "down", "high", "low", etc., in the specification and claims, if present, are used for descriptive purposes and are not necessarily used to describe an unchanging relative position. It should be understood that the words so used are interchangeable under appropriate circumstances, so that the embodiments of the present disclosure described herein, for example, can operate in other orientations than those shown or otherwise described herein. For example, when the device in the drawings is turned over, features originally described as "above" other features may now be described as "below" the other features. The device may also be oriented in other ways (rotated 90 degrees or in other orientations), and the relative spatial relationships will be interpreted accordingly.

[0063] In the specification and claims, when an element is referred to as being "on", "attached", "connected", "coupled", or "contacting" another element, the element may be directly on, directly attached, directly connected, directly coupled, or directly contacting another element, or one or more intermediate elements may be present. In contrast, when an element is referred to as being "directly" "on", "directly attached", "directly connected", "directly coupled", or "directly contacting" another element, there will be no intermediate elements. In the specification and claims, a feature being arranged "adjacent" to another feature may refer to a feature having a portion that overlaps with an adjacent feature or a portion that is located above or below an adjacent feature.

[0064] As used herein, the word "exemplary" means "serving as an example, instance, or illustration" rather than as a "model" to be exactly copied. Any implementation described as an example herein is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, the present disclosure is not to be limited by any expressed or implied theory given in the technical field, background, summary, or detailed description.

[0065] As used herein, the term "substantially" is intended to include any minor variations due to design or manufacturing imperfections, device or component tolerances, environmental influences, and / or other factors. The term "substantially" also allows for deviations from a perfect or ideal situation due to parasitic effects, noise, and other practical considerations that may exist in actual implementations.

[0066] In addition, the terms "first", "second" and the like may also be used herein for reference purposes only and are not intended to be limiting. For example, the terms "first", "second" and other such numerical terms referring to structures or elements do not imply a sequence or order unless the context clearly indicates otherwise.

[0067] It should also be understood that when the term “include / comprises” is used in this document, it indicates the presence of the specified features, integers, steps, operations, units and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, units and / or components and / or their combinations.

[0068] In addition, when used in this application, the words "herein", "above", "below", "hereunder", "above" and words of similar meaning shall refer to the entirety of this application rather than any particular portion of this application. In addition, unless otherwise expressly stated or understood in the context of use, conditional language used herein, such as "may", "might", "for example", "such as", etc., is generally intended to express that certain embodiments include, while other embodiments do not include certain features, elements and / or states. Therefore, such conditional language is generally not intended to imply that one or more embodiments require features, elements and / or states in any way, or whether these features, elements and / or states are included or performed in any particular embodiment.

[0069] In the present disclosure, the term "providing" is used in a broad sense to cover all ways of obtaining an object, so "providing an object" includes but is not limited to "purchasing", "preparing / manufacturing", "arranging / setting", "installing / assembling", and / or "ordering" an object, etc. In addition, in the present disclosure, the terms "circuit", "unit" and "module" can be used interchangeably.

[0070] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0071] Those skilled in the art will appreciate that the boundaries between the above operations are merely illustrative. Multiple operations may be combined into a single operation, a single operation may be distributed in additional operations, and operations may be performed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be changed in various other embodiments. However, other modifications, changes, and substitutions are also possible. The aspects and elements of all embodiments disclosed above may be combined in any manner and / or in combination with aspects or elements of other embodiments to provide multiple additional embodiments. Therefore, this specification and the accompanying drawings should be regarded as illustrative, not restrictive. In fact, the novel devices, methods, and systems described herein may be embodied in various other forms. In addition, various omissions, substitutions, and changes may be made to the forms of the methods and systems described herein without departing from the spirit of the present disclosure. For example, although blocks are presented in a given arrangement, alternative embodiments may perform similar functions with different components and / or circuit topologies, and may delete, move, add, subdivide, combine, and / or modify some blocks. Each of these blocks may be implemented in various different ways.

[0072] The various embodiments of the present disclosure may be described in a progressive manner, and the same or similar parts between the various embodiments may be referred to each other, and each embodiment focuses on the differences from other embodiments. In the present disclosure, the descriptions with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In the present disclosure, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in a suitable manner in any one or more embodiments or examples.

[0073] Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. The various embodiments disclosed herein may be combined in any manner without departing from the spirit and scope of the present disclosure. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A computing circuit, the computing circuit being used at least to calculate a dot product of a first vector and a second vector, wherein: The first vector is a pre-known coefficient vector, and the operation circuit includes: a multiple operation module, the multiple operation module being configured to calculate a preset multiple of a first operand to generate a corresponding second operand, wherein the first operand is generated according to at least one target element in the second vector, and in a dot product calculation, an absolute value of a first coefficient in the first vector multiplied by the target element is greater than or equal to an absolute value of a preset multiple, and the preset multiple is greater than 1; and An inner product operation module, the inner product operation module is communicatively connected to the multiple operation module, and the inner product operation module is configured to calculate the dot product of the first vector and the second vector based on at least a second operand from the multiple operation module and a second coefficient multiplied by the second operand, wherein for each first operand and corresponding second operand, the product of the second coefficient and the preset multiple is less than or equal to the first coefficient.

2. The operation circuit according to claim 1, wherein: The preset multiple is determined according to the first vector; or The preset multiple includes at least one of 3 times, 5 times and 7 times.

3. The operation circuit according to claim 1, wherein: The multiple operation module includes one or more multiple calculation units, and the multiple calculation unit includes: A first shifter is configured to shift the fourth operand to the left by m bits to generate a fifth operand, wherein the fifth operand is 2 m times the fourth operand, the fourth operand is a positive integer multiple of the first operand, and m is a positive integer; or A first adding unit is configured to add a sixth operand and a seventh operand to generate an eighth operand, wherein the sixth operand is a positive integer multiple of the first operand, and the seventh operand is a positive integer multiple of the first operand.

4. The operation circuit according to claim 3, wherein: The multiple operation module also includes: A first register is communicatively connected to at least one multiple calculation unit, and the first register is configured to register a fifth operand or an eighth operand from the multiple calculation unit.

5. The operation circuit according to claim 1, wherein: The inner product operation module is further configured to calculate the dot product of the first vector and the second vector according to the first operand corresponding to the second operand and the third coefficient multiplied by the first operand, wherein, for each first operand and the corresponding second operand, the sum of the product of the second coefficient and the preset multiple plus the third coefficient is equal to the first coefficient; and / or The inner product operation module is also configured to calculate the dot product of the first vector and the second vector based on a third operand and a first coefficient in the first vector multiplied by the third operand, wherein the third operand is generated based on at least one element in the second vector except the element used to generate the first operand.

6. The operation circuit according to claim 5, wherein: The inner product operation module includes at least one of the following: A second shifter is configured to shift the ninth operand to the left by n bits to generate a tenth operand, wherein the tenth operand is 2 n times a ninth operand, the ninth operand being the second operand, the first operand or the third operand, and n is a positive integer; and A second adding unit is configured to calculate a sum of at least a portion of a product of the second operand and the second coefficient, a product of the first operand and the third coefficient, and a product of the third operand and the first coefficient.

7. The operation circuit according to claim 6, wherein: The inner product operation module also includes: A second register is communicatively connected to the second shifter or the second adding unit, and the second register is configured to register a tenth operand from the second shifter or a sum of products from the second adding unit.

8. The operation circuit according to claim 6, further comprising a bitwise inversion module, wherein the bitwise inversion module is configured to, when the first coefficient in the first vector is a negative number, bitwise invert the first operand or the third operand multiplied by the first coefficient, or the second operand generated according to the first operand multiplied by the first coefficient; in, The second adding unit is configured to calculate the sum of at least a portion of the products of the second operand and the second coefficient, the first operand and the third coefficient, and the product of the third operand and the first coefficient and a preset constant, wherein the preset constant is determined based on at least a portion of the first coefficients in the first vector that are negative.

9. The operation circuit according to claim 5, wherein: The inner product operation module comprises: a third adding unit configured to add at least a product of the first operand and the third coefficient and a product of the third operand and the first coefficient to generate an eleventh operand and a twelfth operand, wherein the third adding unit and the multiple operation module operate in the same clock cycle; and A fourth adding unit is communicatively connected to the third adding unit and is configured to add at least the product of the eleventh operand, the twelfth operand, and the second operand from the third adding unit and the second coefficient to generate a thirteenth operand and a fourteenth operand.

10. The operation circuit according to claim 9, wherein: The inner product operation module also includes: a third register, the third register being communicatively connected to the third adding unit and the third register being configured to register an eleventh operand from the third adding unit; a fourth register, the fourth register being communicatively connected to the third adding unit and the fourth register being configured to register a twelfth operand from the third adding unit; a fifth register, the fifth register being communicatively connected to the fourth adding unit and the fifth register being configured to register a thirteenth operand from the fourth adding unit; and A sixth register is communicatively connected to the fourth adding unit and is configured to register a fourteenth operand from the fourth adding unit.

11. The operation circuit according to claim 9, wherein: The inner product operation module also includes: A fifth adding unit is communicatively connected to the fourth adding unit and is configured to add the thirteenth operand and the fourteenth operand to generate a dot product of the first vector and the second vector.

12. The operation circuit according to claim 11, wherein: The inner product operation module also includes: A seventh register is communicatively connected to the fifth adding unit and is configured to register a dot product of the first vector and the second vector from the fifth adding unit.

13. The operation circuit according to claim 1, wherein: The operation circuit is configured to perform an image interpolation operation, and the first vector is a coefficient vector for image interpolation.

14. A computing device comprising one or more computing circuits according to any one of claims 1 to 13.

15. The computing device of claim 14, wherein: In the case where the computing device includes a plurality of operation circuits, at least two operation circuits operate in parallel.

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