Xor iteration based physically unclonable function (PUF) circuit and method of operation thereof

Abstract

The application provides a physical unclonable function (PUF) circuit and an operation method based on XOR iteration, and belongs to the field of PUF design. The circuit comprises a nonvolatile transistor array, and peripheral register circuits, XOR circuits and readout comparison circuits; an initial input challenge signal R [0] , R [1] is subjected to XOR and iteration operations through the nonvolatile transistor array and the peripheral register circuits and XOR circuits, so that an nth iteration result R [n+1] is obtained, and a CRP generation process of the PUF is realized; the application can complete the verification of the PUF through a single challenge signal, significantly improves the complexity of the PUF design through multiple iteration processes, changes the internal fingerprint of the PUF through repeated erase and write operations on the transistor array, so that the PUF design has a reconfigurable function, improves the security of the PUF against machine learning modeling, and significantly reduces the hardware cost and power consumption of the PUF through simple circuit design and working steps.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of physical unclonable function design, and particularly relates to a high-security anti-modeling attack physical unclonable function (PUF) design based on XOR iteration. BACKGROUND

[0002] The vigorous expansion of edge computing and the rapid growth of mobile devices have brought about a huge demand for cloud-edge data interaction. These large numbers of edge hardware devices and the cloud storing important private information such as user security keys, behavior habits, and medical health have become key nodes vulnerable to identity attacks, asset attacks, and other attacks, causing important security problems such as data leakage. As a hardware-level security primitive, physical unclonable function (PUF) uses process fluctuations in device manufacturing or physical random mechanisms in the working process as unpredictable hardware fingerprints, providing a lightweight identity security solution for devices deployed in unattended environments, and is widely used in device identity verification and various communication security protocols. As a physical entity, PUF can perform external undetectable and mathematically unpredictable black-box processing (interaction with its random fluctuations) on a given input (challenge signal Challenge, referred to as C), and then convert it into output (response signal Response, referred to as R).

[0003] Because the black-box operation is essentially determined by the physical mechanism and circuit design inside the PUF, the mapping relationship of its input-output signals, i.e., the challenge-response pair (Challenge-Response Pair, CRP), can be used as a hardware-level unique fingerprint for legal identity verification of devices. In the actual verification process, the CRP is binary, and the PUF will first register with the cloud in a secure environment: the cloud sends enough different C and collects the R returned by the PUF, and establishes a CRP library for the PUF entity in the cloud. In an insecure environment, before the PUF requests to establish communication with the cloud, the cloud will randomly select a small part of C from the established CRP library and send it to the PUF, compare the matching degree of the response result R of the PUF entity this time with the existing R in the library, and if it exceeds the judgment threshold (such as 95%), it can be considered that the PUF is a legal identity.

[0004] Since the "fingerprint" is only determined by the physical differences and manufacturing deviations inside the PUF, and it has the properties of tamper-proof, unmodelable, anti-collision and stable reproducible, etc. The security of PUF is one of the most important indicators. However, the anti-modeling security of the traditional CMOS PUFs such as static random memory (SRAM-PUF) and arbiter-PUF reported at present often needs complex circuit design, which will bring significant hardware and power consumption overhead when deployed in edge devices; at the same time, the traditional CMOS PUF uses the random deviation in the process of manufacturing as an entropy source, and the fingerprint does not have the ability of CRP reconfiguration, which faces the privacy security risk when the user replaces it. In order to solve the above problems of overhead and reconfiguration, new non-volatile (NVM) PUFs such as resistive random memory (RRAM-PUF) and magnetic random memory (MRAM-PUF) are proposed. Among them, RRAM-PUF uses the I-V nonlinearity or threshold switching randomness of the conductive filament as an entropy source, and MRAM-PUF uses the flipping randomness of the free layer under the action of the current magnetic field as an entropy source; finally, the CRP is generated by the linear summation and comparison of the device current in the array. However, the simple spatial coupling method such as linear operation in the CRP generation process has the security problem of PUF under the modeling attack of machine learning, such as the speculation attack based on greedy algorithm and simulated annealing. At the same time, these PUFs need to compare a large number of C and R for identity judgment during verification, but these leaked CRP may cause the attacker to model all CRP through machine learning and other modeling methods. Therefore, it is of great significance to realize the reconfigurable function, improve the CRP coupling complexity of PUF and reduce the leaked CRP information for realizing the PUF circuit with high security and anti-machine learning modeling. SUMMARY

[0005] In view of the problems existing in the prior art, the present application provides a physical unclonable function (PUF) circuit and an operation method thereof based on XOR iterative operation to realize high security and anti-modeling attack, which realizes a CRP generation method that is more difficult to model and predict with lower hardware cost, improves the coupling complexity of CRP, and has a reconfigurable function. Compared with the PUF based on traditional CMOS or NVM, the present application breaks through the verification method of PUF which needs to verify a large number of C and corresponding R at the same time, directly iterates R as a new C, and uses a single C to complete the verification, avoiding the risk of machine learning modeling caused by CRP leakage.

[0006] The technical scheme of the present application is as follows:

[0007] A physical unclonable function (PUF) circuit based on XOR iteration is used for generating PUF challenge-response pairs (CRPs). The circuit comprises: a non-volatile transistor array, and a peripheral register circuit (DFF), an XOR circuit (XOR), and a readout comparison circuit. The non-volatile transistor array is an m-row and m-column array structure composed of basic units composed of two non-volatile transistors connected by a circuit. In the array structure, two word lines WL and The bit line BL of each column of basic units is connected to the drive circuit, and the sense line SL is connected to the readout comparison circuit; the gates of the two non-volatile transistors in the basic unit are opposite and axially symmetrical, with the gate of one transistor connected to the word line WL and the gate of the other transistor connected to the complementary word line WL. The drains of the two non-volatile transistors are connected to the bit line BL and the sources are connected to the sense line SL. In the basic unit, the storage states of the two non-volatile transistors are complementary, and the level states of the two word lines WL connected to their gates are also complementary.

[0008] The register circuit includes a register circuit 1 and a register circuit 2, which are used to store and update the response R vector of the physical unclonable function PUF during the XOR iterative calculation process. The register circuit 1 stores the response R of the current iterative calculation and inputs the binary "1" and "0" in R as high and low levels respectively to the word lines of the row basic units of the non-volatile transistor array in a row-by-row manner. At the same time, the register circuit 1 outputs the response R of the previous iterative calculation to the register circuit 2.

[0009] The readout comparison circuit is used to read and compare the current of the non-volatile transistor array SL, through the sense amplifier (SA) connected to each column SL and the threshold current I ref Perform size comparison and output "1" or "0" bit signal to the XOR circuit;

[0010] The XOR circuit is used to perform a bitwise XOR operation on the R vector output by the register circuit 1 and the current comparison result vector output by the readout comparison circuit, and output the result to the register circuit 2.

[0011] Further, the non-volatile transistor is a floating-gate or charge-trapping field effect transistor, that is, a storage layer is inserted in the gate stack, the storage layer is composed of a floating gate / capture layer and a tunneling dielectric layer, and the threshold voltage of the transistor is modulated by charge trapping / de-trapping of the channel; or a ferroelectric field effect transistor (FeFET), that is, a ferroelectric material is inserted in the gate stack, and the threshold voltage of the transistor is modulated by changing the polarization state of the ferroelectric material.

[0012] The application also provides an operation method of the above-mentioned XOR iteration-based physical unclonable function (PUF) circuit, for generating a PUF challenge-response pair (CRP), characterized in that the steps include:

[0013] 1) Writing a fingerprint matrix W into the basic cells of the m-row and m-column non-volatile transistor array, W being a binary matrix of “0” and “1”, and each basic cell storing one element in W in the two storage states of the complementary transistors;

[0014] 2) Inputting a response R vector corresponding to an initial challenge signal C, denoted as R [0] and R [1] , respectively storing R [0] in register circuit 1 and R [1] in register circuit 2 as the initial seed of iteration;

[0015] 3) Taking the R vector stored in register circuit 2 as the WL input of the non-volatile transistor array, performing in-memory computing in each basic cell, and outputting the current of each column of the non-volatile transistor array to the readout comparison circuit as the SL current, to obtain the comparison result f(R ref ,W) of the current of each column of the non-volatile transistor array and the threshold current I [n] of the sense amplifier, n representing the number of iterations and taking the current iteration number as the value;

[0016] 4) Taking the comparison result f(R [n] ,W) and R [n-1] stored in register circuit 1 as two inputs of the XOR circuit, performing bitwise XOR operation, and obtaining the new input R [n+1] of the next iteration;

[0017] 5) Storing the new input R [n+1] of the next iteration in register circuit 2, and storing R [n] stored in register circuit 2 before this time in register circuit 1, for the next XOR iteration;

[0018] 6) continuously repeat the operation in step 3) to step 5) for a certain number of iteration processes until a predetermined number of iterations is reached, and output the result stored in the register circuit 2 at this time.

[0019] Further, in the operation method, the threshold current I of the sensitive amplifier ref is I ref =m / 2*I on , where I on is the on-state current of the non-volatile transistor output, and m is the number of rows of the non-volatile transistor array, and m is an odd number.

[0020] The present application uses an XOR iterative operation to an initial input challenge signal C=R [0] , R [1] , which is continuously XORed and iterated by the non-volatile transistor array and the peripheral circuit, to obtain the nth iteration result R [n+1] , and realizes the CRP generation process of the PUF. Compared with the previous PUF verification method which requires multiple C and multiple corresponding R, the present application only needs one challenge signal C to complete the verification process, reduces the exposure of PUF information, improves the security of PUF against machine learning modeling, and significantly reduces the hardware cost and power consumption of PUF through simple circuit design and working steps. Compared with the prior art, the present application has the following beneficial effects:

[0021] 1. The present application has essential differences from the existing PUF based on multiple CRPs for identity verification, which uses an XOR iterative scheme to complete the PUF verification with a single challenge signal, avoids the security problem of machine learning modeling attack caused by the need to expose multiple CRPs in traditional PUF, and improves the verification efficiency.

[0022] 2. The present application significantly improves the complexity of PUF design through multiple iteration processes, improves the CRP coupling complexity by continuously XORing and iterating R, further expands the time dimension coupling scheme between the front and rear sequences in the spatial coupling dimension of the conventional PUF design idea, and greatly improves the ability to resist modeling attacks.

[0023] 3. The PUF design of the present application has a reconfigurable function, because the fingerprint matrix W written in the basic unit of the non-volatile transistor array can be changed arbitrarily, and when user replacement or information erasure is needed, the transistor array can be repeatedly erased and written, the internal fingerprint of the PUF is changed, and the CRP relationship is reconstructed. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 is a schematic diagram of the principle of the physical unclonable function PUF;

[0025] Figure 2 Data flow chart and mathematical principle diagram of the XOR iterative PUF described in the present application;

[0026] Figure 3 Data flow chart and mathematical principle diagram of the XOR iterative PUF circuit structure design provided according to an embodiment of the present application;

[0027] Figure 4 An embodiment of the non-volatile transistor described in the present application, i.e. the device structure of the non-volatile transistor; the left and right characteristic curves in the device transfer characteristic curve (drain-source current-gate-source voltage) respectively represent the low threshold voltage (store "1") and the high threshold voltage (store "0");

[0028] Figure 5 PUF randomness simulation results obtained by the XOR iterative operation method proposed in the present application. DETAILED DESCRIPTION

[0029] The present application will be further clarified by the following embodiments, which are described with reference to the accompanying drawings. Although specific embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided so that the present application can be more thoroughly and completely understood, and the scope of the present application can be fully conveyed to those skilled in the art.

[0030] Figure 1 The working diagram of the physical unclonable function, which is a physical entity, processes the input challenge signal and converts it into a response signal for output. According to the challenge-response pair CRP of the PUF, it can be used as its unique identity code for subsequent hardware security requirements. The complexity of the PUF design ensures that it is difficult to predict and model the CRP relationship, and the CRP relationship between the same PUF is different and unique. Before most of the currently reported PUFs work, they will first be registered in a secure environment. At this time, the cloud sends a large number of different C and collects the R returned by the PUF to establish the CRP library of the PUF. When working, the cloud will randomly select a small part of C from the existing CRP library and send it to the PUF, and compare whether the response R returned by the PUF matches the existing R in the library.

[0031] The PUF designed in the present application does not need multiple C and multiple R for verification, only one C=R [0] , R [1] as the initial seed of iteration, which can continuously generate the sequence R [0] , R [1] , R [2] , …, R [n] , R [n+1]The specific operation method of the PUF is as follows: Figure 2 As shown in one embodiment, namely:

[0032]

[0033] In the formula, the square brackets in the subscript of R represent the number of iteration cycles, and the numbers without square brackets represent the sequence index of the vector. R itself is a binary vector of "0" / "1"; and the W matrix is ​​the binary matrix stored in the non-volatile transistor array of the PUF. The function operation f(·) is as follows Figure 2 As shown in the m×m matrix in the solid line frame of the embodiment, the function operation is mathematically equivalent to the input column vector R [n] =[R1,R2,…R m ] T Perform bit-by-bit XOR and column-wise sum operations with each column vector of the fingerprint matrix W (i.e., the Hamming distance between two column vectors), and the result of the j-th column is Where i is the index of the row. Then the HD of each column is obtained. j (From HD1 to HD m ) will be compared with m / 2 (m is a dimensionless odd number to ensure that the result of the comparison will not be "equal") and the output will be bit "1" or "0" according to the size. The result of the function operation is recorded as f(R [n] ,W). Subsequently, f(R [n] ,W) will be the same as the last iteration result R [n-1] Perform bit-by-bit XOR operation to obtain new iterative input Complete one XOR iteration process.

[0034] exist Figure 3 An embodiment of a PUF circuit design based on the above XOR iterative operation is shown in the figure. The circuit includes a non-volatile transistor array, as well as a peripheral register circuit (DFF), an XOR circuit (XOR), and a readout comparison circuit (SA). The non-volatile transistor array is a basic unit composed of two non-volatile transistors with complementary storage states, which are connected by circuits to form a multi-row and multi-column array structure. In the array structure, the two word lines WL and The bit line BL of each column of basic cells is connected to the driving circuit, and the sense line SL is connected to the readout comparison circuit (SA); the drains of the two non-volatile transistors in the basic cell are connected to the bit line BL, the sources are connected to the sense line SL, and the gate of the upper transistor is connected to the word line WL, and the gate of the lower transistor is connected to the complementary word line WL. In a basic cell, the storage states of the two nonvolatile transistors are complementary, and the level states of the two word lines connected to their gates are also complementary.

[0035] The fingerprint matrix W is stored in a non-volatile transistor array, and the R of different iteration cycles is completed through the register circuit DFF and the XOR circuit XOR of the peripheral circuit. [n] The storage and output are completed by the readout comparison circuit SA and I ref =m / 2·I on Specifically, it is based on an AND-type transistor array, whose basic unit is two non-volatile transistors ( Figure 3 The two word lines WL and WL connected to the gate terminals of the two complementary non-volatile transistors are The levels of the leftmost register circuit 2 are always complementary during operation, and the source terminals of the transistors in the same column are connected to the sense line SL. [n] As the level of WL is complementary to the input into the array, the i-th bit signal R [n],i The binary "1" / "0" value of the i-th row word line WL i For example, R [1],1 =1, R [1],2 =0, then the levels of the first to fourth word lines WL should be WL1 = High, And WL2=Low,

[0036] like Figure 4 The figure shows the structure and electrical characteristics of a non-volatile transistor. The additional functional layer in the gate stack can non-volatilely control the potential of the channel, thereby changing the threshold voltage of the device, achieving the ability to non-volatilely store "1" or "0" data, where the low threshold state is "1" and the high threshold state is "0". Since the non-volatile transistor only inputs a voltage level V at the high gate terminal, G = High, storage data is "1" (w ij =1) can output the on-state current I only when both are met on , in other cases it is in the off state I off , so it is essentially a V G and w ij Perform AND operation in the analog domain. Since the word line gate levels and weights in the same basic unit are complementary, the sum of the currents of the two transistors in the i-th row is So the sum of the SL currents of the m 2T cells in the jth column is That is, the jth column SL current and the input vector R [n]and the jth column weight vector w j is proportional to the Hamming distance of R ref and the threshold current I on = m / 2 · I ref The m comparison results of the m columns of SLs can be obtained by simultaneously comparing the current of each column of SLs with the threshold current I [n] The comparison result of the size of each column of SLs and the threshold current I [n-1] is a probability-equal "1" or "0".

[0037] Subsequently, the binary comparison result vector f(R [n+1] , W) will be bitwise XOR operated with the previous iteration result R [n] to obtain a new iteration input vector R [n+1] . Figure 3 The two register circuits in R [n-1] will update the data respectively, wherein the left register DFF circuit 2 will update from R [n] to R [0] , and the lower register DFF circuit 1 will update from R [1] to R [n] , for the next XOR iteration process. When the PUF authentication is performed, the input challenge signal C is the initial iteration seed R [0] and R [1] , and the identity can be authenticated by comparing the output sequence R [n] of a specific iteration number (such as n = 1000, 2000, etc.) with the consistency stored in the cloud. This scheme avoids the security problem caused by exposing many CRPs during authentication, and also reduces the amount of CRP data stored in the cloud and the authentication delay. Because the cloud only needs to store the initial iteration seed R [n+1] and R [n] and the fingerprint matrix W, any R [n] can be obtained by software mathematical iteration.

[0038] Figure 5 The Monte Carlo simulation of R [n+1] = f(R [n] , W) shows the advantages of the XOR iteration scheme of the embodiment of the application (the weight matrix W is omitted in the four formulas written in the figure for convenience). Compared with other iteration operations (including R [n] = f(R min , W), and three different iteration methods), the minimum entropy (that is, H = -log2 max{p0, p1}) of R [n] generated by iteration gradually converges to S = 1.0 as the array size increases, and the convergence speed and effect of the XOR iteration scheme proposed in the application are the best.Figure 5 The output bits on the right directly reflect that the scheme of the present application has a truly random irregular distribution, while the other three schemes have certain graphic regularity.

[0039] The present embodiment completely and in detail sets forth the principle and mode of the high-security PUF based on the XOR iterative operation and the non-volatile transistor array, avoids the potential information exposure problem of needing multiple CRPs for verification, has significantly improved machine learning modeling security compared to other PUF schemes, improves the CRP identity verification speed of the PUF, and simultaneously realizes the reconfigurability of the PUF at a lower hardware cost.

[0040] Finally, it should be noted that the purpose of the disclosed embodiments is to help further understand the present application, but those skilled in the art can understand that various replacements and modifications are possible without departing from the spirit and scope of the present application and the appended claims. Therefore, the present application should not be limited to the disclosed embodiments, and the scope of the present application is defined by the scope of the claims.

Claims

1. A XOR-iteration-based physically unclonable function (PUF) circuit for generation of a PUF challenge-response pair (CRP), characterized in that, The circuit comprises: a non-volatile transistor array and peripheral register circuit DFF, XOR circuit, readout comparison circuit, the non-volatile transistor array is composed of two non-volatile transistors by circuit connection to form the basic unit Row Column array structure, in which the two word lines of each row of basic units And Connected to the register circuit, the bit line BL of each column of basic units is connected to the driving circuit, and the sense line SL is connected to the readout comparison circuit;The gates of the two non-volatile transistors in the basic unit are opposite and in axial symmetry structure, one of which is connected with the word line WL , and the gate of the other transistor is connected with the complementary word line , the drain of which is connected with the bit line BL, and the source of which is connected with the sense line SL, in the basic unit, the storage state of the two non-volatile transistors is complementary, and the level state of the two word lines WL connected with their gates is also complementary. The register circuit includes register circuit 1 and register circuit 2, which are used for storage and update of the response R vector of the physically unclonable function (PUF) in the XOR iterative calculation process; register circuit 2 stores the response R of the current iterative calculation and inputs binary "1" and "0" in R as high and low levels respectively into the word line of the row basic unit of the non-volatile transistor array in rows, while register circuit 2 outputs the response R of the previous iterative calculation to register circuit 1; The readout comparison circuit is used for the readout and comparison of the non-volatile transistor array SL current, through the sensitive amplifier SA connected by each column SL, and the threshold current of the SA I ref The size comparison is performed, and a "1" or "0" bit signal is output to the XOR circuit; The XOR circuit is used for performing bit-by-bit XOR operation on the R vector output by the register circuit 1 and the current comparison result vector output by the readout comparison circuit, and the result is output to the register circuit 2.

2. The XOR iteration based physically unclonable function (PUF) circuit of claim 1, wherein, The non-volatile transistor is a floating-gate type or charge-trapping type field effect transistor, that is, a storage layer is inserted in the gate stack layer, the storage layer adopts a semiconductor material composed of a floating gate / capture layer and a tunneling dielectric layer, and the threshold voltage of the transistor is modulated by charge trapping / de-trapping of the channel; or a ferroelectric field effect transistor, that is, a layer of ferroelectric material is inserted in the gate stack layer, and the threshold voltage of the transistor is non-volatile modulated by changing the polarization state of the ferroelectric material.

3. A method of operation of a XOR-iteration-based physically unclonable function (PUF) circuit, implemented using the XOR-iteration-based physically unclonable function (PUF) circuit of claim 1, for the generation of a PUF challenge-response pair (CRP), characterized by the steps of Comprise: 1) to row basic unit of a nonvolatile transistor array writes a fingerprint matrix W , W is a "0" and "1" binary matrix, two storage states of each basic unit are complementary transistors W one element in 2) Input the response R vector corresponding to the initial challenge signal C, denoted as R [0] and R [1] , respectively R [0] Stored in register circuit 1 and R [1] Stored in register circuit 2 as the initial seed for iteration; 3) R vector stored in register circuit 2 is inputted as WL of non-volatile transistor array, in each basic cell, the in-memory calculation is carried out, and the current outputted as SL to the readout comparison circuit, to obtain the comparison result of each column current of non-volatile transistor array and threshold current of sensitive amplifier I ref , n represents the number of iteration cycles, and takes the current iteration number as the value;​ 4) comparison result and R stored in register circuit 1 [n-1] as two inputs of the XOR circuit, respectively, to perform a bitwise XOR operation to obtain the new input R for the next iteration [n+1] ; 5) the new input R for the next iteration is stored in register circuit 2 and the R previously stored in register circuit 2 is stored in register circuit 1 for the next XOR iteration. [n+1] 5) the new input R for the next iteration is stored in register circuit 2 and the R previously stored in register circuit 2 is stored in register circuit 1 for the next XOR iteration. [n] 5) the new input R for the next iteration is stored in register circuit 2 and the R previously stored in register circuit 2 is stored in register circuit 1 for the next XOR iteration. 6) continuously repeat the operations in steps 3) to 5), perform a certain number of iteration processes, until a predetermined number of iterations is reached, and output the result stored in the register circuit 2 at this time.

4. The method of operation of an XOR iteration based physically unclonable function (PUF) circuit according to claim 3, characterized in that, The threshold current I of the sensitive amplifier in the operation method ref is where I on is the on-state current of the non-volatile transistor output, is the number of rows of the non-volatile transistor array, is an odd number.

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