A layout design method for processing new metal layers and replacing metal layers

Abstract

The object of the present invention is to provide a layout design method for processing newly added metal layers and replacing metal layers, the method comprising: obtaining a process switching requirement; setting layout parameters according to the process switching requirement; and running a verification process to verify the feasibility of the layout. The present invention can consider various possible situations together, perform process replacement at one time, and complete the IPtop module quickly and accurately. While efficiently replacing, it separates power, Ground and signal nets, and processes power and Ground with the emphasis on not increasing EMIR, while clk and data are processed with the emphasis on not increasing RC parasitics.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design. Specifically, it relates to a layout design method for processing newly added metal layers and replacing metal layers. Background Art

[0002] In integrated circuit design, layout design is a very important design link. This is because for an integrated circuit to fully play its role in a certain product system, it not only needs to have professional circuit design but also good layout design to meet the requirements of its installation process. Currently, the importance of integrated circuit layout design in electronic products is increasing, and how to improve the level of integrated circuit layout design has become the most concerned issue for relevant technical personnel. In the process of integrated circuit design, layout design is the last design link, playing a finishing role, and is carried out on the basis of previous system design, logic design, and circuit design. The layout design of an integrated circuit includes many aspects and is a necessary means to topologize a circuit into an electronic chip. Since previous integrated circuit designs were completed on drawings, in order to apply these designs to actual integrated circuit chips, it is necessary to perform circuit layout and layout design on them.

[0003] In chip design, process switches often occur due to various reasons, mainly including the following situations: switching between different metal cross-sections at the same process node in the same semiconductor manufacturer and transplantation between similar process nodes in different semiconductor manufacturers. The present invention is a method applicable to the realization of the first type of switching. And the switching between different metal cross-sections at the same process node in the same semiconductor manufacturer includes the following situations: reduction of metal layers when the metal thickness remains unchanged; increase of metal layers when the metal thickness remains unchanged; change of metal thickness when the number of metal layers remains unchanged; and a combination of the above three situations. For the above various situations, if the switching is purely carried out manually, it is easy to miss processing, and it is found in the verification stage, causing repeated iterative modifications, greatly increasing the labor cost. Currently, in the chip tape-out process, in order to perform MPW or shuttle with other companies, the completed projects are often switched in process, making it difficult to quickly switch the process and ensure the balance between the accuracy after process switching and the unaffected post-simulation verification. Summary of the Invention

[0004] The object of the present invention is to provide a layout design method for processing newly added metal layers and replacing metal layers. This method takes into account all possible situations and performs the process replacement at one time to quickly and accurately complete the IPtop module. While achieving efficient replacement, it separates power, ground, and signal nets. Power and ground are focused on not increasing EMIR, while clk and data are processed in a way that focuses on not increasing RC parasitics.

[0005] A layout design method for processing newly added metal layers and replacing metal layers, comprising:

[0006] Obtaining process switching requirements;

[0007] Setting layout parameters according to the process switching requirements;

[0008] The setting of layout parameters according to the process switching requirements includes:

[0009] For the newly added PDK metal layer, judging the power, ground, and signal nets of the chip layout;

[0010] Judging the DRC situation of the newly added metal layer and the DRC situation of the newly added vias;

[0011] The judging of the DRC situation of the newly added metal layer and the DRC situation of the newly added vias includes:

[0012] If the thickness and DRC of the newly added metal layer are the same as those of the adjacent metal layer in the original PDK, replace the original via with the via define of the new PDK;

[0013] Directly use the current layer as the reference and copy it in the ways of PG and signal respectively;

[0014] Directly copy the metal layer of the current layer at the power and ground nets, and then fill the vias between the newly added metal layer and the adjacent metal layer;

[0015] For the signal net, copy the newly added metal layer at the overlapping part of the original upper and lower layer connections, and then copy the original via metal layer as the upper and lower layer vias of the newly added via layer;

[0016] If the thickness and DRC of the newly added metal layer are different from those of the adjacent metal layer in the original PDK, replace the original via with the via define of the new PDK, and judge the minimum width, maximum width, space of the newly added metal layer and the adjacent metal layer, and the situation of the newly added vias;

[0017] Select the adjacent upper-layer metal, and screen at the place where the maximum width is greater than the maximum width of the newly added metal layer, and change it to the maximum width of the newly added metal layer;

[0018] The minimum space meets the requirements of the newly added metal layer, and the vias are filled according to the rules;

[0019] Run the verification process to verify the feasibility of the layout.

[0020] Preferably, the process switching requirements include:

[0021] Add a new PDK metal layer;

[0022] Replace the PDK metal;

[0023] Both add a new PDK metal layer and replace the PDK metal.

[0024] Preferably, the networks for judging the power, ground, and signal of the chip layout include:

[0025] Mark various networks, and perform additional processing on the POWER after the LDO on the layout;

[0026] If there is no VDD or VSS mark on the power or Ground network, it is defaulted to signal.

[0027] Preferably, the setting of layout parameters according to the process switching requirements includes:

[0028] For replacing the PDK metal, judge the difference between the metal layer after replacement and the existing metal layer;

[0029] Directly replace the metal layer;

[0030] When processing vias, delete the original vias, and then punch holes for the newly added metal layer at the same position. The punching is calculated according to the number of existing holes, and the holes required by the PDK are regenerated according to the parameter information of the original holes.

[0031] Preferably, the setting of layout parameters according to the process switching requirements includes:

[0032] For both adding a new PDK metal layer and replacing the PDK metal, first replace the PDK metal, and then add the PDK metal layer.

[0033] Preferably, the running of the verification process to verify the feasibility of the layout includes:

[0034] Run DRC check to verify whether the layout design rules are correct;

[0035] Run LVS verification to verify whether the layout is consistent with the circuit.

[0036] A layout system for quickly processing new metal layers and replacing metal layers, comprising:

[0037] A data acquisition module for acquiring process switching requirements;

[0038] A data processing module for setting layout parameters according to the process switching requirements;

[0039] A verification module for running a verification process to verify the feasibility of the layout.

[0040] An electronic device, comprising: a chip, a processor, and a memory. The memory is used to store computer program code, and the computer program code includes computer instructions. When the chip executes the computer instructions, the electronic device executes a layout design method for processing new metal layers and replacing metal layers.

[0041] The beneficial effects of the present invention are as follows: Through a series of processes such as SKILL, svrf, gdsmerge, and PV verification, the present invention quickly traverses and processes the layout in the specified library, and finally performs PV verification of the new process on the switched layout, mainly including DRC and LVS verification. In high-speed IP modules, it is also necessary to distinguish signals clk, datanet, and Power / Ground. How to handle these signal nets during the process switch is crucial to the performance of the IP. To ensure that clk and datanet are not affected by the switched process, in the present invention, non-power / ground metal traces are classified into one category, and power and ground are classified into another category. In this way, different logics are used for processing when performing metal layer superposition, replacement, and reduction, quickly completing the process switch and ensuring that the performance of high-speed IP is not affected. It can minimize the later manual modification man-hours. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The accompanying drawings herein are incorporated into the specification and form a part of the specification, indicating the embodiments consistent with the present invention, and are used together with the specification to explain the principles of the present invention.

[0043] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the accompanying drawings required for the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without creative efforts.

[0044] Figure 1 It is a flowchart of a layout design method for processing new metal layers and replacing metal layers according to the present invention;

[0045] Figure 2 Schematic diagram of the layout system structure for quickly processing newly added metal layers and replacing metal layers according to the present invention;

[0046] Figure 3 Schematic diagram of the hardware structure of an electronic device according to the present invention. Detailed implementation manners

[0047] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0048] It should be noted that all directional indications (such as up, down, left, right, front, back...) in the embodiments of the present invention are only used to explain the relative position relationship and movement conditions between components in a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indications will also change accordingly.

[0049] In addition, the descriptions involving "first", "second", etc. in the present invention are only for descriptive purposes, and cannot be understood as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions between various embodiments can be combined with each other, but it must be based on the ability of those of ordinary skill in the art to implement. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the protection scope required by the present invention.

[0050] In chip design, process switches often occur due to various reasons, mainly including the following situations: the switch between different metal cross-sections at the same process node in the same semiconductor manufacturing plant and the transplantation between similar process nodes in different semiconductor manufacturing plants. The present invention is a method applicable to the implementation of the switch based on the first situation. The switch between different metal cross-sections at the same process node in the same semiconductor manufacturing plant includes the following situations: the reduction of metal layers when the metal thickness remains unchanged; the increase of metal layers when the metal thickness remains unchanged; the change of metal thickness when the number of metal layers remains unchanged; and the combined situation of the above three situations. For the above various situations, if the switch is purely carried out manually, it is easy to miss the processing, and it is found in the verification stage, which causes repeated iterative modifications and greatly increases the labor cost. In the current chip tape-out process, in order to conduct MPW or shuttle with other companies, the completed projects are often switched in process. It is difficult to achieve a fast process switch and ensure the accuracy after the process switch, as well as the balance between the post-layout simulation verification not being affected.

[0051] The present invention traverses and processes the layout in the specified library quickly through a series of processes including SKILL, svrf, gdsmerge, and PV verification, and finally conducts PV verification of the new process on the switched layout, mainly including DRC and LVS verification. In high-speed IP modules, it is also necessary to distinguish signals clk, datanet, and Power / Ground. How these signal nets are processed during the process switch is crucial for the performance of the IP. To ensure that clk and datanet are not affected by the process switch, in the present invention, non-power / ground metal traces are classified into one category, and power and ground are classified into another category. In this way, different logics are used for processing when metal layers are stacked, replaced, or reduced, so as to complete the process switch quickly and ensure that the performance of high-speed IP is not affected. It can minimize the later manual modification man-hours.

[0052] Embodiment 1

[0053] A layout design method for processing newly added metal layers and replacing metal layers, referring to Figure 1 , including:

[0054] S100, obtaining the process switch requirement;

[0055] Chip process switching refers to the selection and replacement of different manufacturing processes during different chip manufacturing processes according to market demand and technological development. This switching usually involves transferring from one process to another to meet different production requirements and product characteristics. The main reasons for chip process switching include changes in market demand and the need for technological development. As the market demand for chips with different processes increases, manufacturers need to adjust their production strategies according to market demand. For example, 28nm chips have gradually become the market mainstream due to their wide application fields and price advantages, so manufacturers will step up the production capacity layout of 28nm chips while temporarily canceling the 14nm chip technology.

[0056] S200, set the layout parameters according to the process switching requirements;

[0057] Setting the layout parameters according to the process switching requirements includes:

[0058] For the newly added PDK metal layer, judge the power, ground, and signal networks of the chip layout;

[0059] Judge the DRC situation of the newly added metal layer and the DRC situation of the newly added vias;

[0060] Judging the DRC situation of the newly added metal layer and the DRC situation of the newly added vias includes:

[0061] If the thickness and DRC of the newly added metal layer are the same as those of the adjacent metal layer in the original PDK, replace the original via with the via define of the new PDK;

[0062] Directly use the current layer as the reference and copy it in the ways of PG and signal respectively;

[0063] At the power and ground networks, directly copy the metal layer of the current layer, and then fill the vias between the newly added metal layer and the adjacent metal layer;

[0064] For the signal network, copy the newly added metal layer at the overlapping parts of the original upper and lower layer connections, and then copy the original via metal layer as the upper and lower layer holes of the newly added via layer;

[0065] If the thickness and DRC of the newly added metal layer are different from those of the adjacent metal layer in the original PDK, replace the original via with the via define of the new PDK, and judge the minimum width, maximum width, space of the newly added metal layer and the adjacent metal layer, and the situation of the newly added vias;

[0066] Select the adjacent upper layer metal and screen the places where the maximum width is greater than the maximum width of the newly added metal layer to make it the maximum width of the newly added metal layer;

[0067] The minimum space meets the requirements for adding a new metal layer, and the vias are filled according to the rules;

[0068] The layout is a key step in transforming a circuit design into an actual chip. Through photolithography and etching technologies, the geometric patterns on the layout are transferred onto the silicon wafer to form the actual circuit structure. During the layout design process, strict design rule checks (DRC) and circuit extraction and verification (LVS) are carried out to ensure the correctness of the design and the feasibility of manufacturing, thereby improving the manufacturing accuracy and performance of the chip. The design process of the circuit layout includes: Establishing the design environment: First, a database channel needs to be established to determine the correspondence between the layout and the process. The layout diagram should be as consistent as possible with the circuit Figure 1 to ensure the testability of the chip. Use EDA tools for layout design, including steps such as layout editing, geometric parameter adjustment, connection design, design rule check, circuit extraction, and LVS verification.

[0069] S300, run the verification process to verify the feasibility of the layout.

[0070] The main contents of verifying the layout include the following aspects: DRC (Design Rule Check): Geometric design rule check, used to ensure that the layout complies with specific process design rules, avoiding potential open circuits, short circuits, or adverse effects, thereby improving the yield of chip manufacturing. ERC (Electrical Rule Check): Electrical rule check, checking electrical characteristics such as short circuits between power and ground, floating devices and connections, to ensure the normal operation of the circuit. LVS (Layout vs. Schematic): Netlist consistency check, comparing the netlist proposed by the layout with the netlist of the schematic diagram to ensure correct circuit connection relationships, matching MOS transistor sizes, correct resistance and capacitance values, etc. LPE (Layout Parameter Extraction): Layout parasitic parameter extraction, extracting parameters such as transistor sizes, parasitic capacitances, and resistances from the layout to generate a SPICE-format netlist for post-simulation verification. POSTSIM (Post-Simulation): Post-simulation, checking the impact of parasitic parameters on the design, performing switch-level logic simulation or circuit simulation through actual layout parameters to verify the correctness of the circuit function and timing performance.

[0071] Preferably, in S100, the process switching requirements include:

[0072] Adding a new PDK metal layer;

[0073] Replacing the PDK metal;

[0074] Both adding a new PDK metal layer and replacing the PDK metal.

[0075] The metal layers in the PDK refer to the multi-layer metal interconnect structures used to connect transistors and other electronic components during the integrated circuit design and manufacturing process. These metal layers are typically made of copper or aluminum, isolated in insulating layers, and connected together through vertical connections (vias). Each metal layer has specific design rules, including width, spacing, and connection methods with other layers, etc. In integrated circuit design and manufacturing, the main role of metal layers is to provide complex interconnect solutions to meet different application and performance requirements. The multi-layer metal stack usually includes bottom layers (such as M1, M2, etc.) for local interconnects, while upper layers (such as Mx, where x is a larger number) are used for longer-distance global interconnects or power / ground lines. The number and type of metal layers can be adjusted according to different processes or process variants to adapt to different application and performance requirements. In different processes, the number of metal layers can vary significantly. For example, one process may offer 6 layers of metal interconnects (referred to as the 6M option) or more, such as 10 layers of metal (referred to as the 10M option). Each option has its specific performance and cost trade-offs. More metal layers usually mean higher manufacturing costs, but also offer higher performance and more design flexibility, especially in complex IC designs such as high-performance or multi-core processors.

[0076] Preferably, in S200, setting the layout parameters according to the process switching requirements includes:

[0077] For the newly added PDK metal layer, judge the power, ground, and signal networks of the chip layout;

[0078] ‌PowerNet‌ refers to the power network in the circuit, mainly used to provide the DC power required by the circuit. In the layout, the power network is usually represented by specific layers (such as the VCC or VDD layer), which are used to connect various components and modules in the circuit to ensure that they can obtain a stable power supply. The power network design should ensure a reasonable layout of the power network, avoid long-distance power supply, and reduce voltage drop and electromagnetic interference.

[0079] ‌GroundNet‌ refers to the ground network in the circuit, mainly used for signal return and electromagnetic shielding. The ground network is usually represented by the GND layer to ensure that the current in the circuit can flow back to the negative power supply smoothly, while reducing electromagnetic interference and noise. The design of the ground network is crucial for the stability and performance of the circuit. The ground network design should adopt a single-point grounding or multi-point grounding strategy to ensure the lowest impedance of the signal return path and reduce ground bounce and noise.

[0080] ‌SignalNet‌ refers to the signal network in a circuit, which is used to transmit various electrical signals. The signal network is represented by different layers, such as data lines, control lines, etc., to ensure that signals can be transmitted correctly and stably in the circuit. The design of the signal network needs to consider signal integrity and anti-interference ability. The design of the signal network‌ should optimize the layout and routing of signal lines, avoid long parallel routings and interference from high-frequency signals, and ensure signal integrity and transmission rate.

[0081] Judge the DRC situation of the newly added metal layer and the DRC situation of the newly added vias.

[0082] Before adding a new metal layer, a design rule check (DRC) must be performed to ensure that the design rules allow the addition of the new layer and to understand the usage limitations of the new layer, such as minimum line width, spacing, Via size, etc.

[0083] When selecting the via type, rules such as semi-conductor vias (buried vias) can be set. The specific operations include selecting the via type, setting the semi-conductor via rules, etc.

[0084] Preferably, judging the power, ground, and signal networks of the chip layout includes:

[0085] Mark various networks, and perform additional processing on the POWER after the LDO on the layout;

[0086] ‌The POWER after the LDO usually refers to the output voltage or current regulated by the LDO voltage regulator.‌ LDO (Low Dropout Regulator) is a low-dropout linear voltage regulator, whose main function is to subtract the excess voltage from the input voltage to generate a regulated output voltage. In a circuit, the LDO is usually located between the power supply and the load to provide a stable DC power supply. The output voltage or current regulated by the LDO is called POWER, that is, the power output. The LDO maintains the stability of the output voltage through an internal adjustment element (usually a transistor or a field-effect transistor). When the input voltage changes, the adjustment element will automatically adjust to keep the output voltage near the set reference voltage.

[0087] In the embodiments of the present invention, labeling can facilitate users to quickly and accurately understand the layout information and classify the layout information.

[0088] There is no VDD or VSS label on the power or Ground network, and it is defaulted to signal.

[0089] VDD: It represents "Positive Supply Voltage". In CMOS logic circuits, VDD is often used to represent the supply voltage, usually the positive power supply. In field effect transistors (or CMOS devices), VDD refers to the drain voltage. VSS: It represents "Ground" or "Negative Supply Voltage". In CMOS logic circuits, VSS usually refers to ground or the negative power supply. In field effect transistors (or CMOS devices), VSS refers to the source voltage.

[0090] Preferably, judging the DRC situation of the newly added metal layer and the DRC situation of the newly added vias includes:

[0091] If the thickness and DRC of the newly added metal layer are the same as those of the adjacent metal layer in the original PDK, replace the original via with the via define of the new PDK;

[0092] Via is an important part of printed circuit board (PCB) design, used to connect conducting lines between different layers. Vias are achieved by pre-drilled holes on the PCB and passing the pins of packaged components or connectors through the holes for soldering, thereby realizing electrical connections between different layers. The types of vias include through-hole vias, blind vias, and buried vias, and each type of via has different advantages and applicability in different application scenarios.

[0093] Directly use the current layer as the reference and copy it in the ways of PG and signal respectively;

[0094] Directly copy the metal layer of the current layer at the power and ground networks, and then fill the vias between the newly added metal layer and the adjacent metal layer;

[0095] For the signal network, copy the newly added metal layer at the overlapping places where the original upper and lower layers are connected, and then copy the original via metal layer as the upper and lower layer holes of the newly added via layer;

[0096] If the thickness and DRC of the newly added metal layer are different from those of the adjacent metal layer in the original PDK, replace the original via with the via define of the new PDK, and judge the minimum width, maximum width, space of the newly added metal layer and the situation of the newly added vias;

[0097] Select the adjacent upper layer metal and screen the places where the maximum width is greater than the maximum width of the newly added metal layer to become the maximum width of the newly added metal layer;

[0098] The minimum space meets the requirements for adding a new metal layer, and the vias are filled according to the rules.

[0099] Judge the DRC situation of the newly added layer and the DRC situation of the newly added vias: If the thickness and DRC of the newly added layer are the same as those of the adjacent layers in the original PDK, replace the original vias with the viadefine of the new PDK, and then this layer can be directly used as a reference and copied in the PG and signal manners respectively. For the power and groundnet areas, directly copy this metal layer, and then fill the vias between the newly added layer and the adjacent layers, which can reduce the risk of EMIR; for the signal net, copy the newly added layer at the overlapping areas where the original upper and lower layers are connected, and then copy the original vialayer at this position as the vias for the upper and lower layers of the newly added via layer, which will not increase the parasitic RC of the signal; If the thickness and DRC of the newly added layer are different from those of the adjacent layers in the original PDK, the addition method is the same as described above, but at the same time, it is necessary to check the minwidth, maxwidth, space of the newly added layer and the adjacent layers, and the situation of the newly added vias; Usually, select the adjacent upper metal layer and screen at the places where the maxwidth is greater than the maxwidth of the newly added layer to make it the maxwidth of the newly added layer. The Minspace usually meets the requirements of the newly added layer. Finally, the vias are filled according to the rule.

[0100] Preferably, in S200, set the layout parameters according to the process switching requirements, including:

[0101] For replacing the PDK metal, judge the differences between the metal layer after replacement and the existing metal layer;

[0102] Directly replace the metal layer;

[0103] When processing the vias, delete the original vias, and then punch holes for the newly added metal layer at the same position. The number of holes punched is calculated according to the number of existing holes, and the holes required by the PDK are regenerated according to the parameter information of the original holes.

[0104] Judge the differences between the layer after replacement and the existing layer. This situation is generally an operation between different metal thicknesses. The layer can be directly replaced, but the space and viawidth of the vias will be different. When processing the vias, first delete the original vias, and then punch holes for the newly added layer at the same position. The number of these holes can be calculated according to the number of existing holes, and the holes required by the PDK are regenerated according to the parameter information of the original holes.

[0105] Preferably, in S200, setting the layout parameters according to the process switching requirements includes:

[0106] For adding a new PDK metal layer and replacing the PDK metal, first replace the PDK metal and then add the new PDK metal layer.

[0107] First replace the PDK metal and then add the new PDK metal layer, so that the net connection situation will exist. Otherwise, it is easy to cause problems in LVS after PDK switching.

[0108] Preferably, in S300, running the verification process to verify the layout feasibility includes:

[0109] Running DRC checks to verify whether the layout design rules are correct;

[0110] Running DRC, DRC has the recognition ability and can perform complex recognition work, and checks before generating the finally submitted graphics. When the program checks the file according to the rules and finds an error, it will mark and explain at the error location. Check for short circuits, open circuits, and floating nodes. After ERC detects a short circuit error, it will limit the error prompt to the shortest connection path.

[0111] Running LVS verification to verify whether the layout is consistent with the circuit.

[0112] LVE compares the layout and the circuit schematic diagram, reports the inconsistencies between the layout connections and the schematic diagram, and makes modifications until the layout and the circuit diagram are completely consistent.

[0113] If the layout fails the detection, the layout needs to be modified. It is necessary to judge whether the label is correct, whether the selected layer is correct, whether there are problems with the connection of power and ground, whether the obtained files are reliable, check whether the naming of the device types in the netlist conforms to the specifications, check the design rule. According to the inspection report, see if there are many foogirct nodes. If there are many, there is a broken circuit. If there are few, there is a short circuit. Compare with the schematic diagram to see if there are any incorrect connections.

[0114] The schematic diagram of the result of processing the new metal layer by the method of the present invention: Add vialayer111 and metal layer145. From the newgds, the signals and Power / Ground are also processed separately. And the verification results of DRC and LVS using the newgds: Both LVS and DRC can pass at one time, reducing the workload.

[0115] Schematic diagram of the result of metal layer replacement processed by the method of the present invention: The target process is to convert from TMa process to TMb process, and the thickness of the process metal layer changes from 10K to 14K, which means that both the width and space of the VIA will change. This step is carried out using skill. The library to be replaced is input into the specified variable, the ratio of the VIA is calculated, and the VIA is redrilled according to the new PDK to complete the replacement of the VIA. The size and space of the VIA before and after replacement are different. Under the condition of equal overlap, the VIA is replaced again according to the new size, and it can ensure that the LVS can pass at one time without the occurrence of short and OPEN situations.

[0116] Example 2

[0117] A layout system for quickly processing newly added metal layers and replacing metal layers, referring to Figure 2 , including:

[0118] A data acquisition module for acquiring process switching requirements;

[0119] A data processing module for setting layout parameters according to process switching requirements;

[0120] A verification module for running a verification process to verify the feasibility of the layout.

[0121] Example 3

[0122] An electronic device, including: a chip, a processor, and a memory. The memory is used to store computer program code, and the computer program code includes computer instructions. When the chip executes the computer instructions, the electronic device executes a layout design method for processing newly added metal layers and replacing metal layers.

[0123] Referring to Figure 3 , the electronic device 2 includes a processor 21, a memory 22, an input device 23, and an output device 24. The processor 21, the memory 22, the input device 23, and the output device 24 are coupled through a connector, and the connector includes various interfaces, transmission lines, or buses, etc. The embodiments of the present invention do not limit this. It should be understood that in various embodiments of the present invention, coupling means mutual connection through a specific manner, including direct connection or indirect connection through other devices. For example, it can be connected through various interfaces, transmission lines, buses, etc.

[0124] The processor 21 may be one or more graphics processing units (GPUs). When the processor 21 is a GPU, the GPU may be a single-core GPU or a multi-core GPU. Optionally, the processor 21 may be a processor group composed of multiple GPUs, and multiple processors are coupled to each other through one or more buses. Optionally, the processor may also be other types of processors, etc., which are not limited in the embodiments of the present invention.

[0125] The memory 22 can be used to store computer program instructions and various computer program codes including the program codes for executing the solution of the present invention. Optionally, the memory includes but is not limited to random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), or portable read-only memory (ROM), and this memory is used for relevant instructions and data.

[0126] The input device 23 is used to input data and / or signals, and the output device 24 is used to output data and / or signals. The output device 24 and the input device 23 may be independent devices or an integrated device.

[0127] The present invention verifies a series of processes through SKILL, svrf, gdsmerge, and PV, quickly traverses the layout in the specified library, and finally performs PV verification of the new process on the switched layout, mainly including DRC and LVS verification. In high-speed IP modules, it is also necessary to distinguish signals clk, datanet from Power / Ground. How to handle these signal nets during the process switch is crucial for the performance of the IP. To ensure that clk and datanet are not affected by the switched process, in the present invention, non-power / ground metal traces are classified into one category, and power and ground are classified into another category. In this way, different logics are used for processing when performing metal layer superposition, replacement, and reduction, quickly completing the process switch and ensuring that the performance of high-speed IP is not affected. It can minimize the later manual modification man-hours.

[0128] The above are only specific embodiments of the present invention, enabling those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A layout design method for processing new metal layers and replacement metal layers, characterized in that: include: Obtain process switching requirements; Setting layout parameters according to the process switching requirements; The setting of layout parameters according to the process switching requirements includes: For the newly added PDK metal layer, determine the power network, ground network, and signal network of the chip layout; Determine the DRC status of the newly added metal layer and the DRC status of the newly added vias; The determination of the DRC condition of the newly added metal layer and the DRC condition of the newly added via hole includes: If the thickness and DRC of the newly added metal layer are the same as those of the adjacent metal layer in the original PDK, replace the original vias with the via defines of the new PDK; Directly use the current layer as the reference and copy it in the form of power / ground network and signal network; Directly copy the metal layer of the current layer in the power network and ground network, and then fill the vias of the newly added metal layer and the adjacent metal layer; The signal network duplicates the overlapped parts of the original upper and lower layers to create a new metal layer, and then duplicates the original via metal layer as the upper and lower holes of the newly added via layer; If the thickness and DRC of the newly added metal layer are different from those of the adjacent metal layer in the original PDK, replace the original vias with the via defines of the new PDK, and determine the minimum width, maximum width, space, and newly added vias between the newly added metal layer and the adjacent metal layer; Select the adjacent upper metal layer where the maximum width is greater than the maximum width of the newly added metal layer, and filter it to become the maximum width of the newly added metal layer; The minimum space meets the requirements of the new metal layer, and the vias are filled according to the rules; Run the verification process to verify the feasibility of the layout.

2. A layout design method for processing new metal layers and replacement metal layers according to claim 1, characterized in that: The process switching requirements include: Added PDK metal layer; Replace PDK metal; It is necessary to add a new PDK metal layer and also replace the PDK metal.

3. A layout design method for processing new metal layers and replacement metal layers according to claim 1, characterized in that: The power network, ground network, and signal network of the chip layout judgment include: Mark various networks and perform additional processing on the layout when encountering the power supply network after LDO; If there is no VDD on the power network or the ground network, the VSS label defaults to the signal network.

4. A layout design method for processing new metal layers and replacement metal layers according to claim 1, characterized in that: The setting of layout parameters according to the process switching requirements includes: For replacing PDK metal, determine the difference between the metal layer to be replaced and the existing metal layer; Directly replace the metal layer; When processing vias, the original vias are deleted, and then a new metal layer is punched at the same location. The punching is calculated based on the number of existing holes, and the holes required by the PDK are regenerated based on the parameter information of the original holes.

5. A layout design method for processing new metal layers and replacement metal layers according to claim 1, characterized in that: The setting of layout parameters according to the process switching requirements includes: If both a new PDK metal layer and a PDK metal layer need to be replaced, the PDK metal layer should be replaced first, and then the PDK metal layer should be added.

6. A layout design method for processing new metal layers and replacement metal layers according to claim 1, characterized in that: The operation verification process for verifying the feasibility of the layout includes: Run DRC check to verify whether the layout design rules are correct; Run LVS verification to verify whether the layout is consistent with the circuit.

7. A layout design system for processing new metal layers and replacement metal layers, used to implement the layout design method for processing new metal layers and replacement metal layers as described in any one of claims 1 to 6, characterized in that: include: Data acquisition module, used to obtain process switching requirements; A data processing module, used for setting layout parameters according to the process switching requirements; The verification module is used to run the verification process to verify the feasibility of the layout.

8. An electronic device, characterized in that: include: A chip, a processor and a memory, wherein the memory is used to store computer program codes, wherein the computer program codes include computer instructions. When the chip executes the computer instructions, the electronic device executes a layout design method for processing new metal layers and replacement metal layers as described in any one of claims 1 to 6.

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