Method for designing substrate layout of core particle system

Abstract

The invention provides a method for designing a substrate layout of a core particle system. Comprising the following steps: obtaining the size of each core particle to be arranged, the size of a layout area of a substrate, an interface set formed by each pin on each core particle and each port on the substrate, a connection relation of each interface in the interface set and the position of each pin on the core particle; the layout module is used for initializing a substrate layout and carrying out layout adjustment by taking the bus length of minimized wiring as an optimization target to obtain a first layout result; performing global layout optimization on the first layout result by taking the weighted sum of the minimization of the layout density and the bus length of wiring between the interfaces as an optimization target to obtain a second layout result; and adjusting the second layout result to make the layout accord with layout rationality constraints among the core particles to obtain a third layout result, each of the first to third layout results including the layout position of each core particle and the layout position of each port in the layout area of the substrate.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, in particular to the field of integrated circuit design, and more particularly to a method for designing a substrate layout of a core particle system. Background Art

[0002] With the continuous advancement of integrated circuit technology, chiplet technology has emerged as an innovative integration solution to further enhance the computing power of chips. Chiplet technology optimizes system performance and functional integration by breaking down the complete chip system into smaller, independently designed chiplets. However, as the number of chiplets in the system increases, it also brings problems of increased design complexity and increased lithography costs.

[0003] Current layout algorithms face low efficiency and solution difficulties when dealing with large-scale chiplet system designs. They are unable to adapt to the needs of modern business environments for fast iterative design cycles, and are also unable to meet the requirements of actual production and manufacturing.

[0004] Existing electronic design automation (EDA) tools are insufficient in automation, which limits the improvement of design efficiency and quality, and makes it difficult to effectively cope with the challenges of large-scale chip integration.

[0005] It should be noted that this background technology is only used to introduce the relevant information of the present invention to help understand the technical solution of the present invention, but it does not mean that the relevant information is necessarily the prior art. The relevant information is submitted and disclosed together with the present invention solution. If there is no evidence that the relevant information has been disclosed before the application date of the present invention, the relevant information shall not be regarded as the prior art. Summary of the invention

[0006] Therefore, an object of the present invention is to overcome the above-mentioned defects of the prior art and provide a method for designing a substrate layout of a core particle system.

[0007] The objective of the present invention is achieved through the following technical solutions:

[0008] According to a first aspect of the present invention, there is provided a method for designing a substrate layout of a chiplet system, comprising: obtaining the size of each chiplet to be laid out, the size of a layoutable area of ​​the substrate, a set of interfaces consisting of each pin on each chiplet and each port on the substrate, the connection relationship between each interface in the interface set, and the position of each pin on the chiplet, for initializing the substrate layout and adjusting the layout with minimizing the total length of the wiring as the optimization goal to obtain a first layout result; performing global layout optimization on the first layout result with minimizing the weighted sum of the layout density and the total length of the wiring between interfaces as the optimization goal to obtain a second layout result; adjusting the second layout result so that the layout meets the layout rationality constraints between the chiplets to obtain a third layout result, wherein each of the first to third layout results includes: the layout positions of each chiplet and the layout positions of each port arranged in the layoutable area of ​​the substrate. This solution can at least achieve the following beneficial technical effects: in the initial layout stage, this solution only makes adjustments to minimize the wiring length after initializing the layout, which can avoid adding too many constraints to affect the solution in the initial stage; in the global layout stage, the layout is optimized by combining the layout density and the wiring length to simultaneously optimize the wiring length and the distribution density, so as to effectively eliminate the problem of excessive line length caused by local excessive density; subsequently, the second layout result is adjusted through the layout rationality constraint to achieve a stable layout result that meets the physical constraints.

[0009] Optionally, the method further includes: obtaining the layout constraints of the bumps on the substrate and the layout positions of each port extracted from the third layout result, matching each port with the bump one by one, and updating the layout positions of each port in the third layout result based on the bump position matched by each port, to obtain a fourth layout result. This solution can at least achieve the following beneficial technical effects: since the bumps used to connect to the outside world need to be arranged according to certain rules when manufacturing the core particles, it is necessary to make the port layout meet the layout constraints of the bumps, thereby enhancing the system integration and manufacturability of the entire layout solution.

[0010] Optionally, the first layout result is obtained in the following manner: according to the size of each core particle to be laid out, the size of the substrate layout area and the interface set, the position of each core particle and each port is initially placed in the center of the substrate layout area to obtain the initial layout result; without considering the layout constraints, the estimated total length of all wire nets required based on the preset boundary-boundary model is minimized as the optimization goal, and the layout position of the core particles and ports is adjusted iteratively multiple times based on the initial layout result to obtain the first layout result, wherein each wire net refers to a connection line of a group of interfaces that need to be connected in the interface set, and the length of the wire net is calculated according to the position of each core particle, the position of each pin on the core particle, the layout position of the port and the connection relationship of each interface. This scheme can at least achieve the following beneficial technical effects: in the initial stage of layout, the present invention uses the boundary-boundary model to more accurately estimate the actual wire length after wiring is completed by carefully analyzing the position of the interface in the wire net in the layout space.

[0011] Optionally, the second layout result is obtained in the following manner: obtain a pre-constructed weighted average line length model and a layout density model based on an electrostatic field, wherein the weighted average line length model is used to calculate the total line length according to the layout position of the interface and the preset control precision coefficient, and the layout density model calculates the system potential energy according to the layout position of the interface. In the layout density model, the substrate layout area is regarded as a static electric field, and the core particles and ports as movable elements are regarded as charged bodies with positive charges; with the weighted sum of minimizing the total line length and the system potential energy as the optimization goal, the layout positions of the core particles and ports are adjusted for multiple layout iterations based on the first layout result to obtain the second layout result. This solution can at least achieve the following beneficial technical effects: by introducing a weighted average line length model to smooth the semi-perimeter in the layout; at the same time, drawing on the electrostatic field theory, the layout density problem is mapped into a potential distribution, and a dynamic layout density model is constructed. The density optimization layout calculated by the layout density model achieves density balance, so as to effectively eliminate the problem of excessive line length caused by local excessive density. On this basis, the dual goals of layout density and line length optimization are combined to form a comprehensive layout optimization objective function to better optimize the global layout results.

[0012] Optionally, the second layout result is obtained in the following manner: a pre-constructed weighted average line length model, a density model based on an electrostatic field, and a pin density model of the core particle are obtained, wherein the weighted average line length model is used to calculate the total line length according to the layout position of the interface and a preset control accuracy coefficient, and the layout density model calculates the system potential energy according to the layout position of the interface, and in the layout density model, the substrate layout area is regarded as a static electric field, and the core particles and ports as movable elements are regarded as charged bodies with positive charges; with minimizing the weighted sum of the total line length, system potential energy and pin density as the optimization goal, the layout positions of the core particles and ports are adjusted for multiple layout iterations based on the first layout result to obtain the second layout result. This solution can at least achieve the following beneficial technical effects: by introducing a weighted average line length model, the semi-perimeter in the layout is smoothed to effectively eliminate the problem of excessive line length caused by local excessive density; at the same time, drawing on electrostatic field theory, the layout density problem is mapped into electric potential distribution, and a dynamic layout density model is constructed; in addition, the pins in the core particles are modeled separately as charged bodies. On this basis, a comprehensive layout optimization objective function is formed by combining the multiple objectives of system potential energy, pin density and line length optimization; the uniformity of the overall distribution, the uniformity of the density distribution of the pins in the core particles and the overall wiring length can be better controlled to better improve the overall layout performance indicators.

[0013] Optionally, the third layout result is obtained in the following manner: obtain the layout rationality constraint between the core particles, which includes that any two core particles must maintain a preset spacing between each other, and the value of the spacing is greater than 0; according to the second layout result and the layout rationality constraint, use the simulated annealing algorithm to iteratively adjust the layout position of the core particles to meet the layout rationality constraint, and obtain the third layout result. This solution can at least achieve the following beneficial technical effects: use the simulated annealing algorithm to check and correct the rationality of the layout; the algorithm simulates the physical annealing process, and by controlling the "temperature" parameter of the algorithm, the layout can be widely tried under the "high temperature" state to jump out of the local optimal solution; as the temperature gradually decreases, the layout gradually stabilizes, and finally converges to a reasonable layout result that meets all design rules and has no overlap; this process ensures the feasibility of the layout and effectively reduces the unreasonable design.

[0014] Optionally, the fourth layout result is obtained in the following manner: obtaining the layout constraints of the bumps on the substrate and the layout positions of each port extracted from the third layout result; determining the positions of each bump on the layoutable area of ​​the substrate according to the layout constraints of the bumps, matching each port with the bump one by one based on the principle of proximity, and obtaining a bump-port matching table; for each port, according to the bump-port matching table, using the bump position matched by the port to update the layout position of the port in the third layout result, and obtaining a fourth layout result. This solution can at least achieve the following beneficial technical effects: In order to further improve the efficiency and quality of matching, the algorithm considers the distance factor between the port and the preset bump during the matching process, and preferentially matches the point pairs with a closer distance, thereby reducing the complexity of wiring while meeting the design rules, and improving the compactness and economy of the overall layout.

[0015] According to a second aspect of the present invention, there is provided a computer program product, comprising a computer program / instruction, which implements the steps of the method described in the first aspect when executed by a processor.

[0016] According to a third aspect of the present invention, there is provided an electronic device comprising: one or more processors; and a memory, wherein the memory is used to store executable instructions; the one or more processors are configured to implement the steps of the method described in the first aspect by executing the executable instructions.

[0017] Compared with the prior art, the advantages of the present invention are:

[0018] The method of the present invention only adjusts the wiring length to minimize the wiring length after initializing the layout in the initial layout stage, which can avoid adding too many constraints to affect the solution in the initial stage; in the stage of global layout, the layout is optimized by combining the layout density and the wiring length to optimize the wiring length and the distribution density at the same time, so as to effectively eliminate the problem of excessive line length caused by local excessive density; then, the second layout result is adjusted by the layout rationality constraint to achieve a stable layout result that meets the physical constraints. In addition, the method of the present invention can more effectively improve the design efficiency by gradually increasing the optimization goals and / or constraint schemes to be considered, avoid the problem of difficult solutions caused by premature consideration of global constraints, and can efficiently handle large-scale chip integration, automatically design the substrate layout of the chip system, and obtain layout results. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The embodiments of the present invention are further described below with reference to the accompanying drawings, in which:

[0020] Figure 1 is a schematic diagram of a substrate layout according to an embodiment of the present invention;

[0021] Figure 2A schematic flow chart of a method for designing a substrate layout of a core particle system according to an embodiment of the present invention;

[0022] Figure 3 is a schematic diagram of an internal interface defined in a boundary-boundary model according to an embodiment of the present invention;

[0023] Figure 4 is a schematic diagram of a flow chart for determining a first layout result according to an embodiment of the present invention;

[0024] Figure 5 A schematic diagram showing the principle of mapping layout elements to an electrostatic field system according to an embodiment of the present invention;

[0025] Figure 6 A schematic diagram of optimizing layout results using a simulated annealing algorithm according to an embodiment of the present invention;

[0026] Figure 7 A schematic diagram of a process of pairing ports and bumps using a stable marriage algorithm according to an embodiment of the present invention;

[0027] Figure 8 is a schematic diagram of a layout result according to an embodiment of the present invention. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below through specific embodiments in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0029] As mentioned in the background technology section, the existing electronic design automation tools are insufficient in automation, which limits the improvement of design efficiency and quality, and it is difficult to efficiently cope with the challenges of large-scale chiplet integration. Therefore, innovative automation methods are urgently needed to improve design efficiency and reduce costs. In this regard, the method of the present invention only adjusts the wiring length to minimize the wiring length after initializing the layout in the initial layout stage, which can avoid adding too many constraints to affect the solution in the initial stage; in the stage of global layout, the layout is optimized by combining the layout density and the wiring length to optimize the wiring length and the distribution density at the same time, so as to effectively eliminate the problem of excessive line length caused by local excessive density; then, the second layout result is adjusted by the layout rationality constraint to achieve a stable layout result that meets the physical constraints. In addition, the method of the present invention can more efficiently improve the design efficiency by gradually increasing the optimization goals and / or constraint schemes to be considered, avoid the problem of difficult solutions caused by premature consideration of global constraints, and can efficiently handle large-scale chiplet integration, automatically design the substrate layout of the chiplet system, and obtain the layout result.

[0030] Before describing the embodiments of the present invention in detail, Figure 1 , first explain some of the terms used in it as follows:

[0031] A chiplet (also called a small chip) refers to a chip (Die) that has specified computing functions and can be combined and integrated.

[0032] A core particle system is a system that is integrated by multiple core particles. Figure 1 The core particle system shown in FIG. 1 has three core particles integrated on a substrate, namely core particle 1, core particle 2, and core particle 3.

[0033] The pins of a chip refer to the interface of the chip for external connection. Figure 1 The 9 pins of the chiplet 1 are shown, and the pins of other chiplets are not shown.

[0034] Ports refer to points on the substrate for setting bumps and connecting the pins of the core particles. At the same time, the connection between the pins and / or ports of the core particles can also be achieved through the wiring between the ports on the substrate. Ports can also be regarded as virtual points corresponding to bumps without considering the layout constraints of the bumps.

[0035] Interface, the method of the present invention refers to the pins of ports and core particles as interfaces.

[0036] A wire network refers to a network consisting of two or more interfaces that need to be directly or indirectly connected. For example, according to the connection relationship of each interface in the interface set, assuming that interface 1 and interface 2 need to be connected (directly connected), and interface 2 and interface 3 need to be connected (directly connected), then interfaces 1-3 belong to the same wire network, and interface 1 and interface 3 are indirectly connected. If there are two other interfaces 4 and 5 that are connected to each other (and not connected to interfaces 1-3), interfaces 4 and 5 belong to another wire network.

[0037] Bumps refer to the connection points between the substrate and the package. Figure 1 The final layout result is shown in FIG. 1 . At this time, the positions of the ports and the bumps coincide with each other, as can be seen at the ports / bumps shown in the figure.

[0038] According to one embodiment of the present invention, see Figure 2 , a method for designing a substrate layout of a core particle system is provided, comprising steps S1, S2 and S3, or S1, S2, S3 and S4. In some cases, the method of the present invention may not contain S4, that is, the third layout result may be used as the final result output by the method of the present invention. The matching of ports and bumps is performed manually or by other algorithms. In order to better understand the present invention, each step is described in detail below in conjunction with specific embodiments.

[0039] Step S1: Obtain the size of each chip to be laid out, the size of the layout area of ​​the substrate, the pins on each chip and the interface set composed of the ports on the substrate, the connection relationship between the interfaces in the interface set, and the position of each pin on the chip, so as to initialize the substrate layout and adjust the layout with the minimization of the total wiring length as the optimization goal, and obtain the first layout result.

[0040] According to one embodiment of the present invention, the first layout result is obtained in the following manner: according to the size of each core particle to be laid out, the size of the substrate layout area and the interface set, the position of each core particle and each port is initially placed at the center of the substrate layout area to obtain the initial layout result; without considering the layout constraints, the estimated total length of all wire nets required by the preset boundary-boundary model is minimized as the optimization goal, and the layout position of the core particles and ports is adjusted iteratively multiple times based on the initial layout result to obtain the first layout result, wherein each wire net refers to a connection line of a group of interfaces that need to be connected in the interface set, and the length of the wire net is calculated according to the position of each core particle, the position of each pin on the core particle, the layout position of the port and the connection relationship of each interface. The current core particle and the substrate layout area are usually rectangular, so the size of the core particle and the size of the substrate can be represented by length and width. Of course, if the implementer needs to design a special-shaped core particle and substrate layout area, the corresponding size can also be set according to the definition of the implementer.

[0041] Step S1 is the layout initialization stage (or the starting stage of layout). The method of the present invention uses the boundary-boundary model to more accurately estimate the actual wire length after wiring is completed by carefully analyzing the position of the interface on the wire network in the layout space. In order to optimize this estimation process, the original half-perimeter wirelength estimation (HPWL) problem is converted into a smoother and easier to optimize quadratic form. By splitting the multi-pin wire network into multiple dual-pin connections, the conjugate gradient method is used for efficient solution. This step can obtain preliminary layout results, laying the foundation for subsequent optimization.

[0042] According to an optional embodiment of the present invention, an improved boundary-boundary model is defined as:

[0043]

[0044] Where L represents the total length of the line, E = {e1, e2, ..., e m} represents a network set, e1, e2, ..., e m represents the 1st, 2nd, ..., mth network, V = {v1, v2, ..., v n} is an interface collection, v1, v2, ..., v nRespectively represent the 1st, 2nd, ... nth interfaces, x i ,y i They respectively represent the x- and y-coordinates (i.e., positions) of the ith interface in the network e.

[0045] Since the position of the boundary point has a greater impact on the total line length estimation when estimating the line length, in order to improve the accuracy of line length estimation, the above boundary-boundary model can be further improved. According to another optional embodiment of the present invention, the boundary-boundary model is a quadratic line length model, and the formula of the quadratic line length model is as follows:

[0046]

[0047] Where L represents the total length of the line, E = {e1, e2, ..., e m} represents a network set, e1, e2, ..., e m represents the 1st, 2nd, ..., mth network, V = {v1, v2, ..., v n} is an interface collection, v1, v2, ..., v n Respectively represent the 1st, 2nd, ... nth interfaces, x i ,y i represent the x- and y-direction coordinates (i.e., position) of the ith interface in the network e, respectively, and w x,ij 、w y,ij are the weights in the x and y directions respectively.

[0048] For the improved boundary-boundary model, where w x,ij for:

[0049]

[0050] Where a is a preset minimum value (such as 0.001 or 0.000001) or 0, P represents the total number of interfaces on the current line, and x i represents the x-coordinate of the ith interface in the network e, x j Indicates the x-coordinate of the j-th interface in the network e. An internal interface means that the x-coordinate values ​​of the i-th and j-th interfaces are between the minimum and maximum x-coordinate values ​​of all interfaces in the network to which they belong. y,ij Same as the above formula, but w y,ij The internal interface means that the coordinate values ​​of the y direction of the i-th interface and the j-th interface are between the minimum coordinate value and the maximum coordinate value of the y direction of all interfaces in the current network.

[0051] Indicatively, see Figure 3 , condition v i ,v j∈ internal interface means that for a line network, in the x direction, the minimum value (the schematic value is 0) and the maximum value (the schematic value is ω n ) is the boundary interface, and the other interfaces are internal interfaces.

[0052] Based on the established boundary-boundary model, the conjugate gradient method can be used to optimize the solution to adjust the positions of the core particles and ports to minimize the total length. Figure 4 , provides a schematic diagram of obtaining the layout initialization result, including the steps:

[0053] Initialize the position of the core particle and the port to the center of the layout area of ​​the substrate;

[0054] Construct a connection graph G using a boundary-boundary model based on the netlist information;

[0055] Based on the boundary-boundary model, the conjugate gradient method is used to optimize and solve the HPWL.

[0056] according to Determine whether it converges If yes, the first layout result is obtained; if no, the previous step is repeated to continue to use the conjugate gradient method to optimize and solve the HPWL.

[0057] Among them, the positions of the initialization core particles and ports are the center of the layout area of ​​the substrate, that is, all core particles and ports are set at the center of the layout, giving the initial solution; this information is used as input to establish a secondary line length model and establish the optimization goal. △HPWL is the change value of the semi-perimeter line length, that is, the difference between the HPWL calculated this time and the HPWL calculated last time. When the change value is less than the set threshold e, it means that the algorithm has completed convergence. The conjugate gradient method is used to solve the above quadratic optimization problem. This algorithm is selected for its fast convergence characteristics. It iteratively updates the layout position and gradually approaches the optimal solution for minimizing the line length. The introduction of the conjugate gradient method significantly reduces the number of iterations required for the solution, thereby accelerating the process of layout initialization and laying an efficient and practical starting point for global layout optimization.

[0058] During the initialization of the layout, the x component of the layout optimization target can be mapped in matrix form. After mapping, the sum of the estimated line lengths in the x direction can be expressed as:

[0059]

[0060] in, represents the sum of the estimated line lengths in the x direction, represents the vector of the x-coordinate of the core particle position, T represents the transpose, and the Hessian matrix Q xDescribes the connection matrix between interfaces, and const represents a preset constant. x When it is a non-degenerate (full rank) matrix, the function becomes a strictly convex function with a single minimum. This minimum can be obtained by solving the linear system Using iterative Krylov subspace methods, such as the Conjugate Gradient (CG) method and its variants, this solution can be quickly approximated. x is a symmetric positive definite matrix, and the conjugate gradient method ensures the minimization of the residual norm during the iteration process. Although this method helps to speed up the convergence speed. x It shows the diagonal dominance property. Selecting its diagonal as P, that is, using the Jacobi preconditioner, can further improve the solution efficiency. Similarly, the sum of the estimated line lengths in the y direction can be obtained The total length is

[0061] Step S2: taking minimizing the weighted sum of the layout density and the bus length of the wiring between interfaces as the optimization goal, performing global layout optimization on the first layout result to obtain a second layout result.

[0062] According to an optional embodiment of the present invention, the second layout result is obtained in the following manner: a pre-constructed weighted average line length model and a layout density model based on an electrostatic field are obtained, wherein the weighted average line length model is used to calculate the total line length according to the layout position of the interface and the preset control accuracy coefficient, and the layout density model calculates the system potential energy according to the layout position of the interface, wherein the layout density model regards the substrate layout area as a static electric field, and regards the core particles and ports as movable elements as charged bodies with positive charges; with the weighted sum of minimizing the total line length and the system potential energy as the optimization goal, the layout positions of the core particles and ports are adjusted for multiple layout iterations based on the first layout result to obtain the second layout result. In the global layout optimization stage, the method of the present invention introduces a weighted average line length model to smooth the semi-perimeter in the layout, so as to effectively eliminate the problem of excessive line length caused by local over-density. At the same time, drawing on the electrostatic field theory, the layout density problem is mapped into a potential distribution, and a dynamic layout density model is constructed. On this basis, a comprehensive layout optimization objective function is formed by combining the dual goals of system potential energy and total line length optimization. The weighted average line length model and layout density model are introduced below.

[0063] (1) Weighted average line length model

[0064] Based on the preliminary layout, the method of the present invention introduces a weighted average line length model to assign different weights to the line lengths of different areas, effectively solving the problem of overly dense or sparse local wiring and ensuring the global balance of the layout.

[0065] The global layout is usually regarded as a constrained optimization problem. The layout area is uniformly decomposed into a set of m×n rectangular grids (bins), denoted as B. Based on the layout result v, let ρ b (v) represents the density of each grid b∈B.

[0066]

[0067] Among them, l x (b,i) represents the horizontal (x-direction) overlap between grid b and cell i (core particles and ports are abstracted as cells), l y (b,i) represent the vertical (y-direction) overlap between grid b and cell i. x (b,i) and l y (b,i) both present a rectangular shape that is not differentiable at the boundary points. The goal of the global layout problem is to find a solution v that minimizes the total HPWL while satisfying the density constraints of all grids, as shown in the following formula:

[0068]

[0069] Among them, ρ t Indicates the density threshold.

[0070] Since the HPWL line length is not differentiable, the weighted average line length model is used to approximate the HPWL in the global layout stage. For each line net, the weighted average line length model calculates the line length in the x direction in the horizontal x direction as follows:

[0071]

[0072] Among them, v is the layout result, W e (v) represents the length of the line net e in the layout result v, e represents the line net e, i represents the number of the i-th interface in the line net, and x i Indicates the x-axis coordinate of the ith interface in the wire network, and γ is a coefficient used to control accuracy. The formula for calculating the sum of the line lengths in the vertical y direction is similar. Just replace x with y in the above formula. I will not go into details here. The total line length is calculated using the above W e (v) The formula is obtained by calculating the line length in the x direction and the line length in the y direction of each line grid and then summing them up.

[0073] (2) Layout density model based on electrostatic field

[0074] In the context of global layout optimization, the method of the present invention analogizes the layout density problem on the substrate to the charge distribution problem in an electrostatic field. Schematically speaking, the core particles and ports are regarded as particles with positive charges, and the potential in the layoutable area (layout space) reflects the layout density of these particles. Through this analogy, the electrostatic field theory in physics can be used to analyze and optimize the layout structure, thereby achieving effective control and optimization of the layout density.

[0075] See also Figure 5 , the layout space of the substrate design is analogous to a static electric field, and the movable elements in the substrate, that is, each core particle and each port, are regarded as particles with positive charges. The charge amount of the movable element corresponds to its area, the density of the movable element is regarded as the charge density, the density penalty is the electric potential energy, and the density gradient is the electric field strength. Therefore, the substrate layout process can be regarded as the process of achieving balance among the elements under the action of electrostatic force.

[0076] The force on each movable element i is given by the Lorentz force equation i i =q i ξ i Description, where ξ i represents the local electric field strength at the location of the movable element i. The potential energy of the movable element i is given by the formula N i =q I ψ I The calculated value is denoted as N i ,ψ i is the electric potential. According to Coulomb's law, the electric field and electric potential at a certain position are actually the result of the superposition of all other movable elements i in the system. According to Gauss's law, the relationship between the electric field strength ξ and the electric potential ψ is given by the formula The relationship between charge density ρ and electric field strength ξ is given by the formula describe.

[0077] Therefore, the present invention can calculate the electric field strength ξ by the gradient of the electric potential ψ i :

[0078]

[0079] Among them, ξ x represents the electric field strength in the x direction, ξ y represents the electric field intensity in the y direction, represents the gradient, represents partial derivative.

[0080] Furthermore, the charge density ρ can be calculated from the gradient of the electric field strength ξ:

[0081]

[0082] After analogy with layout components, the original optimization problem can be transformed into the following formula:

[0083]

[0084] Among them, N(v) is the system potential energy of the electrostatic field system, which appears as a density penalty function. By using the penalty factor λ, the global layout problem can be transformed into an unconstrained optimization problem, as shown in the following formula:

[0085]

[0086] Where f is the optimization objective function, W(v) total is the total line length determined by the weighted average line length model, N(v) is the system potential energy, and γ and λ are penalty factors. Since both W(v) and N(v) in the optimization term are differentiable, the gradient-based optimization technique can be used for optimization. It indicates that the optimization goal is to minimize the value of f by adjusting the layout.

[0087] In order to solve the potential problem, that is, to find a reasonable layout density distribution, schematically, the charge density and potential of the electrostatic field system and the Neumann boundary condition can be used to establish the Poisson equation, the spectral method is used to solve the Poisson equation, and the discrete cosine transform (DCT) is used for fast calculation. For example, the Poisson square is used to describe the relationship between the potential ψ(x, y) and the charge density ρ(x, y), and the Neumann boundary condition is used to ensure the legitimacy of the layout at the boundary. By solving the Poisson equation, the potential value at each grid point can be obtained, and then the optimal layout position of the component can be inferred to achieve the purpose of global layout optimization. The spectral method is used to solve the Poisson equation, by expressing the density function and the potential function in the frequency domain, and using the discrete cosine transform (DCT) for fast calculation, which improves the solution efficiency and accuracy. Among them, the input of the Poisson equation is: the charge distribution of the electrostatic field system, that is, the charge amount and position of each unit in the established static point field model, and the boundary conditions of the Poisson equation, and the output is: the potential value at each grid point. Schematically, the established Poisson equation is as follows:

[0088]

[0089] Where ψ(x,y) is the electric potential, ρ(x,y) is the charge density, represents the external normal vector of the layout area R, Represents the boundary of the layout area. The second term in the above formula is the Neumann boundary condition, which enforces the legality of the global layout solution. By defining the Neumann boundary condition, when the movable element approaches the boundary of the layout area, its movement speed will slow down or even stop, thereby preventing the movable element from moving outside the layout area; the third term sets the integral of ρ(x, y) and potential function ψ(x, y) over the entire layout area R to zero. In the global layout optimization stage, reasonable control of layout density is crucial to overall layout quality and cost control. In order to achieve this goal, the present invention combines the layout density model based on the electrostatic field with the weighted average line length model to form a unified optimization framework, in order to achieve the dual optimization goals of minimizing line length and balancing density.

[0090] Since the density distribution of pins in the core particle has a greater impact on the overall wiring, further improvements can be considered for the above scheme for calculating the second layout result. According to another optional embodiment of the present invention, the second layout result is obtained in the following manner: a pre-constructed weighted average line length model, a density model based on an electrostatic field, and a pin density model of the core particle are obtained, wherein the weighted average line length model is used to calculate the total line length according to the layout position of the interface and a preset control accuracy coefficient, and the layout density model calculates the system potential energy according to the layout position of the interface. In the layout density model, the substrate layout area is regarded as a static electric field, and the core particles and ports as movable elements are regarded as charged bodies with positive charges; the pin density model is used to calculate the pin density when the pins of the core particles are regarded as charged bodies separately; with the weighted sum of minimizing the total line length, system potential energy, and pin density as the optimization goal, the layout positions of the core particles and ports are adjusted for multiple layout iterations based on the first layout result to obtain the second layout result.

[0091] The pins in the core particles are modeled as charged bodies, and the pin density item is added as one of the optimization targets in the layout optimization target. This can better control the density distribution of the pins in the core particles, making better use of the wiring in the wiring stage. The optimization target after adding the density constraint is as follows:

[0092]

[0093] Among them, ρ(v) represents the pin density term after the pin is modeled as a charged body, and μ is the penalty factor of the pin density term. Incorporating pin density information into the optimization objective function allows layout optimization to not only consider line length, but also layout density distribution, which is crucial for high-density integrated chip systems. In this way, excessive crowding in local areas can be effectively avoided, pin distribution can be optimized, and the overall manufacturing cost can be reduced and system performance can be improved.

[0094] According to one embodiment of the present invention, in the global layout optimization stage, the Nesterov accelerated gradient method can also be used for iterative optimization. Nesterov is an extension of gradient descent - an improvement on the momentum method. For the momentum method, the parameter update of each iteration is based on the exponential weighted average of past gradients. The improvement of the Nesterov momentum on the momentum method lies in the position of gradient calculation. The momentum method calculates the gradient at the current position, while the Nesterov momentum calculates the gradient at the predicted position of the current parameter position plus the momentum. This makes it possible to obtain gradient information in advance and make more appropriate adjustments. Therefore, in the present invention, the momentum term refers to the position where the gradient is calculated, that is, the calculation The positions of the various gradients of the optimization problem (the total line length gradient and the system potential gradient, or the total line length gradient, the system potential gradient, and the pin density gradient). This method accelerates the convergence speed of the optimization process by introducing the momentum term, and can find a better layout solution in a shorter time than the traditional gradient descent method. During the iteration process, the algorithm continuously adjusts the layout positions of the core particles and ports, while taking into account the influence of the pin density, striving to minimize the line length while meeting the design rules, and improving the efficiency and quality of the overall layout.

[0095] Step S3: Adjust the second layout result so that the layout meets the layout rationality constraints between the core particles, and obtain a third layout result, wherein each layout result from the first to the third layout results includes: the layout position of each core particle and the layout position of each port in the layoutable area of ​​the substrate.

[0096] According to one embodiment of the present invention, the third layout result is obtained in the following manner: obtaining a layout rationality constraint between core particles, the constraint including that any two core particles must maintain a preset spacing between each other, and the value of the spacing is greater than 0; based on the second layout result and the layout rationality constraint, using a simulated annealing algorithm to iteratively adjust the layout positions of the core particles to meet the layout rationality constraint, thereby obtaining a third layout result.

[0097] Step S3 is equivalent to the layout legalization stage. In order to ensure the rationality and manufacturability of the layout, the method of the present invention can apply the simulated annealing algorithm to perform rationality verification and adjustment on the layout of the core particles and ports. The optimization goal of the layout legalization stage is:

[0098] f LG (U) = HPWL (υ) + μ o O m (υ)

[0099] Where HPWL(v) represents the total length of the semi-perimeter estimate, m (v) represents the overlapping area between core particles, μo To optimize the target O m (v) is the weight parameter. In the simulated annealing algorithm adopted in the present invention, two iterations are used, and the indexes of the outer iteration and the inner iteration are j and k respectively. In the inner iteration, a unit is randomly selected, the core particle is moved within an acceptable moving radius, and the value of the objective function is calculated. If it is better, the solution is accepted as the initial solution for the next iteration with a certain probability. At the same time, in each iteration, if a global legal solution appears, the iteration is terminated. After several inner iterations, μ is updated in the outer iteration. o and the unit movement radius to find a legal solution.

[0100] According to an example of the present invention, see Figure 6 , provides a schematic process of using simulated annealing algorithm to adjust the layout rationality, including:

[0101] A1. Input the layout result to be optimized v = (x, y) T , initialize μ o ; The first input is the second layout result, and the subsequent input is the intermediate layout result iteratively adjusted based on the second layout result;

[0102] A2. Set K = 0, initialize temperature t j,0 , moving radius r j,0 ;

[0103] A3. Randomly select a core particle and move it a random distance d <r j,0 ;

[0104] A4. Evaluate the optimization target increment (Δf), where Δf is the sum of two consecutive times using f LG (v) the change in the value calculated by the formula;

[0105] A5. Randomly generate τin(0,1), according to If it is established, determine whether the result after the move has been completed. If it is established, go to A6, otherwise go to A7;

[0106] A6, determine whether the moving result is legal (Overlap=0?, that is, whether it meets the layout rationality constraint. Overlap=0 means it meets, otherwise it does not meet). If so, go to A9, otherwise go to A7;

[0107] A7, K++, Update j,k and r j,k , transfer to A8;

[0108] A8, j++, update μ o , transfer to A2;

[0109] A9. Output the layout result, expressed as v'=(x',y')T =(x1',…,x n ',y1',…,y n ') T . Among them, x1',…,x n ',y1',…,y n ' respectively represent the x-coordinate and y-coordinate of the 1st to nth elements (including core particles and ports).

[0110] In the layout legalization stage, the simulated annealing algorithm is used to check and correct the legality of the layout. The algorithm simulates the physical annealing process. By controlling the temperature parameters of the algorithm, the layout can be extensively tried at high temperature to jump out of the local optimal solution; as the temperature gradually decreases, the layout gradually stabilizes and eventually converges to a reasonable layout solution that satisfies the requirement that the core particles are at least a preset distance apart and there is no core particle overlap. This process ensures the feasibility of the layout and avoids design violations.

[0111] It should be understood that, in addition to the simulated annealing algorithm, implementers may also use other alternative algorithms to optimize layout rationality to achieve similar effects, such as ant colony algorithm or genetic algorithm.

[0112] Step S4: Obtain the layout constraints of the bumps on the substrate and the layout positions of each port extracted from the third layout result, match each port with the bump one by one, update the layout positions of each port in the third layout result based on the bump position matched by each port, and obtain a fourth layout result.

[0113] According to one embodiment of the present invention, the fourth layout result is obtained in the following manner: obtaining the layout constraints of the bumps on the substrate and the layout positions of each port extracted from the third layout result; determining the positions of each bump on the layoutable area of ​​the substrate according to the layout constraints of the bumps, matching each port with the bump one by one based on the proximity principle, and obtaining a bump-port matching table; for each port, according to the bump-port matching table, updating the layout position of the port in the third layout result using the bump position matched by the port, and obtaining a fourth layout result.

[0114] Since the bumps used to connect to the outside world need to be arranged according to certain rules when manufacturing the core particles, it is necessary to make the port layout meet the design rule constraints of the bumps. In the final stage of layout, the present invention adopts a stable marriage algorithm to solve the matching problem between the bumps and the ports. By calculating the distance between each port and the preset bump in advance, it is ensured that each port can form a stable pairing with a bump. This pairing method reduces the line length to the greatest extent, improves the compactness and integration of the layout, and thus enhances the system integration and manufacturability of the entire layout solution.

[0115] According to an embodiment of the present invention, the nearest port to the unmatched convex point can be matched one by one using the proximity principle, and the matched convex points are removed from the unmatched convex points. Alternatively, the stable marriage algorithm (Gale-Shapely) can be applied to perform intelligent matching between convex points and ports. Figure 7 , the schematic process of matching based on the stable marriage algorithm includes:

[0116] The ports are taken as set M and the convex points s are taken as set W;

[0117] Initialize a preference list for ports and bumps based on the proximity principle;

[0118] The port proposes matches (i.e., proposals) to nearby salient points s one by one according to its preference list based on the proximity principle;

[0119] After receiving multiple proposals, each convex point selects the nearest proposal and rejects other proposals;

[0120] When each external port has an accepted match, the iteration stops and the bump-port assignment result (i.e., bump-port matching table) is output.

[0121] The stable marriage algorithm is based on the stable matching theory. Through a series of proposal and acceptance processes, it ensures that each port can form a stable matching relationship with a bump, fully considers the distance factor between the port and the preset bump, and maximizes the integration of the layout. At the same time, it can also reduce the complexity of subsequent wiring and improve the compactness and economy of the overall layout.

[0122] A schematic layout result can be seen Figure 8 , where the left picture shows the layout of the core particles, and the right picture shows the layout of the ports.

[0123] In general, the present invention proposes a systematic solution to the substrate layout problem to improve the efficiency of large-scale integrated circuit design.

[0124] It should be noted that although the above describes the various steps in a specific order, it does not mean that the various steps must be executed in the above specific order. In fact, some of these steps can be executed concurrently or even in a different order as long as the required functions can be achieved.

[0125] The present invention may be a system, a method and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present invention.

[0126] Computer readable storage medium can be a tangible device that holds and stores instructions used by an instruction execution device. Computer readable storage medium can include, for example, but is not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (non-exhaustive list) of computer readable storage medium include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, for example, a punch card or a protruding structure in a groove on which instructions are stored, and any suitable combination thereof.

[0127] The embodiments of the present invention have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A method for designing a substrate layout of a chiplet system, characterized in that: include: The size of each chip to be laid out, the size of the layout area of ​​the substrate, the pins on each chip and the interface set formed by the ports on the substrate, the connection relationship between the interfaces in the interface set, and the position of each pin on the chip are obtained to initialize the substrate layout and perform layout adjustment with minimizing the total wiring length as the optimization goal to obtain a first layout result; Taking minimizing the weighted sum of the layout density and the bus length of the wiring between interfaces as the optimization goal, performing global layout optimization on the first layout result to obtain a second layout result; The second layout result is adjusted so that the layout meets the layout rationality constraints between the core particles, and a third layout result is obtained, wherein each layout result of the first to third layout results includes: the layout position of each core particle and the layout position of each port in the layoutable area of ​​the substrate.

2. The method according to claim 1, characterized in that The method further comprises: The layout constraints of the bumps on the substrate and the layout positions of the ports extracted from the third layout result are obtained, each port is matched with the bump one by one, and the layout positions of the ports in the third layout result are updated based on the bump position matched by each port to obtain a fourth layout result.

3. The method according to claim 2, characterized in that The first layout result is obtained in the following manner: According to the size of each chip to be laid out, the size of the substrate layout area and the interface set, the position of each chip and each port is initially placed at the center of the substrate layout area to obtain an initial layout result; Without considering layout constraints, the optimization goal is to minimize the estimated total length of all wire nets based on a preset boundary-boundary model, and the layout positions of the core particles and ports are iteratively adjusted multiple times based on the initial layout results to obtain a first layout result, wherein each wire net refers to a connection line of a group of interfaces that need to be connected in an interface set, and the length of the wire net is calculated based on the position of each core particle, the position of each pin on the core particle, the layout position of the port and the connection relationship of each interface.

4. The method according to claim 3, characterized in that The second layout result is obtained in the following manner: Obtaining a pre-built weighted average line length model and a layout density model based on an electrostatic field, wherein the weighted average line length model is used to calculate the total line length according to the layout position of the interface and a preset control precision coefficient, and the layout density model calculates the system potential energy according to the layout position of the interface. In the layout density model, the substrate layout area is regarded as a static electric field, and the core particles and ports as movable components are regarded as charged bodies with positive charges; Taking minimizing the weighted sum of the total line length and the system potential energy as the optimization goal, multiple layout iterations are performed on the layout positions of the core particles and the ports based on the first layout result to obtain the second layout result.

5. The method according to claim 3, characterized in that: The second layout result is obtained in the following manner: Obtaining a pre-built weighted average line length model, a density model based on an electrostatic field, and a pin density model of a core particle, wherein the weighted average line length model is used to calculate the total line length according to the layout position of the interface and a preset control precision coefficient, and the layout density model calculates the system potential energy according to the layout position of the interface. In the layout density model, the layoutable area of ​​the substrate is regarded as a static electric field, and the core particles and ports as movable components are regarded as charged bodies with positive charges; Taking minimizing the weighted sum of the total line length, system potential energy and pin density as the optimization goal, multiple layout iterations are performed on the layout positions of the core particles and ports based on the first layout result to obtain the second layout result.

6. The method according to claim 4 or 5, characterized in that: The third layout result is obtained in the following manner: Obtaining the layout rationality constraint between the core particles, the constraint includes that any two core particles must maintain a preset distance between each other, and the value of the distance is greater than 0; According to the second layout result and the layout rationality constraint, the layout position of the core particles is iteratively adjusted using a simulated annealing algorithm to meet the layout rationality constraint, thereby obtaining a third layout result.

7. The method according to claim 2, characterized in that: The fourth layout result is obtained in the following way: Obtaining the layout constraints of the bumps on the substrate and the layout positions of the various ports extracted from the third layout result; Determine the position of each bump on the layout area of ​​the substrate according to the layout constraints of the bumps, match each port with the bump one by one based on the proximity principle, and obtain a bump-port matching table; For each port, according to the bump-port matching table, the layout position of the port in the third layout result is updated using the bump position matched by the port to obtain a fourth layout result.

8. A computer program product, comprising a computer program / instruction, which, when executed by a processor, implements the steps of the method according to any one of claims 1 to 7.

9. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and the computer program can be executed by a processor to implement the steps of the method according to any one of claims 1 to 7.

10. An electronic device, characterized in that: include: one or more processors; as well as A memory, wherein the memory is used to store executable instructions; The one or more processors are configured to implement the steps of the method of any one of claims 1-7 by executing the executable instructions.

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