Integrated circuit chip silver paste bonding process quality control method based on physical state

Abstract

The invention discloses an integrated circuit chip silver paste bonding process quality control method based on a physical state. The method comprises the following steps: performing process decomposition on a bonding process, identifying a physical state, and analyzing each potential fault mode, so as to obtain an FMEA analysis conclusion of the process; the control method and requirements of the bonding technological process are clarified, and effective technical support is provided for improvement and refinement of the quality control level of the chip silver paste bonding technological process.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor devices, in particular to a physical state-based quality control method for silver paste bonding process of integrated circuit chips. Background Art

[0002] The chip silver paste bonding process is an important process link in the packaging of semiconductor devices. With the rapid growth in demand for domestic components, especially in the context of independent and controllable technology, the proportion and quantity of domestic electronic components used in aerospace models continue to increase. Due to the inadequate control of the chip bonding process and poor quality during the device packaging process, it brings great constraints and difficulties to the improvement of the reliability of aerospace components.

[0003] Currently, the FMEA (Failure Mode and Effect Analysis) method is a systematic quality control tool mainly used in large-scale engineering projects such as spacecraft, space stations, and starships. There are no relevant methods for device packaging process quality control, especially there are no relevant methods or requirements for systematic FMEA for component chip bonding processes. Summary of the invention

[0004] The present invention provides a physical state-based quality control method for the silver paste bonding process of integrated circuit chips, the purpose of which is to identify the physical state of the silver paste bonding process, conduct risk analysis and evaluation on the process, formulate process control methods and requirements, and provide effective technical support for the refined management and quality improvement of the silver paste bonding process of aerospace device chips.

[0005] In a first aspect, a physical state-based quality control method for silver paste bonding process of integrated circuit chips is provided, comprising:

[0006] According to the process flow of chip silver paste bonding process, the function of each process of bonding process is analyzed;

[0007] Identify the physical state of the chip silver paste bonding;

[0008] Combined with the physical state, the potential failure mode analysis of each process of the chip silver paste bonding process is carried out to determine the potential failure mode in chip bonding;

[0009] Analyze the failure causes and mechanisms of each potential failure mode to obtain a first analysis result;

[0010] Perform failure impact and risk analysis on each potential failure mode to obtain a second analysis result;

[0011] Outputting a FMEA analysis result table according to the first analysis result and the second analysis result;

[0012] According to the FMEA analysis results, key process elements and weak links are identified, and the corresponding control levels of process elements are divided;

[0013] Based on the control level of process elements, process quality control procedures and requirements are formed.

[0014] In combination with the first aspect, in certain implementations of the first aspect, the function of each step of the bonding process is analyzed according to the process flow of the chip silver paste bonding process, including:

[0015] The process of chip silver paste bonding is decomposed into the following steps: surface treatment of the surface to be bonded, dispensing, bonding, and curing;

[0016] The functional analysis of each process is as follows: surface treatment of the surface to be bonded, removing dirt and loose layers that hinder bonding, increasing surface energy, and improving bonding effect; dispensing, setting a dispensing pattern according to the size of the chip and applying it to the bottom plate of the tube shell; bonding, aligning the bottom plate of the tube shell with the chip after dispensing, bonding, removing air, and mixing the glue layer; curing, hardening the colloid surface under specified temperature and time conditions to achieve a specified degree of cross-linking, eliminating internal stress, and forming bonding.

[0017] In combination with the first aspect, in certain implementations of the first aspect, the physical state of the silver paste bonding of the identified chip includes: chip bonding position, chip bonding direction, bonding voids, silver paste overflow range, silver paste overflow height, silver paste surface morphology, device internal atmosphere, chip bonding strength, and chip shear separation mode.

[0018] In combination with the first aspect, in certain implementations of the first aspect, the step of performing a potential failure mode analysis on each process of the chip silver paste bonding process to determine the potential failure mode in the chip bonding includes:

[0019] Early failure, electrical stress burnout, thermal stress failure, excess conductivity, bonding failure, silver migration.

[0020] In conjunction with the first aspect, in some implementations of the first aspect, the first analysis result includes:

[0021] The reasons for early failure are: insufficient adhesive material, which does not achieve a strong bonding effect; excessive bonding pressure, which makes the chip bear greater pressure and the chip is prone to cracking and damage; the curing speed is too fast, and the adhesive layer becomes brittle;

[0022] The reasons for failure of electrical stress burnout are: the presence of pollutants and severe oxidation affect the wetting of the adhesive on the surface of the adherend, forming large-area bonding voids; insufficient adhesive material and improper dispensing patterns lead to discontinuous and uneven adhesive layers; the bonding pressure is too small, and the internal gas is difficult to discharge, forming bonding voids;

[0023] The reasons for thermal stress failure are: too fast cooling, resulting in large internal stress, causing chip damage;

[0024] The reasons for the failure of excess conductive failure are: too much adhesive and excessive pressure lead to serious accumulation of adhesive at the edge of the device, which contacts the surface of the chip; the chip is close to the external bonding frame, and the adhesive accumulates and climbs to the external bonding area; improper cleaning process after chip bonding leads to the fall of adhesive;

[0025] The reasons for the failure of bonding are: the sticky contamination generated during the bonding process is not treated in accordance with the requirements before bonding, resulting in the risk of the bonding wire being debonded or the bonding tension being reduced after the circuit is screened at high temperature;

[0026] The failure reasons of silver migration are: the environment in which the device is located during and after the process is completed, the humidity and atmosphere are poor, and the silver particles in the silver paste migrate according to the silver migration mechanism;

[0027] In combination with the first aspect, in some implementations of the first aspect, the second analysis result includes:

[0028] The corresponding relationship between the failure mode impact and severity of the chip silver paste bonding process, the corresponding relationship between the failure risk and the frequency of failure mode occurrence, and the corresponding relationship between the failure risk and the detectability of the failure mode.

[0029] In combination with the first aspect, in certain implementations of the first aspect, the FMEA analysis result table includes processes, process parameters corresponding to the processes, failure modes corresponding to the process parameters, failure consequences, failure causes and detection methods corresponding to the failure modes.

[0030] In conjunction with the first aspect, in certain implementations of the first aspect, the division results of the corresponding control levels of the process elements include:

[0031] A-level key and important process elements, high-frequency quality inspection and extremely strict quality control;

[0032] Class B important process elements, conduct medium frequency quality inspection and strict quality control;

[0033] Level C general process elements conduct low-frequency quality inspections and general quality control.

[0034] In conjunction with the first aspect, in certain implementations of the first aspect, the process quality control flow and requirements include:

[0035] Silver paste bonding process quality control process and requirements, quality inspection process and requirements after the bonding process is completed, and process control table.

[0036] In combination with the first aspect, in certain implementations of the first aspect, the process control table includes the process, the control requirements and inspection requirements corresponding to the process, the control levels and control elements corresponding to the control requirements, and the inspection tools, inspection cycles, and inspection capacities corresponding to the inspection requirements.

[0037] Compared with the prior art, the solution provided by the present invention includes at least the following beneficial technical effects:

[0038] The present invention provides an FMEA quality control method for integrated circuit chip bonding process based on physical state, which gives the physical state related to silver paste bonding, analyzes the potential failure modes and corresponding risk impacts in the silver paste bonding process, identifies the key process elements in the process, clarifies the quality control method and requirements of the silver paste bonding process, provides effective technical support for improving and refining the quality control level of the chip silver paste bonding process, and provides improvement guidance to production units. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 It is a flow chart of the steps of FMEA quality control method for integrated circuit chip bonding process based on physical state.

[0040] Figure 2 This is a breakdown diagram of the chip silver paste bonding process.

[0041] Figure 3 This is a chart for dividing the control levels of the chip silver paste bonding process elements.

[0042] Figure 4 It is a flow chart of the quality control method of chip silver paste bonding process.

[0043] Figure 5 This is the quality inspection control flow chart after the chip silver paste bonding process is completed. DETAILED DESCRIPTION

[0044] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0045] Reference Figure 1 , shows a flow chart of the steps of a FMEA quality control method for integrated circuit chip bonding process based on physical state in an embodiment of the present invention. The specific steps are as follows.

[0046] Step 1: According to the process flow of device chip silver paste bonding, analyze the function of each bonding process.

[0047] Reference Figure 2, shows a full-process decomposition diagram of the chip silver paste bonding process in an embodiment of the present invention, and decomposes the silver paste bonding process into material preparation (paste preparation, chip and shell preparation to be bonded), pre-bonding preparation (surface treatment of the surface to be bonded), dispensing, bonding, curing (initial curing, basic curing and post-curing), inspection, and storage, and analyzes the function of each process in the silver paste bonding process.

[0048] The functional analysis of each process is as follows: surface treatment of the surface to be bonded, removing dirt and loose layers that hinder bonding, increasing surface energy, and improving bonding effect; dispensing, setting a dispensing pattern according to the size of the chip and applying it to the bottom plate of the tube shell; bonding, aligning the bottom plate of the tube shell with the chip after dispensing, bonding, removing air, and mixing the glue layer; curing, hardening the colloid surface under specified temperature and time conditions to achieve a specified degree of cross-linking, eliminating internal stress, and forming bonding.

[0049] Step 2: Decompose and identify the physical state of the device chip silver paste bonding to establish a baseline and provide a reference standard for subsequent quality inspection and quality control.

[0050] In this embodiment, after performing process function analysis, combined with device physical inspection methods and historical quality issues, the physical state related to the silver paste bonding process is obtained, including:

[0051] Chip bonding position: X-ray inspection and internal visual inspection can be used to obtain the chip bonding position and tilt.

[0052] Die bonding direction: The die bonding direction can be obtained through X-ray inspection and internal visual inspection.

[0053] Bonding voids: X-ray inspection can be used to determine whether there are voids in the chip bonding, as well as the void area and void ratio.

[0054] Silver paste overflow range: X-ray inspection and internal visual inspection can be used to obtain the overflow range of the silver paste, including whether it overflows and the overflow range, with special attention paid to whether it overflows to the side of the bonding frame outside the tube shell.

[0055] Silver paste overflow height: The overflow height of the silver paste can be obtained through X-ray inspection and internal visual inspection, including the overflow height on the chip side and the overflow height on the external bonding frame side (if the overflow range reaches the external bonding frame side), especially pay attention to whether it reaches the chip surface or the external bonding frame surface.

[0056] Silver paste surface morphology: The surface morphology of the silver paste can be obtained through internal visual inspection, including whether there is peeling, peeling, ridges, cracks, discoloration, etc.

[0057] Atmosphere inside the device: The internal gas composition of the device can be obtained through internal gas composition analysis, including water vapor and other gas components and contents.

[0058] Chip bonding strength: The chip shear strength can be used to obtain the chip bonding strength, i.e. the shear force value.

[0059] Chip shear separation mode: The chip bonding separation mode can be obtained through the chip shear strength, which is divided into broken chips remaining on the tube shell base; the chip and the silver paste are separated at the interface; the silver paste body is damaged or the silver paste tube shell base is separated at the interface.

[0060] Step 3: Based on the above physical conditions, conduct potential failure mode analysis on each process of the chip silver paste bonding process to determine the potential failure mode in the silver paste bonding process.

[0061] In this embodiment, after performing process function analysis and physical state identification, possible failure modes can be analyzed through historical failure cases, process principle analysis, and theoretically existing potential failure possibilities.

[0062] Based on the device manufacturing process, previous inspection results, failure cases during user use, and theoretical analysis, the potential failure modes that can be determined in the process include:

[0063] Early failure: The chip bonding quality does not meet the requirements. The chip is poorly soldered or falls off from the chip area or cavity, and the chip itself is damaged, resulting in the complete loss of function of the integrated circuit.

[0064] Failure due to electrical stress burning: During chip mounting, poor ohmic contact increases the thermal resistance of the device, resulting in uneven heat dissipation, affecting the distribution of current in the device, destroying the thermal stability of the device, and causing the device to burn out and fail.

[0065] Thermal stress failure: When the external temperature changes or the temperature of the device itself changes, the mounting interface is subjected to thermal stress, which gathers at the location of the cavity and causes cracks in the adhesive and even cracks in the silicon wafer, ultimately causing the device to fail due to thermal fatigue.

[0066] Conductive failure due to excess material: Movable conductive excess material is generated during the chip mounting process, or the adhesive material comes into contact with the active area of ​​the chip, causing the device to short-circuit and fail.

[0067] Bonding failure: During the chip mounting process, the bonding pad position is contaminated, which will have an adverse effect on the subsequent bonding process and cause bonding failure.

[0068] Silver migration: Silver particles in the silver paste will migrate according to the silver migration mechanism, and eventually contact the anode to cause a short circuit and irregular current, leading to electrical failure of the device.

[0069] Step 4-1: Analyze the failure cause and mechanism of each potential failure mode to obtain the first analysis result.

[0070] In this embodiment, after each potential failure mode is determined according to step 2, a failure cause and mechanism analysis may be performed for each potential failure mode, thereby providing guidance for process improvement during device manufacturing.

[0071] As shown in Table 1, a table showing the correspondence between failure modes of a chip silver paste bonding process and typical failure causes and mechanisms in an embodiment of the invention is shown.

[0072] Table 1 Correspondence between failure modes and typical failure causes and mechanisms

[0073]

[0074] Step 4-2: Perform failure impact and risk analysis on each potential failure mode to obtain a second analysis result.

[0075] In this embodiment, after determining the potential failure mode of the chip silver paste bonding process according to step 2, the failure cases that have occurred in the device and the possible potential failure modes can be analyzed to obtain the impact that the bonding process may have on the next process, the device itself, etc. under different failure modes, and the degree of impact can be analyzed.

[0076] As shown in Tables 2 to 4, a severity score table, an occurrence frequency score table and a detectability score table of a chip silver paste bonding process in an embodiment of the present invention are shown.

[0077] Table 2 Severity score table

[0078]

[0079] Table 3 Occurrence frequency score table

[0080] Frequency Rating Probability of failure mode occurring Failure mode occurrence probability Pm reference range 1 Very low or never occurs <![CDATA[Pm≤10 -6 ]]> 2 Lower <![CDATA[1×10 -6 <Pm≤1×10 -4 ]]> 3 medium <![CDATA[1×10 -4 <Pm≤1×10 -2 ]]> 4 high <![CDATA[1×10 -2 <Pm≤1×10 -1 ]]> 5 Very high <![CDATA[Pm>10 -1 ]]>

[0081] Table 4 Detectability score table

[0082]

[0083] As shown in Table 2, the second analysis results include the scoring results of the corresponding relationship between the failure mode impact and severity of the chip silver paste bonding process, and the scoring results of the corresponding relationship between the failure risk and the failure mode occurrence frequency and the failure mode detectability.

[0084] Step 5: Output the FMEA analysis result table based on the first analysis result and the second analysis result.

[0085] In this embodiment, after the analysis of steps 1 to 5 above, the potential failure modes of the current device chip silver paste bonding process are analyzed and summarized on the causes, mechanisms, impacts and existing detection methods, and the final FMEA analysis result table (Table 5) is listed and output.

[0086] Table 5 FMEA test analysis results

[0087]

[0088]

[0089]

[0090]

[0091] Step 6: According to the FMEA analysis results, key process elements are identified and weak links are determined to obtain the corresponding control level division results of the process elements.

[0092] In this embodiment, refer to Figure 3 , shows a control grade classification diagram of the silver paste bonding process elements in an embodiment of the present invention, defining Class A as a key and important process element, which requires high-frequency inspection and extremely strict quality control; defining Class B as an important process element, which requires a certain frequency of quality inspection and strict quality control; defining Class C as a general process element, which can be quality inspected at a lower frequency and subject to general quality control.

[0093] Step 7: Based on the control level of process elements, form process quality control procedures and requirements, and feed them back to the production unit to provide technical support and management basis for the control and management of the chip bonding process of its products.

[0094] In this embodiment, refer to Figure 4 and Figure 5 , shows the process quality control method flow chart of the silver paste bonding process in the embodiment of the present invention and the process quality inspection control flow chart after the process is completed, formulates control requirements according to the process element control level, clarifies the inspection cycle and inspection means, and outputs the process control table. Taking part of the process as an example, the output process control table is shown in Table 6.

[0095]

[0096] In summary, the FMEA quality control method for the integrated circuit chip bonding process of the present invention provides a FMEA quality control method for the device chip silver paste bonding process: by decomposing the bonding process, identifying the physical state, and analyzing each potential failure mode, the analysis conclusion of the process FMEA is obtained; the bonding process control method and requirements are clarified, which provides effective technical support for improving and refining the quality control level of the chip silver paste bonding process.

[0097] Although the present invention is disclosed as above in terms of preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope defined by the claims of the present invention.

Claims

1. A physical state based integrated circuit chip silver paste bonding process quality control method, characterized in that: include: According to the process flow of chip silver paste bonding process, the function of each process of bonding process is analyzed; Identify the physical state of the chip silver paste bonding; Combined with the physical state, the potential failure mode analysis of each process of the chip silver paste bonding process is carried out to determine the potential failure mode in chip bonding; Analyze the failure causes and mechanisms of each potential failure mode to obtain a first analysis result; Perform failure impact and risk analysis on each potential failure mode to obtain a second analysis result; Outputting a FMEA analysis result table according to the first analysis result and the second analysis result; According to the FMEA analysis results, key process elements are identified and weak links are determined, and the corresponding control levels of process elements are divided; Based on the control level of process elements, process quality control procedures and requirements are formed.

2. The method according to claim 1, characterized in that According to the process flow of the chip silver paste bonding process, the functions of each process of the bonding process are analyzed, including: The process of chip silver paste bonding is decomposed into the following steps: surface treatment of the surface to be bonded, dispensing, bonding, and curing; The functional analysis of each process is as follows: surface treatment of the surface to be bonded, removing dirt and loose layers that hinder bonding, increasing surface energy, and improving bonding effect; dispensing, setting a dispensing pattern according to the size of the chip and applying it to the bottom plate of the tube shell; bonding, aligning the bottom plate of the tube shell with the chip after dispensing, bonding, removing air, and mixing the glue layer; curing, hardening the colloid surface under specified temperature and time conditions to achieve a specified degree of cross-linking, eliminating internal stress, and forming bonding.

3. The method according to claim 1, characterized in that The physical state of the silver paste bonding of the identification chip includes: chip bonding position, chip bonding direction, bonding cavity, silver paste overflow range, silver paste overflow height, silver paste surface morphology, device internal atmosphere, chip bonding strength, and chip shear separation mode.

4. The method according to claim 1, characterized in that: The potential failure mode analysis of each process of the chip silver paste bonding process is performed to determine the potential failure mode in the chip bonding, including: Early failure, electrical stress burnout, thermal stress failure, excess conductivity, bonding failure, silver migration.

5. The method according to claim 4, characterized in that The first analysis result includes: The reasons for early failure are: insufficient adhesive material, which does not achieve a strong bonding effect; excessive bonding pressure, which makes the chip bear greater pressure and the chip is prone to cracking and damage; the curing speed is too fast, and the adhesive layer becomes brittle; The reasons for failure of electrical stress burnout are: the presence of pollutants and severe oxidation affect the wetting of the adhesive on the surface of the adherend, forming large-area bonding voids; insufficient adhesive material and improper dispensing patterns lead to discontinuous and uneven adhesive layers; the bonding pressure is too small, and the internal gas is difficult to discharge, forming bonding voids; The reasons for thermal stress failure are: too fast cooling, resulting in large internal stress, causing chip damage; The reasons for the failure of excess conductive failure are: too much adhesive and excessive pressure lead to serious accumulation of adhesive at the edge of the device, which contacts the surface of the chip; the chip is close to the external bonding frame, and the adhesive accumulates and climbs to the external bonding area; improper cleaning process after chip bonding leads to the fall of adhesive; The reasons for the failure of bonding are: the sticky contamination generated during the bonding process is not treated in accordance with the requirements before bonding, resulting in the risk of the bonding wire being debonded or the bonding tension being reduced after the circuit is screened at high temperature; The failure reasons of silver migration are: the humidity and atmosphere of the device environment during and after the process are poor, and the silver particles in the silver paste migrate according to the silver migration mechanism.

6. The method according to claim 1, characterized in that The second analysis result includes: The corresponding relationship between the failure mode impact and severity of the chip silver paste bonding process, the corresponding relationship between the failure risk and the frequency of failure mode occurrence, and the corresponding relationship between the failure risk and the detectability of the failure mode.

7. The method according to claim 1, characterized in that The FMEA analysis result table includes the process, the process parameters corresponding to the process, the failure mode corresponding to the process parameters, the failure consequences, failure causes and detection methods corresponding to the failure mode.

8. The method according to claim 1, characterized in that The results of the division of the corresponding control levels of process elements include: A-level key and important process elements, high-frequency quality inspection and extremely strict quality control; Class B important process elements, conduct medium frequency quality inspection and strict quality control; Level C general process elements conduct low-frequency quality inspections and general quality control.

9. The method according to claim 1, characterized in that: The process quality control procedures and requirements include: Silver paste bonding process quality control process and requirements, quality inspection process and requirements after the bonding process is completed, and process control table.

10. The method according to claim 9, characterized in that The process control table includes the process, the control requirements and inspection requirements corresponding to the process, the control levels and control elements corresponding to the control requirements, and the inspection tools, inspection cycles, and inspection capacities corresponding to the inspection requirements.

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