Low power memory with on-demand bandwidth boost

Abstract

Some embodiments of the present disclosure relate to a low power memory with on demand bandwidth boost. In a memory component having a command / address interface, a timing interface, and a data interface, the command / address interface receives a first command / address value from a control component during a first interval, and receives a second command / address value from the control component during a second interval. The timing interface receives a data gate from the control component during a first interval, and receives a data clock from the control component during a second interval, the data gate deviating from the dwell voltage level to start triggering at a time corresponding to receiving the first command / address value, and the data clock being triggered throughout the second interval, and the receiving time of the second command / address value is independent. The data interface samples first write data corresponding to the first command / address value at a time indicated by triggering the data strobe, and samples second write data corresponding to the second command / address value at a time indicated by triggering the data clock.

Description

[0001] Description of the case

[0002] This application is a divisional application of the Chinese national phase patent application of the PCT application with international application number PCT / US2020 / 019606, Chinese national application number 202080016988.4, and invention name “Low-power memory with on-demand bandwidth enhancement”. Technical Field

[0003] The present disclosure relates generally to data processing and, more particularly, to memory systems and components thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] By way of example and not limitation, various embodiments disclosed herein are illustrated in the several figures of the accompanying drawings and in which like reference numerals refer to similar parts and in which

[0005] Figure 1 An embodiment of a synchronous memory system that dynamically switches between a low power gating based data transfer mode and a high bandwidth continuously clocked "boost" mode is illustrated;

[0006] Figure 2 Picture shows Figure 1 Additional signaling details in low power bandwidth mode and increased bandwidth mode are shown;

[0007] Figure 3 The diagram shows the ability to Figure 1 and Figure 2 Embodiments of a memory system of a control component and a memory component for switching between a low power data transfer mode and a bandwidth boost data transfer mode as described;

[0008] Figure 4 Picture shows Figure 3 An exemplary time-varying phase offset between a unified memory clock domain and a timing signal generated within a control component within an embodiment of the present invention;

[0009] Figure 5 Reiterates the initial phase shift and time drift voltage / temperature dependent delay Figure 4 The delay expression shown in Figure 3 Embodiments of a delay tracking arrangement implemented in a memory system of the present invention to periodically (or aperiodically) adjust a timing delay imposed by a phase adjustment circuit therein to compensate for time-varying timing domain skew;

[0010] Figure 6 The diagram shows how to implement Figures 3 to 5 An embodiment of a phase adjustment circuit of the phase adjustment circuit shown;

[0011] Figure 7The diagram shows the Figure 5 An embodiment of a delay generator circuit of the delay generator shown;

[0012] Figure 8 illustrates an alternative embodiment of a memory system having bandwidth boost on demand and communicating read and write data strobe signals between a control component and a memory component via separate (corresponding) signaling links while operating in a low power mode;

[0013] Fig. 9 illustrates an exemplary mode register that may be implemented in the various control component and memory component embodiments discussed herein, respectively; and

[0014] Fig.10 A memory system transition from a low power mode to a high bandwidth mode and then back to a low power mode is illustrated showing exemplary command write data and write data timing signals during the mode transition. DETAILED DESCRIPTION

[0015] In various embodiments herein, a memory controller and a memory component switch between two or more different synchronous data transfer modes (e.g., on demand), thereby operating in a relatively low power data transfer mode until, for example, a high transfer bandwidth is required and then switching to a high bandwidth "boost mode". In several embodiments, read and write data transfers between the memory component and the control component are timed by a source synchronous data strobe signal in a low power mode, which source synchronous data strobe signal - i.e., a timing signal that switches to indicate the presence of valid data on the companion data path but otherwise resides at a steady state level (i.e., does not trigger during idle periods when no data is being transferred), and by a "free running" clock signal that triggers continuously (e.g., in a high bandwidth boost mode), regardless of whether data is being transferred on the companion data path (i.e., the clock triggers during both data transfer intervals and idle intervals). In order to limit system power consumption, the memory component is typically implemented without timing alignment circuitry (e.g., without lock loop circuitry), but instead relies on a control component ("controller") to phase adjust control-side timing signals as needed to accommodate memory-side timing domains that drift with voltage and temperature relative to a controller-generated system clock. Periodic timing calibration operations are performed for mode-specific data timing signals to establish phase delays that accommodate seamless transitions between low-power modes and boosted bandwidth modes. During runtime transitions between these modes, the timing delays imposed by the controller are exchanged in operation (i.e., during system operation) to enforce mode-specific timing alignment, thereby achieving internal phase jumps (i.e., instantaneous phase changes or near-instantaneous phase changes) relative to read and write data timing signals applied within the control component. In several embodiments or programming configurations, the memory system switches between low-power modes and boosted bandwidth modes according to host instructions (e.g., instructions from a processor within a host computing device or appliance) that establish programming settings within the control component (the control component may propagate it to the memory component). In other embodiments or programming configurations, the control component may autonomously switch between low-power modes and boosted bandwidth modes, for example, based on memory transaction volume, source power state (battery vs line power), etc. These and other features and embodiments are discussed in more detail below.

[0016] Figure 1An embodiment of a synchronous memory system 100 is illustrated that dynamically (i.e., during task operation and thus on-the-fly or on-demand) switches between a strobe-based data transfer mode 101 and a continuously clocked "boost" mode 103, which are generally referred to herein as "(strobe-based) low power mode and high bandwidth mode" according to host memory bandwidth requirements, although in all cases, the switching between strobe-timed data transfer and continuously clocked data transfer may be driven by various factors other than (or in addition to) power reduction / bandwidth requirements. As shown, the memory system 100 includes a memory control component 105 ("control component" or "controller"), and a memory component 107, the former of which issues command / address values ​​(control information) as needed to achieve memory read and write access within the data storage array of the latter. Generally speaking, the control component and the memory component are implemented in different (respective) integrated circuit chips and are connected via wired control, timing and data signaling links ( Figure 1 The links may extend across a substrate (motherboard or interposer, e.g., in a modular memory system) or may extend vertically or laterally through conductive vias, wire bonds, cables, etc. within a multi-chip integrated circuit package (e.g., a control component and one or more memory components implemented in a stacked chip memory package). Further, although generally described in the context of a single memory component 107, Figure 1The memory system of the embodiment described below is described, but the system generally includes multiple memory components 107 for each control component 105, wherein each memory component is implemented in a corresponding integrated circuit chip. For example, in the case of a modular memory system, multiple memory components 107 can be arranged side by side on a memory module substrate (i.e., a daughterboard substrate having printed traces extending from module contacts to the memory components, and thus allowing removable insertion into a module connector on a main board or backplane), wherein each memory component is coupled to the control component via a corresponding data signal link (and data timing link) set and a shared command / address path, so that these multiple memory components can operate in lockstep (simultaneous and parallel data transfer to / from the memory column) as a memory column. Multiple memory columns can be implemented on the same memory module (e.g., at least one column on each side of a dual in-line memory module, or multiple columns on each module side in the case of a stacked package of memory components). In yet other embodiments, capacity expansion from one column to two columns (or one column set to two column sets) can be achieved via a master-slave stack, wherein the initial "master" memory module is connected to the control component interface via a point-to-point signaling link as discussed above, and is connected to the "slave" memory module of capacity expansion separately. That is, the memory components in the slave memory module are connected to the corresponding interface on the master memory module (i.e., the master memory module used as an intermediary for signals to and from the host component) via a point-to-point signaling link through a pre-processed protocol, wherein multi-mode data transmission is performed between the master module memory component and the slave module memory component according to the operation mode based on gating and the continuous clocking operation mode discussed herein. In all cases, the memory module can include a registered clock driver (RCD) or other command / address buffer components, and a data buffer component, which together with the memory and the control component are converted between the low-power signaling mode and the enhanced bandwidth signaling mode. More specifically, the various mode-specific circuits and multi-mode data transmissions discussed in the memory component embodiments herein are also applicable to the data buffer component. Further, although memory system operations (e.g., transaction protocols and timing) are generally presented herein in the context of a memory component having a dynamic random access memory (DRAM) storage core, any feasible core storage technology may be deployed within such a memory component (e.g., static random access memory, flash memory, phase change memory, magnetoresistive memory, etc.).

[0017] Still reference Figure 1, in the low power mode shown at 101, data transfers are timed by a source synchronous strobe signal. That is, the strobe signal from the data transfer component (in the depicted write data example, a center eye aligned write data strobe from the control component 105 to the memory component 107) is triggered with a predetermined phase relationship to the data signal and resides at a neutral voltage during idle periods (intervals without data transfer). The active edges in the otherwise resident timing strobe (marking the presence of valid data on the corresponding data path) are preceded and followed by preamble waveforms and postamble waveforms (i.e., protocol defined start / stop symbols) that increase signaling noise (particularly inter-symbol interference (ISI)) relative to a symbol-free free running clock, and thus typically limit the maximum signaling rate to a rate lower than that achievable with a free running clock. Thus, when bandwidth demand exceeds a given threshold, the memory system 100 may switch (autonomously or in response to a host command) from the low power strobe based data timing mode 101 to a high bandwidth continuously clocked data timing mode as shown at 103 (i.e., during the high bandwidth mode of operation, there are no dwells, preambles, or postambles in the data timing signals). Figure 1 In the example of FIG. 1 , the data strobe (during data transfer in low power mode 101) cycles at the system clock rate to provide a clock signal for each system clock cycle (t Ck ) to time the transmission of two consecutive data bits per link (i.e., one bit per rising strobe edge and one bit per falling strobe edge). In contrast, a free-running “data clock” Ck The 4x boost mode example shown at 103 (i.e., each t Ck The data transfer rate is 4x (four times) that of low power mode, where data is transmitted at a given t Ck The data is transmitted on each of the eight data clock edges (rising and falling) within the interval, that is, each t Ck 8 data bits per link instead of every t in low power mode Ck In contrast to the idle strobe in low power mode 101 (the strobe that resides during the idle, no data transmission interval 112), the free running (continuously triggered) data clock continues to cycle during the idle interval, thereby eliminating the preamble waveform / postamble waveform, thus avoiding signal degradation ISI. Figure 1In the example of , when bandwidth demand drops below a mode transition threshold (which may be hysteretic), the memory system 100 autonomously or in response to a host instruction switches back to the low power mode to limit power consumption. As discussed below, other factors besides bandwidth demand may influence the transition between the low power mode of operation and the high bandwidth mode of operation (e.g., an indication that the host system is operating at line power and / or above or below thermal limits).

[0018] Figure 2 Picture shows Figure 1 Additional signaling details in the low power bandwidth mode and the boosted bandwidth mode are shown. In both modes, memory access commands and corresponding memory addresses (collectively referred to as "CA values") are transmitted from the control component to one or more memory components via a command / address signaling link (CA) synchronously with respect to the system clock signal (which itself is transmitted from the control component to the memory component via a clock link Ck). Referring first to the low power mode timing diagram 131, for example, a write command and associated address (collectively referred to as command / address value "WR1") are transmitted on the CA signaling path during a cycle of the system clock, followed by a strobe-timed data burst 133 on the bidirectional data path (DQ). As shown, (on the chip-to-chip data timing link T DQ 141 ) transitions from an idle state at 135 through a preamble phase at 137 prior to an active edge trigger that is used to time the memory side's reception of a serial 8-bit write data burst 133 (i.e., bits D0 through D8) on the corresponding DQ signaling path (i.e., write data reception within the memory component at the time indicated by the active strobe edge). After the data transfer, the strobe ends with a postamble 139 before returning to idle (i.e., residing at a predetermined voltage level) at 141. Shortly thereafter, a memory read command / address value "RD1" is transmitted on the CA signaling path to trigger the memory side read data acquisition and strobe-timed read data transfer. That is, the memory component responds to the RD1 command / address value by: retrieving data from the core storage location indicated by the RD1 address (which address may correspond to the location of a data column within an "activated" data page in the DRAM component); and then transmitting (i) the read data retrieved in one or more serial bit streams 145 (Q0 to Q7) to the control component via a corresponding data signaling link, and (ii) a read data select signal having a predetermined phase alignment with the serial data burst (e.g., a select edge aligned with the edge of the read data "eye" as shown) to the control component.

[0019] Referring now to the boosted bandwidth waveform shown at 151, write command / address values ​​WR1 and WR2 are transmitted from the control component to the memory component in consecutive system clock cycles, followed by corresponding consecutive clocked data bursts at 161 and 163, which are also clocked in parallel (via timing link T DQ Transmitted) free-running write data clock Ck W Synchronous transmission of data bursts, the Ck W Continuing with the exemplary 4x bandwidth increase discussed above, each of the 8-bit write data bursts 161, 163 is cycled at a single t Ck interval (although not necessarily aligned with the system clock edge start / stop), so that within one quarter of the time required for the 8-bit strobe-timed data burst (i.e., each boost pattern bit interval t bit-HBM is the low bandwidth mode bit time t bit-LPM One quarter of t Ck The back-to-back read command / address values ​​RD1 and RD2 are also transmitted to the memory components in consecutive clock cycles and cause 4x accelerated read data bursts 171, 173, which are synchronized with the internally generated read clock (Ck R ) arrives at the control component in alignment, and this internally generated read clock also oscillates at 4x the frequency relative to the system clock.

[0020] As discussed below, transmitting the boosted-mode write clock to the memory component provides the memory-side timing edges required for boosted-mode read data transfers, where Ck is generated by the controller. R The return read data timing signal transmission (from the memory component to the control component) is eliminated. More specifically, in several embodiments, the control component internally generates the boost mode read clock (Ck R ) and phase it to align with the eye center of the incoming read data. In other embodiments, the memory component can steer the incoming boost mode write data clock so that the clock is transmitted back to the control component for use as the boost mode read data clock. Further, although a 4x bandwidth boost is performed in the example presented below, in all cases, the bandwidth and / or signaling rate may be increased by a factor greater than or less than 4. In addition, although the selection between the boost bandwidth operating mode and the low power operating mode is generally presented as a binary conversion from one bandwidth to another, multiple scales of bandwidth modes can be selected (e.g., 2x, 4x, 8x, 16x, and non-power-of-two bandwidth boost factors).

[0021] Figure 3 An embodiment of a memory system 200 is shown in the figure, wherein a control unit 201 and a memory unit 203 of the memory system 200 are capable of Figure 1 and Figure 2 As shown, the control unit 201 includes a control unit 202 that generates a high-speed clock signal (Ck HS ) of the clock generator 211, divides the high-speed clock signal to generate a system clock signal (Ck S ) and a strobe mask circuit 215 that generates a data strobe signal (Str) in response to the system clock signal (i.e., enforcing the preamble / postamble / idle protocol discussed above). The system clock signal is forwarded (transmitted) to the memory components via a signal driver 217 and a system clock link (CK), and is also supplied to a phase adjustment circuit 2191 to generate a command / address clock signal (Ck CA ), the command / address clock signal (Ck CA ) is a phase-adjusted version of the system clock signal (i.e., S Clock signals with the same frequency but with a phase shift). Ck CA The timing input of the command / address storage buffer 221 is then supplied to time the progress of command / address values ​​(received from the processor or other memory access request component of the host system) through the transaction queue therein, thereby controlling the timing of transmission of those command / address values ​​to the memory component 203 via the driver 223 and the command / address signaling link (CA).

[0022] continue Figure 3 , high-speed clock and data strobe signals (Ck HS and Str) are supplied to the corresponding inputs of the mode control multiplexer 225, which controls the mode control multiplexer 225 according to the boost mode signal or boost signal (in Figure 3 The mode control signal (shown as "boost") in FIG. 20 forwards one of the two timing signals to the phase adjustment circuits 2192 and 2193. The boost signal is asserted (e.g., to logic '1') to enable boost bandwidth operation (i.e., high bandwidth mode) and deasserted to enable low power operation, thereby configuring the multiplexer 225 to pass the high speed clock signal (boost = 1) or the strobe signal (boost = 0) to the phase adjustment circuits 2192 and 2193 accordingly. The phase adjustment circuit 2192 transmits the write data transfer signal (WD Tx) is supplied as a phase adjusted version of the multiplexer output to the double data rate timing input of the write data queue 227 to synchronously advance the write data values ​​(received from the processor or other components of the host system) therefrom for sequential output via the signal driver 229, and thus control the transmission timing of the write data values ​​via the data signaling link DQ to the memory component 203. The data within the write data queue 227 can be deserialized before being transmitted to the signal driver 229, so that the write data queue, which is wider than the DQ path, can be loaded with write data values ​​at a lower frequency. The phase adjustment circuit 2193 phase adjusts the timing signal (Ck) output by the multiplexer 225 according to the state of the boost signal. HS The phase adjusted version of the signal is supplied to the signal driver 231 via the data timing link T DQ Output as write data strobe signal (DQS W ) or write data clock signal (Ck W ) (ie, in either case, providing a write data timing signal that arrives at the memory component 203 in desired phase alignment with the write data transmitted via the DQ links).

[0023] During low power operation (boost = 0), read data arriving via the DQ link and signal buffer / amplifier 233 is accompanied by a signal on the data timing link (T DQ ) and conditioned within the buffer / amplifier 235. R The read data select signal propagates through multiplexer 237 (i.e., while boosting = 0 to achieve low power operating mode) and phase adjustment circuit 2194, which generates the read data sampling signal (RD Samp ), which times the double data rate read data sampling (and progression through it) within the read data queue 239 (i.e., captures or latches the read data arriving via the buffer / amplifier 233). During high bandwidth operation (boost = 1), multiplexer 237 converts the high speed clock (also referred to as the read data clock Ck) from the clock generator 211 to the read data queue 239. R ) is forwarded to the phase adjustment circuit 2194, which in turn outputs a continuously triggered (no preamble / postamble / idle) read data sampling signal (RD) with a desired phase alignment relative to the incoming read data (e.g., a clock edge centered within the corresponding read data eye). Samp), which continuously triggers the sampling of incoming data signals (e.g., transmitted at a 4x data rate relative to the low power mode) within the read data queue 239 and the progression of the sampled data therethrough. In either operating mode, high bandwidth or low power deserialization circuitry within the read data queue 239, which is wider than the DQ path, can assemble the continuously sampled read values ​​into a host-oriented read data value (i.e., a data value to be transmitted to a host processor or other host component).

[0024] although Figure 3 Although not specifically shown, data windowing circuitry may be provided within the write data queue 227 and the read data queue 239 to mask read data sampling signals (RD ) other than signals corresponding to valid read and write data transfer events. Samp ) and write data transfer signal (WD Tx ). In both continuous clocked data reception / transmission and gated timed data reception / transmission, for example, the control component can generate windowing signals (e.g., having a deterministic phase relationship with the command / address value transmitted to the memory component 203) supplied to the write and read data queues 227 and 239, respectively, to gate the incoming timing signals (WD Tx and RD Samp ) so that only the timing signal edges corresponding to valid data values ​​are applied to trigger data transmission / data sampling (e.g., masking the preamble / postamble transition of the data strobe signal in the data strobe operation mode, and masking the free-running clock signal Ck R and Ck W edge during the DQ idle interval in data clocked mode of operation).

[0025] Still reference Figure 3 , the memory component 203 includes a memory core 251, a command / address decoder 253 (i.e., a sampling and decoding circuit system), a clock tree 255, a gating mask circuit 257, write and read data queues 259 and 261, a mode control multiplexer 263, output drivers 271 and 273, and signal buffers / amplifiers 275, 277, 279, and 281. The incoming system clock (i.e., the incoming system clock that arrives via the clock link Ck and the buffer / amplifier 275) is propagated through the clock tree 255 to generate a plurality of phase-aligned memory clock signals (Ck Mem), these multiple phase-aligned memory clock signals are distributed to various other synchronous circuit elements, including command / address decoder 253, selection masking circuit 257, and read data queue 261 (i.e., as read data transfer timing signal RD) (via mode control multiplexer 263). Tx ). By using a phase-aligned clock signal Ck Mem The command / receive and read data transfers are timed and are also timed with Ck Mem (For example, the core clock generated in the clock tree is used as Ck Mem Frequency division example) phase-aligned core clock (Ck Mem / n) to time the operation in the memory core, and establishes (by Ck Mem The nominal unified timing domain defined by the edge. Since the incoming write data timing signal (i.e., via driver 231, link T DQ and Ck transmitted by buffer / amplifier 279 W ) is phase-adjusted in controller 201 so that WD Samp and RD Tx (the latter being selected via multiplexer 263 in response to assertion of the boost signal) is aligned with the memory clock signal so that the unified timing domain remains operational when transitioning to the boost bandwidth mode, the operation of which is discussed in more detail below. Like the corresponding data queues within control component 201, the memory-side data queues (259, 261) may include data windowing circuitry (circuitry controlled in a deterministic manner by command / address receiver-decoder 253 in response to incoming command / address values) for masking the write data sampling signal (WD Samp ) and read data transfer signal (RD Tx ) except those corresponding to valid write and read data transfer events.

[0026] In several embodiments, the clock generator 211 within the control component 201 is implemented by a phase-locked loop (PLL) or delay-locked loop (DLL) that phase-aligns a high-speed clock (and / or system clock) with a reference clock signal (not shown) that has a relatively stable frequency regardless of drifting (time-varying) system temperature and supply voltage. In contrast, the open-loop timing architecture within the memory component 203 permits the memory clock domain to drift with voltage and temperature relative to the system clock forwarded by the control component 201. In particular, the clock tree 255 (e.g., implemented by branches of inverters fanning out from a root to generate multiple memory clock instances with similar phase delays relative to the clock tree input) is often sensitive to temperature and voltage changes, so sensitive that the memory clock signal (CkMem ) may be relative to an incoming system clock (eg, a system clock instance Ck at the physical signaling interface of the memory component 203). PHY-M ) drift by 180°, 360°, or more, which means that the skew between the system clock and the memory clock may change by more than one or more bit times in low power mode and many bit times in high bandwidth mode.

[0027] exist Figure 3 In the embodiment of the present invention, the consequences of the time-varying skew between the system clock and the memory clock are compensated by phase adjustment circuits 2191 to 2194 within the control component 201 (an arrangement that avoids complex and power-consuming timing alignment circuitry in the memory component (which in most practical deployments is present in multiple instances in each control component instance)). More specifically, the phase adjustment circuit 2191 adjusts the command / address clock (Ck CA ) phase to time the command / address transmission so that the command / address value is nominally aligned with the memory clock domain (e.g., Ck Mem The phase adjustment circuits 2192 and 2193 adjust the write data transfer signal (WD Tx ) and write data timing signal (Ck W / DQS W ) to affect the write data and write data sampling signals (i.e., WD M and WD Samp Phase adjustment circuit 2194 implements equivalent control-side timing alignment for read data reception, that is, responding to a memory clock signal (low power mode) or a high-speed clock (boost mode, WD) aligned with the memory-side timing domain. Samp ), adjust the read data sampling signal (RD Samp ) phase to match the inbound (i.e., RD C As shown, the read data at the input of the read data queue 239 is aligned. More specifically, in low power mode, the phase adjustment circuit 2194 adjusts the incoming read data strobe DQS R The phase of (given the propagation time offset between these points in space, represented as DQS at the output of the strobe masking circuit 257) R-M , and at the output of the controller-side buffer amplifier 235 represented as DQS R-C ) to align with the incoming read data (RDC), and in high bandwidth mode, circuit 2194 adjusts the internally derived high-speed read clock Ck R (i.e., CkHS or its instance) so as to be in phase with RD C alignment.

[0028] Figure 4 Picture shows Figure 3 The unified memory clock domain (by Ck Mem ) and an exemplary time-varying phase offset between the timing signal generated within the control component. As shown, the system clock at the input of the control-side buffer / amplifier 223 (i.e., also shown in FIG. Figure 3 Ck shown S ) precedes the memory clock signal by the propagation time through the clock link CK (i.e., t Prop(Ck) ) plus the clock tree 255 (i.e., t Prop(Tree) ) propagation delay. In order to make the command / address value sampled by the memory clock signal at the center of the eye (i.e., as shown in 301), the CA transmission clock (Ck CA ) should be ahead of the memory clock signal (Ck Mem ) There is a command / address propagation delay t through the CA link Prop(CA) plus half the CA eye duration (i.e., half a system clock cycle or 0.5t in the low power mode example shown). Ck ). Therefore, the phase adjustment circuit 2191 is configured to S To Ck Mem Phase Lead and Expected Ck CA To Ck Mem The difference between the phase leads, or t Prop(Ck) +T Prop(Tree) –T Prop(CA) –0.5t Ck ( Figure 4 The system clock signal (Ck S ). It should be noted that the signal driver and buffer / amplifier pairing is part of two phase leads (i.e., 217 / 275 and 223 / 277) so that their nominally matched delay times cancel each other out.

[0029] Similarly, the phase adjustment circuit 2192 is configured to adjust the phase according to Ck S To Ck Mem Phase Leading vs. Expected WD Tx To Ck Mem The difference between the phase lead or t Prop(Ck) +t Prop(Tree) -T Prop(WD)-0.5*data-eye-width (ф2 phase delay) to delay the high-speed clock (or, depending on the operation mode, to delay the write data strobe). BIT ) changes between low power mode and bandwidth boost mode (e.g., 0.5t in the 4x bandwidth boost example) CK and 0.125t CK ), the half-eye delay term varies between these two operating modes, for example, changing to 0.25t Ck and 0.0625t Ck , such as the expression ф2 at 305 L and ф2 H Phase adjustment circuit 2193 implements substantially the same delay as circuit 2192, but compensates for the write timing signal propagation time (i.e., Ck W or DQS W The time t used to propagate to the memory control unit Prop(TDQ) ) rather than the write data propagation time, that is, a time-varying phase shift of ф3 is obtained. DQS W The propagation time may include the propagation delay caused within the gating masking logic 215, so that the expression φ3 at 305 is H and ф3 L As shown, the boost mode and low power mode phase delays implemented by phase adjustment circuit 2193 vary in compensating for propagation delay and half data eye offset.

[0030] Still reference Figure 4 The phase adjustment circuit 2194 needs to delay the reading of the data sampling signal (RD Samp ) to match the arrival of the read data queue (i.e., Figure 3 In low power mode (where the incoming read data strobe signal DQS R is delayed to generate a read data sampling signal), the phase delay (i.e., ф4 L ) is the sum of the system clock and clock tree propagation delay plus the read data propagation delay and the half-eye delay (0.5t Ck ) minus the propagation delay of the read data strobe signal—that is, (in the form of RD Samp )Incoming DQS R The signal is effectively shifted to align with the incoming read data eye center by a phase delay, as shown at 309. In the boost bandwidth mode (where a high speed clock is supplied to the 2194), the ф4 delay (ф4 H) is the sum of the system clock and clock tree propagation delays plus the read data propagation delay and half-eye delay referenced to the nearest system clock edge (i.e., 0.0625t in the 4x boost example Ck ). That is, ф4 H or ф4 L Or any other phase delay ф1 to ф3 exceeding one or more system clock cycles (or high-speed clock cycles) can be compensated by registering the subject timing signal in response to the clock signal to apply an integer number of full cycle delays.

[0031] Considering Figure 3 and Figure 4 The number of DQ links per corresponding data timing link may vary in different embodiments and / or programmed system configurations (e.g., each T DQ A timing link may have 1, 2, 4, 8, or more DQ links), and there may be any feasible number of DQ links / timing link groups within a given memory system implementation (e.g., 8 T DQ link, where each T DQ The links correspond to respective subsets of 8 DQ links within the total 64 DQ links. In several embodiments, each DQ link / timing link group is individually calibrated (e.g., with respective sets of ф1 to ф4 settings), and in still other embodiments, individual DQ links within a DQ link / timing link group are individually calibrated (e.g., generating a different phase delay ф2 for each DQ link to provide bit timing calibration for each bit). Such options and variations apply to all embodiments presented herein.

[0032] Figure 4 The propagation time differences and sums of the phase delays ф1 to ф4 shown can cover other voltage-dependent delay sources and temperature-dependent delay sources, including those through Figure 3 The propagation delays of the clock divider 213, multiplexing elements 225, 237, 263, and the gate masking circuits 215, 257 are shown, as well as the non-cancelling propagation delays through the signal receiver and buffer / amplifier pair. For example, in high bandwidth mode, CK R is delivered to the phase adjustment circuit 2194 without incurring driver or buffer / amplifier delays that would otherwise offset (match) the delay through the system clock driver-buffer pair (propagated through Figure 3 The elements 217 and 275 together cause δ trx ) or the delay of reading the data driver-buffer pair 273 / 233 (another δ trx , so there are 2δ trx ). Similarly, in low power mode, DQSR The propagation delay (at least nominally) offsets the read data driver-buffer delay (element 273 / 233), but does not offset the system clock driver-buffer delay (δ trx In various embodiments, all of these voltage / temperature dependent delays, along with clock tree delays (often dominated by voltage / temperature dependent delays), can be compensated by initiating a timing calibration operation and then tracking (and compensating) by periodic calibration operations that produce time-varying phase delays ф1 to ф4 within circuits 2191 to 2194 as needed to meet a desired timing alignment (e.g., as Figure 4 shown).

[0033] Initiating a timing calibration operation (i.e., a timing calibration after system power-up or reset before mission mode memory operations begin) can be implemented in a variety of ways, including memory-side loopback of a sampled signal (thereby enabling the control component to compare the transmitted value with the looped-back value while sweeping the phase of a given timing signal between a maximum phase delay setting and a minimum phase delay setting), returning the sampled signal or sampling error information through a verified low-speed signaling interface (e.g., a serial input / output interface for supporting chip-to-chip communication prior to the initial timing calibration), operating the memory-side receiver as an advance-retard phase detection element through a temporary control-side timing shift that nominally aligns the transmitted signal edge (e.g., a '101010...' oscillating signal) with the memory-side sampling edge, thereby enabling determination of early or late sampling of the transmitted signal (wherein such advance / retard information is returned to the controller to enable corresponding phase adjustments to be made), and so on. More generally, any feasible timing feedback arrangement may be employed within the various memory system embodiments herein to determine the initial phase offset to be applied within the phase adjustment circuits 2191 - 2194 for each system operating mode (low power and high bandwidth).

[0034] In several embodiments, one or more of the startup timing calibration operations may be repeated periodically (or aperiodically) after the mission mode is initiated (e.g., opportunistically when the timing path to be recalibrated is idle) - as frequently as necessary to limit the time-varying (temperature-dependent / voltage-dependent) timing skew to within a specified tolerance. In other embodiments, a dedicated or shared tracking signal path is provided between the memory component and the control component so that the memory component can return a tracking signal indicating the voltage / temperature-dependent delay common to all of the ф1 to ф4 phase offsets (or a subset thereof) discussed above. For example, referring to Figure 3, each of the phase adjustment circuits 2191 to 2194 can be programmed with an initial offset (or two mode-selectable offsets, where different offsets are applied to low power mode and high bandwidth mode), to which a time-varying delay (i.e., voltage-dependent / temperature-dependent delay) determined via a tracking signal is added - a low-overhead arrangement that enables the ф1 to ф4 delays applied by the phase adjustment circuits 2191 to 2194 to drift together in accordance with the time-varying temperature / voltage-induced delays indicated by the tracking signal.

[0035] Figure 5 With respect to the initial phase offset (i.e., offset1, offset2 determined at the start of timing calibration as discussed above), 2L , …, offset 4H ) and time drift voltage / temperature dependent delays reiterate Figure 4 The delay expression shown at 305 in FIG. 1 shows an embodiment of a delay tracking arrangement 350, which is used in Figure 3 The memory system is implemented to periodically (or aperiodically) adjust the ф1 to ф4 phase delays applied by the phase adjustment circuits 2191 to 2194 to compensate for the time-varying timing domain skew. In the depicted example, the phase delays ф1 to ф3 are based on the phase delays applied by the clock tree 255 (δ tree ) drifts with voltage / temperature-dependent changes in the propagation delay (positive or negative) of the 200MS / s (and is therefore updated periodically to reflect such voltage / temperature-dependent changes), while the phase delay ф4 includes an additional time-varying delay due to the uncompensated driver buffer delay as discussed above—δ in low-power mode trx , and 2δ in high bandwidth mode trx In alternative embodiments, other timing path specific delays may be compensated.

[0036] exist Figure 5 In the embodiment, the clock tree delay tracking (δ tree ) through the memory clock signal (Ck Mem ) is achieved via a return transmission of a signal link that is otherwise used to transmit error detection and correction information (EDC). That is, during periodic timing calibration events, multiplexer 351 is switched to transfer the memory clock signal (Ck Mem ) is driven back to the control unit (i.e., via driver 353, EDC / tracking link and buffer / amplifier 355) where the memory clock signal is supplied to delay tracking circuit 360 as feedback clock signal Ck FB The delay tracker 360 additionally receives a high speed clock signal (CkHS ) and a reference select signal (RefSel), which selects (via multiplexer 361) one of three different delayed instances of the high-speed clock as the reference clock (Ck Ref ) are supplied to delay generator 363. In the illustrated embodiment, three delayed instances of the high speed clock include: (i) a baseline reference clock 364, which is delayed by the propagation time through clock divider 213 (i.e., the delay modeled by element 365), thereby nominally canceling any time-varying phase delay introduced by clock divider 213; (ii) a driver / buffer reference clock 366, which is delayed relative to the baseline reference by the nominal propagation delay through the signal driver buffer / amplifier pair (modeled by delay element 367); and (iii) a dual driver / buffer reference clock 368, which is delayed relative to the baseline reference by the nominal propagation delay through the two signal driver buffer / amplifier pairs (modeled by delay elements 367 and 369).

[0037] The reference select signal RefSel is generated by calibration control circuitry within the control unit, which periodically and / or opportunistically enables the feedback clock (Ck FB ) is delivered to the delay tracker 360 (i.e., configures / commands the memory components to drive the memory clock onto the EDC / tracking link) and selects the three time-varying phase delay contributors (δ) to be calibrated during a given calibration sequence by virtue of the reference clock selection in the multiplexer 361. tree , δ tree +δ trx , or δ tree +2δ trx ) to update / adjust the time-varying phase delay contributor in the delay generator. The delay generator outputs digital delay values ​​corresponding to the three time-varying delays, thereby converting the delays corresponding to δ tree The corresponding delay value is supplied to the phase adjustment circuits 2191 to 2193, and is combined with δ tree +δ trx and δ tree +2δ trx The corresponding delay value is supplied to the phase adjustment circuit 2194 (i.e., according to Figure 5 As shown, each of the phase adjustment circuits 2192 to 2194 receives a boost mode signal to enable a mode specific phase delay based on a mode specific initial offset (2192 and 2193) and a mode specific initial offset and mode specific run time tracking delay (2194).

[0038] Figure 6 An embodiment of a phase adjustment circuit 400 is shown, which can be used to implement the following Figures 3 to 5 Phase adjustment circuit 2194 and phase offset φ4 are shown. In the depicted example, registers 401 and 403 store digital phase offset values ​​determined (and loaded into the subject registers) during initial calibration of read data timing for low power operating mode and high bandwidth operating mode, respectively. The contents of registers 401 and 403 are respectively compared with time-varying delay values ​​δ in summing circuits 405 and 407. tree +δ trx and δ tree +2δ trx Addition (i.e., as in e.g. Figure 5 The delay tracking circuit shown in FIG. 1 may be used to provide a digital delay control value PhCtl, or a digital representation of these values, to obtain a digital delay control value PhCtl. ф4L and PhCtl ф4H The delay control values ​​are then supplied to digitally controlled delay lines 409 and 411 to implement time-varying propagation delays through these delay lines, thereby generating DQS R and CK R The multiplexer 413 outputs (selects) two phase adjustment timing signal instances (i.e., DQS R +ф4 L or CK R +ф4 H ) (i.e., the output of delay line 409 if boost = 0, or the output of delay line 411 if boost = 1) as the read data sampling timing signal RD Samp .

[0039] In an alternative embodiment, the phase adjustment circuit 400 can be implemented using a single delay line (eg, 409), wherein the digital delay control value PhCtl ф4L and PhCtl ф4H is multiplexed (i.e., selected according to the state of the boost signal) to the delay control input of the delay line (eliminating the timing signal multiplexer 419 in favor of a control value multiplexer). In addition, instead of a delay line, a phase mixing circuit (potentially providing a finer delay granularity) may be provided to interpolate between phases of the system clock signal or high-speed clock signal. Further, the delay line itself may be subject to clock generation from a clock generator (e.g., Figure 3 and Figure 5211) of the element 211) (i.e., maintaining a relatively constant propagation delay in response to a given digital control value). For example, each delay line can be implemented by one or more current-starved inverter chains, where the delay through each inverter element is controlled by an inverter supply voltage generated within a phase-locked loop or delay-locked loop within the clock generator 211. More generally, in alternative embodiments, any feasible phase delay circuit (whether digitally controlled or analog voltage or current controlled) can be used to implement the phase adjustment circuit 400. Further, variations of the phase adjustment circuit 400 (however implemented) can be used to implement the phase adjustment circuits 2191 to 2193 discussed above. For example, in the implementation of the phase adjustment circuits 2192 and 2193, δ tree A value may be supplied to each of the summing circuits 405 and 407 , and a single summing circuit, offset register, and delay line (without a mode control multiplexer) may be sufficient to implement the phase adjustment circuit 2191 .

[0040] Figure 7 The diagram shows the Figure 5 4. As shown, the multi-phase reference clock (i.e. ... Figure 5 The multiplexer 361 in the embodiment of the present invention forwards the reference clock to the phase selector / mixer circuit 445, which selects and mixes adjacent phase pairs of the reference clock phases according to the digital phase word (PhWd) to generate a mixed-phase clock (Ck Mix In the particular embodiment shown, multiple reference clock phases are within the reference clock period (and thus are represented by Figure 3 and Figure 5 The phase word (PhWd) is equidistant from one another within a period of the high-speed clock signal generated by the clock generator 211 of the embodiment of the present invention—in this 8-clock phase example, the phases are spaced 45° apart within a 360° clock period. The three most significant bits of the phase word (PhWd) constitute a phase pair selector that selects one of eight phase-adjacent clock phase pairs (i.e., Ck0 / Ck45, Ck45 / Ck90, Ck90 / Ck135, ..., Ck270 / Ck315, or Ck315 / Ck0) within the phase selector / mixer 445, and the least significant N bits of the phase word form an interpolated value that also produces a weighted interpolation between (or mixing of) the selected clock phase pairs within the phase selector / mixer 445—thereby deriving a mixed-phase clock (Ck Mix ), where the phase offset is 2 relative to the leading clock phase within the selected pair PhWd[N-1:0] *45° / 2 N (where '*' represents multiplication and ' / ' represents division).

[0041] Still reference Figure 7 , mixed-phase clock and incoming feedback clock (Ck FB ) are supplied together to a phase detector 447 (e.g., a bang-bang phase detector, a ratio phase detector, etc.), which in turn generates a phase up signal / phase down signal depending on which of the phase detector inputs leads the other phase detector input. A reference select signal (RefSel, as discussed above) is supplied to multiplexers 449 and 450 to deliver the phase up signal / phase down signal (via multiplexer 449) to one of three digital counters 451, 453, or 455 (i.e., the "active" counter) depending on the delay value being adjusted, and to forward the output of the active counter (via multiplexer 450) as a digital phase word to the phase selector / mixer circuit 445. Thus, if the mixed-phase clock leads the feedback clock, the phase detector 447 will assert the phase up signal to increment the active counter (thereby incrementing the digital phase word supplied to the phase selector / mixer 445) so as to delay the mixed-phase clock by the phase step size (45° / 2 N ), so that when the interpolated value overflows, it overflows to the next more potential clock phase pair (i.e., the interpolated value overflows from 2 N -1 to 0). Conversely, if the mixed-phase clock lags behind the feedback clock, the phase detector 447 will assert the phase down signal to decrement the active counter, thereby advancing the mixed-phase clock by the phase step size, thereby underflowing to the next potentially lower clock phase pair when the interpolated value overflows. Thus, the delay generator iteratively adjusts the phase of the mixed-phase clock to align it with the feedback clock, thereby correspondingly updating the digital delay value (phase word) maintained in the counter - which can be used as a time-varying delay value (i.e., δ tree , δ tree +δ trx , δ tree +2δ trx ) and may be directly output or may be scaled, filtered and / or further processed to derive such a value (e.g., based on the phase selector / mixer circuit 445 and the reference Figure 6 Further, additional circuitry may be provided within the delay generator 441 to advance or delay the mixed-phase clock signal by an entire reference clock cycle, thereby providing a multi-cycle phase adjustment range.

[0042] Figure 8 An alternative embodiment of a memory system with bandwidth boost on demand is illustrated, which memory system operates in this case in a low power mode while communicating between the control component 481 and the memory component 483 via a separate (corresponding) signaling link (T WDand EDC / Trk / DQS R ) transmits read and write data strobe signals. Further, access to the read data strobe link is time division multiplexed within the memory component (multiplexer 485) to enable EDC data and / or feedback clock (tracking clock) transmission according to the operation commanded by the control component 481. As shown, the shared read data strobe link is coupled to the EDC circuitry 487 and delay tracking circuitry 489 within the memory component, and is also coupled to the read data strobe input of the multiplexer 237 (i.e., to provide a timing source for read data sampling during low power operation). Other circuitry may be provided within the control component and memory component as generally described above.

[0043] Fig. 9 Exemplary mode registers 501 and 503 are illustrated, which may be implemented within the various control component and memory component embodiments discussed above, respectively. In the depicted implementation, the mode register 501 (within the control component) includes a bandwidth mode field (HBM) and a transition control field (TC), the latter of which enables programmable selection of host-controlled or autonomous transitions between an increased bandwidth mode of operation and a low power mode of operation. More specifically, if a logic '0' is stored within the transition control field, the control component will statically operate in either a low power mode or a high bandwidth mode according to the value programmed within the bandwidth mode field, and therefore switch between the two modes in response to changes in the HBM field settings commanded by the host. In contrast, in the autonomous transition mode, the control component monitors the transaction queue (e.g., in reference to the TC field) to determine whether the host has switched to a higher power mode or a lower power mode. Figure 3The fill depth of the transaction queue (e.g., the offset between the pointers to the head and tail of the queue in a circular buffer implementation such as 523) is effectively indicative of the memory bandwidth requested by the host (i.e., fills to a greater depth as command / address values ​​accumulate within the queue 521, and shrinks to a shallower depth or zero depth as bandwidth demand decreases), and can therefore be used to trigger autonomous transitions between low-power and high-bandwidth modes of operation. In one embodiment, for example, a queue manager 525 within the command / address buffer 221 monitors the fill depth of the queue 521, thereby outputting a corresponding depth value to a comparator, which in turn raises or lowers a signal 528 depending on whether a threshold is exceeded. The mode transition threshold ("thresh") itself may be programmed within the control component's mode register 501 (or other storage device), and separate thresholds may be provided for transitions to and from the boost bandwidth mode (i.e., separate thresholds for establishing hysteresis transitions into and out of the boost mode to avoid rapid bouncing back and forth between the two operating modes). In the depicted example, a multiplexer 529 selects either the output of the threshold comparator 527 or the value programmed within the HBM field of the mode register 501 - depending on the value programmed within the TC field of the mode register 501 - to drive the boost signal to other circuitry within the control component (e.g., as discussed above). In one embodiment, the control component responds to a transition in the boost signal (which indicates a transition between a low power mode of operation and a high bandwidth mode of operation) by issuing a mode register program command to the memory component (along with the value to be programmed within the mode register), thereby slaving the operating mode of the memory component to the operating mode of the control component.

[0044] Fig.10A memory system transition from low power mode to high bandwidth mode and then back to low power mode is illustrated, showing exemplary command write data and write data timing signals during the mode transition. As shown, while the system is operating in low power mode, a write command / address (WR1) is transmitted to the memory component via the CA link, causing the write data strobe to transition from idle to preamble to active edge triggered phase (followed by postamble) in a short period of time, where the active edge specifies the memory side data sampling time of the serial data values ​​D0 to D7 within the burst 541. At 543, the memory system begins to transition (autonomously or in response to a host command) from low power mode to boost mode, shortly thereafter issuing a mode register program command (MRS) to the memory component. It should be noted that the low-to-high transition of the boost signal (i.e., from low power mode to high bandwidth mode) may be delayed until after the low power data burst ends (or the mode register transition may be delayed until all low power timing edges have been applied). In any case, link T DQ The timing signal on 545 changes seamlessly (without runt pulses or other glitches) from strobe to high speed clock (optionally truncating the DQS post-lead at 545), thereby preparing for the boost mode (high bandwidth) write data transfer in response to write commands WR2, WR3 and WR4 (triggering high speed data transfers at 551, 553 and 555). At 563, the system returns to low power mode, thereby again issuing a mode register programming command to the memory component and changing the write data timing signal from the free running high speed clock to the resident data strobe. As with the transfer from low power mode to high bandwidth mode, the transition of the boost signal can be postponed until the last of the high bandwidth data transfer operations ends (or an additional delay can be enforced to provide time for such end before the mode transition). In any case, after transitioning back to low power mode, the write command (WR5) triggers the strobe timing write data transfer at 571.

[0045] The various circuits and component architectures disclosed herein may be described using computer-aided design tools and expressed (or represented) in terms of their behavior, register transfers, logic components, transistors, layout geometry, and / or other characteristics as data and / or instructions embodied in various computer-readable media. The formats of files and other objects that may implement such circuit representations include, but are not limited to, formats that support behavioral languages ​​such as C, Verilog, and VHDL, formats that support register-level description languages ​​such as RTL, and formats that support geometry description languages ​​such as GDSII, GDSIII, GDSIV, CIF, MEBES, and any other suitable formats and languages. Computer-readable media in which such formatted data and / or instructions may be embodied include, but are not limited to, various forms of computer storage media (e.g., optical, magnetic, or semiconductor storage media, whether independently distributed in this manner or stored "in situ" in an operating system).

[0046] When received within a computer system via one or more computer-readable media, such data and / or instruction-based representations of the circuits described above can be processed by a processing entity (e.g., one or more processors) within the computer system in conjunction with the execution of one or more other computer programs, including but not limited to netlist generation programs, placement and routing programs, etc., to generate a representation or image of the physical manifestation of such circuits. Such representations or images can thereafter be used in device fabrication, for example, by enabling the generation of one or more masks for forming various components of the circuits during device fabrication.

[0047] In the foregoing description and accompanying drawings, specific terms and accompanying drawings have been elaborated to provide a thorough understanding of the disclosed embodiments. In some instances, the terms and symbols may imply specific details that are not needed for practicing those embodiments. For example, any one of a specific number of bits, signal path width, signaling or operating frequency, bandwidth ratio, clock ratio, signaling protocol, etc. can be different from the specific number of bits, signal path width, signaling or operating frequency, bandwidth ratio, clock ratio, signaling protocol, etc. described above in alternative embodiments. Additionally, the link or other interconnection between an integrated circuit device or an internal circuit element or a block can be shown as a bus or a single signal line. Each bus in a bus can alternatively be a single signal line, and each of a single signal line can alternatively be a bus. However, the signal and signaling link shown or described can be driven using a single-ended signal or a differential signal. Integrated circuit device "programming" may include, for example, but not limited to: loading control values ​​into registers or other storage circuits within the integrated circuit device in response to host instructions (and thereby controlling operational aspects of the device and / or establishing a device configuration), or by a one-time programming operation (e.g., blowing fuses within a configuration circuit during device production), and / or connecting one or more selected pins or other contact structures of the device to a reference voltage line (also referred to as strapping) to establish a specific device configuration or operational aspect of the device. When a signal driver circuit asserts (or if explicitly stated or indicated by the context, deasserts) a signal on a signal line coupled between the signal driver circuit and the signal receiving circuit, the signal driver circuit is said to "output" a signal to the signal receiving circuit. The term "coupled" is used herein to express direct connection as well as connection through one or more intermediate circuits or structures. The terms "exemplary" and "embodiment" are used to express examples, not preferences or requirements. In addition, the terms "may" and "can" are used interchangeably to indicate optional (permitted) subject matter. The absence of any term should not be interpreted as meaning that a given feature or technology is required.

[0048] Various modifications and changes may be made to the embodiments presented herein without departing from the broader spirit and scope of the present disclosure. For example, the features or aspects of any of the embodiments may be applied in combination with any other embodiment or replace the corresponding features or aspects thereof. Thus, the description and drawings are to be regarded as illustrative rather than restrictive.

Claims

1. An integrated circuit memory component (memory IC), comprising: Clock input, used to receive a clock signal; Programmable registers; a command interface for receiving a register programming command in synchronization with the clock signal and storing a control value specifying one of a plurality of operating modes in the programmable register in response to the register programming command; and Synchronous data interface for: If the control value specifies a first operating mode, sampling the write data signal in the first mode to generate a first number of write data bits per cycle of the clock signal; if the control value specifies a second operating mode, sampling the write data signal in the second mode to generate a second number of write data bits per cycle of the clock signal, wherein the second number of data bits exceeds the first number of data bits; as well as A read data signal is transmitted in synchronization with the clock signal.

2. A memory IC according to claim 1, wherein the control value specifying one of the multiple operating modes is composed of a single bit, and when the single bit is in one of two logical states, the first operating mode is specified, and when the single bit is in the other of the two logical states, the second operating mode is specified.

3. The memory IC of claim 1, wherein the second number of data bits is at least twice the first number of data bits.

4. The memory IC of claim 1 further comprising circuitry for generating divided-down instances of the clock signal, and a memory core having circuitry that is clocked by the divided-down instances of the clock signal.

5. The memory IC of claim 4 , wherein the circuitry clocked by the divided instances of the clock signal includes circuitry for transmitting the write data bits from the synchronous data interface to a memory cell array within the memory core, wherein the write data bits are generated by sampling the write data signal in either the first mode or the second mode.

6. The memory IC of claim 5, wherein the memory core is a dynamic random access memory (DRAM) core and the memory cell array comprises a DRAM cell array.

7. The memory IC of claim 1, wherein the clock signal comprises a differential clock signal and the clock input for receiving the clock signal comprises a differential input.

8. The memory IC of claim 1 further comprising a circuit system for generating a divided-down instance of the clock signal, and wherein the command interface for receiving the register programming command in synchronization with the clock signal comprises a circuit system sample signal transmitted via a command / address signaling link at a time indicated by the divided-down instance of the clock signal.

9. The memory IC of claim 8, wherein the divided instance of the clock signal cycles once every N clock signal cycles, where N is an integer equal to or greater than four.

10. The memory IC of claim 1 wherein the command interface includes circuitry to: receiving a memory write command and a memory read command at different times; In response to receiving the memory write command, asserting a first control signal to enable the synchronous data interface to sample the write data signal; and In response to receiving the memory read command, a second control signal is asserted to enable the synchronous data interface to transmit the read data signal.

11. A method of operating in an integrated circuit memory component (memory IC), the method comprising: receiving a clock signal via a clock input; receiving, via a command interface, a register programming command synchronized with the clock signal; storing a control value in a programmable register in response to the register programming command, the control value specifying one of a plurality of operating modes; and If the control value specifies a first operating mode, sampling a write data signal received via the synchronous data interface in the first mode to generate a first number of write data bits per cycle of the clock signal; if the control value specifies a second operating mode, sampling the write data signal in the second mode to generate a second number of write data bits per cycle of the clock signal, the second number of data bits exceeding the first number of data bits; and A read data signal is transmitted via the synchronous data interface in synchronization with the clock signal.

12. The method of claim 11 , wherein the control value specifying one of the plurality of operating modes is comprised of a single bit, the single bit specifying the first operating mode when in one of two logical states, and specifying the second operating mode when in the other of the two logical states.

13. The method of claim 11, wherein the second number of data bits is at least twice the first number of data bits.

14. The method of claim 11, further comprising generating divided instances of the clock signal to clock circuitry within a memory core of the memory IC.

15. The method of claim 11, wherein generating the divided-down instance of the clock signal to clock circuitry within the memory core comprises clock circuitry that transmits the write data bits from the synchronous data interface to a memory cell array within the memory core, wherein the write data bits are generated by sampling the write data signal in either the first mode or the second mode.

16. The method of claim 15, wherein the memory core is a dynamic random access memory (DRAM) core and the memory cell array comprises a DRAM cell array.

17. The method of claim 11, wherein receiving the clock signal via the clock input comprises receiving a differential clock signal via a differential input.

18. The method of claim 11 further comprising generating a divided-down instance of the clock signal, and wherein receiving the register programming command synchronously with the clock signal comprises sampling a signal transmitted via a command / address signaling link at a time indicated by the divided-down instance of the clock signal.

19. The method of claim 18, wherein the frequency division instance of the clock signal cycles once every N clock signal cycles, where N is an integer equal to or greater than four.

20. The method according to claim 11, further comprising: receiving a memory write command and a memory read command via the command interface at corresponding times; in response to receiving the memory write command, asserting a first control signal to enable sampling of the write data signal received via the synchronous data interface; and In response to receiving the memory read command, a second control signal is asserted to enable transmission of the read data signal via the synchronous data interface.

21. An integrated circuit memory component (memory IC), comprising: Programmable registers; means for receiving a clock signal; means for receiving a register programming command synchronously with said clock signal and storing in said programmable register a control value specifying one of a plurality of operating modes in response to said register programming command; and Synchronous data interface with: means for sampling the write data signal in a first mode to generate a first number of write data bits per cycle of the clock signal if the control value specifies a first mode of operation; means for sampling the write data signal in a second mode to generate a second number of write data bits per cycle of the clock signal if the control value specifies a second mode of operation, wherein the second number of data bits exceeds the first number of data bits; as well as means for transmitting a read data signal synchronously with said clock signal.

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