Control circuit and memory

Abstract

This disclosure relates to the field of semiconductor circuit design, and particularly to a control circuit and a memory. The control circuit includes: a first signal conditioning circuit for receiving a first identification signal and a second identification signal output from a mode register of the memory; the first identification signal is used to indicate whether the memory enables Terminal Data strobing (TDQS) function, and the memory performs the terminal data strobing function based on the valid first identification signal; the second identification signal is used to indicate whether the memory enables Data Masking (DM) function, and the memory performs the data masking function based on the valid second identification signal; the first signal conditioning circuit is configured to mask the valid second identification signal based on the valid first identification signal, and adjust the indication signal output from the mode register to avoid conflict between the enabling of the memory's TDQS function and DM function.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor circuit design, and in particular to a control circuit and a memory. Background Technology

[0002] With the development of integrated circuits, the density of integrated circuits is getting higher and higher, and the speed is getting faster and faster. For Dynamic Random Access Memory (DRAM), the circuit complexity is increasing rapidly, and the memory capacity is getting larger and larger.

[0003] For DRAM, there are a large number of memory chips, and the data bit width (including x16bit, x8bit, x4bit, etc.) of different memory chips may be different. The DRAM termination data strobe function (TDQS function) can terminate memory chips with different bit widths, thereby ensuring the load balance of the data strobe signal line.

[0004] However, in DDR3 or DDR4, the TDQS function of the memory can only be enabled in x8bit mode. In DDR3 or DDR4, the TDQS function and the DM function [Input Data Mask when writing to memory, when the DM is high, the corresponding data will be masked or blocked and will not be written] share a pin, and there may be a conflict between enabling the TDQS function and the DM function. Summary of the Invention

[0005] This disclosure provides a control circuit and a memory that adjusts the indication signal output by the mode register to avoid conflict between the activation of the memory's TDQS function and DM function.

[0006] One embodiment of this disclosure provides a control circuit, including: a first signal conditioning circuit, configured to receive a first identification signal and a second identification signal output from a mode register based on a memory; the first identification signal is used to indicate whether the memory starts a Terminal Data Strobe (TDQS) function, and the memory performs the Terminal Data Strobe function based on a valid first identification signal; the second identification signal is used to indicate whether the memory starts a Data Mask (DM) function, and the memory performs the Data Mask function based on a valid second identification signal; the first signal conditioning circuit is configured to mask a valid second identification signal based on a valid first identification signal.

[0007] The control circuit provided in this embodiment adjusts the first and second identifier signals output by the mode register to avoid the first and second identifier signals being effective at the same time, thereby avoiding the conflict between the activation of the memory's TDQS function and DM function.

[0008] Optionally, the control circuit further includes: a second signal conditioning circuit for receiving the first bit width identifier signal and the second bit width identifier signal of the memory; the second signal conditioning circuit is configured to mask the first identifier signal based on an invalid first bit width identifier signal and to mask the second identifier signal based on an invalid second bit width identifier signal.

[0009] Optionally, the first bit-width identifier signal includes an x4 identifier signal and an x16 identifier signal, the second bit-width identifier signal includes an x4 identifier signal, and the second signal conditioning circuit includes: a first inverter, the input of which is used to receive the x4 identifier signal; a second inverter, the input of which is used to receive the x16 identifier signal; a first AND logic circuit, the first input of which is connected to the output of the first inverter, the second input of which is connected to the output of the second inverter, the third input of which is used to receive the first identifier signal, and the output of which is used to output the conditioned first identifier signal; a third inverter, the input of which is used to receive the x4 identifier signal; and a second AND logic circuit, the first input of which is connected to the output of the third inverter, the second input of which is used to receive the second identifier signal, and the output of which is used to output the conditioned second identifier signal.

[0010] Optionally, the first signal conditioning circuit includes: a fourth inverter, the input of which is used to receive a second identification signal; a first NOR logic circuit, the first input of which is connected to the output of the fourth inverter, and the second input of which is used to receive the first identification signal; and a third AND logic circuit, the first input of which is connected to the output of the first NOR logic circuit, the second input of which is used to receive a write enable signal, and the output of which is used to output the conditioned second identification signal.

[0011] Optionally, the output terminal of the first signal conditioning circuit is connected to the input terminal of the second signal conditioning circuit.

[0012] Optionally, the output terminal of the second signal conditioning circuit is connected to the input terminal of the first signal conditioning circuit.

[0013] Optionally, the control circuit further includes: a signal generation circuit configured to generate a selection signal, a configuration signal, and a clock signal based on a control command; and a mode control circuit that receives the selection signal, the configuration signal, and the clock signal and is configured to select a target mode register from multiple mode registers based on the selection signal, wherein the target mode register completes signal configuration based on the configuration signal and the clock signal.

[0014] Optionally, the mode control circuit includes: multiple mode registers and a selection decoder; the selection decoder is configured to generate a selection enable signal based on a selection signal, and the selection enable signal corresponds one-to-one with a mode register; the mode register selected by the selection enable signal completes signal configuration based on a configuration signal and a clock signal.

[0015] Optionally, the mode control circuit further includes: a fourth AND logic circuit, with a first input terminal for receiving a selection enable signal, a second input terminal for receiving a clock signal, and an output terminal for outputting a selection clock signal; and a first D flip-flop, with an input terminal for receiving the configuration value of the mode register, a clock terminal for receiving the selection clock signal, and an output terminal connected to the mode register.

[0016] Optionally, the signal generation circuit includes: a command decoding circuit configured to decode a control command to obtain a configuration control signal, an initial configuration signal, and an initial selection signal; and a configuration control circuit configured to generate a clock signal based on the configuration control signal, sample the initial configuration signal based on the clock signal to obtain a configuration signal, and sample the initial selection signal based on the clock signal to obtain a selection signal.

[0017] Optionally, the command decoding circuit is further configured to decode the control command to obtain a configuration masking signal, which is used to mask the configuration control signal.

[0018] Optionally, the configuration control circuit includes: a first delay unit, with its input terminal for receiving a configuration control signal; a fifth inverter, with its input terminal for receiving a configuration shield signal; a NAND logic circuit, with its first input terminal for receiving the configuration control signal and its second input terminal connected to the output terminal of the fifth inverter; a sixth inverter, with its input terminal connected to the output terminal of the NAND logic circuit; a second D flip-flop, with its input terminal connected to the output terminal of the fifth inverter, its inverted clock terminal connected to the output terminal of the first delay unit, and its output terminal for outputting a clock signal; a second delay unit, with its input terminal connected to the output terminal of the second D flip-flop; a seventh inverter, with its input terminal connected to the output terminal of the second delay unit; and a third D flip-flop, with its input terminal for receiving an initial selection signal and its clock terminal connected to... The output of the NAND logic circuit has its inverted clock terminal connected to the output of the sixth inverter; the fourth D flip-flop has its input connected to the inverted output of the third D flip-flop, its clock terminal connected to the output of the sixth inverter, and its inverted clock terminal connected to the output of the NAND logic circuit, with the inverted output terminal used to output a selection signal; the fifth D flip-flop has its input used to receive the initial configuration signal, its clock terminal connected to the output of the second delay unit, and its inverted clock terminal connected to the output of the seventh inverter; the sixth D flip-flop has its input connected to the inverted output of the fifth D flip-flop, its clock terminal connected to the output of the seventh inverter, and its inverted clock terminal connected to the output of the second delay unit, with the inverted output terminal used to output a configuration signal.

[0019] Another embodiment of this disclosure also provides a memory including the control circuit provided in the above embodiments, which adjusts the indication signal output by the mode register to avoid the activation conflict between the memory's TDQS function and DM function. Attached Figure Description

[0020] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or in the conventional art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the structure of a control circuit for priority shielding provided in an embodiment of the present disclosure;

[0022] Figure 2 A schematic diagram illustrating the timing control principle for priority masking provided in an embodiment of this disclosure;

[0023] Figure 3 This is a schematic diagram of the structure of a second signal conditioning circuit provided in one embodiment of the present disclosure;

[0024] Figure 4 This is a schematic diagram of another second signal conditioning circuit provided in an embodiment of the present disclosure;

[0025] Figure 5 This is a schematic diagram of the structure of a first signal conditioning circuit provided in an embodiment of the present disclosure;

[0026] Figure 6 A schematic diagram illustrating the principle of application scenario shielding provided in an embodiment of this disclosure;

[0027] Figure 7 A schematic diagram of a control circuit that performs application scenario masking first and priority masking second, according to an embodiment of this disclosure;

[0028] Figure 8 This is a schematic diagram illustrating the principle of performing application scenario masking first and priority masking second, as provided in an embodiment of this disclosure.

[0029] Figure 9 A schematic diagram of a control circuit that performs priority masking first and then application scenario masking according to an embodiment of this disclosure;

[0030] Figure 10 This is a schematic diagram illustrating the principle of performing priority masking first and then application scenario masking according to an embodiment of this disclosure;

[0031] Figure 11 A schematic diagram of a control circuit structure including a signal generation circuit and a mode control circuit is provided for an embodiment of this disclosure;

[0032] Figure 12 This is a schematic diagram of the structure of a signal generation circuit provided in an embodiment of the present disclosure;

[0033] Figure 13 This is a schematic diagram of the structure of a mode control circuit provided in an embodiment of the present disclosure. Detailed Implementation

[0034] As is known from the background technology, in DDR3 or DDR4, the TDQS function and the DM function share a single pin, and there may be a conflict in enabling the TDQS function and the DM function in the memory.

[0035] One embodiment of this disclosure provides a control circuit that adjusts the indication signal output by the mode register to avoid a conflict between the activation of the TDQS function and the DM function of the memory.

[0036] It will be understood by those skilled in the art that many technical details have been provided in the various embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments. The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of this disclosure. The various embodiments can be combined with and referenced by each other without contradiction.

[0037] Figure 1 This is a schematic diagram of the control circuit for priority masking provided in an embodiment of the present disclosure. Figure 2 This is a schematic diagram illustrating the timing control principle for priority masking according to an embodiment of the present disclosure. Figure 3 This is a schematic diagram of the structure of a second signal conditioning circuit according to an embodiment of the present disclosure. Figure 4 This is a schematic diagram of another second signal conditioning circuit provided in an embodiment of the present disclosure. Figure 5 This is a schematic diagram of the structure of a first signal conditioning circuit provided in an embodiment of the present disclosure. Figure 6 This is a schematic diagram illustrating the principle of application scenario shielding provided in one embodiment of this disclosure. Figure 7 This is a schematic diagram of the control circuit that performs application scenario masking first and priority masking second, as provided in this embodiment. Figure 8 This is a schematic diagram illustrating the principle of performing application scenario masking first and priority masking second, as provided in an embodiment of this disclosure. Figure 9 This is a schematic diagram of the control circuit that performs priority masking first and then application scenario masking in this embodiment. Figure 10 This is a schematic diagram illustrating the principle of performing priority masking first and then application scenario masking according to an embodiment of this disclosure. Figure 11This is a schematic diagram of a control circuit structure including a signal generation circuit and a mode control circuit, provided in an embodiment of the present disclosure. Figure 12 This is a schematic diagram of the structure of a signal generation circuit provided in an embodiment of the present disclosure. Figure 13 This is a schematic diagram of a mode control circuit provided in an embodiment of the present disclosure. The control circuit provided in this embodiment will be described in detail below with reference to the accompanying drawings:

[0038] It should be noted that the descriptions of various signals in this disclosure use the terms "valid" or "invalid". In the description of this embodiment, "valid" means that the corresponding signal is at a high level, i.e., data "1"; "invalid" means that the corresponding signal is at a low level, i.e., data "0". In specific applications, an inverter can be introduced at the appropriate location in the control circuit so that "valid" means that the corresponding signal is at a low level and "invalid" means that the corresponding signal is at a high level. In addition, since "invalid" means that the corresponding signal is at a low level, in the description of this embodiment, outputting an invalid signal can be regarded as not outputting the corresponding signal.

[0039] For the memory, the control of TDQS and DM functions is achieved through relevant parameters in the mode register. Specifically, the memory changes MR5_OP by encoding the MRW command. <4> The value controls whether the TDQS function is enabled or disabled, and is changed by encoding the MRW command. <5> The value controls whether the DM function is enabled or disabled. Of course, the above encoding command MRW can also be configured to control the implementation of DM and TDQS by changing the values ​​of other specific mode registers.

[0040] In one example, if MR5_OP in the mode register <4> = "1", the mode register outputs the relevant and valid indicator signal to instruct the memory to enable the TDQS function; if MR5_OP <4> If the value is set to "0", the mode register will output a relevant and invalid indicator signal to instruct the memory to disable the TDQS function.

[0041] It should be noted that, in the following description of this embodiment, unless otherwise indicated, the first identification signal output by the mode register is used to indicate whether the memory enables or disables the TDQS function; specifically, the memory performs the TDQS function based on a valid first identification signal.

[0042] In one example, if MR5_OP in the mode register <5> = "1", the mode register outputs the relevant and valid indicator signal to indicate that the memory enables the DM function; if MR5_OP <5> If the value is set to "0", the mode register will output a relevant and invalid indicator signal to instruct the memory to disable the DM function.

[0043] It should be noted that, in the following description of this embodiment, unless otherwise indicated, the second identification signal output by the mode register is used to indicate whether the memory enables or disables the DM function; specifically, the memory performs the DM function based on a valid second identification signal.

[0044] However, as mentioned above, the TDQS and DM functions of the memory share a single pin, meaning that the TDQS and DM functions of the memory cannot be enabled simultaneously. When the first and second identifier signals output by the mode register are both valid, the activation of the TDQS and DM functions of the memory will conflict.

[0045] The control circuit provided in this embodiment adjusts the first and second identifier signals output by the mode register to avoid the first and second identifier signals being effective simultaneously, thereby avoiding the conflict between the activation of the TDQS function and the DM function of the memory. In addition, the adjustment logic of the first and second identifier signals by the control circuit provided in this embodiment matches the activation logic of the mode register for the TDQS function and the DM function.

[0046] Regarding the enabling logic of the mode register for the TDQS and DM functions, as mentioned above, the mode register MR5 controls whether the TDQS function is enabled through the value of OP4 and whether the DM function is enabled through the value of OP5. Under normal operation, OP5 can only be configured to "1" when OP4 = "0". That is, the memory can only enable the DM function if the TDQS function is not enabled. In other words, the priority of the memory's TDQS function is higher than the priority of the DM function.

[0047] In this regard, refer to Figure 1 The control circuit provided in this embodiment includes: a first signal conditioning circuit 101, used to receive a first identification signal and a second identification signal, wherein the first signal conditioning circuit 101 is configured to shield a valid second identification signal based on a valid first identification signal.

[0048] For the adjustment logic of the control circuit for the first and second identifier signals, refer to... Figure 2When the effective times of the first and second identifier signals partially or completely overlap, the activation of the memory's TDQS and DM functions conflicts. In this case, the memory uses the effective first identifier signal to mask the effective second identifier signal, allowing the memory to perform the TDQS function. The effective second identifier signal is only enabled when the first identifier signal is invalid. When the effective times of the first and second identifier signals do not affect each other, that is, when the effective times of the first and second identifier signals are staggered, the activation of the memory's TDQS and DM functions does not conflict, and the effective times of the first and second identifier signals do not affect each other. The memory performs its operation by adjusting the first and second identifier signals through the control circuit, ensuring normal operation of the memory while avoiding the scenario of conflict between the activation of the memory's TDQS and DM functions.

[0049] In some embodiments, the control circuit further includes a second signal conditioning circuit 102, configured to receive a first bit width identifier signal and a second bit width identifier signal from the memory. The second signal conditioning circuit 102 is configured to mask the first identifier signal based on an invalid first bit width identifier signal, and to mask the second identifier signal based on an invalid second bit width identifier signal.

[0050] Specifically, refer to Figure 3 The second signal conditioning circuit 102 receives the first identifier signal and the first bit width identifier signal through the first AND gate 201, thereby achieving the shielding of the first identifier signal based on the first bit width identifier signal; similarly, the second signal conditioning circuit 102 receives the second identifier signal and the second bit width identifier signal through the second AND gate 202, thereby achieving the shielding of the second identifier signal based on the second bit width identifier signal.

[0051] In other words, when the first wide identifier signal is valid, the second signal conditioning circuit 102 outputs the first identifier signal normally, and when the second wide identifier signal is valid, the second signal conditioning circuit 102 outputs the second identifier signal normally. By limiting the validity time of the first identifier signal through the first wide identifier signal and the validity time of the second identifier signal through the second wide identifier signal, the erroneous activation of the DM function of the memory's TDQS function is avoided.

[0052] In some embodiments, the first wide identifier signal and the second wide identifier signal may include the same identifier signal; for example, both the TDQS function and the DM function of the memory can be started in x8-bit mode, meaning that both the first wide identifier signal and the second wide identifier signal can include the identifier signal corresponding to the x8-bit mode. Alternatively, in some embodiments, the first wide identifier signal and the second wide identifier signal may include different identifier signals; for example, the TDQS function of the memory can be started in x8-bit mode, and the DM function of the memory can be started in x16-bit mode, meaning the first wide identifier signal includes the identifier signal corresponding to the x8-bit mode, and the second wide identifier signal includes the identifier signal corresponding to the x16-bit mode, i.e., the identifier signals included in the first wide identifier signal and the second wide identifier signal are different. Similarly, in some embodiments, the first wide identifier signal or the second wide identifier signal may include multiple identifier signals; for example, the DM function of the memory can be started in both x8-bit mode and x16-bit mode, meaning the second wide identifier signal includes the identifier signals corresponding to both x8-bit mode and x16-bit mode.

[0053] It should be noted that the purpose of introducing the first wide identifier signal and the second wide identifier signal in this embodiment is to disable the effective enabling of the TDQS function or the DM function. As for the specific content of the first wide identifier signal and the second wide identifier signal, this embodiment does not limit it. Those skilled in the art can obtain the signal content of the first wide identifier signal and the second wide identifier signal based on the driving mode of the TDQS function and the DM function in the applied memory.

[0054] In some embodiments, the bit width identifier signal can be received via an inverter, in which case the second signal conditioning circuit 102 is configured to mask the first identifier signal and the second identifier signal when the corresponding bit width output mode is used.

[0055] As is known from the background technology, in DDR3 or DDR4, the TDQS function of the memory can only be enabled in x8-bit mode; correspondingly, in DDR3 or DDR4, the DM function of the memory can only be enabled in x8-bit and x16-bit modes. In other words, the memory needs to mask the first identification signal in x4-bit and x16-bit modes to prevent the TDQS function from being erroneously enabled, and the memory needs to mask the second identification signal in x4-bit mode to prevent the DM function from being erroneously enabled.

[0056] refer to Figure 4 and Figure 5The first bit width identifier signal includes an x4 identifier signal and an x16 identifier signal. The second bit width identifier signal includes an x4 identifier signal, where the x4 identifier signal is used to indicate that the memory is in x4-bit mode, the x8 identifier signal is used to indicate that the memory is in x8-bit mode, and the x16 identifier signal is used to indicate that the memory is in x16-bit mode. The second signal conditioning circuit 102 includes: a first inverter 310, whose input terminal is used to receive the x4 identifier signal; a second inverter 320, whose input terminal is used to receive the x16 identifier signal; a first AND logic circuit 301, whose first input terminal is connected to the output terminal of the first inverter 310, whose second input terminal is connected to the output terminal of the second inverter, whose third input terminal is used to receive the first identifier signal, and whose output terminal is used to output the conditioned first identifier signal; a third inverter 330, whose input terminal is used to receive the x4 identifier signal; and a second AND logic circuit 302, whose first input terminal is connected to the output terminal of the third inverter 330, whose second input terminal is used to receive the second identifier signal, and whose output terminal is used to output the conditioned second identifier signal.

[0057] Specifically, when the memory is in x4-bit mode, the x4 identifier signal is valid. After being inverted by the first inverter 310 or the third inverter 330, the outputs of the first inverter 310 and the third inverter 330 are low. For the first AND logic circuit 301 and the second AND logic circuit 302, their outputs are low, thus enabling both the valid first identifier signal and the valid second identifier signal. When the memory is in x16-bit mode, the x16 identifier signal is valid. After being inverted by the second inverter 320, the output of the second inverter 320 is low. For the first AND logic circuit 301, its output is low, thus enabling the valid first identifier signal.

[0058] It should be noted that, Figure 4 In the circuit structure of the second signal conditioning circuit 102 shown, the first inverter 310 and the third inverter 330 have the same function. In some embodiments, the first inverter 310 and the third inverter 330 can be implemented based on the same inverter.

[0059] In some embodiments, reference Figure 5 The first signal conditioning circuit 101 includes: a fourth inverter 403, the input of which is used to receive a second identification signal; a first NOR logic circuit 401, the first input of which is connected to the output of the fourth inverter 403, and the second input of which is used to receive the first identification signal; and a third AND logic circuit 402, the first input of which is connected to the output of the first NOR logic circuit 401, the second input of which is used to receive an output enable signal DQ_Enable, and the output of which is used to output the conditioned second identification signal.

[0060] Specifically, as is known from the background technology, the DM function of a memory is the input data mask when writing to memory. When the DM accompanying the writing to memory is high, the corresponding data will be masked or blocked and will not be written. Therefore, the DM function of the memory needs to be combined with the writing function. In this embodiment, the write enable signal DQ_Enable is used to control the writing function of the memory. The third logic circuit 402 combines the effective write enable signal DQ_Enable and the high level output of the first NOR logic circuit 401 to generate an effective second identification signal to enable the DM function of the memory. For the first NOR logic circuit 401, the output is high only when all inputs are low. At this time, the first identification signal is low and the second identification signal is high. When the first identification signal is high, the output of the first NOR logic circuit 401 is low, and the first signal conditioning circuit 102 cannot generate an effective second identification signal, thereby achieving the shielding of the second identification signal based on the effective first identification signal.

[0061] As can be seen from the preceding text, the first signal conditioning circuit 101 sets the shielding logic according to the priority of the first identification signal and the second identification signal, and the second signal conditioning circuit 102 sets the shielding logic according to the usage scenario of the first identification signal and the second identification signal. Different connection relationships between the first signal conditioning circuit 101 and the second signal conditioning circuit 102 may result in different output results.

[0062] In some embodiments, reference Figure 7 and Figure 8 The output of the second signal conditioning circuit 102 is connected to the input of the first signal conditioning circuit 101, meaning the control circuit first performs application scenario masking and then priority masking; in some embodiments, refer to Figure 9 and Figure 10 The output terminal of the first signal conditioning circuit 101 is connected to the input terminal of the second signal conditioning circuit 102, that is, the control circuit first performs priority masking and then performs application scenario masking.

[0063] refer to Figure 7 and Figure 8 The first identification signal and the second identification signal are indication signals output by the mode register. The first identification signal-1 and the second identification signal-2 are the output results after adjustment based on the second signal adjustment circuit 102, and the second identification signal-2 are the output results after adjustment based on the first signal adjustment circuit 101. The first identification signal-1 and the second identification signal-2 are used to indicate whether the memory enables the TDQS function and the DM function.

[0064] Specifically, ideally, assuming the memory operates in x4-bit mode (i.e., when the x4 identifier signal is valid), if both the first and second identifier signals are valid simultaneously, the memory neither enables TDQS nor DM functions. When both the first and second identifier signals output by the mode register are valid, the application scenario shielding of the second signal conditioning circuit 102 renders both the first and second identifier signals output by the second signal conditioning circuit 102 invalid, as expected. Assuming the memory operates in x8-bit mode (i.e., when the x8 identifier signal is valid), if both the first and second identifier signals are valid simultaneously, the memory only enables TDQS. When both the first and second identifier signals output by the mode register are valid, the application scenario shielding of the second signal conditioning circuit 102 renders both the first and second identifier signals output by the second signal conditioning circuit 102 valid. However, due to priority shielding by the first signal conditioning circuit 101, the second identifier signal output by the first signal conditioning circuit 101 is invalid, as expected. Assuming the memory operates in x16-bit mode, i.e., when the x16 identifier signal is valid, when both the first and second identifier signals are valid, the memory only enables the DM function. When both the first and second identifier signals output by the mode register are valid, the first identifier signal output by the second signal conditioning circuit 102 is invalid after the application scenario shielding of the second signal conditioning circuit 102. After the priority shielding of the first signal conditioning circuit 101, the second identifier signal output by the first signal conditioning circuit 101 is valid, which is as expected.

[0065] refer to Figure 9 and Figure 10 The first and second identification signals are indication signals output by the mode register. The second identification signal-3 is the output result after adjustment based on the first signal adjustment circuit 101. The first and second identification signals-4 are the output results after adjustment based on the second signal adjustment circuit 102. The first and second identification signals-4 are used to indicate whether the memory enables the TDQS and DM functions.

[0066] Specifically, ideally, assuming the memory operates in x4-bit mode (i.e., when the x4 identifier signal is valid), if both the first and second identifier signals are valid simultaneously, the memory neither enables TDQS nor DM functions. When both the first and second identifier signals output by the mode register are valid, the second identifier signal output by the first signal conditioning circuit 101 is invalidated after priority masking by the first signal conditioning circuit 101. Then, after application scenario masking by the second signal conditioning circuit 102, the first identifier signal output by the second signal conditioning circuit 102 is invalid, which is as expected. Assuming the memory operates in x8-bit mode (i.e., when the x8 identifier signal is valid), if both the first and second identifier signals are valid simultaneously, the memory only enables TDQS. When both the first and second identifier signals output by the mode register are valid, the second identifier signal output by the first signal conditioning circuit 101 is invalidated after priority masking by the first signal conditioning circuit 101. Then, after application scenario masking by the second signal conditioning circuit 102, the first identifier signal output by the second signal conditioning circuit 102 is valid, which is as expected. Assuming the memory operates in x16-bit mode, i.e., when the x16 identifier signal is valid, when the first identifier signal and the second identifier signal are both valid, the memory only enables the DM function. When the first identifier signal and the second identifier signal output by the mode register are both valid, after priority masking by the first signal conditioning circuit 101, the second identifier signal output by the first signal conditioning circuit 101 is invalid. Then, after application scenario masking by the second signal conditioning circuit 101, the second identifier signal output by the second signal conditioning circuit 102 is invalid, which does not meet expectations.

[0067] The above analysis shows that both circuits have certain applicability, whether the priority masking logic is executed first or the application scenario masking logic is executed first. However, the logic of executing the application scenario masking logic first and then the priority masking logic has a wider range of applicability.

[0068] In some embodiments, reference Figure 11 The control circuit also includes a signal generation circuit 501 and a mode control circuit 502.

[0069] Specifically, the signal generation circuit 501 is configured to generate a selection signal, a configuration signal, and a clock signal based on the control command MRW. The control command, issued by the memory controller, includes signals such as PCLK_E / O, CS_n, and CA. The selection signal MRAB<7:0> generated by the signal generation circuit 501 is used to select a target mode register from multiple mode registers in the memory. The configuration signal OPB<7:0> and the clock signal MRW_CLK are used to configure the selected target mode register. For example, configuring the specific values ​​of OP0 to OP7 in mode register MR5. The mode control circuit 502 receives the selection signal, configuration signal, and clock signal, and is configured to select a target mode register from multiple mode registers based on the selection signal. The target mode register completes signal configuration based on the configuration signal and the clock signal.

[0070] Continue to refer Figure 11 In some embodiments, the signal generation circuit 501 includes a command decoding circuit 511 and a configuration control circuit 521. The command decoding circuit 511 is configured to decode a control command to obtain a configuration control signal MRW_CMD, an initial configuration signal OP<7:0>, and an initial selection signal MRA<7:0>. The configuration control circuit 521 is configured to generate a clock signal MRW_CLK based on the configuration control signal MRW_CMD, sample the initial configuration signal OP<7:0> based on the clock signal MRW_CLK to obtain a configuration signal OPB<7:0>, and sample the initial selection signal based on the clock signal MRW_CLK to obtain a selection signal MRAB<7:0>.

[0071] In some embodiments, the command decoding circuit 511 is further configured to decode the control command to obtain a configuration masking signal CW, which is used to mask the configuration control signal MRW_CMD; specifically, when the configuration masking signal CW is valid, the configuration control signal MRW_CMD is masked.

[0072] refer to Figure 12In some embodiments, the configuration control circuit 521 includes: a first delay unit 701, whose input is used to receive a configuration control signal MRW_CMD; a fifth inverter 801, whose input is used to receive a configuration shield signal CW; a NAND logic circuit 702, whose first input is used to receive the configuration control signal MRW_CMD, and whose second input is connected to the output of the fifth inverter 801; a sixth inverter 802, whose input is connected to the output of the NAND logic circuit; a second D flip-flop 703, whose input is connected to the output of the fifth inverter 801, whose inverted clock input is connected to the output of the first delay unit 801, and whose output is used to output a clock signal MRW_CLK; a second delay unit 704, whose input is connected to the output of the second D flip-flop 703; a seventh inverter 808, whose input is connected to the output of the second delay unit 704; and a third D flip-flop 705, whose input is used to receive an initial selection signal. The first D flip-flop, MRA<7:0>, has its clock input connected to the output of the NAND logic circuit 702, and its inverted clock input connected to the output of the sixth inverter 802. The fourth D flip-flop, 706, has its input connected to the inverted output of the third D flip-flop 705, its clock input connected to the output of the sixth inverter 802, and its inverted clock input connected to the output of the NAND logic circuit 702. Its inverted output is used to output the selection signal MRAB<7:0>. The fifth D flip-flop, 707, has its input used to receive the initial configuration signal OP<7:0>, its clock input connected to the output of the second delay unit 704, and its inverted clock input connected to the output of the seventh inverter 803. The sixth D flip-flop, 708, has its input connected to the inverted output of the fifth D flip-flop 707, its clock input connected to the output of the seventh inverter 803, and its inverted clock input connected to the output of the second delay unit 704. Its inverted output is used to output the configuration signal OPAB<7:0>.

[0073] The first delay unit 701 is used to delay the effective level of the configuration control signal MRW_CMD. The fifth inverter 801 is used to generate the inverted configuration mask signal CWB. The input terminal of the NAND logic circuit 702 is used to receive the configuration control signal MRW_CMD and the inverted configuration mask signal CWB. The output terminal is connected to the clock terminal CK and the inverted clock terminal CKB of the third D flip-flop 705 and the fourth D flip-flop 706. When the configuration control signal MRW_CMD is valid and the configuration mask signal CW is invalid, the NAND logic circuit 702 outputs a low level based on the valid configuration control signal MRW_CMD and the inverted configuration mask signal CWB. At this time, MRSB is low and MRSD is high. The third D flip-flop 705 and the fourth D flip-flop 706 sample the initial selection signal MRA<7:0> based on MRSB and MRSD to obtain the selection signal MRAB<7:0>. Similarly, the second D flip-flop 703 generates a clock signal MRW_CLK based on the inverted configuration mask signal CWB and the configuration control signal MRW_CMD. After delaying and inverting the clock signal MRW_CLK, it generates MRWB and MRWD. When the configuration control signal MRW_CMD is valid and the configuration mask signal CW is invalid, the clock signal MRW_CLK sampled by the second D flip-flop 703 is valid. At this time, MRWB is high and MRWD is low. The fifth D flip-flop 707 and the sixth D flip-flop 708 sample the initial configuration signal OP<7:0> based on MRWB and MRWD to configure the signal OPB<7:0>.

[0074] In some embodiments, reference Figure 11 The mode control circuit 502 includes multiple mode registers 522 (MR0 to MRn) and a selection decoder 512. The selection decoder 512 is configured to generate a selection enable signal based on the selection signal MRAB<7:0>. The selection enable signal corresponds one-to-one with the mode register and is used to select the target mode register 522 among the multiple mode registers 522 for enabling. The mode register 522 selected by the selection enable signal completes signal configuration based on the configuration signal OPB<7:0> and the clock signal MRW_CLK.

[0075] In some embodiments, reference Figure 13 The mode control circuit 502 further includes: a fourth AND logic circuit 601, whose first input is used to receive a selection enable signal, whose second input is used to receive a clock signal MRW_CLK, and whose output is used to output a selection enable signal; and a first D flip-flop 602, whose input is used to receive the configuration value of the mode register, whose clock is used to receive the selection clock signal, and whose output is used to connect to the mode register.

[0076] Specifically, for mode register MR5, the configuration signals OPB<7:0> include the configuration value OP. <0> ~OP <7> OP <0> ~OP <7> MR5_OP is used to configure the mode register MR5. <0> ~MR5_OP <7> For example, when OP <4> When = 1, it is used to set MR5_OP in the mode register MR5. <4> Set to 1.

[0077] The control circuit provided in this embodiment adjusts the first and second identifier signals output by the mode register to avoid the first and second identifier signals being effective at the same time, thereby avoiding the conflict between the activation of the memory's TDQS function and DM function.

[0078] It should be noted that the features disclosed in the control circuit provided in the above embodiments can be arbitrarily combined without conflict to obtain new control circuit embodiments.

[0079] Another embodiment of this disclosure provides a memory including the control circuit provided in the above embodiments, which adjusts the indication signal output by the mode register to avoid conflict between the activation of the memory's TDQS function and DM function.

[0080] For the adjustment logic of the control circuit for the first and second identifier signals, refer to... Figure 2 When the effective times of the first and second identifier signals partially or completely overlap, the activation of the memory's TDQS and DM functions conflicts. In this case, the memory uses the effective first identifier signal to mask the effective second identifier signal, allowing the memory to perform the TDQS function. The effective second identifier signal is only enabled when the first identifier signal is invalid. When the effective times of the first and second identifier signals do not affect each other, that is, when the effective times of the first and second identifier signals are staggered, the activation of the memory's TDQS and DM functions does not conflict, and the effective times of the first and second identifier signals do not affect each other. The memory performs its operation by adjusting the first and second identifier signals through the control circuit, ensuring normal operation of the memory while avoiding the scenario of conflict between the activation of the memory's TDQS and DM functions.

[0081] In some examples, memory can be a storage cell or device based on a semiconductor device or component. For example, a memory device can be volatile memory, such as Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate Synchronous Dynamic Random Access Memory (LPDDR SDRAM), Graphics Double Data Rate Synchronous Dynamic Random Access Memory (GDDR SDRAM), Double Data Rate Type Dual Synchronous Dynamic Random Access Memory (DDR2 SDRAM), Double Data Rate Type Triple Synchronous Dynamic Random Access Memory (DDR3 SDRAM), Double Data Rate Type Fourth Generation Synchronous Dynamic Random Access Memory (DDR4 SDRAM), Thyristor Random Access Memory (TRAM), etc.; or it can be non-volatile memory, such as Phase Change Random Access Memory (PRAM), Magnetic Random Access Memory (MRAM), Resistive Random Access Memory (RRAM), etc.

[0082] Those skilled in the art will understand that the above embodiments are specific embodiments for implementing the present disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the present disclosure.

Claims

1. A control circuit, characterized in that, include: A first signal conditioning circuit is used to receive a first identification signal and a second identification signal output from a memory-based mode register; The first identification signal is used to indicate whether the memory starts the Terminal Data Steering (TDQS) function, and the memory performs the Terminal Data Steering function based on the valid first identification signal; The second identification signal is used to indicate whether the memory enables the data masking (DM) function, and the memory performs the data masking function based on a valid second identification signal; The first signal conditioning circuit is configured to mask a valid second identification signal based on a valid first identification signal; A second signal conditioning circuit is configured to receive a first bit width identifier signal of the memory, the first bit width identifier signal including at least an x16 identifier signal; the second signal conditioning circuit is configured to mask the first identifier signal based on an invalid first bit width identifier signal; the output of the second signal conditioning circuit is connected to the input of the first signal conditioning circuit.

2. The control circuit according to claim 1, characterized in that, The second signal conditioning circuit is also used to receive the second bit-width identifier signal of the memory, wherein; The second signal conditioning circuit is further configured to mask the second identifier signal based on an invalid second bit-width identifier signal.

3. The control circuit according to claim 2, characterized in that, The first bit-width identifier signal further includes an x4 identifier signal, the second bit-width identifier signal includes the x4 identifier signal, and the second signal conditioning circuit includes: The first inverter has its input terminal used to receive the x4 identification signal; The second inverter has its input terminal used to receive the x16 identifier signal; The first AND logic circuit has a first input terminal connected to the output terminal of the first inverter, a second input terminal connected to the output terminal of the second inverter, a third input terminal for receiving the first identification signal, and an output terminal for outputting the adjusted first identification signal. The third inverter has its input terminal used to receive the x4 identification signal; The second AND logic circuit has a first input terminal connected to the output terminal of the third inverter, a second input terminal for receiving the second identification signal, and an output terminal for outputting the adjusted second identification signal.

4. The control circuit according to claim 1, characterized in that, The first signal conditioning circuit includes: The fourth inverter has its input terminal used to receive the second identification signal; The first NOR logic circuit has a first input terminal connected to the output terminal of the fourth inverter, and a second input terminal used to receive the first identification signal. The third AND logic circuit has a first input terminal connected to the output terminal of the first OR logic circuit, a second input terminal for receiving a write enable signal, and an output terminal for outputting the adjusted second identification signal.

5. The control circuit according to claim 1, characterized in that, Also includes: The signal generation circuit is configured to generate a selection signal, a configuration signal, and a clock signal based on control commands. The mode control circuit receives the selection signal, the configuration signal, and the clock signal, and is configured to select a target mode register from multiple mode registers based on the selection signal, wherein the target mode register completes signal configuration based on the configuration signal and the clock signal.

6. The control circuit according to claim 5, characterized in that, The mode control circuit includes: Multiple mode registers, and a selection decoder; The selection decoder is configured to decode and generate a selection enable signal based on the selection signal, and the selection enable signal corresponds one-to-one with the mode register; The mode register selected by the selected enable signal completes signal configuration based on the configuration signal and the clock signal.

7. The control circuit according to claim 6, characterized in that, The mode control circuit further includes: The fourth logic circuit has a first input terminal for receiving the selected enable signal, a second input terminal for receiving the clock signal, and an output terminal for outputting the selected clock signal. The first D flip-flop has an input terminal for receiving the configuration value of the mode register, a clock terminal for receiving the selected clock signal, and an output terminal connected to the mode register.

8. The control circuit according to claim 5, characterized in that, The signal generation circuit includes: The command decoding circuit is configured to decode the control command to obtain a configuration control signal, an initial configuration signal, and an initial selection signal. The configuration control circuit is configured to generate the clock signal based on the configuration control signal, sample the initial configuration signal based on the clock signal to obtain the configuration signal, and sample the initial selection signal based on the clock signal to obtain the selection signal.

9. The control circuit according to claim 8, characterized in that, The command decoding circuit is further configured to decode the control command to obtain a configuration masking signal, which is used to mask the configuration control signal.

10. The control circuit according to claim 9, characterized in that, The configuration control circuit includes: The first delay unit has an input terminal used to receive the configuration control signal; The fifth inverter has its input terminal used to receive the configured shielding signal; The NAND logic circuit has a first input terminal for receiving the configuration control signal and a second input terminal connected to the output terminal of the fifth inverter. The sixth inverter has its input connected to the output of the NAND logic circuit; The second D flip-flop has its input terminal connected to the output terminal of the fifth inverter, its inverted clock terminal connected to the output terminal of the first delay unit, and its output terminal used to output a clock signal. The second delay unit has its input connected to the output of the second D flip-flop. The seventh inverter has its input connected to the output of the second delay unit; The third D flip-flop has an input terminal for receiving the initial selection signal, a clock terminal connected to the output terminal of the NAND logic circuit, and an inverted clock terminal connected to the output terminal of the sixth inverter. The fourth D flip-flop has its input connected to the inverted output of the third D flip-flop, its clock input connected to the output of the sixth inverter, its inverted clock input connected to the output of the NAND logic circuit, and its inverted output used to output the selection signal. The fifth D flip-flop has its input terminal used to receive the initial configuration signal, its clock terminal connected to the output terminal of the second delay unit, and its inverting clock terminal connected to the output terminal of the seventh inverter. The sixth D flip-flop has its input terminal connected to the inverted output terminal of the fifth D flip-flop, its clock terminal connected to the output terminal of the seventh inverter, its inverted clock terminal connected to the output terminal of the second delay unit, and its inverted output terminal used to output the configuration signal.

11. A memory, characterized in that, Includes the control circuit described in any one of claims 1 to 10.

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