Semiconductor device related to generation of internal commands

Abstract

The invention relates to a semiconductor device related to generating internal commands. The semiconductor device may include: a jump-out control circuit configured to select one of a plurality of jump signals as a selection jump signal in response to a test mode signal, and generate a jump-out signal in response to the selection jump signal; a mode control circuit configured to generate a mode signal to change the mode in response to the jump-out signal until a preset final mode is entered; and a command control circuit configured to generate an internal command for each mode in response to the mode signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0139063, filed on October 17, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor device related to generating an internal command. Background Art

[0004] Generally, a semiconductor device receives an external command through an external device such as a controller and performs internal operations such as an activation operation, a read operation, and a write operation. In order to perform a test to check whether the internal operation performed in the semiconductor device is correctly performed, the semiconductor device may receive an external command from a test device.

[0005] When there is a difference in the operating speeds of the semiconductor device and the test device, the semiconductor device may not be able to receive an external command from the test device and may need to generate an internal command for testing itself. Summary of the invention

[0006] According to an embodiment of the present disclosure, a semiconductor device may include: a jump exit control circuit, which is configured to set one of a plurality of jump signals as a selection jump signal in response to a test mode signal, and generate a jump exit signal in response to the selection jump signal; a mode control circuit, which is configured to generate a mode signal in response to the jump exit signal to change the mode until a preset final mode is entered; and a command control circuit, which is configured to generate an internal command for each mode in response to the mode signal.

[0007] According to an embodiment of the present disclosure, a semiconductor device may include: a jump control circuit configured to generate a command pulse and a plurality of jump signals in response to a jump exit signal; a mode control circuit configured to generate a mode signal in response to the jump exit signal to change a mode until a preset final mode is entered; and a command control circuit configured to generate an internal command for each mode in response to the command pulse and the mode signal. In the present disclosure, the jump exit signal may be generated in response to a selection jump signal, and the selection jump signal may be set to one of the plurality of jump signals in response to a test mode signal.

[0008] According to an embodiment of the present disclosure, a semiconductor device may include: a jump exit control circuit, configured to select one of a plurality of jump signals as a first selected jump signal in response to a first test mode signal in a first mode, and to generate a jump exit signal from the first selected jump signal in synchronization with a clock, the jump exit signal being activated to enter a second mode; a mode control circuit, configured to generate a first mode signal to enter the first mode when the jump exit signal is activated in an initial mode, and to generate a second mode signal to enter the second mode when the jump exit signal is activated in the first mode; and a command control circuit, configured to generate a first internal command in the first mode in response to the first mode signal, and to generate a second internal command in the second mode in response to the second mode signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram showing a configuration of a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 2 It shows that according to Figure 1 A block diagram showing a configuration of an embodiment of a clock control circuit included in a semiconductor device shown.

[0011] Figure 3 is based on Figure 2 A circuit diagram of an embodiment of a reset adjustment signal generating circuit is shown.

[0012] Figure 4 is based on Figure 2 A circuit diagram of an embodiment of a clock generation circuit is shown.

[0013] Figure 5 It shows that according to Figure 1 A block diagram showing a configuration of an embodiment of a skip control circuit included in a semiconductor device shown.

[0014] Figure 6 is based on Figure 5 A circuit diagram of an embodiment of a command pulse control circuit included in a skip control circuit is shown.

[0015] Figure 7 is based on Figure 5 A circuit diagram of an embodiment of a skip signal generating circuit included in a skip control circuit is shown.

[0016] Figure 8 is based on Figure 1 A circuit diagram of an embodiment of a skip exit control circuit included in a semiconductor device is shown.

[0017] Fig. 9 It shows that according to Figure 1FIG. 2 is a block diagram showing a configuration of an embodiment of a mode control circuit included in a semiconductor device shown in FIG.

[0018] Fig.10 is based on Fig. 9 The circuit diagram of an embodiment of a mode reset signal generating circuit and a mode change pulse generating circuit included in the mode control circuit shown.

[0019] Fig.11 is based on Fig. 9 A circuit diagram of an embodiment of a mode signal generating circuit included in a mode control circuit is shown.

[0020] Fig.12 It shows that according to Figure 1 A block diagram showing a configuration of an embodiment of a command control circuit included in a semiconductor device shown.

[0021] Fig.13 is based on Fig.12 A circuit diagram of an embodiment of an internal command generation circuit included in a command control circuit is shown.

[0022] Fig.14 is based on Fig.12 A circuit diagram of an embodiment of an end command generation circuit included in a command control circuit is shown.

[0023] Fig.15 It is shown Fig.14 The timing diagram of the operation of the end command generation circuit is shown.

[0024] Figures 16 to 21 It is shown Figures 1 to 15 A timing diagram of an internal command generation operation of a semiconductor device described in FIG.

[0025] Figures 22 to 33 It is shown Figures 1 to 15 A circuit diagram of an internal command generating operation of a semiconductor device described in FIG. DETAILED DESCRIPTION

[0026] In the description of the following embodiments, when a parameter is referred to as "predetermined", it may mean that the value of the parameter is determined in advance when the parameter is used in a process or algorithm. The value of the parameter may be set at the start of the process or algorithm, or may be set during the period of execution of the process or algorithm.

[0027] It will be understood that although the terms "first", "second", "third", etc. are used herein to describe multiple elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element and are not intended to imply the order or quantity of the elements. Therefore, the first element in some embodiments may be referred to as the second element in other embodiments without departing from the teachings of the present disclosure.

[0028] In addition, it will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be intervening elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0029] A logic "high" level and a logic "low" level can be used to describe the logic level of an electrical signal. A signal with a logic "high" level can be different from a signal with a logic "low" level. For example, when a signal with a first voltage corresponds to a signal with a logic "high" level, a signal with a second voltage can correspond to a signal with a logic "low" level. In an embodiment, a logic "high" level can be set to a voltage whose voltage level is higher than a logic "low" level. At the same time, the logic level of a signal can be set to be different or opposite according to the embodiment. For example, a signal with a logic "high" level in one embodiment can be set to have a logic "low" level in another embodiment.

[0030] The word "set" can be used as a noun as well as a verb. The Merriam-Webster Dictionary provides multiple definitions for the noun form of "set." It also provides several definitions for the verb form of "set." For the present disclosure, the noun form of "set" refers to "a plurality of things of the same kind belonging to or used together." For example, a group of eight binary digits constitutes a binary word.

[0031] As used herein, the verb form of "set" means to cause a particular value to assume. For example, when a binary number is set, its value is equal to a logical one or a logical zero. As used herein, the context in which "set" is used will determine whether "set" is used as a noun or a verb.

[0032] The term "logical bit group" may mean a combination of logic levels of bits included in a signal. When the logic level of each bit included in the signal changes, the logic bit group of the signal may be set differently. For example, when the signal includes two bits, if the logic levels of the two bits included in the signal are "logic low level, logic low level", the logic bit group of the signal may be set to a first logic bit group, that is, one or more binary values ​​are specified, and if the logic levels of the two bits included in the signal are "logic low level and logic high level", the logic bit group of the signal may be set to a second logic bit group.

[0033] Various embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. However, the embodiments described herein are only for illustrative purposes and are not intended to limit the scope of the present disclosure.

[0034] Figure 1 1 is a block diagram showing the configuration of a semiconductor device 1 according to an embodiment of the present disclosure. Figure 1 As shown, the semiconductor device 1 may include a clock control circuit (CLK CTR) 11 , a skip control circuit (SKIP CTR) 13 , a skip exit control circuit (SKIPEXIT CTR) 15 , a mode control circuit (MODE CTR) 17 , and a command control circuit (CMD CTR) 19 .

[0035] The clock control circuit 11 can generate a reset adjustment signal RST_REG, an inverted reset adjustment signal RST_REGB, a clock CLK, and an inverted clock CLKB in response to a start pulse STARTP input signal, an end command BIST_CTRL input signal, and a reset signal RST input signal. When at least one of the start pulse STARTP, the end command BIST_CTRL, and the reset signal RST is activated, the clock control circuit 11 can generate a reset adjustment signal RST_REG and an inverted reset adjustment signal RST_REGB. The start pulse STARTP can be activated to start a test mode for generating internal commands such as an activation command ACT, a column access (CAS) command CAS, a precharge command PCG, and an end command BIST_CTRL. The end command BIST_CTRL can be activated to terminate the test mode for generating internal commands ACT, CAS, PCG, and BIST_CTRL. The reset signal RST can be activated to perform an initialization operation of the semiconductor device 1. When the start pulse STARTP is activated to start the test mode, the clock control circuit 11 can generate a flipped clock CLK and an inverted clock CLKB. When the end command BIST_CTRL is activated to terminate the test mode or the reset signal RST is activated for the initialization operation, the clock control circuit 11 may generate the clock CLK and the inverted clock CLKB whose logic levels are fixed.

[0036] When the inverted skip exit signal SKIP_EXITB is activated, the skip control circuit 13 may generate an activated command pulse CMDP in synchronization with the clock CLK. After the inverted skip exit signal SKIP_EXITB is activated, the skip control circuit 13 may generate at least one skip signal SKIP including bits that are sequentially activated (e.g., set to logic 1). As described below, the skip signal SKIP may include a first skip signal SKIP1, a second skip signal SKIP2, a third skip signal SKIP3, a fourth skip signal SKIP4, and a fifth skip signal SKIP5 (e.g., Figure 7 ), but this is only an example and the present disclosure is not limited thereto.

[0037] The skip exit control circuit 15 may generate a skip setting signal (eg, Figure 8 In the present embodiment, the test mode signal TR_TM may include a first test mode signal TRCD_TM<0:2>, a second test mode signal TCCD_TM<0:2>, a third test mode signal TWR_TM<0:2>, and a fourth test mode signal TRP_TM<0:2>, but this is only an example and the present disclosure is not limited thereto. The jump exit control circuit 15 may respond to the mode signal MODE and the jump setting signal (e.g., Figure 8 TRCD, TCCD, TWR, and TRP) to generate a mode setting signal (e.g., Figure 8 ASYNC1 and ASYNC2) as intermediate signals to generate the inverted skip exit signal SKIP_EXITB. In the mode setting signal (for example, Figure 8 After ASYNC1 and ASYNC2 in the SKIP_EXIT control circuit 15 are activated for each mode, the skip exit control circuit 15 may generate an activated skip exit signal SKIP_EXIT and an inverted skip exit signal SKIP_EXITB in synchronization with the clock CLK. In an exemplary embodiment, the mode may include a plurality of operation modes, for example, at least one test mode and at least one activation mode, etc. In an exemplary embodiment, the mode may include a test mode and an activation mode, and the test mode and the activation mode include an initial mode and first to nth modes.

[0038] When one of the inverted reset signal RSTB and the end command BIST_CTRL is activated, the mode control circuit 17 can generate an initialized mode signal MODE. Whenever at least one of the jump exit signal SKIP_EXIT and the inverted jump exit signal SKIP_EXITB is activated, the mode control circuit 17 can generate the mode signal MODE to change the mode until the preset final mode is entered. For example, the jump exit signal SKIP_EXIT and the inverted jump exit signal SKIP_EXITB can be activated at different logic levels. When the jump exit signal SKIP_EXIT and the inverted jump exit signal SKIP_EXITB are activated after entering the preset final mode, the mode control circuit 17 can generate the mode signal MODE to maintain the mode.

[0039] The command control circuit 19 may generate an activation command ACT, a CAS command CAS, a precharge command PCG, and an end command BIST_CTRL in response to the command pulse CMDP and the mode signal MODE. The command control circuit 19 may generate an activated activation command ACT when entering the first mode in response to the mode signal MODE when the command pulse CMDP is activated. The command control circuit 19 may generate an activated CAS command when entering the second mode in response to the mode signal MODE when the command pulse CMDP is activated. The command control circuit 19 may generate an activated precharge command PCG when entering the fourth mode in response to the mode signal MODE when the command pulse CMDP is activated. When entering the fifth mode in response to the mode signal MODE when the command pulse CMDP is activated, the command control circuit 19 may generate an activated end command BIST_CTRL when a preset end delay section has passed after the end pulse ENDP is activated.

[0040] Figure 2 It shows that according to Figure 1 FIG. 1 is a block diagram showing a configuration of a clock control circuit 11A of an embodiment of the clock control circuit 11. Figure 2 As shown, the clock control circuit 11A may include a reset regulation signal generating circuit (RST_REG GEN) 111 and a clock generating circuit (CLK GEN) 113 .

[0041] The reset adjustment signal generating circuit 111 may generate a reset adjustment signal RST_REG and an inverted reset adjustment signal RST_REGB in response to a start pulse STARTP, an end command BIST_CTRL, and a reset signal RST. When at least one of the start pulse STARTP, the end command BIST_CTRL, and the reset signal RST is activated, the reset adjustment signal generating circuit 111 may generate an activated reset adjustment signal RST_REG and an inverted reset adjustment signal RST_REGB. The reset signal RST may be activated for use in a semiconductor device ( Figure 1 1) initialization operation. The start pulse STARTP, the end command BIST_CTRL, the reset signal RST and the reset adjustment signal RST_REG may be set to be activated at a logic "high" level, and the inverted reset adjustment signal RST_REGB may be set to be activated at a logic "low" level. However, this is only an example, and the present disclosure is not limited thereto.

[0042] The clock generation circuit 113 may generate a clock CLK and an inverted clock CLKB in response to a start pulse STARTP, an end command BIST_CTRL, and a reset signal RST. When the start pulse STARTP is activated to start the test mode, the clock generation circuit 113 may generate a flipped clock CLK and an inverted clock CLKB. When the end command BIST_CTRL is activated to terminate the test mode, the clock generation circuit 113 may generate a clock CLK and an inverted clock CLKB whose logic levels are fixed. When the reset signal RST is activated to perform an initialization operation, the clock generation circuit 113 may generate a clock CLK and an inverted clock CLKB whose logic levels are fixed.

[0043] Figure 3 is based on Figure 2 The circuit diagram of the reset adjustment signal generating circuit 111A of the embodiment of the reset adjustment signal generating circuit 111 is shown.

[0044] like Figure 3 As shown, when at least one of the start pulse STARTP, the end command BIST_CTRL, and the reset signal RST is activated at a logic "high" level, the reset adjustment signal generation circuit 111A may generate an inverted reset adjustment signal RST_REGB activated at a logic "low" level. In addition, when at least one of the start pulse STARTP, the end command BIST_CTRL, and the reset signal RST is activated at a logic "high" level, the reset adjustment signal generation circuit 111A may generate a reset adjustment signal RST_REG activated at a logic "high" level. For example, the reset adjustment signal generation circuit 111A may include an OR gate.

[0045] Figure 4 is based on Figure 2 FIG. 1 is a circuit diagram of a clock generating circuit 113A of an embodiment of the clock generating circuit 113 shown in FIG. Figure 4 As shown, the clock generating circuit 113A may include a clock segment signal generating circuit 211 and an oscillator 213 .

[0046] The clock segment signal generating circuit 211 may generate a clock segment signal EN in response to a start pulse STARTP. When the start pulse STARTP is activated at a logic "high" level, the clock segment signal generating circuit 211 may generate an inverted start pulse STARTPB set to a logic "low" level. When the start pulse STARTP changes from a logic "high" level to a logic "low" level, the clock segment signal generating circuit 211 may generate a clock segment signal EN activated at a logic "high" level according to the inverted start pulse STARTPB set to a logic "high" level. The oscillator 213 may be connected to the clock segment signal generating circuit 211 to receive the clock segment signal EN from the clock segment signal generating circuit 211. The oscillator 213 may be connected to the clock segment signal generating circuit 211, and may generate a clock CLK and an inverted clock CLKB in response to the clock segment signal EN. When the clock segment signal EN is activated at a logic "high" level, the clock generating circuit 113 may generate a flipped clock CLK and an inverted clock CLKB.

[0047] Figure 5 It shows that according to Figure 1 FIG. 1 is a block diagram showing a configuration of a jump control circuit 13A of an embodiment of the jump control circuit 13. Figure 5 As shown, the skip control circuit 13A may include a command pulse control circuit (CMDP CTR) 131 and a skip signal generating circuit (SKIP GEN) 133 .

[0048] The command pulse control circuit 131 may generate a command pulse CMDP, a skip reset signal SKIP_RST, and an inverted skip reset signal SKIP_RSTB in response to a clock CLK, an inverted clock CLKB, a reset adjustment signal RST_REG, and an inverted skip exit signal SKIP_EXITB. When at least one of the start pulse STARTP, the end command BIST_CTRL, and the reset signal RST is activated, the command pulse control circuit 131 may generate an activated skip reset signal SKIP_RST and an inverted skip reset signal SKIP_RSTB. When the inverted skip exit signal SKIP_EXITB is activated, the command pulse control circuit 131 may generate an activated skip reset signal SKIP_RST and an inverted skip reset signal SKIP_RSTB. The command pulse control circuit 131 may generate an activated command pulse CMDP in synchronization with the clock CLK after the inverted skip reset signal SKIP_RSTB is activated.

[0049] The skip signal generating circuit 133 may be connected to the command pulse control circuit 131 to receive the skip reset signal SKIP_RST and the inverted skip reset signal SKIP_RSTB from the command pulse control circuit 131. The skip signal generating circuit 133 may generate the skip signal SKIP in response to the clock CLK, the inverted clock CLKB, the skip reset signal SKIP_RST and the inverted skip reset signal SKIP_RSTB. When at least one of the skip reset signal SKIP_RST and the inverted skip reset signal SKIP_RSTB is activated, the skip signal generating circuit 133 may initialize the skip count signal SKIP_CNT<0:2> and the inverted skip count signal SKIP_CNTB<0:2>. For example, the skip reset signal SKIP_RST and the inverted skip reset signal SKIP_RSTB may be activated at different logic levels. When at least one of the skip reset signal SKIP_RST and the inverted skip reset signal SKIP_RSTB is deactivated, the skip signal generating circuit 133 may generate the skip signal SKIP including the sequentially activated bits in synchronization with the clock CLK.

[0050] Figure 6 is based on Figure 5 FIG. 1 is a circuit diagram of a command pulse control circuit 131A of an embodiment of the command pulse control circuit 131 shown in FIG. Figure 6 As shown, the command pulse control circuit 131A may include a skip initialization signal generating circuit 221 and a command pulse generating circuit 223 .

[0051] The skip initialization signal generation circuit 221 may generate a skip reset signal SKIP_RST and an inverted skip reset signal SKIP_RSTB in response to the reset adjustment signal RST_REG and the inverted skip exit signal SKIP_EXITB. When at least one of the start pulse STARTP, the end command BIST_CTL, and the reset signal RST is activated and the reset adjustment signal RST_REG is activated at a logic "high" level, the skip initialization signal generation circuit 221 may generate a skip reset signal SKIP_RST activated at a logic "high" level and an inverted skip reset signal SKIP_RSTB activated at a logic "low" level. When the inverted skip exit signal SKIP_EXITB is activated at a logic "low" level, the skip initialization signal generation circuit 221 may generate a skip reset signal SKIP_RST activated at a logic "high" level and an inverted skip reset signal SKIP_RSTB activated at a logic "low" level.

[0052] The command pulse generation circuit 223 may be connected to the skip initialization signal generation circuit 221 to receive the inverted skip reset signal SKIP_RSTB from the skip initialization signal generation circuit 221. After the inverted skip reset signal SKIP_RSTB is activated at a logic "low" level, at a time point when the clock CLK transitions from a logic "low" level to a logic "high" level (hereinafter referred to as a "rising edge"), the command pulse generation circuit 223 may generate the inverted skip set signal SKIP_SETB activated at a logic "low" level and the command pulse CMDP activated at a logic "high" level.

[0053] Figure 7 is based on Figure 5 FIG. 1 is a circuit diagram of a skip signal generating circuit 133A of an embodiment of the skip signal generating circuit 133 shown in FIG. Figure 7 As shown, the skip signal generating circuit 133A may include a skip counter 231 and a skip decoder 233 .

[0054] The skip counter 231 may generate a skip count signal SKIP_CNT<0:2> and an inverted skip count signal SKIP_CNTB<0:2> in response to the clock CLK, the inverted clock CLKB, the skip reset signal SKIP_RST, and the inverted skip reset signal SKIP_RSTB. When the skip reset signal SKIP_RST activated at a logic "high" level and the inverted skip reset signal SKIP_RSTB activated at a logic "low" level are received, the skip counter 231 may generate a skip count signal SKIP_CNT<0:2> initialized to a logic "low" level and an inverted skip count signal SKIP_CNTB<0:2> initialized to a logic "high" level. When receiving the skip reset signal SKIP_RST deactivated at a logic "low" level and the inverted skip reset signal SKIP_RSTB deactivated at a logic "high" level, the skip counter 231 may count the falling edge of the flipped clock CLK to generate a skip count signal SKIP_CNT<0:2> and an inverted skip count signal SKIP_CNTB<0:2> whose logic bit groups are sequentially changed. As an example, the skip counter 231 may generate the skip count signal SKIP_CNT<0:2> set to have a first logic bit group in synchronization with a first falling edge of the clock CLK, and generate the skip count signal SKIP_CNT<0:2> set to have a second logic bit group in synchronization with a second falling edge of the clock CLK.

[0055] The skip decoder 233 may be connected to the skip counter 231 to receive a skip count signal SKIP_CNT<0:2> and an inverted skip count signal SKIP_CNTB<0:2> from the skip counter 231. The skip decoder 233 may decode the skip count signal SKIP_CNT<0:2> and the inverted skip count signal SKIP_CNTB<0:2> to generate a first skip signal SKIP1, a second skip signal SKIP2, a third skip signal SKIP3, a fourth skip signal SKIP4, and a fifth skip signal SKIP5. When the skip count signal SKIP_CNT<0:2> set to have a first logic bit group is received in synchronization with a first falling edge of the clock CLK, the skip decoder 233 may generate a first skip signal SKIP1 activated at a logic “high” level. The case where the skip count signal SKIP_CNT<0:2> is set to have a first logic bit group may mean that the first bit SKIP_CNT of the skip count signal SKIP_CNT<0:2> is <0> The skip decoder 233 may generate a second skip signal SKIP2 activated at a logic "high" level when the skip count signal SKIP_CNT<0:2> is set to have a logic "high" level, and the second bit and the third bit SKIP_CNT<1:2> of the skip count signal SKIP_CNT<0:2> are both set to have a logic "low" level, but the present disclosure is not limited thereto. When the skip count signal SKIP_CNT<0:2> set to have a second logic bit group is received in synchronization with the second falling edge of the clock CLK, the skip decoder 233 may generate a second skip signal SKIP2 activated at a logic "high" level. The skip count signal SKIP_CNT<0:2> is set to have a second logic bit group may mean that the second bit SKIP_CNT<0:2> of the skip count signal SKIP_CNT<0:2> is set to have a second logic bit group. <1> is set to have a logic “high” level, and the first bit SKIP_CNT of the skip count signal SKIP_CNT<0:2> <0> and the third bit SKIP_CNT of the skip count signal SKIP_CNT<0:2> <2> The case where both are set to have a logic “low” level, but the present disclosure is not limited thereto. When the skip count signal SKIP_CNT<0:2> set to have a third logic bit group is received in synchronization with the third falling edge of the clock CLK, the skip decoder 233 may generate a third skip signal SKIP3 activated at a logic “high” level. The case where the skip count signal SKIP_CNT<0:2> is set to have a third logic bit group may mean that both the first bit and the second bit SKIP_CNT<0:1> of the skip count signal SKIP_CNT<0:2> are set to have a logic “high” level, and the third bit SKIP_CNT of the skip count signal <2> The case where φ is set to have a logic “low” level, but the present disclosure is not limited thereto.When the skip count signal SKIP_CNT<0:2> set to have the fourth logic bit group is received in synchronization with the fourth falling edge of the clock CLK, the skip decoder 233 may generate a fourth skip signal SKIP4 activated at a logic "high" level. The case where the skip count signal SKIP_CNT<0:2> is set to have the fourth logic bit group may mean that the first bit and the second bit SKIP_CNT<0:1> of the skip count signal are both set to have a logic "low" level, and the third bit SKIP_CNT<0:2> of the skip count signal SKIP_CNT<0:1> is set to have a logic "low" level. <2> The case where the skip count signal SKIP_CNT<0:2> is set to have a logic "high" level, but the present disclosure is not limited thereto. When the skip count signal SKIP_CNT<0:2> set to have a fifth logic bit group is received in synchronization with the fifth falling edge of the clock CLK, the skip decoder 233 may generate a fifth skip signal SKIP5 activated at a logic "high" level. The case where the skip count signal SKIP_CNT<0:2> is set to have a fifth logic bit group may mean that the first bit SKIP_CNT of the skip count signal SKIP_CNT<0:2> is <0> and the third bit SKIP_CNT of the skip count signal SKIP_CNT<0:2> <2> are all set to have a logic “high” level, and the second bit SKIP_CNT of the skip count signal SKIP_CNT<0:2> is <1> is set to have a logic "low" level, but the present disclosure is not limited thereto. In the present embodiment, a case where five skip signals SKIP1 to SKIP5 are generated in the skip decoder 233 has been described as an example, but this is only an example and the present disclosure is not limited thereto.

[0056] Figure 8 is based on Figure 1 FIG. 1 is a circuit diagram of an example of a jump exit control circuit 15A. Figure 8 As shown, the skip exit control circuit 15A may include a test mode setting circuit 241 , a mode setting signal generating circuit 243 , and a skip exit signal generating circuit 245 .

[0057] The test mode setting circuit 241 can generate a first jump setting signal TRCD, a second jump setting signal TCCD, a third jump setting signal TWR and a fourth jump setting signal TRP from the first jump signal SKIP1, the second jump signal SKIP2 and the third jump signal SKIP3 in response to the first test mode signal TRCD_TM<0:2>, the first inverted test mode signal TRCD_TMB<0:2>, the second test mode signal TCCD_TM<0:2>, the second inverted test mode signal TCCD_TMB<0:2>, the third test mode signal TWR_TM<0:2>, the third inverted test mode signal TWR_TMB<0:2>, the fourth test mode signal TRP_TM<0:2> and the fourth inverted test mode signal TRP_TMB<0:2>.

[0058] As used herein, the phrase "inverting buffer" refers to the buffering and inversion or complementation of a signal. Buffering and inversion of analog or digital signals can be accomplished by analog inverters. Digital inverters can be used to buffer and invert pure digital signals.

[0059] The test mode setting circuit 241 of the skip exit control circuit 15A can select one of the first skip signal SKIP1, the second skip signal SKIP2, and the third skip signal SKIP3 as the first selected skip signal in response to the first test mode signal TRCD_TM<0:2> and the first inverted test mode signal TRCD_TMB<0:2>. The test mode setting circuit 241 can also generate the first skip setting signal TRCD in response to the first selected skip signal. As an example, when the test mode setting circuit 241 receives the second bit TRCD_TM of the first test mode signal that is activated at a logic "high" level, <1> and the second bit TRCD_TMB of the first inverted test mode signal is activated at a logic “low” level <1> When , the test mode setting circuit 241 may invert and buffer the second skip signal SKIP2 selected as the first selection skip signal to generate the first skip setting signal TRCD.

[0060] The test mode setting circuit 241 may select one of the first skip signal SKIP1, the second skip signal SKIP2, and the third skip signal SKIP3 as a second selected skip signal in response to the second test mode signal TCCD_TM<0:2> and the second inverted test mode signal TCCD_TMB<0:2>, and generate a second skip setting signal TCCD from the second selected skip signal. As an example, when the third bit TCCD_TM of the second test mode signal is activated at a logic “high” level, <2> and the third bit TCCD_TMB of the second inverted test mode signal is activated at a logic “low” level <2> When received, the test mode setting circuit 241 may invert and buffer the third skip signal SKIP3 set as the second selection skip signal to generate the second skip setting signal TCCD.

[0061] The test mode setting circuit 241 may select one of the first skip signal SKIP1, the second skip signal SKIP2, and the third skip signal SKIP3 as a third selected skip signal in response to the third test mode signal TWR_TM<0:2> and the third inverted test mode signal TWR_TMB<0:2>, and generate a third skip setting signal TWR based on the third selected skip signal. As an example, when the test mode setting circuit 241 receives the second bit TWR_TM activated at a logic “high” level of the third test mode signal <1> and the second bit TWR_TMB of the third inverted test mode signal is activated at a logic “low” level <1> When , the test mode setting circuit 241 may invert and buffer the second skip signal SKIP2 selected as the third selection skip signal to generate the third skip setting signal TWR.

[0062] The test mode setting circuit 241 may select one of the first skip signal SKIP1, the second skip signal SKIP2, and the third skip signal SKIP3 as a fourth selected skip signal in response to the fourth test mode signal TRP_TM<0:2> and the fourth inverted test mode signal TRP_TMB<0:2>, and generate a fourth skip setting signal TRP based on the fourth selected skip signal. As an example, when the test mode setting circuit 241 receives the first bit TRP_TM activated at a logic “high” level of the fourth test mode signal <0> and the first bit TRP_TMB of the fourth inverted test mode signal is activated at a logic “low” level <0> When , the test mode setting circuit 241 may invert and buffer the first skip signal SKIP1 set as the fourth selection skip signal to generate the fourth skip setting signal TRP.

[0063] The mode setting signal generating circuit 243 may be connected to the test mode setting circuit 241 to receive the first jump setting signal TRCD, the second jump setting signal TCCD, the third jump setting signal TWR, and the fourth jump setting signal TRP from the test mode setting circuit 241. The mode setting signal generating circuit 243 may generate the first mode setting signal ASYNC1 and the second mode setting signal ASYNC2 from the first jump setting signal TRCD, the second jump setting signal TCCD, the third jump setting signal TWR, and the fourth jump setting signal TRP in response to the first mode signal MODE1, the second mode signal MODE2, the third mode signal MODE3, and the fourth mode signal MODE4.

[0064] When the first mode signal MODE1, the second mode signal MODE2, the third mode signal MODE3 and the fourth mode signal MODE4 are all at a logic “low” level in the initial mode (for example, when Fig.11 MODE0 in the example is set to have a logic “high” level), the mode setting signal generating circuit 243 may generate a first mode setting signal ASYNC1 and a second mode setting signal ASYNC2 both of which are activated at a logic “high” level.

[0065] When the first mode signal MODE1 is at a logic "high" level and the first inverted mode signal MODE1B is at a logic "low" level in the first mode, the mode setting signal generating circuit 243 may invert and buffer the first skip setting signal TRCD to generate the first mode setting signal ASYNC1 and the second mode setting signal ASYNC2 activated at a logic "high" level. For example, because the second skip signal SKIP2 is buffered and the first mode setting signal ASYNC1 is generated when the second skip signal SKIP2 is inverted and buffered and the first skip setting signal TRCD is generated, the first mode setting signal ASYNC1 may be activated at a logic "high" level when the second skip signal SKIP2 is activated at a logic "high" level.

[0066] When the second mode signal MODE2 is at a logic "high" level and the second inverted mode signal MODE2B is at a logic "low" level in the second mode, the mode setting signal generating circuit 243 may inversion-buffer the second skip setting signal TCCD to generate the first mode setting signal ASYNC1 and the second mode setting signal ASYNC2 activated at a logic "high" level. For example, because the third skip signal SKIP3 is buffered and the first mode setting signal ASYNC1 is generated when the third skip signal SKIP3 is inversion-buffered and the second skip setting signal TCCD is generated, the first mode setting signal ASYNC1 may be activated at a logic "high" level when the third skip signal SKIP3 is activated at a logic "high" level.

[0067] When the third mode signal MODE3 is at a logic "high" level and the third inverted mode signal MODE3B is at a logic "low" level in the third mode, the mode setting signal generating circuit 243 may invert and buffer the third skip setting signal TWR to generate the second mode setting signal ASYNC2 and the first mode setting signal ASYNC1 activated at a logic "high" level. For example, because the second skip signal SKIP2 is buffered and the second mode setting signal ASYNC2 is generated when the second skip signal SKIP2 is inverted and buffered and the third skip setting signal TWR is generated, the second skip signal SKIP2 is buffered and the second mode setting signal ASYNC2 is generated, so when the second skip signal SKIP2 is activated at a logic "high" level, the second mode setting signal ASYNC2 may be activated at a logic "high" level.

[0068] When the fourth mode signal MODE4 is at a logic "high" level and the fourth inverted mode signal MODE4B is at a logic "low" level in the fourth mode, the mode setting signal generating circuit 243 of the skip exit control circuit 15A may invert and buffer the fourth skip setting signal TRP to generate the second mode setting signal ASYNC2 and the first mode setting signal ASYNC1 activated at a logic "high" level. For example, because the first skip signal SKIP1 is buffered and the second mode setting signal ASYNC2 is generated when the first skip signal SKIP1 is inverted and buffered and the fourth skip setting signal TRP is generated, the second mode setting signal ASYNC2 may be activated at a logic "high" level when the first skip signal SKIP1 is activated at a logic "high" level.

[0069] The skip exit signal generating circuit 245 of the skip exit control circuit 15A may be connected to the mode setting signal generating circuit 243 to receive the first mode setting signal ASYNC1 and the second mode setting signal ASYNC2 from the mode setting signal generating circuit 243. The skip exit signal generating circuit 245 may generate a skip exit signal SKIP_EXIT and an inverted skip exit signal SKIP_EXITB in response to the first mode setting signal ASYNC1, the second mode setting signal ASYNC2, the reset adjustment signal RST_REG, the clock CLK, and the inverted clock CLKB. After both the first mode setting signal ASYNC1 and the second mode setting signal ASYNC2 are activated, the skip exit signal generating circuit 245 may generate an inverted skip exit signal SKIP_EXITB activated at a logic "low" level and a skip exit signal SKIP_EXIT activated at a logic "high" level in synchronization with the rising edge of the clock CLK.

[0070] Fig. 9 It shows that according to Figure 1 FIG. 1 is a block diagram showing a configuration of a mode control circuit 17A of an embodiment of the mode control circuit 17 shown in FIG. Fig. 9 As shown, the mode control circuit 17A may include a mode reset signal generating circuit (MODE_RST GEN) 171 , a mode change pulse generating circuit (MODE_CHP GEN) 173 , and a mode signal generating circuit (MODE GEN) 175 .

[0071] The mode reset signal generation circuit 171 may generate a mode reset signal MODE_RST and an inverted mode reset signal MODE_RSTB in response to an inverted reset signal RSTB and an end command BIST_CTRL. When one of the inverted mode reset signal MODE_RSTB and the end command BIST_CTRL is activated, the mode reset signal generation circuit 171 may generate an activated mode reset signal MODE_RST and an inverted mode reset signal MODE_RSTB. The inverted reset signal RSTB may be activated for use in a semiconductor device ( Figure 1 1) initialization operation.

[0072] The mode change pulse generating circuit 173 may be connected to the mode reset signal generating circuit 171 and the mode signal generating circuit 175. The mode change pulse generating circuit 173 may receive the mode reset signal MODE_RST output from the mode reset signal generating circuit 171, and receive the mode signal MODE from the mode signal generating circuit 175. The mode change pulse generating circuit 173 may generate a mode change pulse MODE_CHP and an inverted mode change pulse MODE_CHPB in response to the mode reset signal MODE_RST, the skip exit signal SKIP_EXIT, the inverted skip exit signal SKIP_EXITB, and in response to the mode signal MODE output from the mode signal generating circuit 175. When the mode reset signal MODE_RST is activated, the mode change pulse generating circuit 173 may generate a deactivated mode change pulse MODE_CHP and an inverted mode change pulse MODE_CHPB. Whenever at least one of the skip exit signal SKIP_EXIT and the inverted skip exit signal SKIP_EXITB is activated, the mode change pulse generation circuit 173 may generate a mode change pulse MODE_CHP and an inverted mode change pulse MODE_CHPB activated to change the mode until a preset final mode is entered in response to the mode signal MODE. As an example, when at least one of the skip exit signal SKIP_EXIT and the inverted skip exit signal SKIP_EXITB is activated for the first time, the mode change pulse generation circuit 173 may generate a mode change pulse MODE_CHP and an inverted mode change pulse MODE_CHPB activated to enter the first mode. In addition, when the skip exit signal SKIP_EXIT and the inverted skip exit signal SKIP_EXITB are activated for the second time, the mode change pulse generation circuit 173 may generate a mode change pulse MODE_CHP and an inverted mode change pulse MODE_CHPB activated to enter the second mode. When entering a preset final mode in response to the mode signal MODE, the mode change pulse generation circuit 173 may generate a deactivated mode change pulse MODE_CHP and an inverted mode change pulse MODE_CHPB when at least one of the skip exit signal SKIP_EXIT and the inverted skip exit signal SKIP_EXITB is activated.

[0073] The mode signal generating circuit 175 may be connected to the mode reset signal generating circuit 171 and the mode change pulse generating circuit 173. The mode signal generating circuit 175 may receive the mode reset signal MODE_RST and the inverted mode reset signal MODE_RSTB from the mode reset signal generating circuit 171, and receive the mode change pulse MODE_CHP and the inverted mode change pulse MODE_CHPB from the mode change pulse generating circuit 173. The mode signal generating circuit 175 may generate the mode signal MODE in response to the mode reset signal MODE_RST, the inverted mode reset signal MODE_RSTB, the mode change pulse MODE_CHP, and the inverted mode change pulse MODE_CHPB. When at least one of the mode reset signal MODE_RST and the inverted mode reset signal MODE_RSTB is activated, the mode signal generating circuit 175 may generate the initialized mode signal MODE. As an example, when at least one of the mode reset signal MODE_RST and the inverted mode reset signal MODE_RSTB is activated, the mode signal generating circuit 175 may generate the initialized mode signal MODE to enter the initial mode (e.g., Fig.11 MODE0 in ). When at least one of the mode change pulse MODE_CHP and the inverted mode change pulse MODE_CHPB is activated, the mode signal generation circuit 175 may generate the mode signal MODE to change the mode until the preset final mode is entered in response to the mode signal MODE. As an example, when at least one of the skip exit signal SKIP_EXIT and the inverted skip exit signal SKIP_EXITB is activated for the first time, the mode signal generation circuit 175 may generate the mode signal MODE for entering the first mode, and when at least one of the skip exit signal SKIP_EXIT and the inverted skip exit signal SKIP_EXITB is activated for the second time, the mode signal generation circuit 175 may generate the mode signal MODE for entering the second mode. When the preset final mode is entered in response to the mode signal MODE, the mode signal generation circuit 175 may generate the mode signal MODE to maintain the mode.

[0074] Fig.10 is based on Fig. 9 The circuit diagram of the mode reset signal generating circuit 171A and the mode change pulse generating circuit 173A of the embodiment of the mode reset signal generating circuit 171 and the mode change pulse generating circuit 173 shown in FIG.

[0075] like Fig.10 As shown, when the inverted reset signal RSTB is activated at a logic "low" level for Figure 1During the initialization operation of the semiconductor device 1, the mode reset signal generating circuit 171A may generate a mode reset signal MODE_RST activated at a logic "high" level and an inverted mode reset signal MODE_RSTB activated at a logic "low" level. In addition, when the end command BIST_CTRL is activated at a logic "high" level, the mode reset signal generating circuit 171A may generate a mode reset signal MODE_RST activated at a logic "high" level and an inverted mode reset signal MODE_RSTB activated at a logic "low" level.

[0076] like Fig.10 As shown, when the mode reset signal MODE_RST activated at a logic "high" level is received, the mode change pulse generating circuit 173A may generate a mode change pulse MODE_CHP deactivated at a logic "low" level and an inverted mode change pulse MODE_CHPB deactivated at a logic "high" level. In addition, when at least one of the skip exit signal SKIP_EXIT and the inverted skip exit signal SKIP_EXITB is activated without entering the fifth mode and the fifth mode signal MODE5 is at a logic "low" level, the mode change pulse generating circuit 173A may generate a mode change pulse activated at a logic "high" level and an inverted mode change pulse MODE_CHPB activated at a logic "low" level to sequentially change from the first mode to the fifth mode. In addition, when the jump exit signal SKIP_EXIT or the inverted jump exit signal SKIP_EXITB is activated when entering the fifth mode and the fifth mode signal MODE5 is in a logic "high" level, the mode change pulse generating circuit 173A can generate a mode change pulse MODE_CHP deactivated at a logic "low" level and an inverted mode change pulse MODE_CHPB deactivated at a logic "high" level.

[0077] Fig.11 is based on Fig. 9 FIG. 1 is a circuit diagram of a mode signal generating circuit 175A of an embodiment of the mode signal generating circuit 175 shown in FIG. Fig.11 As shown, the mode signal generating circuit 175A may include a mode counter 251 and a mode decoder 253 .

[0078] The mode counter 251 may generate a mode count signal MODE_CNT<0:2> and an inverted mode count signal MODE_CNTB<0:2> in response to a mode reset signal MODE_RST, an inverted mode reset signal MODE_RSTB, a mode change pulse MODE CHP, and an inverted mode change pulse MODE CHPB. When the mode reset signal MODE_RST is activated at a logic "high" level and the inverted mode reset signal MODE_RSTB is activated at a logic "low" level, the mode counter 251 may generate a mode count signal MODE_CNT<0:2> initialized to a logic "low" level and an inverted mode count signal MODE_CNTB<0:2> initialized to a logic "high" level. In a state where the mode reset signal MODE_RST is deactivated at a logic "low" level and the inverted mode reset signal MODE_RSTB is deactivated at a logic "high" level, when the mode change pulse MODE_CHP is activated at a logic "high" level and the inverted mode change pulse MODE_CHPB is activated at a logic "low" level, the mode counter 251 may count to generate a mode count signal MODE_CNT<0:2> and an inverted mode count signal MODE_CNTB<0:2> whose logic bit groups sequentially change. As an example, when at least one of the mode change pulse MODE_CHP and the inverted mode change pulse MODE_CHPB is activated for the first time, the mode counter 251 may generate the mode count signal MODE_CNT<0:2> set to have a first logic bit group, and when at least one of the mode change pulse MODE_CHP and the inverted mode change pulse MODE_CHPB is activated for the second time, the mode counter 251 may generate the mode count signal MODE_CNT<0:2> set to have a second logic bit group.

[0079] The mode decoder 253 may be connected to the mode counter 251 to receive the mode count signal MODE_CNT<0:2> and the inverted mode count signal MDE_CNTB<0:2> from the mode counter 251. The mode decoder 253 may decode the mode count signal MODE_CNT<0:2> and the inverted mode count signal MDE_CNTB<0:2> to generate an initial mode signal MODE0, a first mode signal MODE1, a second mode signal MODE2, a third mode signal MODE3, a fourth mode signal MODE4, and a fifth mode signal MODE5. When the inverted mode count signal MODE_CNTB<0:2> is initialized to a logic “high” level, the mode decoder 253 may generate the initial mode signal MODE0 activated at a logic “high” level. When at least one of the mode change pulse MODE_CHP and the inverted mode change pulse MODE_CHPB is activated for the first time and the mode count signal MODE_CNT<0:2> set to have the first logic bit group is input to the mode decoder 253, the mode decoder 253 may generate the first mode signal MODE1 activated at a logic "high" level. The case where the mode count signal MODE_CNT<0:2> is set to have the first logic bit group may mean a case where the first bit of the mode count signal MODE_CNT<0:2> is set to have the first logic bit group. <0> The second bit and the third bit of the mode count signal MODE_CNT<1:2> are set to have a logic “high” level, and the second bit and the third bit of the mode count signal MODE_CNT<1:2> are both set to have a logic “low” level, but the present disclosure is not limited thereto.

[0080] When the mode change pulse MODE_CHP and the inverted mode change pulse MODE_CHPB are activated for the second time and the mode count signal MODE_CNT<0:2> set to have the second logic bit group is received, the mode decoder 253 may generate the second mode signal MODE2 activated at a logic "high" level. The case where the mode count signal MODE_CNT<0:2> is set to have the second logic bit group may mean a case where the second bit MODE_CNT of the mode count signal <1> is set to have a logic "high" level, and the first bit of the mode count signal MODE_CNT <0> and the third bit of the mode count signal MODE_CNT <2> Both are set to have a logic “low” level, but the present disclosure is not limited thereto.

[0081] When at least one of the mode change pulse MODE_CHP and the inverted mode change pulse MODE_CHPB is activated for the third time and the mode count signal MODE_CNT<0:2> set to have the third logic bit group is input to the mode decoder 253, the mode decoder 253 may generate the third mode signal MODE3 activated at a logic "high" level. The case where the mode count signal MODE_CNT<0:2> is set to have the third logic bit group may mean a case where the first bit of the mode count signal MODE_CNT<0:2> is set to have the third logic bit group. <0> and the second bit of the mode count signal MODE_CNT <1> are set to have a logic "high" level, and the third bit MODE_CNT of the mode count signal <2> is set to have a logic “low” level, but the present disclosure is not limited thereto.

[0082] When at least one of the mode change pulse MODE_CHP and the inverted mode change pulse MODE_CHPB is activated for the fourth time and the mode count signal MODE_CNT<0:2> set to have the fourth logic bit group is input to the mode decoder 253, the mode decoder 253 may generate the fourth mode signal MODE4 activated at a logic "high" level. The case where the mode count signal MODE_CNT<0:2> is set to have the fourth logic bit group may mean a case where the third bit of the mode count signal MODE_CNT<0:2> is set to have the fourth logic bit group. <2> are set to have a logic “high” level, and both the first and second bits of the mode count signal MODE_CNT<0:1> are set to have a logic “low” level, but the present disclosure is not limited thereto.

[0083] When at least one of the mode change pulse MODE_CHP and the inverted mode change pulse MODE_CHPB is activated for the fifth time and the mode count signal MODE_CNT<0:2> set to have the fifth logic bit group is input to the mode decoder 253, the mode decoder 253 may generate the fifth mode signal MODE5 activated at a logic "high" level. The case where the mode count signal MODE_CNT<0:2> is set to have the fifth logic bit group may mean a case where the first bit of the mode count signal MODE_CNT<0:2> is set to have the fifth logic bit group. <0> And the third bit MODE_CNT <2> are set to have a logic "high" level, and the second bit of the mode count signal MODE_CNT <1> is set to have a logic “low” level, but the present disclosure is not limited thereto.

[0084] Fig.12 It shows that according to Figure 1FIG. 1 is a block diagram of a configuration of a command control circuit 19A of an embodiment of the command control circuit 19 shown in FIG. As described below, the command control circuit 19A is configured to generate an internal command for each mode in response to the mode signal MODE. Fig.12 As shown, the command control circuit 19A may include an internal command generation circuit (ICMD GEN) 191 and a termination command generation circuit (BIST_CTRL GEN) 193 .

[0085] The internal command generation circuit 191 may generate an activation command ACT, a CAS command CAS, a precharge command PCG, and an end pulse ENDP in response to the command pulse CMDP and the mode signal MODE. The internal command generation circuit 191 may generate an activated activation command ACT when entering the first mode in response to the mode signal MODE in a state where the command pulse CMDP is activated. The activation command ACT may be activated to perform an activation operation to access the semiconductor device ( Figure 1 The internal command generation circuit 191 may generate an activated CAS command when entering the second mode in response to the mode signal MODE in a state where the command pulse CMDP is activated. The CAS command may be activated to Figure 1 1) in which column operations such as read operations and write operations are performed. The internal command generation circuit 191 may generate an activated precharge command PCG when entering the fourth mode in response to the mode signal MODE in a state where the command pulse CMDP is activated. The precharge command PCG may be activated to Figure 1 The internal command generation circuit 191 may generate an activated end pulse ENDP when entering the fifth mode in response to the mode signal MODE in a state where the command pulse CMDP is activated.

[0086] The end command generation circuit 193 may be connected to the internal command generation circuit 191 to receive the end pulse ENDP from the internal command generation circuit 191. The end command generation circuit 193 may generate an end command BIST_CTRL in response to the end pulse ENDP. When a preset end delay section has passed after the end pulse ENDP is activated, the end command generation circuit 193 may generate the activated end command BIST_CTRL.

[0087] Fig.13 is based on Fig.12 2 is a circuit diagram of an internal command generation circuit 191A of an embodiment of the internal command generation circuit 191 shown.

[0088] like Fig.13As shown, when the first mode signal MODE1 is activated at a logic "high" level to enter the first mode in a state where the command pulse CMDP is activated at a logic "high" level, the internal command generation circuit 191A may generate an activation command ACT activated at a logic "high" level. When the second mode signal MODE2 is activated at a logic "high" level to enter the second mode in a state where the command pulse CMDP is activated at a logic "high" level, the internal command generation circuit 191A may generate a CAS command activated at a logic "high" level. When the fourth mode signal MODE4 is activated at a logic "high" level to enter the fourth mode in a state where the command pulse CMDP is activated at a logic "high" level, the internal command generation circuit 191A may generate a precharge command PCG activated at a logic "high" level. When the fifth mode signal MODE5 is activated at a logic "high" level to enter the fifth mode in a state where the command pulse CMDP is activated at a logic "high" level, the internal command generation circuit 191A may generate an end pulse ENDP activated at a logic "high" level.

[0089] Fig.14 is based on Fig.12 FIG. 1 is a circuit diagram of an end command generation circuit 193A of an embodiment of the end command generation circuit 193 shown in FIG. Fig.14 As shown in , the end command generation circuit 193A may include an end pulse delay circuit 261 , an end pulse inversion delay circuit 263 , and an end command output circuit 265 .

[0090] The end pulse delay circuit 261 may delay the end pulse ENDP to generate a delayed end pulse ENDPd. The end pulse inversion delay circuit 263 may invert and delay the delayed end pulse ENDPd to generate an inverted delayed end pulse ENDPdB. When both the delayed end pulse ENDPd and the inverted delayed end pulse ENDPdB are set to have a logic "high" level, the end command output circuit 265 may generate an end command BIST_CTRL activated at a logic "high" level.

[0091] Fig.15 It is shown Fig.14 The timing diagram of the operation of the end command generation circuit 193A is shown in FIG. Fig.14 and Fig.15As shown, the end pulse delay circuit 261 can invert and delay the end pulse ENDP to generate an inverted end pulse ENDPB. The end pulse inversion delay circuit 263 can invert and delay the inverted end pulse ENDPB to generate a delayed end pulse ENDPd. When the inverted end pulse ENDPB and the delayed end pulse ENDPd are both set to have a logic "high" level, the end command output circuit 265 can generate an end command BIST_CTRL activated at a logic "high" level. When the end delay section td has passed from the time point when the end pulse ENDP is generated, the end command generation circuit 193A can generate an activated end command BIST_CTRL.

[0092] Figures 16 to 21 It is shown Figures 1 to 15 A timing diagram of an internal command generation operation of the semiconductor device 1 described in Figures 22 to 33 is a circuit diagram showing an internal command generating operation of the semiconductor device 1 .

[0093] refer to Fig.16 and Fig. 22 When the start pulse STARTP is activated at a logic “high” level “H” to start the test mode to generate internal commands ACT, CAS, PCG and BIST_CTRL, the reset adjustment signal generating circuit 111A can generate an inverted reset adjustment signal RST_REGB activated at a logic “low” level “L” and a reset adjustment signal RST_REG activated at a logic “high” level “H”.

[0094] Reference Fig.16 and Fig.23 When the start pulse STARTP is activated at a logic “high” level “H”, the clock segment signal generating circuit 211 may generate an inverted start pulse STARTPB set to a logic “low” level “L”, and when the start pulse STARTP changes from a logic “high” level “H” to a logic “low” level “L”, the clock segment signal generating circuit 211 may generate a clock segment signal EN activated at a logic “high” level “H” according to the inverted start pulse STARTPB set to a logic “high” level “H”. When the clock segment signal EN is activated at a logic “high” level “H”, the oscillator 213 may generate a flipped clock CLK and an inverted clock CLKB.

[0095] Reference Fig.17 and Fig.24In the section before the time point T1, when the initial mode signal MODE0 is set to have a logic "high" level "H" and the first mode signal MODE1, the second mode signal MODE2, the third mode signal MODE3 and the fourth mode signal MODE4 are all set to have a logic "low" level "L", the mode setting signal generating circuit 243 may generate the first mode setting signal ASYNC1 and the second mode setting signal ASYNC2 both activated at a logic "high" level "H". The skip exit signal generating circuit 245 may generate the inverted skip exit signal SKIP_EXITB activated at a logic "low" level "L" and the skip exit signal SKIP_EXIT activated at a logic "high" level "H" in synchronization with T1, which is a time point (hereinafter, referred to as a "falling edge") when the clock CLK changes from a logic "high" level to a logic "low" level in a state where the first mode setting signal ASYNC1 and the second mode setting signal ASYNC2 are both activated at a logic "high" level "H".

[0096] Reference Fig.17 and Fig.25 , in the section before T1, it is in the initial mode, and the mode reset signal generating circuit 171A can generate the mode reset signal MODE_RST deactivated at the logic "low" level "L" and the inverted mode reset signal MODE_RSTB deactivated at the logic "high" level "H" according to the inverted reset signal RSTB deactivated at the logic "high" level "H" and the end command BIST_CTRL deactivated at the logic "low" level "L". In addition, at the falling edge of the inverted skip exit signal SKIP_EXITB at the time point T1, the mode change pulse generating circuit 173A can generate the mode change pulse MODE_CHP activated at the logic "high" level "H" and the inverted mode change pulse MODE_CHPB activated at the logic "low" level "L" according to the fifth mode signal MODE5 deactivated at the logic "low" level "L" and the mode reset signal MODE_RST deactivated at the logic "low" level "L".

[0097] Reference Fig.17 and Fig.26At time point T1, the mode counter 251 may be activated at a logic “high” level “H” by the mode change pulse MODE_CHP and the inverted mode change pulse MODE_CHPB in a state where the mode reset signal MODE_RST is deactivated at a logic “low” level “L” and the inverted mode reset signal MODE_RSTB is deactivated at a logic “high” level “H”, and the first bit MODE_CNT of the mode count signal MODE_CNT<0:2> is set to “0:2”. <0> Set to logic “high” level and invert the first bit MODE_CNTB of the mode counting signal MODE_CNTB<0:2> <0> In this case, the second bit and the third bit MODE_CNT<1:2> of the mode count signal MODE_CNT<0:2> may maintain the initialized logic "low" level "L", and the second bit and the third bit MODE_CNTB<1:2> of the inverted mode count signal MODE_CNTB<0:2> may maintain the initialized logic "high" level "H". Therefore, the mode decoder 253 may be configured to have a logic "high" level "H" by setting the first bit MODE_CNT<0:2> of the mode count signal MODE_CNTB<0:2> to the logic "high" level "H". <0> The second bit and the third bit of the inverted mode count signal MODE_CNTB<1:2> are used to generate the first mode signal MODE1 activated at the logic "high" level "H". At the time point T1, because the first mode signal MODE1 is activated at the logic "high" level "H", Figure 1 The semiconductor device 1 may enter the first mode.

[0098] Reference Fig.18 and Fig. 27 At the time point T1, the skip initialization signal generating circuit 221 may generate the inverted skip reset signal SKIP_RSTB activated at the logic "low" level "L" by the inverted skip exit signal SKIP_EXITB activated at the logic "low" level "L". Therefore, after the inverted skip reset signal SKIP_RSTB is activated at the logic "low" level "L", the command pulse generating circuit 223 may generate the command pulse CMDP activated at the logic "high" level "H" at the time point T2 (the rising edge of the clock CLK).

[0099] refer to Fig.19 and Fig.28 At the time point T2, the internal command generation circuit 191A may generate an activation command ACT activated at a logic “high” level “H” through the command pulse CMDP activated at a logic “high” level “H” and the first mode signal MODE1 activated at a logic “high” level “H”.

[0100] Reference Fig.18 and Fig.29 , in the first mode segment During the period, in a state where the skip reset signal SKIP_RST deactivated at the logic “low” level “L” and the inverted skip reset signal SKIP_RSTB deactivated at the logic “high” level “H” are received, the skip counter 231 can generate the first bit SKIP_CNT of the skip count signal set to have the logic “high” level “H” in synchronization with the time point T11 (the falling edge of the clock CLK). <0> and the first bit SKIP_CNTB of the inverted skip count signal set to have a logic “low” level “L” <0> In this case, the second and third bits SKIP_CNT<1:2> of the skip count signal may maintain the initialized logic “low” level “L”, and the second and third bits SKIP_CNTB<1:2> of the inverted skip count signal may maintain the initialized logic “high” level “H”. Therefore, the skip decoder 233 may be configured to receive the first bit SKIP_CNT<1:2> of the skip count signal by setting the first bit SKIP_CNT<1:2> of the skip count signal to have the logic “high” level “H”. <0> The first skip signal SKIP1 activated at a logic “high” level “H” is generated by combining the second and third bits of the inverted skip count signal SKIP_CNTB<1:2>.

[0101] Reference Fig.18 and Fig.30 , in the first mode period During the segment, in a state where the skip reset signal SKIP_RST deactivated at a logic “low” level “L” and the inverted skip reset signal SKIP_RSTB deactivated at a logic “high” level “H” are received, the skip counter 231 can generate the first bit SKIP_CNT of the skip count signal set to have a logic “low” level “L” in synchronization with the time point T12 (the falling edge of the clock CLK). <0> , the second bit SKIP_CNT of the skip count signal is set to have a logic “high” level “H” <1> , the first bit SKIP_CNTB of the inverted skip count signal is set to have a logic “high” level “H” <0> and the second bit SKIP_CNTB of the inverted skip count signal which is set to have a logic “low” level “L” <1> In this case, the third bit of the skip count signal SKIP_CNT <2> The initialization logic "low" level "L" can be maintained, and the third bit SKIP_CNTB of the inverted skip count signal <2> The initialized logic “high” level “H” may be maintained. Therefore, the skip decoder 233 generates a first bit SKIP_CNTB of the inverted skip count signal SKIP_CNT<0:2> which is all set to have a logic “high” level “H”. <0> , the second bit SKIP_CNT of the skip count signal SKIP_CNT<0:2> <1> and the third bit SKIP_CNTB of the inverted skip count signal SKIP_CNT<0:2> <2> And the second skip signal SKIP2 activated at the logic “high” level “H” is generated.

[0102] Reference Fig. 20 and Fig.31The test mode setting circuit 241 can be configured to set the second bit TRCD_TMB of the first test mode signal <1> The second bit TRCD_TMB of the first inverted test mode signal TRCD_TMB<0:2> is set to have a logic “high” level “H” <1> In a state set to have a logic "low" level "L", the inversion buffering second skip signal SKIP2 outputs the inversion buffered signal as the first skip setting signal TRCD. In addition, during the section T1-T3 in the first mode, the mode setting signal generating circuit 243 can output the first skip setting signal TRCD as the first mode setting signal ASYNC1 by the first mode signal MODE1 activated at a logic "high" level "H" and the first inversion mode signal MODE1B activated at a logic "low" level "L", and generate the second mode setting signal ASYNC2 maintaining a logic "high" level "H". The skip exit signal generating circuit 245 can generate the inversion skip exit signal SKIP_EXITB activated at a logic "low" level "L" and the skip exit signal SKIP_EXIT activated at a logic "high" level "H" in synchronization with the time point T3 (the falling edge of the clock CLK) in a state where both the first mode setting signal ASYNC1 and the second mode setting signal ASYNC2 are activated at a logic "high" level "H".

[0103] Reference Fig.17 and Fig.10 The mode change pulse generating circuit 173A can generate a mode change pulse MODE_CHP activated at a logic “high” level “H” and an inverted mode change pulse MODE_CHPB activated at a logic “low” level “L” according to the fifth mode signal MODE5 deactivated at a logic “low” level “L” and the mode reset signal MODE_RST deactivated at a logic “low” level “L” at a time point T3 (the falling edge of the inverted jump exit signal SKIP_EXITB).

[0104] refer to Fig.17 and Fig.11At time point T3, when the mode reset signal MODE_RST is deactivated at a logic “low” level “L” and the inverted mode reset signal MODE_RSTB is deactivated at a logic “high” level “H”, the mode counter 251 may change the first bit MODE_CNT of the mode count signal MODE_CNT<0:2> according to the mode change pulse MODE_CHP activated at a logic “high” level “H” and the inverted mode change pulse MODE_CHPB activated at a logic “low” level “L”. <0> Set to have a logic “low” level “L”, and the first bit MODE_CNTB of the inverted mode count signal MODE_CNTB<0:2> is set ... <0> The second bit MODE_CNT<0:2> of the mode counting signal MODE_CNT<0:2> is set to have a logic “high” level “H”. <1> is set to have a logic “high” level “H”, and the second bit MODE_CNTB of the inverted mode count signal MODE_CNTB<0:2> ... <1> is set to have a logic “low” level “L”. In this case, the third bit MODE_CNT of the mode count signal MODE_CNT<0:2> <2> The initialized logic “low” level “L” may be maintained, and the third bit MODE_CNTB of the mode counting signal MODE_CNTB<0:2> may be inverted. <2> The initialized logic “high” level “H” may be maintained. Therefore, the mode decoder 253 may be configured to output the first bit MODE_CNTB of the inverted mode count signal MODE_CNTB<0:2> which is all set to the logic “high” level “H”. <0> , the second bit MODE_CNT of the mode counting signal MODE_CNT<0:2> <1> and the third bit MODE_CNTB of the inverted mode count signal MODE_CNTB<0:2> <2> , and generates the second mode signal MODE2 activated at the logic "high" level "H". At time point T3, because the second mode signal MODE2 is activated at the logic "high" level "H", Figure 1 The semiconductor device 1 can enter the second mode.

[0105] Reference Fig.18 and Figure 6 At the time point T3, the skip initialization signal generating circuit 221 can generate the inverted skip reset signal SKIP_RSTB activated at the logic "low" level "L" by the inverted skip reset signal SKIP_RSTB activated at the logic "low" level "L". Therefore, the command pulse generating circuit 223 can generate the command pulse CMDP activated at the logic "high" level "H" at the time point T4 (the rising edge of the clock CLK) after the inverted skip reset signal SKIP_RSTB is activated at the logic "low" level "L".

[0106] Reference Fig.19 and Fig.13 At time point T4, the internal command generation circuit 191A may generate a CAS command CAS activated at a logic “high” level “H” through a command pulse CMDP activated at a logic “high” level “H” and a second mode signal MODE2 activated at a logic “high” level “H”.

[0107] Reference Fig.18 and Figure 7 , in the second mode segment During this period, in the state of receiving the skip reset signal SKIP_RST deactivated at the logic “low” level “L” and the inverted skip reset signal SKIP_RSTB deactivated at the logic “high” level “H”, the skip counter 231 can generate the first bit SKIP_CNT of the skip count signal SKIP_CNT<0:2> set to have the “high” level “H” in synchronization with the time point T41 (the falling edge of the clock CLK). <0> and the first bit SKIP_CNTB of the inverted skip count signal SKIP_CNTB<0:2> is set to have a logic “low” level “L” <0> In this case, the second bit and the third bit SKIP_CNT<1:2> of the skip count signal SKIP_CNT<0:2> may maintain the initialized logic “low” level “L”, and the second bit and the third bit SKIP_CNTB<1:2> of the inverted skip count signal SKIP_CNTB<0:2> may maintain the initialized logic “high” level “H”. Therefore, the skip decoder 233 may be configured to receive the first bit SKIP_CNT<0:2> of the skip count signal SKIP_CNT<0:2> which is all set to have the logic “high” level “H”. <0> and inverts the second bit and the third bit SKIP_CNTB<1:2> of the skip count signal SKIP_CNTB<0:2> to generate the first skip signal SKIP1 activated at a logic “high” level “H”.

[0108] Reference Fig.18 and Figure 7 , in the second mode segment During the partial period, in the state of receiving the skip reset signal SKIP_RST deactivated at the logic “low” level “L” and the inverted skip reset signal SKIP_RSTB deactivated at the logic “high” level “H”, the skip counter 231 can generate the first bit SKIP_CNT of the skip count signal SKIP_CNT<0:2> set to have the “low” level “L” in synchronization with the time point T42 (the falling edge of the clock CLK). <0> , the second bit SKIP_CNT of the skip count signal SKIP_CNT<0:2> is set to have a logic “high” level “H” <1> , the first bit SKIP_CNTB of the inverted skip count signal SKIP_CNTB<0:2> is set to have a logic “high” level “H” <0> and the second bit SKIP_CNTB of the inverted skip count signal SKIP_CNTB<0:2> is set to have a logic “low” level “L” <1> In this case, the third bit SKIP_CNT of the skip count signal SKIP_CNT<0:2> <2> The initialized logic “low” level “L” may be maintained, and the third bit SKIP_CNTB of the skip count signal SKIP_CNTB<0:2> may be inverted. <2> The initialized logic “high” level “H” may be maintained. Therefore, the skip decoder 233 may be configured to output the first bit SKIP_CNTB of the inverted skip count signal SKIP_CNTB<0:2> which is all set to have the logic “high” level “H”. <0> , the second bit SKIP_CNT of the skip count signal SKIP_CNT<0:2> <1> and the third bit SKIP_CNTB of the inverted skip count signal SKIP_CNTB<0:2> <2> And the second skip signal SKIP2 activated at the logic “high” level “H” is generated.

[0109] Reference Fig.18 and 7 , in the second mode segment During this period, in the state of receiving the skip reset signal SKIP_RST deactivated at the logic “low” level “L” and the inverted skip reset signal SKIP_RSTB deactivated at the logic “high” level “H”, the skip counter 231 can generate the first bit SKIP_CNT of the skip count signal SKIP_CNT<0:2> set to have the “high” level “H” in synchronization with the time point T43 (the falling edge of the clock CLK). <0> , the second bit SKIP_CNT of the skip count signal SKIP_CNT<0:2> is set to have a logic “high” level “H” <1> , the first bit SKIP_CNTB of the inverted skip count signal SKIP_CNTB<0:2> is set to have a logic “low” level “L” <0> and the second bit SKIP_CNTB of the inverted skip count signal SKIP_CNTB<0:2> is set to have a logic “low” level “L” <1> In this case, the third bit SKIP_CNT of the skip count signal SKIP_CNT<0:2> <2> The initialized logic “low” level “L” may be maintained, and the third bit SKIP_CNTB of the skip count signal SKIP_CNTB<0:2> may be inverted. <2> The initialized logic “high” level “H” may be maintained. Therefore, the skip decoder 233 may be configured to output the first bits SKIP_CNT of the skip count signals SKIP_CNT<0:2> all set to have the logic “high” level “H”. <0> , the second bit SKIP_CNT of the skip count signal SKIP_CNT<0:2> <1> and the third bit SKIP_CNTB of the inverted skip count signal SKIP_CNTB<0:2> <2> And the third skip signal SKIP3 activated at the logic “high” level “H” is generated.

[0110] Reference Fig. 20 and Figure 8The test mode setting circuit 241 can set the third bit TCCD_TM of the second test mode signal <2> The third bit TCCD_TMB is set to have a logic “high” level “H” and the second inverted test mode signal TCCD_TMB<0:2> <2> In the state of being set to have a logic "low" level "L", the inversion buffered third skip signal SKIP3 outputs an inversion buffered signal as the second skip setting signal TCCD. In addition, during the section T3-T5 section in the second mode, the mode setting signal generating circuit 243 can output the second skip setting signal TCCD as the first mode setting signal ASYNC1 through the second mode signal MODE2 activated at a logic "high" level "H" and the second inversion mode signal MODE2B activated at a logic "low" level "L", and generate the second mode setting signal ASYNC2 maintaining a logic "high" level "H". The skip exit signal generating circuit 245 can generate the inversion skip exit signal SKIP_EXITB activated at a logic "low" level "L" and the skip exit signal SKIP_EXIT activated at a logic "high" level "H" in synchronization with the time point T5 (the falling edge of the clock CLK) in the state where both the first mode setting signal ASYNC1 and the second mode setting signal ASYNC2 are activated at a logic "high" level "H".

[0111] Reference Fig.17 and Fig.10 The mode change pulse generating circuit 173A can generate a mode change pulse MODE_CHP activated at a logic “high” level “H” and an inverted mode change pulse MODE_CHPB activated at a logic “low” level “L” according to the fifth mode signal MODE5 deactivated at a logic “low” level “L” and the mode reset signal MODE_RST deactivated at a logic “low” level “L” at a time point T5 (the falling edge of the inverted jump exit signal SKIP_EXITB).

[0112] Reference Fig.17 and Fig.11At time point T5, when the mode reset signal MODE_RST is deactivated at a logic “low” level “L” and the inverted mode reset signal MODE_RSTB is deactivated at a logic “high” level “H”, the mode counter 251 may set the first bit MODE_CNT of the mode count signal MODE_CNT<0:2> to zero according to the mode change pulse MODE_CHP activated at a logic “high” level “H” and the inverted mode change pulse MODE_CHPB activated at a logic “low” level “L”. <0> Set to have a logic “high” level “H”, the first bit MODE_CNTB of the inverted mode count signal MODE_CNTB<0:2> <0> The second bit MODE_CNT<0:2> of the mode counting signal MODE_CNT<0:2> is set to have a logic “low” level “L”. <1> The second bit MODE_CNTB of the inverted mode count signal MODE_CNTB<0:2> is set to have a logic “high” level “H”. <1> The third bit MODE_CNT<0:2> of the mode counting signal MODE_CNT<0:2> is set to have a logic “low” level “L”. <2> is set to have a logic “low” level “L”, and the third bit MODE_CNTB of the inverted mode count signal MODE_CNTB<0:2> ... <2> is set to have a logic “high” level “H”. Therefore, the mode decoder 253 can detect the first bit MODE_CNT of the mode count signal MODE_CNT<0:2> by <0> , the second bit MODE_CNT of the mode counting signal MODE_CNT<0:2> <1> and the third bit MODE_CNTB of the inverted mode count signal MODE_CNTB<0:2> <2> The third mode signal MODE3 activated at the logic "high" level "H" is generated. At the time point T5, since the third mode signal MODE3 is activated at the logic "high" level "H", the semiconductor device ( Figure 1 1) can enter the third mode.

[0113] Reference Fig.18 and Figure 6 At the time point T5, the skip initialization signal generating circuit 221 can generate the inverted skip reset signal SKIP_RSTB activated at the logic "low" level "L" by the inverted skip reset signal SKIP_RSTB activated at the logic "low" level "L". Therefore, the command pulse generating circuit 223 can generate the command pulse CMDP activated at the logic "high" level "H" at the time point T6 (the rising edge of the clock CLK) after the inverted skip reset signal SKIP_RSTB is activated at the logic "low" level "L".

[0114] Reference Fig.18 and Figure 7 During the section T5 to T7 in the third mode, upon receiving the skip reset signal SKIP_RST deactivated at a logic “low” level “L” and the inverted skip reset signal SKIP_RSTB deactivated at a logic “high” level “H”, the skip counter 231 may generate the first bit SKIP_CNT of the skip count signal SKIP_CNT<0:2> set to have a “high” level “H” in synchronization with the time point T61 (the falling edge of the clock CLK). <0> and the first bit SKIP_CNTB of the inverted skip count signal SKIP_CNTB<0:2> is set to have a logic “low” level “L” <0> In this case, the second bit and the third bit SKIP_CNT<1:2> of the skip count signal SKIP_CNT<0:2> may maintain the initialized logic “low” level “L”, and the second bit and the third bit SKIP_CNTB<1:2> of the inverted skip count signal may maintain the initialized logic “high” level “H”. Therefore, the skip decoder 233 may be configured to receive the first bit SKIP_CNT<0:2> of the skip count signal SKIP_CNT<0:2> which is all set to have the logic “high” level “H”. <0> and inverts the second bit and the third bit SKIP_CNTB<1:2> of the skip count signal SKIP_CNTB<0:2> to generate the first skip signal SKIP1 activated at a logic “high” level “H”.

[0115] Reference Fig.18 and Figure 7During the section T5-T7 in the third mode, upon receiving the skip reset signal SKIP_RST deactivated at a logic “low” level “L” and the inverted skip reset signal SKIP_RSTB deactivated at a logic “high” level “H”, the skip counter 231 may generate the first bit SKIP_CNT of the skip count signal SKIP_CNT<0:2> set to have a “low” level “L” in synchronization with the time point T62 (the falling edge of the clock CLK). <0> , the second bit SKIP_CNT of the skip count signal SKIP_CNT<0:2> is set to have a logic “high” level “H” <1> , the first bit SKIP_CNTB of the inverted skip count signal SKIP_CNTB<0:2> is set to have a logic “high” level “H” <0> and the second bit SKIP_CNTB of the inverted skip count signal SKIP_CNTB<0:2> is set to have a logic “low” level “L” <1> In this case, the third bit of the skip count signal SKIP_CNT <2> The initialization logic "low" level "L" can be maintained, and the third bit SKIP_CNTB of the inverted skip count signal <2> The initialized logic “high” level “H” may be maintained. Therefore, the skip decoder 233 may be configured to output the first bit SKIP_CNTB of the inverted skip count signal SKIP_CNTB<0:2> which is all set to have the logic “high” level “H”. <0> , the second bit SKIP_CNT of the skip count signal SKIP_CNT<0:2> <1> and the third bit SKIP_CNTB of the inverted skip count signal SKIP_CNTB<0:2> <2> And the second skip signal SKIP2 activated at the logic “high” level “H” is generated.

[0116] Reference Fig. 20 and Figure 8, the test mode setting circuit 241 can be configured to generate a signal at the second bit TWR_TM of the third test mode signal TWR_TM<0:2>. <1> The second bit TWR_TMB of the third inverted test mode signal TWR_TMB<0:2> is set to have a logic “high” level “H” <1> In a state set to have a logic “low” level “L”, the inversion buffering second skip signal SKIP2 outputs the inversion buffered signal as the third skip setting signal TWR. In addition, during the section T5-T7 in the third mode, the mode setting signal generating circuit 243 can output the third skip setting signal TWR as the second mode setting signal ASYNC2 by the third mode signal MODE3 activated at a logic “high” level “H” and the third inversion mode signal MODE3B activated at a logic “low” level “L”, and generate the first mode setting signal ASYNC1 maintaining a logic “high” level “H”. The skip exit signal generating circuit 245 can generate the inversion skip exit signal SKIP_EXITB activated at a logic “low” level “L” and the skip exit signal SKIP_EXIT activated at a logic “high” level “H” in synchronization with the time point T7 (the falling edge of the clock CLK) in a state where both the first mode setting signal ASYNC1 and the second mode setting signal ASYNC2 are activated at a logic “high” level “H”.

[0117] Reference Fig.17 and Fig.10 At time point T7, at the falling edge of the inverted jump exit signal SKIP_EXITB, the mode change pulse generating circuit 173A can generate a mode change pulse MODE_CHP activated at a logic "high" level "H" and an inverted mode change pulse MODE_CHPB activated at a logic "low" level "L" according to the fifth mode signal MODE5 deactivated at a logic "low" level "L" and the mode reset signal MODE_RST deactivated at a logic "low" level "L".

[0118] Reference Fig.17 and Fig.11At time point T7, when the mode reset signal MODE_RST is deactivated at a logic “low” level “L” and the inverted mode reset signal MODE_RSTB is deactivated at a logic “high” level “H”, the mode counter 251 may set the first bit MODE_CNT of the mode count signal according to the mode change pulse MODE_CHP activated at a logic “high” level “H” and the inverted mode change pulse MODE_CHPB activated at a logic “low” level “L”. <0> Set to have a logic "low" level "L" to invert the first bit of the mode count signal MODE_CNTB <0> The second bit MODE_CNT<0:2> of the mode counting signal MODE_CNT<0:2> is set to have a logic “high” level “H”. <1> The second bit MODE_CNTB of the inverting mode counting signal MODE_CNTB<0:2> is set to have a logic “low” level “L”. <1> is set to have a logic “high” level “H”, and the third bit MODE_CNT of the mode count signal MODE_CNT<0:2> is set to have a logic “high” level “H”, and the third bit MODE_CNT <2> The third bit MODE_CNTB of the inverted mode count signal MODE_CNTB<0:2> is set to have a logic “high” level “H”. <2> Therefore, the mode decoder 253 can detect the first bit MODE_CNTB of the inverted mode counting signal MODE_CNTB<0:2> by setting all bits MODE_CNTB to the logic “high” level “H”. <0> , the second bit of the inverted mode counting signal MODE_CNTB <1> and the third bit MODE_CNT of the mode count signal MODE_CNT<0:2> <2> , and generates the fourth mode signal MODE4 activated at the logic "high" level "H". At the time point T7, because the fourth mode signal MODE4 is activated at the logic "high" level "H", the semiconductor device ( Figure 1 1) can enter the fourth mode.

[0119] Reference Fig.18 and Figure 6 At time point T7, the skip initialization signal generating circuit 221 can generate the inverted skip reset signal SKIP_RSTB activated at a logic "low" level "L" by the inverted skip reset signal SKIP_RSTB activated at a logic "low" level "L". Therefore, the command pulse generating circuit 223 can generate the command pulse CMDP activated at a logic "high" level "H" at time point T8 (the rising edge of the clock CLK) after the inverted skip reset signal SKIP_RSTB is activated at a logic "low" level "L".

[0120] Reference Fig.19 and Fig.13At time point T8, the internal command generation circuit 191A may generate a precharge command PCG activated at a logic “high” level “H” through the command pulse CMDP activated at a logic “high” level “H” and the fourth mode signal MODE4 activated at a logic “high” level “H”.

[0121] Reference Fig.18 and Figure 7 , during the sections T7 to T9 in the fourth mode, upon receiving the skip reset signal SKIP_RST deactivated at a logic “low” level “L” and the inverted skip reset signal SKIP_RSTB deactivated at a logic “high” level “H”, the skip counter 231 may generate the first bit SKIP_CNT<0:2> of the skip count signal SKIP_CNT<0:2> set to have a “high” level “H” in synchronization with the time point T81 (the falling edge of the clock CLK). <0> and the first bit SKIP_CNTB of the inverted skip count signal SKIP_CNTB<0:2> is set to have a logic “low” level “L” <0> In this case, the second and third bits of the skip count signal SKIP_CNT<1:2> may maintain the initialized logic “low” level “L”, and the second and third bits of the inverted skip count signal SKIP_CNTB<0:2> may maintain the initialized logic “high” level “H”. Therefore, the skip decoder 233 may be configured to receive the first bit SKIP_CNT<0:2> of the skip count signal SKIP_CNT<0:2> which is all set to have the logic “high” level “H”. <0> and inverts the second bit and the third bit SKIP_CNTB<1:2> of the skip count signal SKIP_CNTB<0:2> to generate the first skip signal SKIP1 activated at a logic “high” level “H”.

[0122] Reference Fig. 20 and Figure 8The test mode setting circuit 241 can be configured to generate a first bit TRP_TM of the fourth test mode signal TRP_TM<0:2>. <0> The first bit TRP_TMB of the fourth inverted test mode signal is set to have a logic “high” level “H” and <0> In the state of being set to have a logic "low" level "L", the inversion buffering first skip signal SKIP1 outputs the inversion buffered signal as the fourth skip setting signal TRP. In addition, during the sections T7 to T9 in the fourth mode, the mode setting signal generating circuit 243 can output the fourth skip setting signal TRP as the second mode setting signal ASYNC2 through the fourth mode signal MODE4 activated at a logic "high" level "H" and the fourth inversion mode signal MODE4B activated at a logic "low" level "L", and generate the first mode setting signal ASYNC1 maintaining a logic "high" level "H". The skip exit signal generating circuit 245 can generate the inversion skip exit signal SKIP_EXITB activated at a logic "low" level "L" and the skip exit signal SKIP_EXIT activated at a logic "high" level "H" in synchronization with the time point T9 (the falling edge of the clock CLK) in the state where both the first mode setting signal ASYNC1 and the second mode setting signal ASYNC2 are activated at a logic "high" level "H".

[0123] Reference Fig.17 and Fig.10 At time point T9, at the falling edge of the inverted jump exit signal SKIP_EXITB, the mode change pulse generating circuit 173A can generate a mode change pulse MODE_CHP activated at a logic "high" level "H" and an inverted mode change pulse MODE_CHPB activated at a logic "low" level "L" according to the fifth mode signal MODE5 deactivated at a logic "low" level "L" and the mode reset signal MODE_RST deactivated at a logic "low" level "L".

[0124] Reference Fig.17 and Fig.32At time point T9, when the mode reset signal MODE_RST is deactivated at a logic “low” level “L” and the inverted mode reset signal MODE_RSTB is deactivated at a logic “high” level “H”, the mode counter 251 may change the first bit MODE_CNT of the mode count signal MODE_CNT<0:2> according to the mode change pulse MODE_CHP activated at a logic “high” level “H” and the inverted mode change pulse MODE_CHPB activated at a logic “low” level “L”. <0> Set to have a logic “high” level “H”, the first bit MODE_CNTB of the inverted mode count signal MODE_CNTB<0:2> <0> The second bit MODE_CNT<0:2> of the mode counting signal MODE_CNT<0:2> is set to have a logic “low” level “L”. <1> The second bit MODE_CNTB of the inverting mode counting signal MODE_CNTB<0:2> is set to have a logic “low” level “L”. <1> is set to have a logic “high” level “H”, and the third bit MODE_CNT of the mode count signal MODE_CNT<0:2> is set to have a logic “high” level “H”, and the third bit MODE_CNT <2> is set to have a logic “high” level “H”, and the third bit MODE_CNTB of the inverted mode count signal MODE_CNTB<0:2> ... <2> is set to have a logic “low” level “L”. Therefore, the mode decoder 253 can detect the first bit MODE_CNT of the mode count signal MODE_CNT<0:2> by setting all bits MODE_CNT to a logic “high” level “H”. <0> , the second bit MODE_CNTB of the inverted mode counting signal MODE_CNTB<0:2> <1> and the third bit MODE_CNT of the mode count signal MODE_CNT<0:2> <2> , and the fifth mode signal MODE5 activated at the logic "high" level "H" is generated. At the beginning of T9, because the fifth mode signal MODE5 is activated at the logic "high" level "H", Figure 1 The semiconductor device 1 can enter the fifth mode.

[0125] Reference Fig.18 and Figure 6 At the beginning of time point T9, the skip initialization signal generating circuit 221 can generate the inverted skip reset signal SKIP_RSTB activated at a logic "low" level "L" by the inverted skip reset signal SKIP_RSTB activated at a logic "low" level "L". Therefore, the command pulse generating circuit 223 can generate the command pulse CMDP activated at a logic "high" level "H" at the beginning of T10 (the rising edge of the clock CLK) after the inverted skip reset signal SKIP_RSTB is activated at a logic "low" level "L".

[0126] Reference Fig.19 and Fig.13 At the beginning of T10, the internal command generation circuit 191A may generate an end pulse ENDP activated at a logic "high" level "H" by the command pulse CMDP activated at a logic "high" level "H" and the fifth mode signal MODE5 activated at a logic "high" level "H". At a time point T11 when a preset end delay section has passed from the time point T10, the internal command generation circuit 191A may generate an end command BIST_CTRL activated at a logic "high" level "H".

[0127] Reference Fig. 20 and Fig.23 When the end command BIST_CTRL is activated at a logic “high” level “H” at time point T11, the mode reset signal generating circuit 171A may generate a mode reset signal MODE_RST activated at a logic “high” level “H” and an inverted mode reset signal MODE_RSTB activated at a logic “low” level “L”.

[0128] Reference Fig. 20 and Fig.11 When the mode reset signal MODE_RST is activated at a logic “high” level “H” and the inverted mode reset signal MODE_RSTB is activated at a logic “low” level “L”, the mode signal generating circuit 175A can generate a mode counting signal MODE_CNT<0:2> initialized to a logic “low” level “L” and an inverted mode reset signal MODE_RSTB initialized to a logic “high” level “H”, and generate an initial mode signal MODE0 activated at a logic “high” level “H” to enter the initial mode.

[0129] Reference Fig.21 , when the end command BIST_CTRL is activated at a logic “high” level “H” at the time point T11 , since the clock segment signal EN is deactivated at a logic “low” level, the inversion of the clock CLK may be stopped.

[0130] The semiconductor device 1 configured as described above can control the timing of generating an internal command in response to the skip signals SKIP1, SKIP2, SKIP3, SKIP4, and SKIP5 and the selection skip signal according to the test mode signals TRCD_TM<0:2>, TCCD_TM<0:2>, TWR_TM<0:2>, and TRP_TM<0:2>. Therefore, the semiconductor device 1 can easily control the timing of generating an internal command in a state where no external command is applied. In addition, the semiconductor device 1 can set one of SKIP1, SKIP2, SKIP3, SKIP4, and SKIP5 as the selection skip signal for each mode according to the test mode signals TRCD_TM<0:2>, TCCD_TM<0:2>, TWR_TM<0:2>, and TRP_TM<0:2>, and control the timing of generating each of the multiple internal commands in response to the selection skip signal of each mode. Therefore, the semiconductor device 1 can easily control the timing of generating each of the multiple internal commands in a state where no external command is applied.

[0131] Concepts have been disclosed in conjunction with some of the embodiments described above. Those skilled in the art will appreciate that multiple modifications, additions, and substitutions are possible without departing from the scope and spirit of the present disclosure. Therefore, the embodiments disclosed in this specification should not be considered restrictive, but exemplary. The scope of the concept is not limited to the above description, but is defined by the appended claims, and all distinguishing features within the scope of equivalents should be interpreted as being included in the concept.

Claims

1. A semiconductor device comprising: a skip exit control circuit that: selects one of a plurality of skip signals as a selected skip signal in response to a test mode signal; and generates a skip exit signal in response to the selected skip signal; a mode control circuit, which: generates a mode signal in response to the jump exit signal to change the mode until a preset final mode is entered; and A command control circuit generates an internal command for each mode in response to the mode signal.

2. The semiconductor device according to claim 1, wherein The skip exit control circuit generates the skip exit signal in synchronization with a clock after the selection skip signal is activated for a mode. 3 . The semiconductor device according to claim 2 , further comprising a clock control circuit that generates the clock in response to an enable pulse that enables a test mode.

4. The semiconductor device according to claim 1, in, The modes include a first mode and a second mode, The test mode signal includes a first test mode signal and a second test mode signal. The selection jump signal includes a first selection jump signal and a second selection jump signal, and Wherein, the jump exit control circuit: generating the skip exit signal substantially synchronously with the clock after the first select skip signal selected in response to the first test mode signal is activated in the first mode, and The skip exit signal is generated in synchronization with the clock after the second selection skip signal selected in response to the second test mode signal is activated in the second mode.

5. The semiconductor device according to claim 1, wherein The jump exit control circuit comprises: a test mode setting circuit, which: sets a skip setting signal in response to the selection skip signal; a mode setting signal generating circuit that: generates a mode setting signal from the jump setting signal in response to the mode signal; and A jump exit signal generating circuit generates the jump exit signal in synchronization with the mode setting signal and the clock.

6. The semiconductor device according to claim 5, wherein: The test mode setting circuit inverts and buffers the selection skip signal to generate the skip setting signal.

7. The semiconductor device according to claim 6, wherein: The mode setting signal generating circuit inverts and buffers the skip setting signal to generate the mode setting signal.

8. The semiconductor device according to claim 5, wherein The jump exit signal generating circuit generates the jump exit signal in synchronization with the clock after the mode setting signal is activated.

9. The semiconductor device according to claim 1, in, The modes include an initial mode, a first mode, and a second mode. The mode signal includes a first mode signal and a second mode signal, and Wherein, the mode control circuit generates the first mode signal to enter the first mode when the jump exit signal is activated in the initial mode.

10. The semiconductor device according to claim 9, wherein The mode control circuit generates the second mode signal to enter the second mode when the jump exit signal is activated in the first mode.

11. The semiconductor device according to claim 1, wherein The mode control circuit generates the mode signal to enter the initial mode when an end command is generated in the preset final mode to terminate the test mode.

12. The semiconductor device according to claim 1, wherein The mode control circuit comprises: A mode reset signal generating circuit, which: generates a mode reset signal in response to a reset signal and an end command; a mode change pulse generating circuit, which: generates a mode change pulse in response to the mode reset signal and the skip exit signal; and A mode signal generating circuit generates the mode signal in response to the mode reset signal and the mode change pulse.

13. The semiconductor device according to claim 1, in, The mode signal includes a first mode signal and a second mode signal, The internal command includes a first internal command and a second internal command, and Wherein, the command control circuit: generating the first internal command in response to the first mode signal and the command pulse, and The second internal command is generated in response to the second mode signal and the command pulse.

14. The semiconductor device according to claim 1, in, The internal commands include an activation command, a CAS command, a precharge command, and an end command, and The command control circuit sequentially generates the activation command, the CAS command, the precharge command and the end command for each mode changed in response to the jump exit signal.

15. The semiconductor device according to claim 1, wherein The command control circuit comprises: an internal command generating circuit, which: generates the internal command and the end pulse in response to the mode signal and the command pulse; and An end command generating circuit generates an end command in response to the end pulse.

16. The semiconductor device according to claim 15, wherein: The end command generating circuit generates the end command at a time point after a preset end delay section has passed since the time point when the end pulse is activated. 17 . The semiconductor device according to claim 1 , further comprising a skip control circuit that generates at least one of a command pulse and the skip signal in response to the skip exit signal.

18. The semiconductor device according to claim 17, wherein: The skip control circuit generates the command pulse which is activated in synchronization with a clock after the skip exit signal is activated.

19. The semiconductor device according to claim 17, wherein: The jump control circuit: Count the clock; generating a jump count signal; decoding the skip count signal; and The skip signal is generated after the skip exit signal is activated.

20. A semiconductor device comprising: a skip control circuit that: generates a command pulse and generates a plurality of skip signals in response to a skip exit signal; a mode control circuit, which: generates a mode signal for changing the mode in response to the jump exit signal until a preset final mode is entered; and a command control circuit, which generates an internal command for each mode in response to the command pulse and the mode signal, wherein the jump exit signal is generated in response to a select jump signal, and The selection skip signal is selected from one of the plurality of skip signals in response to a test mode signal.

21. The semiconductor device according to claim 20, wherein: The skip control circuit generates the command pulse which is activated in synchronization with a clock after the skip exit signal is activated. 22 . The semiconductor device according to claim 21 , further comprising a clock control circuit that generates the clock in response to a start pulse that starts the test mode.

23. The semiconductor device according to claim 20, wherein: The jump control circuit: counting the clock to generate a skip count signal; and After the skip exit signal is activated, the skip count signal is decoded to generate the skip signal.

24. The semiconductor device according to claim 20, in, The modes include an initial mode, a first mode, and a second mode. The mode signal includes a first mode signal and a second mode signal, and Wherein, the mode control circuit generates the first mode signal to enter the first mode when the jump exit signal is activated in the initial mode.

25. The semiconductor device according to claim 24, wherein: The mode control circuit generates the second mode signal to enter the second mode when the jump exit signal is activated in the first mode.

26. The semiconductor device according to claim 20, wherein: The mode control circuit generates the mode signal to enter the initial mode when an end command is generated in the final mode to terminate the test mode.

27. The semiconductor device according to claim 20, wherein: The mode control circuit comprises: A mode reset signal generating circuit, which: generates a mode reset signal in response to a reset signal and an end command; a mode change pulse generating circuit, which: generates a mode change pulse in response to the mode reset signal and the skip exit signal; and A mode signal generating circuit generates the mode signal in response to the mode reset signal and the mode change pulse. 28 . The semiconductor device according to claim 20 , further comprising a skip exit control circuit that generates the skip exit signal in synchronization with a clock after the selection skip signal is activated for each mode.

29. The semiconductor device according to claim 28, wherein: The jump exit control circuit comprises: a test mode setting circuit that generates a skip setting signal in response to the selection skip signal; a mode setting signal generating circuit that generates a mode setting signal from the jump setting signal in response to the mode signal; and A skip exit signal generating circuit generates the skip exit signal in synchronization with the mode setting signal and the clock.

30. A semiconductor device comprising: a skip exit control circuit that: selects one of a plurality of skip signals as a first selected skip signal in response to a first test mode signal in a first mode; and generates a skip exit signal from the first selected skip signal in synchronization with a clock, the skip exit signal being activated to enter a second mode; a mode control circuit that: generates the first mode signal to enter the first mode when the jump exit signal is activated in an initial mode; and generates the second mode signal to enter the second mode when the jump exit signal is activated in the first mode; and A command control circuit generates a first internal command in the first mode in response to the first mode signal and generates a second internal command in the second mode in response to the second mode signal. 31 . The semiconductor device according to claim 30 , further comprising a clock control circuit that generates the clock in response to a start pulse that starts a test mode.

32. The semiconductor device according to claim 31, wherein The mode control circuit generates an initial mode signal in response to the start pulse to enter the initial mode.

33. The semiconductor device according to claim 31, wherein The mode control circuit initializes the first mode signal and the second mode signal to enter the initial mode when an end command for terminating the test mode is generated in a final mode.

34. A method for generating an internal command of a semiconductor device, comprising: generating a skip exit signal in response to a selected skip signal, the selected skip signal being generated by the test mode signal; changing an operation mode of the semiconductor device in response to a mode signal generated by the selected skip signal; as well as The generation timing of each of the internal commands is controlled in response to the mode signal without input of an external command.

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