Storage and calculation integrated circuit and SRAM (Static Random Access Memory)
By designing a circuit structure for reading and writing separation in the integrated storage and computing circuit, the problem of insufficient stability and integration of read and write operations in the prior art is solved, and higher stability and smaller area occupation are achieved.
Patent Information
- Application Number
- CN202311354697.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-18
- Publication Date
- 2025-04-18
AI Technical Summary
The existing memory and computing integrated circuits and SRAM memory have shortcomings in read and write operation stability and integration, especially in AI edge devices, where energy consumption and latency need to be further optimized.
A memory-based integrated circuit is designed, and by setting the same coupling point between the write operation unit circuit and the read operation unit circuit, the write operation unit circuit and the read operation unit circuit are isolated from each other, thereby realizing read-write separation. This circuit uses only three transistors and one resistive memory, reducing area footprint.
It improves the stability of read and write operations of the memory and computing integrated circuit, while reducing the area of the circuit and enhancing the integration of SRAM memory.
Smart Images
Figure CN119851720A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a storage-computation integrated circuit and an SRAM memory. Background Art
[0002] Computation-in-one memory (CIM) parallelizes multiplication and accumulation (MAC) computations and reduces off-chip weight accesses to reduce energy consumption and latency, especially for AI edge devices. Previous CIM approaches have traded off in terms of area, noise margin, process variation, and weight accuracy. 6T SRAM offers the smallest cell area for CIM, but cell stability limits the number of activated cells, resulting in low parallelism. 10T and twin-8T isolate read and write paths to improve noise margin, but both require special design of bit cells using logic layout rules, resulting in more than 2x area overhead compared to foundry yield-optimized 6T SRAM.
[0003] At present, the read and write stability of SRAM memory still needs to be improved. Summary of the invention
[0004] The problem solved by the embodiments of the present invention is to provide a storage-computation integrated circuit and an SRAM memory, which are beneficial to improving the stability of the read and write operations of the storage-computation integrated circuit and improving the integration of the SRAM memory.
[0005] To solve the above problems, an embodiment of the present invention provides a storage and computing integrated circuit, including: a write operation unit circuit, including a first transistor and a resistive memory coupled to the first transistor; a read operation unit circuit coupled to the write operation unit circuit, including a second transistor and a third transistor coupled to the second transistor, and the coupling point between the second transistor and the resistive memory, the coupling point between the first transistor and the second transistor, and the coupling point between the first transistor and the resistive memory are the same coupling point.
[0006] Optionally, the first transistor includes a first gate, a first source and a first drain; the write operation unit circuit also includes: a word line and a bit line, the word line is coupled to the first gate, and the bit line is coupled to the first drain.
[0007] Optionally, the resistive random access memory includes an active electrode, an inert electrode, and a dielectric layer located between the active electrode and the inert electrode; the active electrode is coupled to the first source of the first transistor; the write operation unit circuit also includes: a first ground terminal, which is coupled to the inert electrode.
[0008] Optionally, the third transistor includes a third gate, a third source and a third drain; the read operation unit circuit also includes: a read word line and a read bit line, the read word line is coupled to the third gate of the third transistor, and the read bit line is coupled to the third drain of the third transistor; the read word line signal control unit is electrically connected to the read word line; the pre-charging circuit unit is electrically connected to the read bit line, and the pre-charging circuit unit pre-charges the read bit line.
[0009] Optionally, the material of the active electrode includes active metal; the material of the inert electrode includes inert metal.
[0010] Optionally, the material of the active electrode includes Ag or Au; the material of the inert electrode includes Pt or Al.
[0011] Optionally, the first transistor, the second transistor and the third transistor are all NMOS transistors.
[0012] Correspondingly, an embodiment of the present invention also provides an SRAM memory for product and accumulation operations, including: a plurality of storage and calculation integrated circuits provided by embodiments of the present invention arranged in multiple rows and columns; a read word line signal control unit for outputting a drive signal to drive a read operation unit circuit; and a precharge circuit unit for precharging the read operation unit circuit.
[0013] Optionally, the third transistor includes a third gate, a third source and a third drain; the read operation unit circuit also includes: a read word line, the read word line is coupled to the third gate of the third transistor; a read bit line, the read bit line is coupled to the third drain of the third transistor; the read word line signal control unit is electrically connected to the read word line; the pre-charging circuit unit is electrically connected to the read bit line, and the pre-charging circuit unit pre-charges the read bit line.
[0014] Optionally, each row has a plurality of the storage-and-computation-in-one circuits, and the read word lines of the plurality of the storage-and-computation-in-one circuits in the same row are the same word line.
[0015] Optionally, each column has a plurality of the integrated storage and calculation circuits, and the read bit lines of the plurality of integrated storage and calculation circuits in the same column are the same bit line.
[0016] Optionally, the read bit line has an input end and an output end, and the precharge circuit unit is connected to the input end; the SRAM memory also includes: a charge sharer, which is connected to the output end of the read bit line and is used to collect the charge signal on the read bit line; an analog-to-digital converter, which is connected to the charge sharer and is used to convert the charge signal collected by the charge sharer into a digital signal.
[0017] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:
[0018] The storage-computing integrated circuit provided by an embodiment of the present invention comprises a write operation unit circuit including a first transistor and a resistive memory coupled to the first transistor, a read operation unit circuit coupled to the write operation unit circuit including a second transistor and a third transistor coupled to the second transistor, a coupling point between the second transistor and the resistive memory, a coupling point between the first transistor and the second transistor, and a coupling point between the first transistor and the resistive memory being the same coupling point, and the write operation unit circuit and the read operation unit circuit being arranged so as to isolate the write operation unit circuit and the read operation unit circuit from each other, that is to say, the storage-computing integrated circuit has a separate write operation path and a read operation path, that is, the storage-computing integrated circuit has a read-write separation function, thereby improving the read and write operation stability of the storage-computing integrated circuit, and at the same time, compared with the existing storage-computing integrated circuit with read-write functions comprising 6 transistors, the present embodiment only uses three transistors and one resistive memory, thereby reducing the area occupied by the storage-computing integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1 It is a circuit diagram of an embodiment of a storage-computation integrated circuit of the present invention;
[0020] Figure 2 It is a waveform diagram of a word line, a bit line, a resistive random access memory, a read bit line, and a read word line when a write operation writes "0" and a read operation reads "0" according to the present invention;
[0021] Figure 3 It is a waveform diagram of a word line, a bit line, a resistive random access memory, a read bit line, and a read word line when a write operation writes "1" and a read operation reads "1" according to the present invention;
[0022] Figure 4 It is a schematic diagram of the arrangement of the SRAM memory of the present invention;
[0023] Figures 5 to 7 It is a schematic diagram of the SRAM memory of the present invention performing in-memory calculations. DETAILED DESCRIPTION
[0024] As can be seen from the background technology, currently, the reading and writing of 6T SRAM memory are not separated, the reading and writing stability of the SRAM memory is not high, and at the same time, the area occupied by the SRAM memory is too large.
[0025] In order to solve the above technical problems, an embodiment of the present invention provides a storage and computing integrated circuit, including: a write operation unit circuit, including a first transistor and a resistive memory coupled to the first transistor; a read operation unit circuit coupled to the write operation unit circuit, including a second transistor and a third transistor coupled to the second transistor, and the coupling point between the second transistor and the resistive memory, the coupling point between the first transistor and the second transistor, and the coupling point between the first transistor and the resistive memory are the same coupling point.
[0026] The storage-computing integrated circuit provided by an embodiment of the present invention comprises a write operation unit circuit including a first transistor and a resistive memory coupled to the first transistor, a read operation unit circuit coupled to the write operation unit circuit including a second transistor and a third transistor coupled to the second transistor, a coupling point between the second transistor and the resistive memory, a coupling point between the first transistor and the second transistor, and a coupling point between the first transistor and the resistive memory being the same coupling point, and the write operation unit circuit and the read operation unit circuit being arranged so as to isolate the write operation unit circuit and the read operation unit circuit from each other, that is to say, the storage-computing integrated circuit has a separate write operation path and a read operation path, that is, the storage-computing integrated circuit has a read-write separation function, thereby improving the read and write operation stability of the storage-computing integrated circuit, and at the same time, compared with the existing storage-computing integrated circuit with read-write functions comprising 6 transistors, the present embodiment only uses three transistors and one resistive memory, thereby reducing the area occupied by the storage-computing integrated circuit.
[0027] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0028] Figure 1 It is a circuit diagram of an embodiment of a storage-computation integrated circuit of the present invention; Figure 2 It is a waveform diagram of a word line, a bit line, a resistive random access memory, a read bit line, and a read word line when a write operation writes "0" and a read operation reads "0" according to the present invention; Figure 3 It is a waveform diagram of the word line, bit line, resistive random access memory, read bit line and read word line when the write operation of the present invention writes "1" and the read operation reads "1".
[0029] The storage and computing integrated circuit includes: a write operation unit circuit 130, including a first transistor 153 and a resistive memory 120 coupled to the first transistor 153; a read operation unit circuit 150 coupled to the write operation unit circuit 130, including a second transistor 151 and a third transistor 152 coupled to the second transistor 151, and the coupling point between the second transistor 151 and the resistive memory 120, the coupling point between the first transistor 153 and the second transistor 151, and the coupling point between the first transistor 153 and the resistive memory 120 are the same coupling point.
[0030] It should be noted that by setting the write operation unit circuit 130 and the read operation unit circuit 150, the write operation unit circuit 130 and the read operation unit circuit 150 are isolated from each other, that is, the storage-computing integrated circuit has a separate write operation path and a read operation path, that is, the storage-computing integrated circuit has the function of reading and writing separation, thereby improving the read operation and write operation stability of the storage-computing integrated circuit. At the same time, compared with the existing storage-computing integrated circuit with read and write functions that includes 6 transistors, this embodiment only uses three transistors and one resistive memory 120, thereby reducing the area occupied by the storage-computing integrated circuit.
[0031] The write operation unit circuit 130 is used to perform a write operation in the SRAM memory cell.
[0032] In this embodiment, the write operation unit circuit 130 includes a first transistor 153 and a resistive random access memory 120 coupled to the first transistor 153 .
[0033] The first transistor 153 plays a role of turning on and off in the write operation unit circuit 130. By providing a turn-on voltage to the first transistor 153, the first transistor 153 is in a turned-on state, so that the resistive random access memory 120 coupled to the first transistor 153 can be in a low resistance state LRS or a high resistance state HRS.
[0034] As an example, the first transistor 153 is an NMOS transistor. By adopting an NMOS transistor, the characteristic of low hole carrier mobility can be avoided, thereby increasing the rate at which the storage-computing integrated circuit performs write operations.
[0035] In this embodiment, the first transistor 153 includes a first gate, a first source and a first drain.
[0036] The first gate is used to control the on and off of the first transistor 153 .
[0037] The first source and the first drain are used as a channel for carrier migration of the first transistor 153 .
[0038] In this embodiment, the write operation unit circuit 130 further includes a word line WL, and the word line WL is coupled to the first gate.
[0039] In the write operation unit circuit 130, the word line WL is used to control whether to perform a write operation. When the word line WL is at a high level, it means that a write operation is performed.
[0040] In this embodiment, the write operation unit circuit 130 further includes a bit line BL, and the bit line BL is coupled to the first drain.
[0041] In the write operation unit circuit 130 , the bit line BL is used to transfer data when a write operation is performed.
[0042] When the write operation is not performed, the resistive memory 120 is in a high resistance state HRS. During the write operation, the metal of the active electrode of the resistive memory 120 will be ionized. Under the action of the electric field, the metal ions will migrate and form a conductive channel, thereby turning on the resistive memory 120, which means that the resistive memory 120 is in a low resistance state LRS. When a higher current passes through the resistive memory 120, the resistive memory 120 is in a high resistance state HRS, thereby enabling the resistive memory 120 to freely switch between the high resistance state HRS and the low resistance state LRS.
[0043] In this embodiment, the resistive random access memory 120 includes an active electrode (AE), an inert electrode (IE), and a dielectric layer located between the active electrode and the inert electrode.
[0044] It should be noted that during the write operation, the high level will cause the active electrode to be ionized. Under the action of the electric field, the ions will move from the active electrode through the dielectric layer to the inert electrode, thereby forming a current path between the active electrode and the inert electrode, thereby putting the resistive random access memory 120 in an on state.
[0045] It should also be noted that during the write operation, assuming that the high level is too large, the resistive random access memory 120 in the on state will be blown under the action of Joule, which means that the resistive random access memory 120 is converted from the on state to the off state, that is, the resistive random access memory 120 is converted from the low resistance state LRS to the high resistance state HRS.
[0046] To this end, as an example, during the write operation, the low resistance state LRS of the resistive memory 120 in the storage-computing integrated circuit can be displayed as "0", and the high resistance state HRS of the resistive memory 120 in the storage-computing integrated circuit can be displayed as "1", so that "0" or "1" can be written during the write operation.
[0047] In this embodiment, the active electrode is coupled to the first source of the first transistor 153 .
[0048] Specifically, the active electrode is coupled to the first source of the first transistor 153 , so that the high level loaded on the word line WL and the bit line BL can flow into the resistive memory 120 , thereby realizing the conversion of the resistive memory 120 between “0” and “1”.
[0049] In this embodiment, the material of the active electrode includes active metal.
[0050] Active metals at high levels will produce active ions, which will cause the active ions to migrate under the action of the electric field.
[0051] As an example, the material of the active electrode includes Ag or Au.
[0052] In this embodiment, the material of the inert electrode includes an inert metal.
[0053] Specifically, the inert metal does not generate ions at a high level, and the probability of the metal elements of the inert metal being replaced is very low, so that the inert metal is always in a high resistance state HRS, so that the high resistance state HRS of the resistive random access memory 120 can meet the performance requirements.
[0054] As an example, the material of the inert electrode includes Pt or Al.
[0055] In this embodiment, the write operation unit circuit 130 further includes: a first ground terminal 121 , and the first ground terminal 121 is coupled to the inert electrode.
[0056] Specifically, the first ground terminal 121 is used to protect the write operation unit circuit 130. When leakage or static electricity occurs in the write operation unit circuit 130, the large current generated by the leakage or static electricity can be introduced into the first ground terminal 121, thereby reducing the probability of damage to the storage and computing integrated circuit.
[0057] It should be noted that the read operation unit circuit 150 is used to perform read operations in the SRAM storage unit. At the same time, the read operation unit circuit 150 and the write operation unit circuit 130 are isolated from each other, that is, the storage-computing integrated circuit has a separate write operation path and a read operation path, that is, the storage-computing integrated circuit has the function of read-write separation, thereby improving the stability of the read and write operations of the storage-computing integrated circuit.
[0058] In this embodiment, the read operation unit circuit 150 includes a second transistor 151 and a third transistor 152 coupled to the second transistor 151 .
[0059] The third transistor 152 plays a role of turning on and off in the write operation unit circuit 130. By providing a start voltage or no voltage to the third transistor 152, the third transistor 152 is turned on or off, thereby controlling whether the read operation unit circuit is discharged.
[0060] The second transistor 151 controls whether RBL (i.e., the read bit line) is discharged during the read operation. When a "0" is stored, the second transistor 151 is in a closed state and RBL is not discharged. When a "1" is stored, the second transistor 151 is in a conducting state and RBL is discharged.
[0061] As an example, the second transistor 151 and the third transistor 152 are both NMOS transistors. By adopting NMOS transistors, the characteristic of low hole carrier mobility can be avoided, thereby increasing the speed at which the storage-computing integrated circuit performs read operations.
[0062] In this embodiment, the second transistor 151 includes a second gate, a second source and a second drain, and the third transistor 152 includes a third gate, a third source and a third drain.
[0063] The second gate is used to control the turning on and off of the second transistor 151 .
[0064] The second source and the second drain are used as a channel for carrier migration of the transistor.
[0065] In this embodiment, the third source of the third transistor 152 is coupled to the second drain of the second transistor 151 , so that a current path is formed between the second transistor 151 and the third transistor 152 .
[0066] In this embodiment, the second gate of the second transistor 151 is coupled to the active electrode of the resistive random access memory 120 , so that “0” or “1” stored in the write operation unit circuit 130 can be read during a read operation.
[0067] In this embodiment, the read operation unit circuit 150 further includes a read word line RWL, and the read word line RWL is coupled to the second gate of the third transistor 152 .
[0068] In the write operation unit circuit 130, the word line WL is used to control whether to perform a write operation. When the word line WL is at a high level, the third transistor 152 is turned on, which means that a read operation begins.
[0069] In this embodiment, the read operation unit circuit 150 further includes a read bit line RBL, and the read bit line RBL is coupled to the third drain of the third transistor 152 .
[0070] In the read operation unit circuit 150 , the bit line BL is used to transfer data when a read operation is performed.
[0071] In this embodiment, the read operation unit circuit 150 further includes: a second ground terminal 126 , and the second ground terminal 126 is coupled to the source of the second transistor 151 .
[0072] Specifically, the second ground terminal 126 is used to protect the read operation unit circuit 150. When leakage or static electricity occurs in the read operation unit circuit 150, the large current generated by the leakage or static electricity can be introduced into the second ground terminal 126, thereby reducing the probability of damage to the storage and computing integrated circuit.
[0073] Combination Figure 1 The storage and calculation integrated circuit diagram shown in FIG. 1 takes the case where a write operation writes "0" and a read operation reads "0" as an example. Figure 2 As shown, the waveforms of the word line WL, the bit line BL, the resistive memory 120, the read bit line RBL and the read word line RWL are shown when the write operation writes "0" and the read operation reads "0".
[0074] As an example, during the execution of the write operation and the read operation, the low resistance state LRS of the resistive memory 120 in the storage-computing integrated circuit can be shown as "0", and the high resistance state HRS of the resistive memory 120 in the storage-computing integrated circuit can be shown as "1".
[0075] When the write operation and the read operation process are not performed, the resistive memory 120 is in a high resistance state HRS, and the word line WL, the bit line BL, the read bit line RBL and the read word line RWL are all in a low level state.
[0076] The write operation is first performed by the write operation unit circuit 130 .
[0077] During the write operation, a high level is added to the word line WL and the bit line BL, and the first transistor 153 is turned on. At this time, the high level will cause the active electrode in the resistive random access memory 120 to be ionized. Under the action of the electric field, the ions will move from the active electrode through the dielectric layer to the inert electrode, thereby forming a current path between the active electrode and the inert electrode, thereby putting the resistive random access memory 120 in a conductive state, that is, the resistive random access memory 120 changes from a high resistance state HRS to a low resistance state LRS.
[0078] To do this, write "0" during a write operation.
[0079] The read operation is then performed by the read operation unit circuit 150 .
[0080] The write operation is performed through the write operation unit circuit 130, and a high level is added to the read word line RWL and the read bit line RBL, and the third transistor 152 is turned on. However, since the resistive memory 120 is in the low resistance state LRS, the low resistance state LRS is shown as "0". In the case of "0", the second transistor 151 is in the cut-off state, which means that the read bit line RBL, the third transistor 152 and the second transistor 151 are in a short-circuit state and cannot form a path, so that the high level of the read bit line RBL does not show a downward trend, that is, the read bit line RBL does not discharge and there is no charge fluctuation.
[0081] For this purpose, "0" is read out during a read operation.
[0082] Combination Figure 1 The storage and calculation integrated circuit diagram shown in FIG. 1 takes the case where a write operation writes "1" and a read operation reads "1" as an example. Figure 3 As shown, the waveforms of the word line WL, the bit line BL, the resistive memory 120, the read bit line RBL and the read word line RWL are shown when the write operation writes "1" and the read operation reads "1".
[0083] The specific process of writing "1" for the write operation and reading "1" for the read operation will not be repeated here.
[0084] Correspondingly, an embodiment of the present invention further provides an SRAM memory for product-and-accumulate (MAC) operation.
[0085] Figure 4 It is a schematic diagram of the arrangement of the SRAM memory of the present invention; Figures 5 to 7 It is a schematic diagram of the SRAM memory of the present invention performing in-memory calculations.
[0086] The memory includes: a plurality of storage-computation-in-one circuits provided in the present embodiment arranged in multiple rows and columns; a read word line signal control unit for outputting a drive signal to drive a read operation unit circuit; and a precharge circuit unit for precharging the read operation unit circuit.
[0087] It should be noted that the storage-computing integrated circuit has a write operation unit circuit and a read operation unit circuit, and the write operation unit circuit and the read operation unit circuit are isolated from each other, that is, the storage-computing integrated circuit has a separate write operation path and a read operation path, that is, the storage-computing integrated circuit has the function of read-write separation, thereby improving the read and write operation stability of the SRAM memory. At the same time, compared with the existing storage-computing integrated circuit with read-write functions that includes 6 transistors, the storage-computing integrated circuit of this embodiment only uses three transistors and one resistive memory, thereby reducing the area occupied by the SRAM memory.
[0088] Please refer to the above for the detailed description of the integrated storage and computing circuit, which will not be repeated here.
[0089] In this embodiment, the third transistors each include a third gate, a third source and a third drain.
[0090] The third gate is used to control the turning on and off of the third transistor.
[0091] The third source and the third drain are used as a channel for carrier migration of the transistor.
[0092] In this embodiment, the read operation unit circuit further includes: a read word line, and the read word line is coupled to the third gate of the third transistor.
[0093] In the write operation unit circuit, the word line is used to control whether to perform a write operation. When the word line is at a high level, the third transistor is turned on, which means that the read operation begins.
[0094] In this embodiment, the read operation unit circuit further includes: a read bit line, and the read bit line is coupled to the third drain of the third transistor.
[0095] In the read operation unit circuit, the bit line is used to transfer data when performing a read operation.
[0096] The read word line signal control unit is used to output a driving signal to drive the read operation unit circuit, and provide a periodic voltage signal for the read operation unit circuit.
[0097] As an example, the read word line signal control unit is electrically connected to the read word line, so that the read word line signal control unit can perform a read operation on the SRAM memory through the read word line.
[0098] In this embodiment, each row has a plurality of the storage-and-calculation-in-one circuits, and the read word lines of the plurality of the storage-and-calculation-in-one circuits in the same row are the same word line.
[0099] It should be noted that each row has multiple storage-computation-in-one circuits, and the read word lines of the multiple storage-computation-in-one circuits in the same row are the same word line, so that the read word line signal control unit can simultaneously control the multiple storage-computation-in-one circuits through the same word line, and then perform multiple read operations at the same time. At the same time, by simultaneously controlling multiple storage-computation-in-one circuits through the same word line, the area occupied by the SRAM memory is saved.
[0100] The precharge circuit unit is used to precharge the read operation unit circuit.
[0101] In this embodiment, the precharge circuit unit is electrically connected to the read bit line, and the precharge circuit unit precharges the read bit line.
[0102] As an example, each column has a plurality of the integrated storage and calculation circuits, and the read bit lines of the plurality of integrated storage and calculation circuits in the same column are the same bit line.
[0103] It should be noted that each column has multiple storage-computation-in-one circuits, and the read word lines of the multiple storage-computation-in-one circuits in the same column are the same bit line, so that the pre-charging circuit unit can simultaneously control the multiple storage-computation-in-one circuits for pre-charging through the same bit line, and then perform multiple read operations at the same time. At the same time, by simultaneously controlling multiple storage-computation-in-one circuits through the same bit line, the area occupied by the SRAM memory is saved.
[0104] As an example, the read bit line has an input terminal and an output terminal, and the precharge circuit unit is connected to the input terminal.
[0105] In this embodiment, the SRAM memory further includes: a charge sharer, which is connected to the output end of the read bit line and is used to collect the charge signal on the read bit line.
[0106] The charge signal on the read bit line is collected by a charge sharer to obtain the voltage signals of multiple storage-computation integrated circuits on each column.
[0107] In this embodiment, the SRAM memory further includes: an analog-to-digital converter, which is connected to the charge sharer and is used to convert the charge signal collected by the charge sharer into a digital signal.
[0108] Specifically, the voltage signal collected by the charge sharer is converted into a digital signal, so that the SRAM memory can output a digital signal.
[0109] like Figure 5 As shown, a schematic diagram of an SRAM memory with multiple storage-computation-in-one circuits arranged in 2×2 for in-memory calculation is shown.
[0110] like Figure 5 As shown, Input represents the input value of the read word line (RWL), that is, whether the read word line is in a high level state or a low level state, the high level state represents "1", and the low level state represents "0".
[0111] Weight represents whether the resistive memory is in a high resistance state or a low resistance state, that is, the resistive memory is "0" or "1".
[0112] Specifically, the product-and-accumulate operation (MAC) refers to multiplying first and then summing, that is, each storage-and-calculation circuit first performs a product operation on itself, and then the product operation values of each storage-and-calculation circuit are summed.
[0113] like Figure 6 As shown, a tabular schematic diagram of in-memory calculations performed by multiple storage-computation-in-one circuits arranged in 2×2 is shown.
[0114] Specifically, when Input is "1" and Weight is also "1", the multiplication value is "1", and in all other cases it is "0".
[0115] By summing up the product operation values of each integrated storage and calculation circuit, it can be concluded that when multiple integrated storage and calculation circuits arranged in 2×2 are performing in-memory calculations, the product and cumulative operation value is "1".
[0116] In other embodiments, there may be a plurality of storage-computation-in-one circuits arranged in 2×3, a plurality of storage-computation-in-one circuits arranged in 3×3, a plurality of storage-computation-in-one circuits arranged in 4×4, and so on.
[0117] like Figure 7 As shown, a schematic diagram of multiple storage-computation integrated circuits arranged in a row of SRAM memories performing in-memory calculations is shown.
[0118] The read word line is in a high state or a low state, the high state represents "1" and the low state represents "0".
[0119] The resistive memory is in a high resistance state or a low resistance state, that is, the resistive memory is "0" or "1".
[0120] Specifically, the product-and-accumulate operation (MAC) is to perform product first and then sum, that is, each storage-and-calculation circuit first performs a product operation on itself, and then the product operation values of each storage-and-calculation circuit are summed.
[0121] like Figure 7 As shown, in the process of performing in-memory calculations on multiple storage-computation-in-one circuits arranged in a column, each storage-computation-in-one circuit first performs a product operation on itself. Specifically, when the read word line is "1" and the resistive memory is also "1", the multiplication operation value is "1", which means that the read bit line of the storage-computation-in-one circuit has a discharge behavior. The rest of the cases are "0", that is, the read bit line is not discharged, so that the same read bit line (RWL) in a column can be used to sum and calculate the charge change value on the read bit line in the multiple storage-computation-in-one circuits arranged in a column.
[0122] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A storage and computing integrated circuit, characterized in that: include: A write operation unit circuit, comprising a first transistor and a resistive memory coupled to the first transistor; The read operation unit circuit coupled to the write operation unit circuit includes a second transistor and a third transistor coupled to the second transistor, and the coupling point between the second transistor and the resistive memory, the coupling point between the first transistor and the second transistor, and the coupling point between the first transistor and the resistive memory are the same coupling point.
2. The storage-computation-in-one circuit according to claim 1, characterized in that: The first transistor includes a first gate, a first source and a first drain; The write operation unit circuit further includes: a word line and a bit line, the word line is coupled to the first gate, and the bit line is coupled to the first drain.
3. The storage-computation-in-one circuit according to claim 2, characterized in that: The resistive random access memory comprises an active electrode, an inert electrode, and a dielectric layer located between the active electrode and the inert electrode; The active electrode is coupled to a first source of the first transistor; The write operation unit circuit further includes: a first ground terminal coupled to the inert electrode.
4. The storage-computation-in-one circuit according to claim 3, characterized in that: The second transistor includes a second gate, a second source and a second drain; the third transistor includes a third gate, a third source and a third drain; A third source of the third transistor is coupled to a second drain of the second transistor; The second gate of the second transistor is coupled to the active electrode of the resistive memory; The read operation unit circuit further includes: a read word line and a read bit line, the read word line is coupled to the third gate of the third transistor, and the read bit line is coupled to the third drain of the third transistor; A second ground terminal is coupled to a second source of the second transistor.
5. The storage-computation-in-one circuit according to claim 3, characterized in that: The material of the active electrode includes active metal; the material of the inert electrode includes inert metal.
6. The storage-computation-in-one circuit according to claim 3, characterized in that: The material of the active electrode includes Ag or Au; the material of the inert electrode includes Pt or Al.
7. The storage-computation-in-one circuit according to claim 1, characterized in that: The first transistor, the second transistor and the third transistor are all NMOS transistors.
8. A SRAM memory for product and accumulation operations, characterized in that: include: A plurality of integrated storage and computing circuits as claimed in any one of claims 1 to 7 arranged in a plurality of rows and columns; A read word line signal control unit, used to output a drive signal to drive a read operation unit circuit; The precharge circuit unit is used to precharge the read operation unit circuit.
9. The SRAM memory according to claim 8, wherein: The third transistor includes a third gate, a third source and a third drain; The read operation unit circuit further includes: a read word line, the read word line is coupled to the third gate of the third transistor; a read bit line, the read bit line is coupled to the third drain of the third transistor; The read word line signal control unit is electrically connected to the read word line; The precharge circuit unit is electrically connected to the read bit line, and the precharge circuit unit precharges the read bit line.
10. The SRAM memory according to claim 9, wherein: Each row has a plurality of the storage-and-calculation-in-one circuits, and the read word lines of the plurality of the storage-and-calculation-in-one circuits in the same row are the same word line.
11. The SRAM memory according to claim 9, wherein: Each column has a plurality of the storage-and-calculation integrated circuits, and the read bit lines of the plurality of the storage-and-calculation integrated circuits in the same column are the same bit line.
12. The SRAM memory according to claim 9, wherein: The read bit line has an input end and an output end, and the precharge circuit unit is connected to the input end; The SRAM memory further comprises: a charge sharer, the charge sharer is connected to the output end of the read bit line, and the charge sharer is used to collect the charge signal on the read bit line; An analog-to-digital converter is connected to the charge sharer and is used to convert the charge signal collected by the charge sharer into a digital signal.