Chip and internal eFuse programming power supply providing circuit and programming method thereof

Abstract

The invention provides a chip, an eFuse programming power supply providing circuit in the chip and a programming method, which are applied to the technical field of integrated circuits and eFuses, and a controlled switching circuit is additionally arranged between an eFuse programming power supply end and a chip power supply end. According to the invention, one controlled switch circuit is additionally arranged between an eFuse programming power supply end and a multiplexed low-voltage interface, and another controlled switch circuit is additionally arranged between the eFuse programming power supply end and the multiplexed low-voltage interface, so that a programming power supply or a working power supply is correspondingly provided for eFuse by utilizing a high-voltage power supply and a working power supply outside the chip through the connection or disconnection of the two controlled switch circuits, and the chip can be used for programming the eFuse under the condition of not occupying too much chip pins. And the high-voltage power supply and the working power supply required by eFuse programming in the chip can be provided in a low-cost manner, so that the high-voltage power supply and the working power supply are very suitable for being popularized and applied in various chips containing eFuse.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits and electronic fuses (eFuse), and in particular to a chip and an internal eFuse programming power supply circuit and a programming method thereof. Background Art

[0002] eFuse (electronic fuse) is a programmable fuse technology commonly used in integrated circuit (IC) design. Inside the chip, eFuse usually requires a higher power supply voltage than other circuits to complete the programming. For example, for a digital circuit with a 5V standard BCD process with eFuse, a voltage range of 3 to 5.5V is generally required for normal operation. When programming eFuse, the eFuse programming power supply needs to be raised to more than 8V.

[0003] To address the need for a higher power supply voltage when programming eFuse, traditional solutions mainly include the following methods: First, a separate chip PAD is required to implement this function, so that programming can only be performed during the wafer probe test (Chip Probe); second, a separate pin needs to be reserved for eFuse programming after the chip packaging is completed, but some chips do not have extra pins available; third, a high-voltage PIN pin needs to be reused, and eFuse programming can be performed after the chip packaging is completed, which requires the use of high-voltage devices and consumes a large amount of chip circuit area. Summary of the invention

[0004] In view of this, the present application provides a chip and its internal eFuse burning power supply circuit and burning method, which provides burning power for the eFuse burning inside the chip by reusing low-voltage interface pins. The circuit structure is simple, occupies a small area, and is easy to implement inside the chip.

[0005] This application provides the following technical solutions: The present application provides a chip internal eFuse burning power supply providing circuit, including: a low voltage interface, a first switch circuit and a second switch circuit; the first switch circuit is connected in series between the low voltage interface and the burning power supply port, and the second switch circuit is connected in series between the chip power supply end and the burning power supply port; wherein the burning power supply port is a port in the chip that provides power for the eFuse; the low voltage interface is used to connect to the high voltage power supply when the eFuse inside the chip needs to be burned, and serves as the IO of the chip when the eFuse inside the chip does not need to be burned; the first switch circuit is used to turn on or off under the control of a first signal to connect or disconnect the connection between the low voltage interface and the burning power supply port. The second switch circuit is used to turn on or off under the control of the second signal to connect or disconnect the connection between the chip power supply terminal and the burning power supply port, wherein when the eFuse inside the chip needs to be burned, the first signal controls the first switch circuit to turn on, and the second signal controls the second switch circuit to turn off, so that the high-voltage power supply connected to the low-voltage interface is input to the burning power supply terminal to provide the eFuse with the voltage required for burning, and when the chip eFuse does not need to be burned, the first signal controls the first switch circuit to turn off, and the second signal controls the second switch circuit to turn on, so that the voltage at the chip power supply terminal is input to the burning power supply terminal to provide the eFuse with the voltage required for normal operation.

[0006] Preferably, the first switch circuit comprises a first MOS tube, a gate of the first MOS tube inputs the first signal, a drain of the first MOS tube is connected to the low voltage interface, and a source of the first MOS tube is connected to the programming power supply terminal; And / or, the second switch circuit includes a second MOS tube, a gate of the second MOS tube inputs the second signal, a drain of the second MOS tube is connected to the chip power supply terminal, and a source of the second MOS tube is connected to the programming power supply terminal.

[0007] Preferably, the first switch circuit further includes a fourth MOS tube and a first resistor, wherein the gate of the first MOS tube inputs the first signal, the drain of the first MOS tube is connected to the gate of the fourth MOS tube, the source of the first MOS tube is grounded, the drain of the fourth MOS tube is connected to the low voltage interface, the source of the fourth MOS tube is connected to the programming power supply terminal, and the first resistor is connected between the gate and the source of the fourth MOS tube; And / or, the second switch circuit also includes a third MOS tube and a second resistor, wherein the gate of the second MOS tube inputs the second signal, the drain of the second MOS tube is connected to the gate of the third MOS tube, the source of the second MOS tube is grounded, the drain of the third MOS tube is connected to the chip power supply terminal, the source of the third MOS tube is connected to the programming power supply terminal, and the second resistor is connected between the gate and source of the third MOS tube.

[0008] Preferably, the fourth MOS transistor and / or the third MOS transistor is a MOS transistor including a body diode, so as to utilize the body diode to block the path after the MOS is turned off.

[0009] Preferably, the first switch circuit further includes a fifth MOS tube, wherein the drain of the first MOS tube is connected to the gate of the fourth MOS tube and the gate of the fifth MOS tube, the source of the fourth MOS tube is connected to the source of the fifth MOS tube, and the drain of the fifth MOS tube is connected to the programming power supply terminal; And / or, the first switch circuit further includes a voltage stabilizing diode, which is connected between the gate and source of the fourth MOS tube to clamp the voltage of the gate and source of the fourth MOS tube.

[0010] Preferably, the fifth MOS transistor is a MOS transistor including a body diode, so as to utilize the body diode to block the path after the MOS is turned off.

[0011] Preferably, the first switch circuit further includes a third resistor, which is connected in series between the source of the first MOS tube and the ground, so that the operating current of the voltage regulator diode is within a preset range.

[0012] Preferably, the chip internal eFuse burning power supply circuit described in any one of the present applications further includes an inverter, and the inverter is used to provide a first signal and a second signal with opposite phases.

[0013] The present application also provides a method for burning eFuse inside a chip, including: When the internal eFuse of the chip needs to be burned, the high-voltage power supply required for burning is connected to the low-voltage interface in the internal eFuse burning power supply circuit of the chip as described in any one of the present applications, and by configuring the first signal and the second signal, the burning power supply port in the internal eFuse burning power supply circuit of the chip as described in any one of the present applications is connected to the low-voltage interface and disconnected from the chip power supply terminal, so that the eFuse uses the high-voltage power supply connected to the low-voltage interface to perform the burning operation; After the eFuse is burned, the high voltage power supply is disconnected from the low voltage interface, and by configuring the first signal and the second signal, the burning power supply port is disconnected from the low voltage interface and connected to the chip power supply terminal, so that the eFuse can work normally using the power supply voltage provided by the chip power supply terminal.

[0014] The present application also provides a chip, which includes an eFuse and an eFuse burning power supply circuit, wherein the eFuse burning power supply circuit is an internal eFuse burning power supply circuit of the chip as described in any one of the items in the present application.

[0015] Compared with the prior art, the beneficial effects that can be achieved by at least one of the above technical solutions adopted in the present application include at least: The present application reuses low-voltage IO and adds corresponding switching circuits inside the chip, and uses a high-voltage power supply independent of the outside of the chip to provide the required burning power for the eFuse burning inside the chip. It is a new circuit architecture solution with low cost and small circuit area. It can consume a very small chip area without occupying too many chip pins, and provide the high-voltage power required for burning the eFuse inside the chip in a low-cost manner. It is very suitable for promotion and application in various chips containing eFuse. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 It is a schematic diagram of the structure of the eFuse burning power supply circuit inside the chip in this application; Figure 2 It is a schematic diagram of the structure of the chip internal eFuse burning power supply circuit based on a single MOS tube in this application; Figure 3 It is a structural schematic diagram of a chip internal eFuse burning power supply circuit based on multiple MOS tubes in this application; Figure 4 It is a structural schematic diagram of a chip internal eFuse burning power supply circuit based on multiple MOS tubes in this application; Figure 5 It is a schematic diagram of the structure of the chip internal eFuse programming power supply circuit using clamping and current limiting protection in this application; Figure 6 It is a flowchart of the method for burning eFuse inside the chip in this application. DETAILED DESCRIPTION

[0018] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0019] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0020] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspect described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0021] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0022] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the examples can be practiced without these specific details.

[0023] As analyzed above, some traditional methods have their own limitations and cannot adapt to the current chip's flexible burning needs for electronic fuses (eFuse). For example, the eFuse burning method can only be performed during the wafer testing stage, and general chips often no longer use this method, so this method is only used in chips with special applications; for example, because the reuse of high-voltage PIN pins requires a large circuit area, and the circuit area of ​​the chip is a very important chip design indicator, the practice of reusing high-voltage PIN pins can only be used for chips that do not have strict design requirements for the circuit area; for example, the practice of reserving a separate pin to provide a burning power supply, because the chip pin resources are a relatively scarce chip resource, this method can only be limited to individual chip designs, and it also cannot meet the current chip's requirements for flexibility.

[0024] In view of this, through in-depth research and improvement exploration on the power supply required for eFuse burning of the chip, as well as the chip area, resources, etc., it is found that: in the chip, the input and output interfaces working at a lower voltage (referred to as low-voltage interfaces in this application, also called low-voltage IO, without distinction) are some necessary resources that each chip has, and at least some or all of these IOs usually have multiplexing capabilities, that is, the chip design can make the IO work in different modes to achieve multiplexing functions.

[0025] In other words, if a low-voltage interface in the chip can be reused to provide high-voltage power for eFuse burning, that is, to provide the high-voltage power required for eFuse burning operations inside the chip, flexibility will be completely changed and improved.

[0026] Based on this, the present application proposes a circuit architecture solution that provides programming power for the eFuse inside the chip from outside the chip by multiplexing low-voltage interface pins: Figure 1 As shown, a controlled switch circuit (denoted as S2) is added between the eFuse burning power supply terminal (denoted as V_fuse) and the chip power supply terminal (denoted as VDD), and another controlled switch circuit (denoted as S1) is added between the eFuse burning power supply terminal V_fuse and the reused low-voltage interface (denoted as V_IO), so as to provide working power or burning power for the eFuse by controlling the conduction or shutdown of S1 and S2.

[0027] Specifically, when S1 is turned on and S2 is turned off, the high voltage power supply connected to the low voltage interface V_IO (i.e., the higher voltage power supply required for eFuse burning, because the high voltage power supply is located outside the chip, Figure 1The high voltage power supply is not shown in the figure) is input to the programming power supply terminal V_fuse, thereby providing the power required for programming for the eFuse; when S1 is turned off and S2 is turned on, the chip working power connected to VDD (that is, the lower voltage power required for the normal operation of the eFuse) is input to V_fuse, thereby providing the working power for the eFuse.

[0028] By adding two controlled switch circuits S1 and S2 in the chip, since the switch circuit can use a semiconductor electronic switch, and the electronic switch only needs to complete the basic function of on or off to connect the power required by the eFuse (i.e., the programming power supply or the working power supply), that is, the electronic switch only needs to realize reliable on or off functions, and does not need to realize complex circuit functions, so the area occupied by the switch circuit on the chip can generally be very small. In addition, the power required for eFuse programming is provided from the outside of the chip by reusing the low-voltage IO, that is, when the programming power supply is required, the higher voltage programming power supply is connected to the low-voltage IO to provide the higher voltage power required for the eFuse programming, and after the eFuse programming is completed (i.e., no programming is required), the programming power supply can be disconnected from the low-voltage IO, so the programming power supply can be independent of the outside of the chip, that is, the programming power supply does not need to occupy the internal area of ​​the chip, avoiding the overhead of increasing the chip area by integrating the programming power supply inside the chip.

[0029] It should be noted that the low-voltage IO is a multiplexed IO pin in the chip, and the external high-voltage power supply connected to the low-voltage IO is used to provide the power supply voltage required for burning the eFuse inside the chip.

[0030] In summary, the technical solution provided by the present application occupies a very small chip area, so that it can flexibly meet the various internal chip designs of the chip and meet the design requirements of the chip flexibly providing burning power for eFuse, and well meet the flexibility requirements of the chip providing burning power for eFuse.

[0031] The technical solutions provided by various embodiments of the present application are described below in conjunction with the accompanying drawings.

[0032] like Figure 1 As shown, the present application provides a chip internal eFuse burning power supply circuit, including: a low voltage interface (denoted as V_IO), a first switch circuit (denoted as S1) and a second switch circuit (denoted as S2). Since the low voltage interface is the IO resource of the chip itself, when providing burning power for the eFuse, only the first switch circuit S1 and the second switch circuit S2 need to be added inside the chip, which has a small circuit area overhead and is convenient for design and application inside the chip.

[0033] refer to Figure 1The circuit connection diagram of the programming power supply circuit is as follows: the first switch circuit S1 is connected in series between the low voltage interface (recorded as V_IO) and the programming power port (recorded as V_fuse), and the second switch circuit S2 is connected in series between the chip power terminal (recorded as VDD) and the programming power port V_fuse. Among them, the first switch circuit S1 is used to turn on or off under the control of the first signal (recorded as Signal1) to connect or disconnect the connection between the low voltage interface V_IO and the programming power port V_fuse, and the second switch circuit S2 is used to turn on or off under the control of the second signal (recorded as Signal2) to connect or disconnect the connection between the chip power terminal VDD and the programming power port V_fuse accordingly.

[0034] It should be pointed out that the power port V_fuse is the eFuse in the chip ( Figure 1 The low-voltage interface V_IO is a type of input-output interface (IO) used for low-voltage operation in the chip. Here, the interface is multiplexed as follows: when the eFuse inside the chip needs to be programmed, it is used to access the high-voltage power supply (i.e., a higher voltage power supply. Because the programming voltage of the eFuse is often higher than the working voltage, the high-voltage power supply required for programming is provided to the eFuse from outside the chip through the multiplexed low-voltage IO. When the eFuse inside the chip does not need to be programmed, the low-voltage IO is restored to the general IO of the chip.

[0035] refer to Figure 1 The working principle of the circuit is as follows: when the eFuse inside the chip needs to be burned, the first signal Signal1 controls the first switch circuit S1 to be turned on, and the second signal Signal2 controls the second switch circuit S2 to be turned off, so that the high voltage power supply ( Figure 1 The first signal Signal1 controls the first switch circuit S1 to turn off, and the second signal Signal2 controls the second switch circuit S2 to turn on, so that the voltage of the chip power supply terminal VDD is input to the programming power supply terminal V_fuse, so as to provide the eFuse with the voltage required for normal operation.

[0036] In summary, by reusing low-voltage IO, only a switching circuit for turning on or off needs to be added inside the chip to realize that the eFuse burning power supply is independently provided from outside the chip, which significantly reduces the circuit area occupied by the eFuse burning power supply circuit inside the chip. This allows each chip (i.e., containing eFuse) to very conveniently use the technical solution provided by the present application to provide the high-voltage power required for burning the eFuse inside the chip, thereby improving the flexibility of design and application of the eFuse burning power supply circuit inside the chip.

[0037] In some implementations, a MOS tube is used to form a switch circuit, thereby utilizing the characteristics of the MOS tube having low on-resistance and high off-resistance to achieve switch performance.

[0038] In implementation, one or more MOS tubes are used as core components of the switch circuit, so that the switch circuit occupies a smaller chip area while meeting the switch performance.

[0039] In an example, the first switch circuit S1 is implemented by a MOS transistor, and / or the second switch circuit S2 is implemented by a MOS transistor.

[0040] refer to Figure 2 As shown in the figure, the first switch circuit S1 includes a first MOS tube M1, wherein the gate of M1 inputs the first signal Signal1, the drain is connected to the low voltage interface V_IO, and the source is connected to the programming power supply terminal V_fuse. Therefore, under the control of Signal1, M1 is turned on or off accordingly, thereby realizing the connection or disconnection between the low voltage interface V_IO and the programming power supply interface V_fuse accordingly.

[0041] refer to Figure 2 As shown in the figure, the second switch circuit S2 includes a second MOS tube M2, wherein the gate of M2 inputs the second signal, the drain is connected to the chip power supply terminal VDD, and the source is connected to the programming power supply terminal V_fuse. Therefore, under the control of Signal2, M2 is turned on or off accordingly, thereby realizing the connection or disconnection between the chip power supply terminal VDD and the programming power supply interface V_fuse.

[0042] It should be noted that when the eFuse inside the chip needs to be burned, M1 is turned on and M2 is turned off, so that a path is formed between the low-voltage interface V_IO and the burning power supply terminal V_fuse, and a circuit is formed between the chip power supply terminal VDD and the burning power supply terminal V_fuse. When the external high-voltage power supply is connected to V_IO, the high-voltage power supply can be applied to the eFuse inside the chip, so that the eFuse can use the high-voltage power supply for burning. In addition, since M2 is in the off state, the high-voltage power supply will not be applied to the chip power supply terminal VDD; conversely, that is, the eFuse inside the chip does not need to be burned, then M1 When M1 is turned off and M2 is turned on, a path is formed between the chip power supply terminal VDD and the programming power supply terminal V_fuse, and a circuit is broken between the low-voltage interface V_IO and the programming power supply terminal V_fuse. When the chip power supply terminal VDD is connected to the working power supply, the working power supply can be applied to the eFuse inside the chip, so that the eFuse can work normally using the working power supply. In addition, since M1 is in the off state, the working power supply will not be applied to the low-voltage interface V_IO. Even if the high-voltage power supply is still connected to the low-voltage interface V_IO, since M1 is turned off, the high-voltage power supply will not affect the eFuse inside the chip.

[0043] In an example, the first switch circuit S1 is implemented by using a plurality of MOS transistors, and / or the second switch circuit S2 is implemented by using a plurality of MOS transistors.

[0044] In implementation, the switch circuit includes a MOS tube for power supply and a MOS tube for control, thereby improving the overall performance of the switch circuit with a small increase in chip area overhead.

[0045] refer to Figure 3 As shown, the first switch circuit S1 further includes a fourth MOS tube M4 and a first resistor R1. That is, the core components of the first switch circuit S1 are two MOS tubes M1 and M4, where M4 is used as a switch tube on the path, M1 is used as a control tube of M4, and R1 is used as a bias resistor between the gate and the source of M4.

[0046] The circuit connection diagram is as follows: the gate of M1 inputs the first signal Signal1, the drain of M1 is connected to the gate of M4, the source of M1 is grounded, the drain of M4 is connected to the low voltage interface V_IO, the source of M4 is connected to the programming power supply terminal V_fuse, and R1 is connected between the gate and source of M4.

[0047] The working principle is as follows: the gate of M1 is controlled by Signal1. When M1 is turned on, the gate of M4 is pulled down, so that M4 is stably turned on under the action of R1. At this time, a path is formed between the low-voltage interface V_IO and the programming power supply terminal V_fuse; conversely, when M1 is turned off, the gate of M4 is pulled high, so that M4 is stably turned off under the action of R1. At this time, a circuit is formed between the low-voltage interface V_IO and the programming power supply terminal V_fuse.

[0048] Similarly, the second switch circuit also adopts a switch circuit form of a switch tube and a control tube.

[0049] refer to Figure 3 As shown, the second switch circuit S2 further includes a third MOS tube M3 and a second resistor R2. That is, the core components of the second switch circuit S2 are two MOS tubes M2 and M3, wherein M3 is used as a switch tube on the path, M2 is used as a control tube of M3, and R2 is used as a bias resistor between the gate and the source of M3.

[0050] The circuit connection diagram is as follows: the gate of M2 inputs the second signal Signal2, the drain of M2 is connected to the gate of M3, the source of M2 is grounded, the drain of M3 is connected to the chip power supply terminal VDD, the source of M3 is connected to the programming power supply terminal V_fuse, and R2 is connected between the gate and source of M3.

[0051] The working principle is as follows: the gate of M2 is controlled by Signal2. When M2 is turned on, the gate of M3 is pulled down, so that M3 is stably turned on under the action of R2, and a path is formed between the chip power supply terminal VDD and the programming power supply terminal V_fuse; conversely, when M2 is turned off, the gate of M3 is pulled up, so that M3 is stably turned off under the action of R2, and a circuit is formed between the chip power supply terminal VDD and the programming power supply terminal V_fuse.

[0052] In summary, the switch tube in the path is used to provide a good performance on or off function, and the control tube is used to realize on or off control of the switch tube, which further improves the on and off performance while spending a small amount of chip area (that is, the chip area of ​​one more MOS tube), and the circuit reliability is higher.

[0053] In some embodiments, a MOS tube located in the path can have a reverse diode added between the drain and the source, wherein the diode can be an external diode connected in parallel between the drain and the source, or the body diode of the MOS tube itself can be used, thereby utilizing the reverse bias cutoff characteristics of the diode to enhance the turn-off performance between the drain and the source of the MOS tube.

[0054] refer to Figure 3In the example, a diode is connected in parallel between the drain and source of M4 and / or M3, or M4 and / or M3 is a MOS tube including a body diode, so as to utilize the reverse cutoff characteristic of the diode to further block the path after the MOS is turned off, that is, the diode is utilized to further improve the cutoff performance between the drain and the source of the MOS tube in the off state. For example, when M3 is turned off, the high voltage from V_IO to V_fuse is in reverse bias due to the diode between the drain and the source of M3, so the turn-off performance of M3 is better at this time. Similarly, the diode on M4 is used to enhance the turn-off performance of M4.

[0055] In some implementations, for the switch tube on the path, a plurality of MOS tubes may be used to form a circuit form of the switch tube.

[0056] refer to Figure 4 As shown, the first switch circuit S1 further includes a fifth MOS tube M5, that is, in the path of the first switch circuit S1, the core components are two MOS tubes M4 and M5, wherein the two MOS tubes M4 and M5 form a switch tube circuit with better turn-off characteristics.

[0057] The circuit connection diagram is as follows: the drain of M1 is connected to the gate of M4 and the gate of M5, the source of M4 is connected to the source of M5, and the drain of M5 is connected to the programming power supply terminal V_fuse.

[0058] The working principle is as follows: when the chip is in normal working mode, that is, eFuse does not need to be burned, M2 is turned on (i.e., turned on) under the control of Signal2, and M1 is turned off (i.e., turned off) under the control of Signal1, thereby pulling down the gate potential V1 of M3, so that M3 is turned on. At this time, the voltage of the chip working power supply terminal VDD is provided to the eFuse burning power supply terminal V_fuse; when the chip is in the burning mode, that is, eFuse needs to be burned, M2 is closed under the control of Signal2, and M1 is turned on under the control of Signal1. At this time, the gate-source voltage of M3 is set to 0 by the initial resistor R2 and cannot be turned on, and M1 pulls down the gate voltage V2 of M4 and M5, so that M4 and M5 are turned on, and the voltage V_IO of the low-voltage IO pin is provided to V_fuse, that is, the external power supply is provided to V_fuse as the voltage required for eFuse burning by multiplexing the chip IO pin.

[0059] In some embodiments, similar to the aforementioned example, a reverse diode is provided between the drain and source of M5, or the body diode of M5 itself is utilized (i.e., M5 is a MOS tube with a body diode), so that when the MOS tube is turned off, the diode is reverse biased and cut off, thereby making the path cutoff performance after being turned off better.

[0060] In one example, during normal operation, Signal1 is low and M1 is turned off. At this time, the initial resistance makes V2=V3, and the channels of M4 and M5 cannot be turned on. In addition, the parasitic body diodes of M4 and M5 form a back-to-back structure, blocking the path from V_IO to V_fuse. In addition, Signal2 is high, M5 is turned on, and the gate voltage V1 of M3 is pulled down to 0, and the channel of M3 is turned on. At this time, V_fuse=VDD, and the chip power supply VDD directly provides the operating voltage for the eFuse.

[0061] When eFuse programming is required, Signal1 is high, M4 is turned on, the gate voltage V2 of M1 and M2 is pulled down, then the channels of M1 and M2 are turned on, V_fuse=V_IO, and the voltage V_IO of the multiplexed IO pin provides the power supply voltage for eFuse. At this time, the voltage of the IO pin can be raised to the voltage required for eFuse programming outside the chip. In some implementations, a voltage regulator tube may be added to the switch tube in the path to maintain the stability and clamping of the gate-source voltage, so that the MOS tube can work more stably and reliably.

[0062] refer to Figure 5 As shown, the first switch circuit S1 further includes a voltage stabilizing diode D1, so that D1 is used to provide a stable gate-source voltage for M4 and / or M5. D1 is connected across the gate and source of M4 to clamp the voltage of the gate and source of M4 to achieve voltage stabilization protection.

[0063] In some implementations, corresponding current limiting resistors may be added to the switch tubes on the path so that the operating current of the switch tubes on the path is set within a suitable range.

[0064] For example, for a circuit with a voltage-stabilizing diode D1 added, a current-limiting resistor is added to the control tube M1. Specifically, the first switch circuit S1 further includes a third resistor R3, wherein R3 is connected in series between the source of M1 and the ground, so that R3 is used to set the working current of the voltage-stabilizing diode D1 to be within a suitable preset range, thereby allowing the voltage-stabilizing diode D1 to stably provide clamping voltage-stabilizing protection for M4.

[0065] The working principle is as follows: When the eFuse needs to be burned, M4 is turned on (see the previous example, M1 is turned on, so M4 is turned on), V3 = V_IO, and due to the clamping Zener diode D1, V2 = V_IO-V D1 , where V D1 is the voltage drop of the Zener diode D1. In order to prevent the current of D1 from being too large, a current limiting resistor R3 is added from the source of the switch tube M1 to the ground. At this time, the current of D1 is limited to (V Signal1 -VGS_M1 ) / R3. In addition, Signal2 is low, M2 is turned off, and the initial resistance R2 makes the gate potential V1 of M3 equal to V_fuse=V_IO. Note that V_IO is generally greater than VDD, so the channel of M3 cannot be turned on. In addition, the diode of M3 is connected from VDD to V_fuse, so the diode is also blocked at this time, and no current path can be formed between VDD and V_fuse.

[0066] When eFuse does not need to be burned, M4 and M5 are turned off, and the parasitic body diodes of M4 and M5 form a back-to-back structure, further blocking the path from V_IO to V_fuse. In addition, Signal2 is high, M2 is turned on, and the gate voltage V1 of M3 is pulled down to 0, and the channel of M3 is turned on, then V_fuse = VDD, and the chip working power supply VDD directly provides the working voltage for the eFuse.

[0067] In some implementations, since the first signals Signal1 and Signal2 are used to control the working states of M1 and M2, and the working states of M1 and M2 are opposite, the same control signal can be used to obtain Signal1 and Signal2 through an inverter, further reducing the chip area occupied by the signal circuit.

[0068] The chip internal eFuse burning power supply providing circuit described in any one of the present applications generates the same signal into inverted Signal1 and Signal2 by using an inverter, that is, the inverter is used to provide a first signal and a second signal with opposite phases.

[0069] In some examples, Signal1 and Signal2 can be generated by soft signals or by setting external IO levels. For example, when using external IO levels to configure Signal1 and Signal2, when eFuse programming is required, the external IO corresponding to Signal1 is set to the corresponding level, such as Signal1 is a high level that turns on M1 of the NMOS tube, and on the contrary, the external IO corresponding to Signal2 is set to a low level that turns off M2 of the NMOS tube. For example, when using an inverter to generate Signal1 and Signal2, they can be obtained by setting the same external IO to a low level or a high level.

[0070] Based on the same inventive concept, the present application also provides a method for burning eFuse inside a chip. By utilizing the burning power supply circuit provided by the present application, the burning method can very conveniently burn the eFuse inside the chip.

[0071] refer to Figure 6 Schematic diagram of a method for programming eFuse inside a chip, comprising: Step S202, determine the working mode of the chip: when the chip is in the eFuse burning mode, that is, when the eFuse inside the chip needs to be burned, execute step S204, otherwise execute step S206.

[0072] Step S204, when the internal eFuse of the chip needs to be burned, that is, the chip is in the eFuse burning mode, the high-voltage power supply required for burning is connected to the low-voltage interface (referred to as low-voltage IO in this application, recorded as V_IO) in the internal eFuse burning power supply circuit of the chip as described in any one of the present applications, and by configuring the first signal and the second signal, the burning power supply port in the internal eFuse burning power supply circuit of the chip as described in any one of the present applications is connected to the low-voltage interface and disconnected from the chip power supply end respectively, so that the eFuse uses the high-voltage power supply connected to the low-voltage interface to perform the burning operation.

[0073] Step S206, the chip is not in the eFuse burning mode (i.e., in the normal working mode). For example, after the eFuse is burned, the high voltage power supply is disconnected from the low voltage interface, and by configuring the first signal and the second signal, the burning power supply port is correspondingly disconnected from the low voltage interface and connected to the chip power supply terminal, so that the eFuse can work normally using the power supply voltage provided by the chip power supply terminal.

[0074] It should be noted that an external high-voltage power supply (also referred to as a programming power supply) independent of the chip and a chip working power supply are each provided to the programming power supply terminal V_fuse. Please refer to the aforementioned implementation examples for details and will not be expanded here.

[0075] Based on the same inventive concept, the present application also provides a chip, which includes an electronic fuse (eFuse) and an eFuse burning power supply circuit, wherein the eFuse burning power supply circuit is an internal eFuse burning power supply circuit of the chip as described in any one of the present applications.

[0076] By simply reusing low-voltage IO and adding switching circuits, the power supply circuit required for eFuse burning can be implemented inside the chip with an extremely small chip area, making it convenient for various chips containing eFuse to realize eFuse burning power supply design and burning operations with only simple chip design.

[0077] In this specification, the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the embodiments described later, the description is relatively simple, and the relevant parts can be referred to the partial description of the previous embodiments.

[0078] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A chip internal eFuse burning power supply circuit, characterized in that: include: A low voltage interface, a first switch circuit and a second switch circuit; The first switch circuit is connected in series between the low voltage interface and the programming power port, and the second switch circuit is connected in series between the chip power supply end and the programming power supply port; wherein the programming power supply port is a port in the chip that provides power for the eFuse; the low voltage interface is used to connect the high voltage power supply when the eFuse inside the chip needs to be programmed, and serves as the IO of the chip when the eFuse inside the chip does not need to be programmed; the first switch circuit is used to turn on or off under the control of the first signal to connect or disconnect the connection between the low voltage interface and the programming power supply port, and the second switch circuit is used to turn on or off under the control of the second signal to connect or disconnect the connection between the chip power supply end and the programming power supply port, wherein when the eFuse inside the chip needs to be programmed, the first signal controls the first switch circuit to turn on, and the second signal controls the second switch circuit to turn off, so that the high voltage power connected to the low voltage interface is input to the programming power supply end to provide the eFuse with the voltage required for programming, and when the chip eFuse does not need to be programmed, the first signal controls the first switch circuit to turn off, and the second signal controls the second switch circuit to turn on, so that the voltage at the chip power supply end is input to the programming power supply end to provide the eFuse with the voltage required for normal operation.

2. The chip internal eFuse burning power supply circuit according to claim 1, characterized in that: The first switch circuit includes a first MOS tube, a gate of the first MOS tube inputs a first signal, a drain of the first MOS tube is connected to a low voltage interface, and a source of the first MOS tube is connected to a programming power supply terminal; And / or, the second switch circuit includes a second MOS tube, a gate of the second MOS tube inputs the second signal, a drain of the second MOS tube is connected to the chip power supply terminal, and a source of the second MOS tube is connected to the programming power supply terminal.

3. The chip internal eFuse burning power supply circuit according to claim 2, characterized in that: The first switch circuit also includes a fourth MOS tube and a first resistor, wherein the gate of the first MOS tube inputs the first signal, the drain of the first MOS tube is connected to the gate of the fourth MOS tube, the source of the first MOS tube is grounded, the drain of the fourth MOS tube is connected to the low voltage interface, the source of the fourth MOS tube is connected to the programming power supply terminal, and the first resistor is connected between the gate and the source of the fourth MOS tube; And / or, the second switch circuit also includes a third MOS tube and a second resistor, wherein the gate of the second MOS tube inputs the second signal, the drain of the second MOS tube is connected to the gate of the third MOS tube, the source of the second MOS tube is grounded, the drain of the third MOS tube is connected to the chip power supply terminal, the source of the third MOS tube is connected to the programming power supply terminal, and the second resistor is connected between the gate and source of the third MOS tube.

4. The chip internal eFuse burning power supply circuit according to claim 3, characterized in that: The fourth MOS tube and / or the third MOS tube is a MOS tube including a body diode, so as to utilize the body diode to block the path after the MOS is turned off.

5. The chip internal eFuse burning power supply circuit according to claim 3, characterized in that: The first switch circuit also includes a fifth MOS tube, wherein the drain of the first MOS tube is connected to the gate of the fourth MOS tube and the gate of the fifth MOS tube, the source of the fourth MOS tube is connected to the source of the fifth MOS tube, and the drain of the fifth MOS tube is connected to the programming power supply terminal; And / or, the first switch circuit further includes a voltage stabilizing diode, which is connected between the gate and source of the fourth MOS tube to clamp the voltage of the gate and source of the fourth MOS tube.

6. The chip internal eFuse burning power supply circuit according to claim 5, characterized in that: The fifth MOS tube is a MOS tube including a body diode, so as to utilize the body diode to block the path after the MOS is turned off.

7. The chip internal eFuse burning power supply circuit according to claim 5, characterized in that: The first switch circuit also includes a third resistor, which is connected in series between the source of the first MOS tube and the ground, so that the operating current of the voltage regulator diode is within a preset range.

8. The chip internal eFuse burning power supply circuit according to any one of claims 1 to 7, characterized in that: The chip internal eFuse burning power supply circuit also includes an inverter, and the inverter is used to provide a first signal and a second signal with opposite phases.

9. A method for burning eFuse inside a chip, characterized in that: include: When the eFuse inside the chip needs to be burned, the high-voltage power supply required for burning is connected to the low-voltage interface in the chip internal eFuse burning power supply circuit as described in any one of claims 1-8, and by configuring the first signal and the second signal, the burning power supply port in the chip internal eFuse burning power supply circuit as described in any one of claims 1-8 is connected to the low-voltage interface and disconnected from the chip power supply terminal, so that the eFuse uses the high-voltage power supply connected to the low-voltage interface to perform the burning operation; After the eFuse is burned, the high voltage power supply is disconnected from the low voltage interface, and by configuring the first signal and the second signal, the burning power supply port is disconnected from the low voltage interface and connected to the chip power supply terminal, so that the eFuse can work normally using the power supply voltage provided by the chip power supply terminal.

10. A chip, comprising an eFuse, characterized in that: The chip also includes an eFuse burning power supply circuit, wherein the eFuse burning power supply circuit is a chip internal eFuse burning power supply circuit as described in any one of claims 1-8.

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