Memory device, control method thereof, storage medium, and electronic apparatus

Abstract

The invention provides a storage device and a control method thereof, a storage medium and electronic equipment. The method comprises the following steps: receiving a logic address under uniform addressing; reading storage data of the first memory bank and redundant data of the second memory bank according to the logic address; according to the invention, after address decoding is carried out by the memory bank controller, the fault verification of the memory device can be realized according to whether the read storage data is matched with the redundant data, and a special coding and decoding circuit is not required to be arranged for an access address; according to the method, the address and the data do not need to be uniformly coded and decoded, so that the data bit width is greatly reduced, the processing efficiency of the system is improved, the chip cost is greatly reduced, and the problem of ECC errors caused by address ECC verification faults is clearly diagnosed in an indirect mode.

Description

Technical Field

[0001] The present invention relates to the technical field of storage devices, and in particular to a storage device and a control method thereof, a storage medium and an electronic device. Background Art

[0002] In related technologies, such as Figure 1 As shown, a storage body is used to uniformly store the data, address elliptic curve cryptography (ECC) code and data ECC code corresponding to each address unit in the address space corresponding to the address unit, and the storage body increases the storage bit width to store at least ECC check codes that can perform two-check and one-correct, including address ECC check codes and data ECC check codes; a unified storage body controller is used, and when the controller receives the system's access command and access address, a special encoding and decoding circuit is set for the access address, or the address ECC code and the data address ECC code are uniformly encoded and decoded.

[0003] However, the above method requires not only the design of the data ECC encoding and decoding circuit of the storage body, but also the design of an additional address ECC encoding and decoding circuit, and the address decoding logic in the controller needs to perform redundant checking accordingly; the address ECC code and the data address ECC code are uniformly encoded and decoded, and the data bit width is increased in addition to the original data bit width, which reduces processing efficiency and seriously affects system performance; in addition, the space used for additional ECC storage in the storage body will be fixed and can only be used to store ECC check codes. The entire design implementation is relatively complex, resulting in an increase in chip cost and fixed functions when achieving high security goals, which greatly reduces the product's competitive advantage in terms of cost and performance. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art.

[0005] To this end, an object of the present invention is to propose a control method for a storage device. After the storage body controller performs address decoding, the method can realize fault checking of the storage device according to whether the read storage data and redundant data match. There is no need to set up a special encoding and decoding circuit for the access address, nor is there a need to uniformly encode and decode the address and data, which greatly reduces the data bit width, thereby improving the processing efficiency of the system, greatly reducing the chip cost, and clearly diagnosing the ECC error problem caused by the failure of the address ECC check in an indirect way.

[0006] Therefore, a second object of the present invention is to provide a memory device.

[0007] To this end, a third object of the present invention is to provide a computer-readable storage medium.

[0008] To this end, a fourth objective of the present invention is to provide an electronic device.

[0009] In order to achieve the above-mentioned purpose, an embodiment of the first aspect of the present invention proposes a control method for a storage device, wherein the storage device includes a first storage body and a second storage body, and the control method includes: receiving a logical address under unified addressing; reading storage data of the first storage body and redundant data of the second storage body according to the logical address; and performing fault checking on the storage device according to the storage data and the redundant data.

[0010] According to the control method of the storage device of the embodiment of the present invention, by setting two independent storage bodies, such as the first storage body and the second storage body, after receiving the logical address under the unified addressing, the storage data of the first storage body and the redundant data of the second storage body are read respectively according to the logical address, and the fault detection of the storage device is implemented according to the above data. It can be understood that since the same logical address is received, after the storage body controller performs address decoding, the fault detection of the storage device can be implemented according to whether the read storage data and redundant data match. There is no need to set a special encoding and decoding circuit for the access address, and there is no need to uniformly encode and decode the address and data, which greatly reduces the data bit width, thereby improving the processing efficiency of the system, greatly reducing the chip cost, and clearly diagnosing the ECC error problem caused by the failure of the address ECC check in an indirect way.

[0011] In some embodiments, performing a fault check on the storage device according to the storage data and the redundant data includes: if the storage data and the redundant data do not match, determining that the storage device is faulty.

[0012] In some embodiments, the storage data of the first storage body and the redundant data of the second storage body are read according to the logical address, including: determining the physical address of the logical address in the first storage body and the target logical address of the logical address in the second storage body; reading the storage data under the physical address and the redundant data under the target logical address.

[0013] In some embodiments, determining the physical address of the logical address in the first storage body includes: using the logical address as the physical address of the first storage body.

[0014] In some embodiments, determining the target logical address of the logical address in the second storage body includes: obtaining a preset address relationship configuration table; and determining the target logical address according to the preset address relationship configuration table and the logical address.

[0015] In some embodiments, determining the target logical address according to the preset address relationship configuration table and the logical address includes: obtaining the address offset of the logical address in the preset address relationship configuration table; and determining the target logical address according to the address offset and the logical address.

[0016] In some embodiments, determining the target logical address according to the address offset and the logical address includes: calculating an address sum of the address offset and the logical address, and using the address sum as the target logical address.

[0017] In some embodiments, reading the stored data at the physical address includes: acquiring a first storage space at the physical address in response to a data read instruction; and reading the stored data in the first storage space.

[0018] In some embodiments, reading the redundant data under the target logical address includes: acquiring a second storage space under the target logical address in response to a data read instruction; and reading the redundant data in the second storage space.

[0019] In some embodiments, obtaining a first storage space under the physical address includes: decoding the physical address to obtain the first storage space.

[0020] In some embodiments, obtaining a second storage space under the target logical address includes: decoding the target logical address to obtain the second storage space.

[0021] In some embodiments, before receiving the logical address under unified addressing, it also includes: determining that the stored data is written into the first storage body and the redundant data is written into the second storage body.

[0022] In some embodiments, before determining that the storage data is written to the first storage body, it also includes: receiving the logical address and the storage data; determining the physical address of the logical address in the first storage body; and writing the storage data to the physical address.

[0023] In some embodiments, before determining that the redundant data is written to the second storage body, it also includes: receiving the logical address and the storage data; determining the target logical address of the logical address in the second storage body; determining the redundant data corresponding to the storage data based on the storage data; and writing the redundant data to the target logical address.

[0024] In some embodiments, before reading the storage data of the first storage bank and the redundant data of the second storage bank according to the logical address, the method further includes: determining whether an error correction function of the storage device is turned on.

[0025] In order to achieve the above-mentioned purpose, an embodiment of the second aspect of the present invention proposes a storage device, which includes: a first storage body; a second storage body; a storage body controller, which is respectively connected to the first storage body and the second storage body, and is used to receive a logical address under a unified addressing, and read the storage data of the first storage body and the redundant data of the second storage body according to the logical address; a decoding circuit, which is connected to the storage body controller, and is used to perform fault checking on the storage device according to the storage data and the redundant data.

[0026] According to the storage device of the embodiment of the present invention, by setting two independent storage bodies, such as a first storage body and a second storage body, after receiving the logical address under the unified addressing, the storage data of the first storage body and the redundant data of the second storage body are read respectively according to the logical address, and the fault detection of the storage device is implemented according to the above data. It can be understood that since the same logical address is received, after the storage body controller performs address decoding, the fault detection of the storage device can be implemented according to whether the read storage data and redundant data match. There is no need to set a special encoding and decoding circuit for the access address, and there is no need to uniformly encode and decode the address and data, which greatly reduces the data bit width, thereby improving the processing efficiency of the system, greatly reducing the chip cost, and clearly diagnosing the ECC error problem caused by the failure of the address ECC check in an indirect way.

[0027] In order to achieve the above-mentioned purpose, an embodiment of the third aspect of the present invention proposes a computer-readable storage medium, on which a control program of a storage device is stored. When the control program of the storage device is executed by a processor, the control method of the storage device described in the above-mentioned embodiment is implemented.

[0028] In order to achieve the above-mentioned purpose, an embodiment of the fourth aspect of the present invention proposes an electronic device, which includes: a processor, which is electrically connected to a memory; the memory stores a computer program that can be executed by the processor, and when the processor executes the computer program, the control method of the storage device described in the above embodiment is implemented.

[0029] According to the electronic device of the embodiment of the present invention, by setting two independent storage bodies, such as a first storage body and a second storage body, after receiving the logical address under the unified addressing, the storage data of the first storage body and the redundant data of the second storage body are read respectively according to the logical address, and the fault detection of the storage device is implemented according to the above data. It can be understood that since the same logical address is received, after the storage body controller performs address decoding, the fault detection of the storage device can be implemented according to whether the read storage data and redundant data match. There is no need to set a special encoding and decoding circuit for the access address, and there is no need to uniformly encode and decode the address and data, which greatly reduces the data bit width, thereby improving the processing efficiency of the system, greatly reducing the chip cost, and clearly diagnosing the ECC error problem caused by the failure of the address ECC check in an indirect way.

[0030] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0032] Figure 1 It is a schematic diagram of the structure of a storage device in the related art;

[0033] Figure 2 is a schematic structural diagram of a storage device according to an embodiment of the present invention;

[0034] Figure 3 is a flow chart of a method for controlling a storage device according to an embodiment of the present invention;

[0035] Figure 4 is a schematic diagram of a preset address relationship configuration according to an embodiment of the present invention;

[0036] Figure 5 is a flow chart of a method for controlling a storage device according to a specific embodiment of the present invention;

[0037] Figure 6 is a structural block diagram of a memory device according to an embodiment of the present invention. Description of the drawings:

[0039] Storage device 2;

[0040] A first memory bank 21 ; a second memory bank 22 ; a memory bank controller 23 ; and a decoding circuit 24 . DETAILED DESCRIPTION

[0041] Embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Embodiments of the present invention are described in detail below.

[0042] At present, due to the large storage space of the memory bank in the high-security level chip, the failure rate is relatively high, which seriously affects the normal and reliable operation of the high-security level chip. Therefore, for the high-security level microcontroller unit (MCU) chip, the memory bank and its controller need to be designed with a high degree of security to reduce the random hardware failure rate so that the MCU meets the high security level standard.

[0043] In the related art, after the controller receives the access address of the system, it decodes it through the address decoding circuit and the address decoding redundant circuit. When the decoding is the same, the storage body can be accessed normally; the controller usually adopts a lock-step control method, or performs legal control protection on key read and write control signals. However, since the same storage body is used to store storage data and redundant data, the same storage body can only receive one address. When there is a problem with the row and column decoding circuit in the storage body itself, such as an error in the row and column decoding control circuit, and the data is accessed to the wrong place, the fault cannot be diagnosed because there is no comparison reference.

[0044] Let's combine Figure 2 A memory device according to an embodiment of the present invention is described, the memory device comprising a first memory bank, a second memory bank, a memory bank controller and a decoding circuit, wherein:

[0045] The first storage body and the second storage body are two independent storage bodies. The first storage body only stores storage data, and the second storage body only stores redundant data. There is no need for address ECC encoding and decoding circuits and address decoding redundant circuits. They are uniformly controlled by a storage body controller. The bit width of the first storage body is 64 bits, and the bit width of the second storage body is 8 bits. The 64-bit bit width data uses an 8-bit bit width ECC check code, which can realize data error detection of checking two and correcting one.

[0046] The second storage body supports the selection of two functional modes: functional safety mode and general mode. When the functional mode is functional safety mode, the ECC encoding and decoding circuit is connected to work, and the stored data needs to be processed by the ECC encoding and decoding circuit to generate 8 bits of redundant data from the 64-bit storage data. In the functional safety mode, there are 4 64-bit storage data A, B, C, and D for access, and the corresponding 8-bit redundant data are AE, BE, CE, and DE respectively.

[0047] In the general mode, the two storage bodies are independent of the controller, and the second storage body can be fully released and used as a normal data storage function, thereby improving the applicability of the chip.

[0048] Combine the following Figure 2-Figure 5 The control method of the storage device according to the embodiment of the present invention is described by way of example.

[0049] like Figure 3 As shown, the control method of the storage device according to the embodiment of the present invention at least includes steps S1 to S4.

[0050] Step S1, receiving a logical address under unified addressing.

[0051] In an embodiment, when performing a data write operation, the system only issues a logical address under a unified addressing, for example, recorded as address 1, address 2, ..., address n. After the storage body controller receives and only receives the logical address, it decodes the logical address into specific addresses used for writing data to different storage bodies according to the address relationship between two independent storage bodies under the control of the same storage body controller, so as to identify and configure the access addresses of different storage bodies.

[0052] Step S2, reading the storage data of the first storage body and the redundant data of the second storage body according to the logical address.

[0053] The redundant data is an ECC check code corresponding to the stored data. By acquiring the stored data and the redundant data, the decoding circuit can perform fault check on the storage device.

[0054] In an embodiment, after receiving a logical address under unified addressing, when performing a data read operation, two independent storage bodies, namely a first storage body and a second storage body, are uniformly controlled by a storage body controller, the first storage body only stores storage data, and the second storage body only stores redundant data. The first storage body determines the specific address of its write data, and reads the storage data at the specific address through row and column decoding; the second storage body determines the specific address of its write data, and reads the redundant data at the specific address through row and column decoding, so that the decoding circuit can perform fault check on the storage device.

[0055] Step S3, performing fault check on the storage device according to the stored data and the redundant data.

[0056] In an embodiment, after acquiring the storage data and the redundant data, the storage data and the redundant data are simultaneously sent to a decoding circuit, and a fault check is performed on the storage device according to the decoding result. When the decoding circuit checks that the storage data and the redundant data do not match, an error must have occurred after the ECC check, and it is determined that the storage device has a check fault; when the decoding circuit checks that the storage data and the redundant data match, it is determined that the storage device has not failed, the current data check is successful, and the storage body can be accessed normally.

[0057] According to the control method of the storage device of the embodiment of the present invention, by setting two independent storage bodies, such as the first storage body and the second storage body, after receiving the logical address under the unified addressing, the storage data of the first storage body and the redundant data of the second storage body are read respectively according to the logical address, and the fault detection of the storage device is implemented according to the above data. It can be understood that since the same logical address is received, after the storage body controller performs address decoding, the fault detection of the storage device can be implemented according to whether the read storage data and redundant data match. There is no need to set a special encoding and decoding circuit for the access address, and there is no need to uniformly encode and decode the address and data, which greatly reduces the data bit width, thereby improving the processing efficiency of the system, greatly reducing the chip cost, and clearly diagnosing the ECC error problem caused by the failure of the address ECC check in an indirect way.

[0058] In some embodiments, performing a fault check on the storage device according to the storage data and the redundant data includes: if the storage data and the redundant data do not match, determining that the storage device is faulty.

[0059] In an embodiment, after acquiring the storage data and redundant data, when one or more bits of the storage data and redundant data are erroneous due to random hardware failure or transient failure, the decoding circuit checks that the storage data and redundant data do not match, and determines that the storage device has a verification failure.

[0060] Or when the first storage body read / write control unit, the second storage body read / write control unit, the first storage body row / column decoder, the second storage body row / column decoder fail due to random hardware failure or transient failure, or the address data stream is erroneous due to transient interference during address transmission, the decoding circuit checks that the stored data and redundant data do not match. For example, the stored data is A data, the correct redundant data is AE data, but the redundant data read out is BE data or other data, then it is determined that the storage device has a verification failure.

[0061] If the decoding circuit verifies that the stored data matches the redundant data, it is determined that the storage device is not faulty, the current data verification is successful, and the storage body can be accessed normally.

[0062] In some embodiments, storage data of a first storage body and redundant data of a second storage body are read according to a logical address, including: determining a physical address of the logical address in the first storage body and a target logical address of the logical address in the second storage body; reading storage data under the physical address and redundant data under the target logical address.

[0063] In an embodiment, after receiving the logical address under unified addressing, the logical address is decoded into the specific address of the first storage body to write data, which is determined as the physical address, and the logical address is decoded into the specific address of the second storage body to write data, which is determined as the target logical address, thereby determining the specific addresses of the first storage body and the second storage body to write data, thereby facilitating reading the data at the corresponding positions.

[0064] After determining the physical address and the target logical address, when performing a data read operation, the system issues a data read instruction, and the first storage body reads the stored data under the physical address according to the received data read instruction. Similarly, the second storage body reads the redundant data under the target logical address according to the received data read instruction.

[0065] In some embodiments, determining the physical address of the logical address in the first storage body includes: using the logical address as the physical address of the first storage body.

[0066] In some embodiments, after receiving the logical address under unified addressing, the logical address is used as the physical address of the first storage body, thereby determining the specific address of the first storage body to write data, which facilitates reading data at a corresponding position of the first storage body.

[0067] In some embodiments, determining a target logical address of the logical address in the second storage body includes: obtaining a preset address relationship configuration table; and determining the target logical address according to the preset address relationship configuration table and the logical address.

[0068] In an embodiment, after receiving the logical address under the unified addressing, such as Figure 4 As shown, a preset address relationship configuration table is obtained from inside the storage body controller to identify and configure the address relationship between the first storage body and the second storage body under unified addressing, and the target logical address is obtained according to the preset address relationship configuration and the logical address, so as to determine the specific address of the second storage body to write data, so as to facilitate reading the data at the corresponding position of the second storage body.

[0069] In some embodiments, determining the target logical address according to a preset address relationship configuration table and the logical address includes: obtaining an address offset of the logical address in the preset address relationship configuration table; and determining the target logical address according to the address offset and the logical address.

[0070] In an embodiment, after obtaining a preset address relationship configuration table, the address offset corresponding to the logical address is determined in the preset address relationship configuration table, for example, recorded as N, as shown in Table 1, the target logical address is obtained according to the address offset N and the logical address, the address sum of the address offset N and the logical address is calculated, and the address sum is used as the target logical address. For example, the logical address is address 1, the physical address 1 of the first storage body is address 1, and the target logical address is address 1 of the second storage body, then the physical address 1 of the first storage body + the address offset N = the target logical address 1 of the second storage body, and other target logical addresses are determined by analogy.

[0071] Table 1

[0072] Logical address Physical Address Target logical address Fixed relationship Address 1 Address 1 Address 1+N Address offset N of unified addressing Address 2 Address 2 Address 2+N Address offset N of unified addressing ... ... ... ... Address Address Address n+N Address offset N of unified addressing

[0073] In some embodiments, reading the stored data at the physical address includes: acquiring a first storage space at the physical address in response to a data read instruction; and reading the stored data in the first storage space.

[0074] In an embodiment, when performing a data read operation, the system issues an instruction to read the physical address and the physical address, and sends the physical address to the first storage body read-write control unit. After the first storage body read-write control unit receives the data read instruction and the physical address, it decodes the physical address according to the data read instruction to obtain the first access space corresponding to the physical address, and sends the address decoding result to the first storage body. When the first storage body receives the decoding result, it reads the stored data in the first access space through row and column decoding.

[0075] In some embodiments, reading redundant data under the target logical address includes: acquiring a second storage space under the target logical address in response to a data read instruction; and reading redundant data in the second storage space.

[0076] In an embodiment, when performing a data read operation, the system issues an instruction to read the target logical address and the target logical address, and sends the target logical address to the second storage body read-write control unit. After the second storage body read-write control unit receives the data read instruction and the target logical address, it decodes the target logical address according to the data read instruction to obtain the second access space corresponding to the target logical address, and sends the address decoding result to the second storage body. When the second storage body receives the decoding result, it reads the redundant data in the second access space through row and column decoding.

[0077] In some embodiments, obtaining a first storage space under a physical address includes: decoding the physical address to obtain the first storage space.

[0078] In an embodiment, after the first storage body read and write control unit receives a data read instruction and a physical address, i.e., the physical address of the first storage body, it decodes the physical address to obtain the physical address in the first access space of the first storage body, and decodes the obtained physical address into the access space for the first storage body to access the stored data in the first storage body.

[0079] In some embodiments, obtaining a second storage space under a target logical address includes: decoding the target logical address to obtain the second storage space.

[0080] In an embodiment, after the second storage body read and write control unit receives a data read instruction and a target logical address, i.e., the target logical address of the second storage body, it decodes the target logical address to obtain the target logical address in the second access space of the second storage body, and decodes the obtained target logical address into an access space for the second storage body to access redundant data in the second storage body.

[0081] In some embodiments, before receiving the logical address under unified addressing, it also includes: determining to write the storage data into the first storage body and the redundant data into the second storage body.

[0082] In an embodiment, before receiving the logical address under the unified addressing, a data write operation needs to be performed first. It is assumed that the system writes the storage data to the physical address of the first storage body under the unified addressing according to the software settings, and writes the redundant data to the target logical address of the second storage body under the unified addressing to complete the writing of the storage data and the redundant data.

[0083] In some embodiments, before determining that the storage data is written into the first storage body, the method further includes: receiving a logical address and storage data; determining a physical address of the logical address in the first storage body; and writing the storage data into the physical address.

[0084] In an embodiment, a logical address and storage data under unified addressing are received, the logical address is used as the physical address of the first storage body, and the physical address is sent to the first storage body read-write control unit. After the first storage body read-write control unit receives the data write instruction and the physical address, it decodes the physical address according to the data write instruction to obtain the physical address in the first access space of the first storage body. The first storage body read-write control unit sends the address decoding result and the storage data to the first storage body. Then, after the first storage body receives the decoding command and the storage data, it writes the storage data into the first access space to complete the data write action.

[0085] In some embodiments, before determining that redundant data is written to the second storage body, it also includes: receiving a logical address and storage data; determining a target logical address of the logical address in the second storage body; determining redundant data corresponding to the storage data based on the storage data; and writing the redundant data to the target logical address.

[0086] In an embodiment, a logical address and storage data under unified addressing are received, a target logical address is obtained according to a configuration table of the relationship between the logical address and a preset address stored internally, and the target logical address is sent to a second storage body read-write control unit; at the same time, the storage data is sent to a decoding circuit so that the decoding circuit obtains corresponding redundant data according to the storage data, and sends the redundant data to the second storage body read-write control unit; after the second storage body read-write control unit receives a data write instruction and a target logical address, it decodes the target logical address according to the data write instruction to obtain the target logical address in a second access space of the second storage body, and the second storage body read-write control unit sends the address decoding result and the redundant data to the second storage body, and then after the second storage body receives the decoding command and the redundant data, it writes the redundant data into the second access space to complete the data write action, and the storage data and the corresponding redundant data complete the storage of two independent storage bodies.

[0087] In some embodiments, before reading the storage data of the first storage bank and the redundant data of the second storage bank according to the logical address, the method further includes: determining whether an error correction function of the storage device is turned on.

[0088] In an embodiment, before reading the storage data of the first storage body and the redundant data of the second storage body according to the logical address, it is determined that the error correction function of the storage device, that is, the functional safety mode, is turned on. At this time, the preset address relationship configuration is turned on, which is convenient for identifying and configuring the address relationship between the first storage body and the second storage body under unified addressing.

[0089] In the general mode, the decoding circuit will be disabled, the address offset N in the preset address relationship configuration is 0, the offset function is disabled, and no offset is performed. At this time, the first storage body and the second storage body are two independent storage units, which can be used for data storage separately. The data path will not be verified and calculated by the decoding circuit, and directly interact with the system. At this time, the typical implementation is that the system can support 72-bit data access, that is, 64bit+8bit, or access 8-bit data separately. More specifically, at this time, after the storage body controller obtains the access address of the system, it directly decodes it. If the address is the logical address of the first storage body, it sends the address to the first storage body read-write control unit for processing, and directly accesses the first storage body; similarly, if the address is the target logical address of the second storage body, it sends the address to the second storage body read-write control unit for processing, and directly accesses the second storage body. At this time, the system still uniformly addresses the address of the first storage body and the access address of the second storage body, so the logical address of the first storage body and the target logical address of the second storage body are different addresses for the system.

[0090] Reference below Figure 5The control method of the storage device according to the embodiment of the present invention is described by way of example.

[0091] like Figure 5 As shown, the control method of the storage device according to the embodiment of the present invention at least includes steps S11 to S25.

[0092] Step S11, receiving a logical address and storage data; determining a physical address of the logical address in a first storage body; and writing the storage data into the physical address.

[0093] Step S12, receiving the logical address and the storage data; determining the target logical address of the logical address in the second storage body; determining the redundant data corresponding to the storage data according to the storage data; and writing the redundant data into the target logical address.

[0094] Step S13, receiving a logical address under unified addressing.

[0095] Step S14, determining whether the error correction function of the storage device is turned on.

[0096] Step S15: Using the logical address as the physical address of the first storage body.

[0097] Step S16, obtaining a preset address relationship configuration table.

[0098] Step S17, obtaining the address offset of the logical address in the preset address relationship configuration table.

[0099] Step S18, calculating the address offset and the address sum of the logical address, and taking the address sum as the target logical address.

[0100] Step S19, in response to the data read instruction, decoding the physical address to obtain the first storage space.

[0101] Step S20, reading the stored data in the first storage space.

[0102] Step S21, in response to a data read instruction, decoding a target logical address to obtain a second storage space.

[0103] Step S22, reading redundant data in the second storage space.

[0104] Step S23, determine whether the stored data and the redundant data match, if so, execute step S25; otherwise, execute step S24.

[0105] Step S24, determining that the storage device has a verification failure.

[0106] Step S25, determining that the storage device is not faulty.

[0107] According to the control method of the storage device of the embodiment of the present invention, by setting two independent storage bodies, such as the first storage body and the second storage body, after receiving the logical address under the unified addressing, the storage data of the first storage body and the redundant data of the second storage body are read respectively according to the logical address, and the fault detection of the storage device is implemented according to the above data. It can be understood that since the same logical address is received, after the storage body controller performs address decoding, the fault detection of the storage device can be implemented according to whether the read storage data and redundant data match. There is no need to set a special encoding and decoding circuit for the access address, and there is no need to uniformly encode and decode the address and data, which greatly reduces the data bit width, thereby improving the processing efficiency of the system, greatly reducing the chip cost, and clearly diagnosing the ECC error problem caused by the failure of the address ECC check in an indirect way.

[0108] Combine the following Figure 6 A memory device 2 according to an embodiment of the present invention is described.

[0109] like Figure 6 As shown, the memory device 2 of the embodiment of the present invention comprises: a first memory bank 21, a second memory bank 22, a memory bank controller 23 and a decoding circuit 24, wherein:

[0110] The storage body controller 23 is connected to the first storage body 21 and the second storage body 22 respectively, and is used to receive the logical address under the unified addressing, and read the storage data of the first storage body 21 and the redundant data of the second storage body 22 according to the logical address; the decoding circuit 24 is connected to the storage body controller 23, and is used to perform fault check on the storage device according to the storage data and the redundant data.

[0111] According to the storage device 2 of the embodiment of the present invention, by setting two independent storage bodies, such as a first storage body and a second storage body, after receiving the logical address under the unified addressing, the storage data of the first storage body and the redundant data of the second storage body are read respectively according to the logical address, and the fault detection of the storage device is implemented according to the above data. It can be understood that since the same logical address is received, after the storage body controller performs address decoding, the fault detection of the storage device can be implemented according to whether the read storage data and redundant data match. There is no need to set a special encoding and decoding circuit for the access address, and there is no need to uniformly encode and decode the address and data, which greatly reduces the data bit width, thereby improving the processing efficiency of the system, greatly reducing the chip cost, and clearly diagnosing the ECC error problem caused by the failure of the address ECC check in an indirect way.

[0112] The following describes a computer-readable storage medium according to an embodiment of the present invention.

[0113] A control program of a storage device is stored on a computer-readable storage medium in an embodiment of the present invention. When the control program of the storage device is executed by a processor, the control method of the storage device in the above embodiment is implemented.

[0114] The electronic device according to the embodiment of the present invention is described below.

[0115] The electronic device of the embodiment of the present invention comprises: a processor, the processor is electrically connected to a memory; the memory stores a computer program executable by the processor, and the control method of the memory device of the above embodiment is implemented when the processor executes the computer program.

[0116] According to the electronic device of the embodiment of the present invention, by setting two independent storage bodies, such as a first storage body and a second storage body, after receiving the logical address under the unified addressing, the storage data of the first storage body and the redundant data of the second storage body are read respectively according to the logical address, and the fault detection of the storage device is implemented according to the above data. It can be understood that since the same logical address is received, after the storage body controller performs address decoding, the fault detection of the storage device can be implemented according to whether the read storage data and redundant data match. There is no need to set a special encoding and decoding circuit for the access address, and there is no need to uniformly encode and decode the address and data, which greatly reduces the data bit width, thereby improving the processing efficiency of the system, greatly reducing the chip cost, and clearly diagnosing the ECC error problem caused by the failure of the address ECC check in an indirect way.

[0117] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0118] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A method for controlling a storage device, characterized in that: The storage device includes a first storage bank and a second storage bank, and the control method includes: Receive the logical address under unified addressing; Reading the storage data of the first storage body and the redundant data of the second storage body according to the logical address; Failure check is performed on the storage device according to the storage data and the redundant data.

2. The control method of the storage device according to claim 1, characterized in that: Performing a fault check on the storage device according to the storage data and the redundant data includes: If the stored data and the redundant data do not match, it is determined that the storage device is faulty.

3. The control method of the storage device according to claim 1, characterized in that: Reading the storage data of the first storage body and the redundant data of the second storage body according to the logical address includes: Determine a physical address of the logical address in the first storage body and a target logical address of the logical address in the second storage body; The storage data at the physical address and the redundant data at the target logical address are read.

4. The control method of the storage device according to claim 3, characterized in that: Determining the physical address of the logical address in the first storage body includes: The logical address is used as the physical address of the first storage body.

5. The control method of the storage device according to claim 3, characterized in that: Determining a target logical address of the logical address in the second storage body includes: Get the preset address relationship configuration table; The target logical address is determined according to the preset address relationship configuration table and the logical address.

6. The control method of the storage device according to claim 5, characterized in that: Determining the target logical address according to the preset address relationship configuration table and the logical address includes: Obtaining the address offset of the logical address in the preset address relationship configuration table; The target logical address is determined according to the address offset and the logical address.

7. The method for controlling a storage device according to claim 6, wherein: Determining the target logical address according to the address offset and the logical address includes: The address sum of the address offset and the logical address is calculated, and the address sum is used as the target logical address.

8. The control method of the storage device according to claim 3, characterized in that: Reading the stored data at the physical address includes: In response to a data read instruction, acquiring a first storage space under the physical address; The stored data in the first storage space is read.

9. The control method of the storage device according to claim 3, characterized in that: Reading redundant data under the target logical address includes: In response to a data read instruction, acquiring a second storage space under the target logical address; The redundant data in the second storage space is read.

10. The control method of the storage device according to claim 8, characterized in that: Acquiring a first storage space under the physical address includes: The physical address is decoded to obtain the first storage space.

11. The control method of the storage device according to claim 9, characterized in that: Acquiring a second storage space under the target logical address includes: The target logical address is decoded to obtain the second storage space.

12. The method for controlling a storage device according to claim 1, wherein: Before receiving the logical address under unified addressing, it also includes: It is determined that the storage data is written into the first storage bank and the redundant data is written into the second storage bank.

13. The control method of the storage device according to claim 12, characterized in that: Before determining that the stored data is written into the first storage body, the method further includes: receiving the logical address and the storage data; Determining a physical address of the logical address in the first storage body; The storage data is written to the physical address.

14. The control method of the storage device according to claim 12, characterized in that: Before determining that the redundant data is written into the second storage body, the method further includes: receiving the logical address and the storage data; determining a target logical address of the logical address in the second storage body; Determine the redundant data corresponding to the stored data according to the stored data; The redundant data is written to the target logical address.

15. The control method of the storage device according to claim 1, characterized in that: Before reading the storage data of the first storage body and the redundant data of the second storage body according to the logical address, the method further includes: It is determined that an error correction function of the memory device is turned on.

16. A storage device, characterized in that: include: a first storage bank; a second storage bank; a storage body controller, connected to the first storage body and the second storage body respectively, for receiving a logical address under unified addressing, and reading storage data of the first storage body and redundant data of the second storage body according to the logical address; A decoding circuit is connected to the memory body controller and is used to perform a fault check on the memory device according to the storage data and the redundant data.

17. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a control program of the storage device, and when the control program of the storage device is executed by the processor, the control method of the storage device according to any one of claims 1 to 15 is implemented.

18. An electronic device, characterized in that: include: A processor, the processor being electrically connected to the memory; The memory stores a computer program that can be executed by the processor, and when the processor executes the computer program, the control method of the storage device according to any one of claims 1 to 15 is implemented.

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