Diffusion doping method

Abstract

The invention relates to the technical field of semiconductor manufacturing, and discloses a diffusion doping method which comprises the following steps: providing a silicon wafer; forming an oxide layer on one side surface of the silicon wafer; forming an isolation layer on the surface of one side, back to the silicon wafer, of the oxide layer; performing a patterning process on the isolation layer to form a plurality of diffusion windows which penetrate through the isolation layer and expose the surface of one side, opposite to the silicon wafer, of a part of the oxide layer; doping the oxide layer and the silicon wafer from the diffusion window by adopting a doping source, and forming a doping layer on one side, facing the oxide layer, of the silicon wafer; by-products are formed on the surface of one side, back to the silicon wafer, of the oxide layer and the surface of one side, back to the oxide layer, of the isolation layer during doping; and removing the oxide layer, the isolation layer and byproducts through a cleaning process. Compared with the prior art, the method has the advantages that the removal efficiency of the by-products on the surface of the silicon wafer can be improved, no by-product residue exists on the surface of the diffused silicon wafer, and the electrical property and reliability of a device are further improved.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor manufacturing, and in particular to a diffusion doping method. Background Art

[0002] P-type silicon plays an indispensable role in the design and manufacture of semiconductor devices. P-type heavy doping diffusion is usually achieved in a high-temperature diffusion furnace tube equipment by a diffusion process, using BN (boron nitride) to react with H2O (g) and O2 to generate B2O3 and other byproducts (borates), and then B2O3 reacts with silicon to generate SiO2 to precipitate "B" atoms and diffuse into silicon to form a p-type doping area with a doping concentration of > E20 / cm 3 , or even higher.

[0003] B2O3 and other byproducts produced during the diffusion process adhere to the silicon surface and are difficult to completely remove. Since borate substances are insoluble in corrosive solutions such as BOE (buffered oxide etchant), it is difficult to completely remove these byproducts using conventional wet etching methods. The wet removal efficiency is low, resulting in B2O3 and byproduct residues, color differences and other defects on the silicon surface; while the dry sandblasting method is used to remove B2O3 and byproducts, which will cause varying degrees of physical damage to the wafer surface, introduce silicon lattice defects, and have poor repeatability. Both methods of removing B2O3 and byproducts cause varying degrees of leakage, soft breakdown, poor reliability and other problems in the device. Summary of the invention

[0004] In view of this, the present invention provides a diffusion doping method to solve the problem of low removal efficiency of B2O3 and other by-products generated in the diffusion process in the related art. The removal process will damage the surface of the silicon wafer and introduce silicon lattice defects, thereby causing leakage, soft breakdown and poor reliability of the device.

[0005] In a first aspect, the present invention provides a diffusion doping method, the diffusion doping method comprising:

[0006] Provide silicon wafers;

[0007] An oxide layer is formed on the surface of one side of the silicon wafer;

[0008] forming an isolation layer on a surface of the oxide layer facing away from the silicon wafer;

[0009] Performing a patterning process on the isolation layer to form a plurality of diffusion windows, wherein the diffusion windows penetrate the isolation layer and expose a portion of the surface of the oxide layer facing away from the silicon wafer;

[0010] The oxide layer and the silicon wafer are doped with a doping source from a diffusion window to form a doping layer on the side of the silicon wafer facing the oxide layer; a byproduct is formed during the doping process on the surface of the oxide layer facing away from the silicon wafer and the surface of the isolation layer facing away from the oxide layer;

[0011] The oxide layer, isolation layer and by-products are removed through the cleaning process.

[0012] The diffusion doping method provided by the present invention forms an oxide layer and an isolation layer on the surface of a silicon wafer, and forms a diffusion window on the isolation layer, and uses a doping source to dope the oxide layer and the silicon wafer from the diffusion window. The oxide layer can be used as a buffer layer for direct contact between byproducts and silicon, so that byproducts do not appear on the surface of the silicon wafer, but only appear on the surface of the oxide layer and the isolation layer, and the oxide layer, the isolation layer and the byproducts can be completely removed by a cleaning process. The diffusion doping method provided by the present invention improves the removal efficiency of byproducts on the surface of the silicon wafer, so that no byproducts remain on the surface of the silicon wafer after diffusion, avoids defects such as color difference on the surface of the silicon wafer, and makes the surface roughness of the silicon wafer low and color-free, thereby improving the electrical performance and reliability of the device. At the same time, this solution also omits the dry sandblasting step, avoids the introduction of lattice defects on the surface of the silicon wafer, and also avoids particle contamination caused by the sandblasting process. In addition, the process repeatability of this solution is high, and the process is more stable and more controlled.

[0013] In an optional embodiment, the cleaning process includes a first cleaning process, a second cleaning process and a third cleaning process;

[0014] The first cleaning process includes: using a first cleaning solution at a first cleaning temperature to preliminarily remove byproducts;

[0015] The second cleaning process includes: using a second cleaning solution at a third cleaning temperature to remove the isolation layer and residual byproducts on the isolation layer surface;

[0016] The third cleaning process includes: removing the oxide layer and residual byproducts on the surface of the oxide layer by using a third cleaning solution at a third cleaning temperature.

[0017] In the diffusion doping method provided by the present invention, byproducts only exist on the isolation layer surface and the oxide layer surface. Therefore, the byproducts are firstly removed preliminarily using a first cleaning liquid at a first cleaning temperature, and then the isolation layer and the residual byproducts on the isolation layer surface are removed using a second cleaning liquid at a third cleaning temperature. Finally, the oxide layer and the residual byproducts on the oxide layer surface are removed using a third cleaning liquid at a third cleaning temperature. By removing the isolation layer and the oxide layer step by step, the byproducts on the isolation layer surface and the oxide layer surface can be completely removed, the removal efficiency of the byproducts is improved, the surface roughness of the silicon wafer is low and there is no color difference, and the electrical performance and reliability of the silicon wafer device are improved.

[0018] In an alternative embodiment, the composition of the by-product includes B2O3;

[0019] The first cleaning solution and the third cleaning solution are BOE buffered oxide etching solutions;

[0020] The composition of the second cleaning solution is H3PO4;

[0021] The first cleaning temperature and the third cleaning temperature are 20°C to 25°C;

[0022] The second cleaning temperature is 160°C to 190°C.

[0023] In an optional embodiment, the second cleaning liquid and the third cleaning liquid are isotropically corrosive;

[0024] The composition of the first cleaning solution and the third cleaning solution is NH4F:HF=7.5:1;

[0025] Etching rate of the first cleaning process

[0026] The second cleaning process is an over-etch of 120%.

[0027] In an optional embodiment, the step of doping the oxide layer and the silicon wafer with a doping source from a diffusion window, and forming a doping layer on a side of the silicon wafer facing the oxide layer includes:

[0028] The oxide layer and the silicon wafer are isotropically doped using a doping source from a diffusion window to form a doping layer on the side of the silicon wafer facing the oxide layer; the doping layer is a continuous structure over the entire surface.

[0029] The diffusion doping method provided by the present invention is to isotropically dope the oxide layer and the silicon wafer with a doping source from a diffusion window, so as to form a continuous doping layer on the side of the silicon wafer facing the oxide layer, thereby achieving full-surface doping of the silicon wafer. At the same time, due to the presence of the oxide layer in the diffusion window, by-products will not appear on the surface of the silicon wafer, but only on the surfaces of the oxide layer and the isolation layer. In the process of removing the isolation layer and the oxide layer, the by-products on the surfaces of the isolation layer and the oxide layer can be removed at the same time, thereby improving the removal efficiency of the by-products, making the surface roughness of the silicon wafer low and free of color difference, thereby improving the electrical performance and reliability of the device of the silicon wafer.

[0030] In an optional embodiment, the doping source simultaneously diffuses downward longitudinally and diffuses toward the surroundings laterally in the oxide layer and the silicon wafer;

[0031] The rate of lateral diffusion V1 is less than the rate of longitudinal diffusion V2;

[0032] In the cross section perpendicular to the silicon wafer surface, the lateral diffusion distance X is greater than the diffusion depth Y;

[0033] The width A of the isolation layer between adjacent diffusion windows is less than or equal to the lateral diffusion distance X and greater than the diffusion depth Y.

[0034] In an optional embodiment, the lateral diffusion rate V1=0.7V2~0.8V2;

[0035] The distance of lateral diffusion is X = 1.4Y ​​to 1.6Y;

[0036] The width of the isolation layer between adjacent diffusion windows is A=1.2Y-1.6Y.

[0037] The diffusion doping method provided by the present invention adjusts the width of the diffusion window and the width A of the isolation layer between adjacent diffusion windows according to the diffusion depth Y, so that when the longitudinal diffusion reaches the diffusion depth Y, the lateral diffusion distance X can completely cover the width A of the isolation layer between adjacent diffusion windows, thereby achieving full-surface doping of the silicon wafer and forming a continuous doping layer on the entire surface.

[0038] In an optional embodiment, the diffusion window is a groove with a square cross section;

[0039] The width of the diffusion window is 5μm to 15μm;

[0040] The diffusion depth Y is 40 μm;

[0041] The width of the isolation layer between adjacent diffusion windows is 50 μm to 64 μm.

[0042] In an optional embodiment, the step of isotropically doping the oxide layer and the silicon wafer from the diffusion window and forming a doping layer on the side of the silicon wafer facing the oxide layer includes:

[0043] Taking BN as the doping source, O2 and H2 are introduced at the first diffusion temperature and maintained for a certain time to activate BN; at the second diffusion temperature, H2 is stopped and only O2 is introduced and maintained for a certain time to convert BN into B2O3 to complete pre-doping; the first diffusion temperature is 400℃~550℃; the second diffusion temperature is 600℃~800℃;

[0044] Allow B2O3 to penetrate and diffuse into the oxide layer to form a mixed doping source;

[0045] N2 and O2 are introduced at a third diffusion temperature, so that B atoms are precipitated from the mixed doping source and diffused into the silicon wafer to form a B-doped P-type doping layer; the third diffusion temperature is 1200°C to 1280°C.

[0046] In an optional embodiment, the material of the oxide layer is silicon dioxide; the material of the isolation layer is Si3N4;

[0047] The thickness of the oxide layer is

[0048] The thickness of the isolation layer is

[0049] The doping concentration of the doping layer is greater than or equal to E20 / cm 3 ,

[0050] The roughness of the doped layer is less than 0.5. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the related technologies, the drawings required for use in the specific embodiments or the related technical descriptions will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0052] Figure 1 It is a schematic flow chart of a diffusion doping method according to an embodiment of the present invention.

[0053] Figure 2 It is a structural schematic diagram of forming an oxide layer in a diffusion doping method according to an embodiment of the present invention.

[0054] Figure 3 In a diffusion doping method according to an embodiment of the present invention, Figure 2 Schematic diagram of the structure of forming an isolation layer on the foundation.

[0055] Figure 4 In a diffusion doping method according to an embodiment of the present invention, Figure 3 Schematic diagram of the structure of forming a photoresist layer on the basis.

[0056] Figure 5 It is a structural schematic diagram of forming a diffusion window in a diffusion doping method according to an embodiment of the present invention.

[0057] Figure 6 Schematic diagram of a top view of a diffusion window in a diffusion doping method according to an embodiment of the present invention.

[0058] Figure 7 It is a schematic structural diagram of forming a doping layer in a diffusion doping method according to an embodiment of the present invention.

[0059] Figure 8 It is a structural schematic diagram of removing by-products in a first cleaning process in a diffusion doping method according to an embodiment of the present invention.

[0060] Fig. 9It is a structural schematic diagram of removing the isolation layer and the by-products remaining on the surface of the isolation layer in a second cleaning process in a diffusion doping method according to an embodiment of the present invention.

[0061] Fig.10 It is a structural schematic diagram of removing the oxide layer and the by-products remaining on the surface of the oxide layer in the third cleaning process in a diffusion doping method according to an embodiment of the present invention.

[0062] Fig.11 It is a schematic diagram of a specific process of a diffusion doping method according to an embodiment of the present invention.

[0063] Fig. 12A This is the macroscopic appearance of a silicon wafer after being doped using the conventional diffusion doping process in the prior art.

[0064] Fig. 12B This is an image of the surface roughness of a silicon wafer after doping using a conventional diffusion doping process in the prior art under a 500x microscope.

[0065] Fig.13A This is the macroscopic appearance of a silicon wafer after doping by a diffusion doping method according to an embodiment of the present invention.

[0066] Fig. 13B This is an image of the surface roughness of a silicon wafer under a 500x microscope after doping using a diffusion doping method according to an embodiment of the present invention.

[0067] Reference numerals:

[0068] 1. Silicon wafer; 2. Oxide layer; 3. Isolation layer; 4. Photoresist layer; 5. Diffusion window; 6. Doping source; 7. Doping layer; 8. By-products. DETAILED DESCRIPTION

[0069] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0070] In the following description, the description of known structures and technologies is omitted to avoid unnecessary confusion of the concept of the present invention. Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified for the purpose of clear expression, and some details may be omitted. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships between them are only exemplary, and may be deviated due to manufacturing tolerances or technical limitations in practice, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs. In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be a middle layer / element between them. In addition, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "under" the other layer / element.

[0071] P-type silicon plays an indispensable role in the design and manufacture of semiconductor devices. Controlling the doping dosage can present different and controllable conductive properties, and is applied to the p-type region of pn junction diodes, the p-well region of n-MOS devices, the source / drain region of p-MOS devices, the p-type region of "pin" diodes, the base region of bipolar devices, and the microstructure of MEMS devices. These applications all reflect its key value and role.

[0072] P-type silicon plays an indispensable role in the design and manufacture of semiconductor devices. P-type heavy doping diffusion is usually achieved in a high-temperature diffusion furnace tube equipment by a diffusion process, using BN (boron nitride) to react with H2O (g) and O2 to generate B2O3 and other byproducts (borates), and then B2O3 reacts with silicon to generate SiO2 to precipitate "B" atoms and diffuse into silicon to form a p-type doping area with a doping concentration of > E20 / cm 3 , or even higher.

[0073] B2O3 and byproducts produced during the diffusion process adhere to the silicon surface and are difficult to completely remove. Since borate substances are insoluble in corrosive solutions such as BOE (buffered oxide etchant), conventional wet etching methods are difficult to completely remove these byproducts, resulting in B2O3 and byproduct residues, color differences and other defects on the silicon surface; and the use of dry sandblasting to remove B2O3 and byproducts will cause varying degrees of physical damage to the wafer surface, introduce silicon lattice defects, and have poor repeatability. Both methods of removing B2O3 and byproducts cause varying degrees of leakage, soft breakdown, poor reliability and other problems in the device.

[0074] The current diffusion process method: Wafer (silicon wafer) standard wet cleaning → Wafer (silicon wafer) is loaded into the diffusion furnace → O2 and H2 process gases are introduced to activate BN → diffusion under the action of O2 → wet etching → dry sandblasting → surface inspection. This process method can remove B2O3 and byproducts on the surface of the wafer (silicon wafer) after diffusion to a certain extent, but it causes certain physical damage to the surface of the wafer (silicon wafer), introduces silicon lattice defects, and has poor repeatability. Therefore, we proposed a diffusion doping process to solve the above problems.

[0075] like Figure 1 As shown, this embodiment provides a diffusion doping method, and the preparation method includes but is not limited to steps S101 to S106.

[0076] Step S101, providing a silicon wafer 1.

[0077] Step S102, forming an oxide layer 2 on one side of the silicon wafer 1, such as Figure 2 shown.

[0078] Step S103, forming an isolation layer 3 on the surface of the oxide layer 2 facing away from the silicon wafer 1, such as Figure 3 shown.

[0079] Step S104, patterning the isolation layer 3 to form a plurality of diffusion windows 5, wherein the diffusion windows 5 penetrate the isolation layer 3 and expose a portion of the surface of the oxide layer 2 facing away from the silicon wafer 1, such as Figure 5 and Figure 6 As shown, the isolation layer 3 between adjacent diffusion windows 5 forms an isolation region.

[0080] Step S105, doping the oxide layer 2 and the silicon wafer 1 with a doping source 6 from the diffusion window 5, and forming a doping layer 7 on the side of the silicon wafer 1 facing the oxide layer 2, such as Figure 7 As shown; the surface of the oxide layer 2 facing away from the silicon wafer 1 and the surface of the isolation layer 3 facing away from the oxide layer 2 form byproducts 8 during the doping process, such as Figure 8 shown.

[0081] In a specific implementation, the doping layer 7 is P-type doped. The formed doping layer 7 can be heavily doped (doping dose>E19 / cm3) deep junction (diffusion depth is 20-100um) or ultra-deep junction (diffusion depth>100um) full-surface diffusion doping, or lightly doped (doping dose<E18) shallow junction (diffusion depth≤5um) selective diffusion doping.

[0082] Step S106, removing the oxide layer 2, the isolation layer 2 and the byproduct 8 by a cleaning process, such as Figure 8 to Figure 10 shown.

[0083] The diffusion doping method provided in this embodiment forms an oxide layer and an isolation layer on the surface of a silicon wafer, and forms a diffusion window on the isolation layer, and uses a doping source to dope the oxide layer and the silicon wafer from the diffusion window. The oxide layer can be used as a buffer layer for direct contact between the byproduct and the silicon, so that the byproduct does not appear on the surface of the silicon wafer, but only appears on the surface of the oxide layer and the isolation layer, and the oxide layer, the isolation layer and the byproduct can be completely removed by a cleaning process. The diffusion doping method provided by the present invention improves the removal efficiency of byproducts on the surface of the silicon wafer, so that there is no residual byproduct on the surface of the silicon wafer after diffusion, avoids defects such as color difference on the surface of the silicon wafer, and makes the surface roughness of the silicon wafer low and color-free, thereby improving the electrical performance and reliability of the device. At the same time, this solution also omits the dry sandblasting step, avoids the introduction of lattice defects on the surface of the silicon wafer, and also avoids particle contamination caused by the sandblasting process. In addition, the process repeatability of this solution is high, and the process is more stable and more controlled.

[0084] In some optional embodiments, the cleaning process includes a first cleaning process, a second cleaning process, and a third cleaning process;

[0085] The first cleaning process includes: using a first cleaning solution at a first cleaning temperature to preliminarily remove byproducts 8, such as Figure 8 As shown;

[0086] The second cleaning process includes: using a second cleaning solution at a third cleaning temperature to remove the isolation layer 3 and the byproducts 8 remaining on the isolation layer surface, such as Fig. 9 As shown;

[0087] The third cleaning process includes: using a third cleaning solution at a third cleaning temperature to remove the oxide layer 2 and the byproducts 8 remaining on the surface of the oxide layer, such as Fig.10 shown.

[0088] In the diffusion doping method provided in this embodiment, byproducts only exist on the isolation layer surface and the oxide layer surface. Therefore, the byproducts are firstly removed by using a first cleaning liquid at a first cleaning temperature, and then the isolation layer and the residual byproducts on the isolation layer surface are removed by using a second cleaning liquid at a third cleaning temperature. Finally, the oxide layer and the residual byproducts on the oxide layer surface are removed by using a third cleaning liquid at a third cleaning temperature. By removing the isolation layer and the oxide layer step by step, the byproducts on the isolation layer surface and the oxide layer surface can be completely removed, thereby improving the removal efficiency of the byproducts, making the silicon wafer surface roughness lower and without color difference, thereby improving the electrical performance and reliability of the silicon wafer device.

[0089] In some optional embodiments, the composition of the by-product includes B2O3;

[0090] The first cleaning solution and the third cleaning solution are BOE buffered oxide etching solutions;

[0091] The composition of the second cleaning solution is H3PO4;

[0092] The first cleaning temperature and the third cleaning temperature are 20°C to 25°C;

[0093] The second cleaning temperature is 160°C to 190°C.

[0094] In a specific implementation, the components of the by-products include B2O3 and other by-products.

[0095] In some optional embodiments, the second cleaning solution and the third cleaning solution are isotropically corrosive;

[0096] The composition of the first cleaning solution and the third cleaning solution is NH4F:HF=7.5:1;

[0097] Etching rate of the first cleaning process

[0098] The second cleaning process is an over-etch of 120%.

[0099] In some optional embodiments, the step of doping the oxide layer 2 and the silicon wafer 1 with the doping source 6 from the diffusion window 5, and forming the doping layer 7 on the side of the silicon wafer 1 facing the oxide layer 2 includes:

[0100] The oxide layer 2 and the silicon wafer 1 are isotropically doped using a doping source 6 from the diffusion window 5, and a doping layer 7 is formed on the side of the silicon wafer 1 facing the oxide layer 2; the doping layer 7 is a continuous structure on the entire surface, such as Figure 7 shown.

[0101] The diffusion doping method provided in this embodiment is to isotropically dope the oxide layer and the silicon wafer using a doping source from a diffusion window, so as to form a continuous doping layer on the side of the silicon wafer facing the oxide layer, thereby achieving full-surface doping of the silicon wafer. At the same time, due to the presence of the oxide layer in the diffusion window, by-products will not appear on the surface of the silicon wafer, but only on the surfaces of the oxide layer and the isolation layer. In the process of removing the isolation layer and the oxide layer, the by-products on the surfaces of the isolation layer and the oxide layer can be removed at the same time, thereby improving the removal efficiency of the by-products, making the surface roughness of the silicon wafer low and free of color difference, thereby improving the electrical performance and reliability of the devices of the silicon wafer.

[0102] In some optional embodiments, the doping source 6 simultaneously diffuses downward longitudinally and diffuses toward the surroundings laterally in the oxide layer 2 and the silicon wafer 1;

[0103] The rate of lateral diffusion V1 is less than the rate of longitudinal diffusion V2;

[0104] In the cross section perpendicular to the silicon wafer surface, the lateral diffusion distance X is greater than the diffusion depth Y;

[0105] The width A of the isolation layer between adjacent diffusion windows is less than or equal to the lateral diffusion distance X and greater than the diffusion depth Y.

[0106] In some optional embodiments, the rate of lateral diffusion V1=0.7V2~0.8V2;

[0107] The distance of lateral diffusion is X = 1.4Y ​​to 1.6Y;

[0108] The width of the isolation layer between adjacent diffusion windows is A=1.2Y-1.6Y.

[0109] The diffusion doping method provided in this embodiment adjusts the width of the diffusion window and the width A of the isolation layer between adjacent diffusion windows according to the diffusion depth Y, so that when the longitudinal diffusion reaches the diffusion depth Y, the lateral diffusion distance X can completely cover the width A of the isolation layer between adjacent diffusion windows, thereby achieving full-surface doping of the silicon wafer and forming a continuous doping layer on the entire surface.

[0110] In some optional embodiments, the diffusion window is a groove with a square cross-section;

[0111] The width of the diffusion window is 5μm to 15μm;

[0112] The diffusion depth Y is 40 μm;

[0113] The width A of the isolation layer between adjacent diffusion windows 5 is 50 μm to 64 μm.

[0114] In a specific implementation, in one example, the isolation layer 3 is Si3N4, and the diffusion depth Y is designed to be 40μm. Other dimensions are designed as follows. According to the thermal diffusion doping model, the lateral diffusion rate V1 = 70% to 80% of the longitudinal diffusion rate V2; and the lateral diffusion is diffused in all directions. On the cross section perpendicular to the surface of the silicon wafer, the lateral diffusion is bidirectional diffusion, then the lateral diffusion distance X = 2*40μm*70% to 2*40μm*80% = 56μm to 64μm. In order to ensure full-surface doping and isolate by-products, the width A of the isolation region between adjacent diffusion windows 5 is 50μm to 64μm, of which 50μm to 54μm is optimal.

[0115] For the design of the width of the diffusion window, the concentration of "B" in the BN source is E22 / cm 3 ~E23 / cm 3 Between, doping concentration E20 / cm 3Under this circumstance, the consumed "B" source accounts for 1% to 1‰ of the total "B" source, and the opening size is greater than 1 / 100 of the isolation conductor size. Taking the above-mentioned diffusion depth Y = 40μm as an example, the width of the diffusion window should be greater than 64μm / 100 = 0.64μm. However, in order not to affect the diffusion efficiency (considering economic benefits) and to avoid excessive diffusion of by-products into the window (considering quality control), it is particularly important to appropriately adjust the opening size. Therefore, it is best to set the width of the diffusion window to 5μm to 15μm.

[0116] In some optional embodiments, the step of isotropically doping the oxide layer 2 and the silicon wafer 1 through the diffusion window 5 and forming the doping layer 7 on the side of the silicon wafer 1 facing the oxide layer 2 includes:

[0117] Taking BN as the doping source, O2 and H2 are introduced at the first diffusion temperature and maintained for a certain time to activate BN; at the second diffusion temperature, H2 is stopped and only O2 is introduced and maintained for a certain time to convert BN into B2O3 to complete pre-doping; the first diffusion temperature is 400℃~550℃; the second diffusion temperature is 600℃~800℃;

[0118] Allow B2O3 to penetrate and diffuse into the oxide layer 2 to form a mixed doping source;

[0119] N2 and O2 are introduced at a third diffusion temperature, so that the mixed doping source precipitates B atoms, and the B atoms are diffused into the silicon wafer 1 to form a B-doped P-type doping layer; the third diffusion temperature is 1200°C to 1280°C.

[0120] In some optional embodiments, the material of the oxide layer 2 is silicon dioxide; the material of the isolation layer 3 is Si3N4;

[0121] The thickness of oxide layer 2 is For example or

[0122] The thickness of the isolation layer 3 is For example or

[0123] The doping concentration of the doping layer 7 is greater than or equal to E20 / cm 3 ;

[0124] The roughness of the doped layer 7 is less than 0.5.

[0125] In some optional embodiments, before the step of forming the oxide layer 2 on one side of the silicon wafer 1 , the step further includes: performing a pre-cleaning process on the silicon wafer 1 .

[0126] The pre-cleaning process includes: cleaning with 120°C SC3 (H2SO4:H2O2=5:1) solution for 10 minutes; cleaning with room temperature DHF (HF:H2O=1:100) solution for 30 seconds; cleaning with 65°C SC1 (NH4OH:H2O2:H2O=1:1:7) solution for 10 minutes; cleaning with 65°C SC2 (HCl:H2O2:H2O=1:1:7) solution for 10 minutes.

[0127] In some optional embodiments, the material of the oxide layer 2 is silicon dioxide; the step of forming the oxide layer 2 on the surface of one side of the silicon wafer 1 includes: growing a layer of Thickness SiO2( The thermal oxidation temperature is controlled in the range of 785℃~875℃. The silicon dioxide grown in this temperature range has a low density, which is conducive to being penetrated by B2O3 and has a good silicon dioxide / silicon interface.

[0128] In some optional embodiments, the material of the isolation layer 3 is Si3N4; the step of forming the isolation layer 3 on the surface of the oxide layer 2 facing away from the silicon wafer 1 includes: depositing a layer of Si3N4 on SiO2 by LPCVD (low pressure chemical vapor deposition) at a process temperature of 760°C to 900°C (the temperature determines the blocking effect of Si3N4, which is specifically selected according to the diffusion depth Y and the doping concentration), and the specific thickness of Si3N4 is selected according to the doping depth of the "p" type region of the product design, so that the diffusion rate of "B" in Si3N4 is one percent of its diffusion rate in Si. Si3N4 serves as a shielding layer for B2O3 and other byproducts to contact the Si surface, and also as a diffusion window.

[0129] like Fig.11 The present invention also provides a specific flow chart of a diffusion doping method, which includes the following steps:

[0130] Step S201, providing a silicon wafer 1; and performing a pre-cleaning process on the silicon wafer 1.

[0131] In specific implementation, the pre-cleaning process includes: cleaning with 120°C SC3 (H2SO4:H2O2=5:1) solution for 10 minutes; cleaning with room temperature DHF (HF:H2O=1:100) solution for 30 seconds; cleaning with 65°C SC1 (NH4OH:H2O2:H2O=1:1:7) solution for 10 minutes; cleaning with 65°C SC2 (HCl:H2O2:H2O=1:1:7) solution for 10 minutes.

[0132] Step S202, forming an oxide layer 2 on one side of the silicon wafer 1; the material of the oxide layer 2 is silicon dioxide.

[0133] In the specific implementation, at a process temperature of 850°C, 8SLM of O2 is introduced into the oxidation furnace tube and maintained for a certain period of time to form an oxide layer 2 on the surface of one side of the silicon wafer 1. The material of the oxide layer 2 is silicon dioxide, such as Figure 2 The chemical reaction formula is: Si+O2→SiO2. A layer of Thick SiO2 serves as a buffer layer for direct contact between B2O3 and other byproducts and silicon in the subsequent doping process.

[0134] Step S203, forming an isolation layer 3 on the surface of the oxide layer 2 facing away from the silicon wafer 1 by LPCVD process; the material of the isolation layer 3 is Si3N4.

[0135] In the specific implementation, in the LPCVD equipment, at a process temperature of 760°C to 900°C, 300 SCCM of SiH2Cl2 and 2400 SCCM of NH3 are introduced, and maintained for a certain period of time to form an isolation layer 3 on the surface of the oxide layer 2; the material of the isolation layer 3 is Si3N4, such as Figure 3 As shown. The chemical reaction formula is: 3SiH2Cl2+4NH3→Si3N4+6HCl+6H2.

[0136] Step S204, forming a patterned photoresist layer 4 on the side of the isolation layer 3 facing away from the oxide layer 2, such as Figure 4 shown.

[0137] During specific implementation, a photoresist layer 4 corresponding to the diffusion window is formed through coating, exposure and development.

[0138] Step S205, patterning the isolation layer 3 according to the photoresist layer 4 to form a plurality of diffusion windows 5, the diffusion windows 5 penetrate the isolation layer 3 and expose a portion of the surface of the oxide layer 2 facing away from the silicon wafer 1, such as Figure 4 As shown; the isolation layer 3 between adjacent diffusion windows 5 constitutes an isolation region.

[0139] In specific implementation, Si3N4 dry etching is used to open the diffusion window 5. The diffusion window is a groove with a square cross section; the width of the diffusion window is 5μm to 15μm; the diffusion depth Y is 40μm; the width A of the isolation layer between adjacent diffusion windows 5 is 50μm to 64μm.

[0140] Step S206, isotropically doping the oxide layer 2 and the silicon wafer 1 with a doping source 6 from the diffusion window 5, and forming a doping layer 7 on the side of the silicon wafer 1 facing the oxide layer 2; the doping layer 7 is a continuous structure on the entire surface; at the same time, a by-product 8 is formed on the surface of the oxide layer 2 facing away from the silicon wafer 1 and the surface of the isolation layer 3 facing away from the oxide layer 2 during the doping process; the components of the by-product include B2O3.

[0141] In the specific implementation, first use BN as the doping source, maintain the furnace temperature at 450°C (at this temperature, the hard-to-remove components in the by-products are the least), first introduce 8SLM of O2 and 3SLM of H2 and maintain for 3 minutes to activate BN; then raise the temperature to 675°C (at this temperature, the conversion rate of BN to B2O3 is best matched with the utilization efficiency of the BN source), stop introducing H2, and only introduce 8SLM of O2 and maintain for a certain time to convert BN into B2O3 to complete the pre-doping; at the same time, allow B2O3 to penetrate and diffuse into the oxide layer to form a mixed doping source; finally, raise the temperature to 1200°C~1280°C, introduce 10SLM of N2 and 100SCCM of O2, and maintain for a certain time, so that the mixed doping source precipitates B atoms, and diffuses the B atoms into the silicon wafer to form a B-doped P-type heavily doped region, and form B2O3 and other by-products on the surface of the silicon wafer. The chemical reaction formulas involved in this step are: O2+2H2→2H2O; 3H2O+2BN→B2O3+2NH3; 3O2+4BN→2B2O3+2N2; 2B2O3+3Si→4B+3SiO2.

[0142] Step S207, first cleaning process: using a first cleaning solution at a first cleaning temperature to preliminarily remove the by-product 8.

[0143] In the specific implementation, the first cleaning temperature is 23°C; the first cleaning solution is BOE buffered oxide etching solution; the composition of the first cleaning solution is NH4F:HF=7.5:1; the corrosion rate of the first cleaning process is The cleaning time of the first cleaning process is 150 seconds.

[0144] Step S208, second cleaning process: using a second cleaning solution at a second cleaning temperature to remove the isolation layer 3 and the byproducts 8 remaining on the surface of the isolation layer 3.

[0145] In the specific implementation, the second cleaning temperature is 160°C, the second cleaning liquid is composed of H3PO4, the second cleaning liquid is isotropic etching, and the second cleaning process is 120% over-etching. The Si3N4 layer is stripped by H3PO4 etching, and the B2O3 and other byproducts remaining on the surface of Si3N4 are removed.

[0146] Step S209, third cleaning process: using a third cleaning solution at a third cleaning temperature to remove the oxide layer 2 and the byproducts 8 remaining on the surface of the oxide layer 2.

[0147] In the specific implementation, the third cleaning temperature is 23°C; the third cleaning liquid is BOE buffered oxide etching liquid; the composition of the third cleaning liquid is NH4F:HF=7.5:1; the third cleaning liquid is isotropic etching. The bottom SiO2 layer is stripped by BOE etching (etching time 30s), and the B2O3 and other byproducts remaining on the SiO2 surface are removed.

[0148] Step S210: surface microscopic inspection, SiO2 residual film test, and roughness Rs test.

[0149] In one example, silicon wafers 1#, 2#, and 3# are processed as follows: Fig.11 The process flow shown in the figure was used for doping, and the conventional diffusion doping process in the prior art was performed on silicon wafers 4#, 5#, and 6#. In order to further determine the surface damage of the wafer, the surface roughness of the six doped silicon wafers was tested, and the test data is shown in the following table:

[0150] Table 1 Comparison of silicon wafer surface roughness

[0151]

[0152] Table 1 shows the measurement results of the silicon wafer surface roughness after the diffusion process. The results show that the diffusion process causes almost no damage to the silicon wafer surface.

[0153] In order to further determine the removal effect of B2O3, other byproducts and SiO2, the SiO2 residual film test was carried out on the silicon wafer (this verification of the previous value of the SiO2 film thickness ), the test data is shown in the following table:

[0154] Table 2 SiO2 residual film thickness on silicon wafer surface

[0155]

[0156] Table 2 shows the measurement results of the SiO2 residual film thickness on the silicon wafer surface after the diffusion process is completed. The results show that the degree of oxidation on the silicon wafer surface is better than the natural oxidation of silicon in the air (natural oxide layer thickness: ) level, indicating that there is no SiO2, B2O3 and other by-products on the silicon wafer surface.

[0157] To further determine the doping concentration, the silicon wafer was tested for Rs. The test data is shown in the following table:

[0158] Table 3 Silicon wafer surface Rs (sheet resistance) data

[0159]

[0160] Table 3 shows the measurement results of Rs on the silicon wafer surface after the diffusion process. The results show that after the diffusion process, the entire surface of the silicon wafer is doped, and the doping concentration of the p-type doping area is greater than 1E20 / cm 3 .

[0161] In order to visually observe the surface conditions of the silicon wafers after the two diffusion processes, the images under a 500x microscope were compared. Figure 12A to Figure 12B This is a conventional diffusion doping process effect diagram in the prior art. Fig. 12A This is the macroscopic appearance of the doped silicon wafer. Fig. 12B This is an image of the surface roughness of a silicon wafer taken under a 500x microscope. Figures 13A to 13B The diffusion doping process effect diagram provided in this embodiment is as follows: Fig.13A This is the macroscopic appearance of the doped silicon wafer. Fig. 13B The image of the surface roughness of the silicon wafer under a 500-fold microscope. In the description of this specification, the description of the reference terms "this embodiment", "an embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily target the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples without contradiction. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" can explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0162] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0163] The above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described above, and that various obvious changes, readjustments, combinations and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention is described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may also include more other equivalent embodiments without departing from the concept of the present invention. The scope of protection of the present invention is determined by the scope of the attached claims.

Claims

1. A diffusion doping method, characterized in that: include: Provide silicon wafers; forming an oxide layer on a surface of one side of the silicon wafer; forming an isolation layer on a surface of the oxide layer facing away from the silicon wafer; Performing a patterning process on the isolation layer to form a plurality of diffusion windows, wherein the diffusion windows penetrate the isolation layer and expose a portion of the surface of the oxide layer facing away from the silicon wafer; doping the oxide layer and the silicon wafer with a doping source from the diffusion window to form a doping layer on a side of the silicon wafer facing the oxide layer; The surface of the oxide layer facing away from the silicon wafer and the surface of the isolation layer facing away from the oxide layer form byproducts during the doping process; The oxide layer, the isolation layer and the by-products are removed by a cleaning process.

2. The diffusion doping method according to claim 1, characterized in that: The cleaning process includes a first cleaning process, a second cleaning process and a third cleaning process; The first cleaning process includes: using a first cleaning solution at a first cleaning temperature to preliminarily remove the byproducts; The second cleaning process includes: removing the isolation layer and residual byproducts on the surface of the isolation layer by using a second cleaning solution at a third cleaning temperature; The third cleaning process includes: using a third cleaning solution at a third cleaning temperature to remove the oxide layer and residual byproducts on the surface of the oxide layer.

3. The diffusion doping method according to claim 2, characterized in that: The components of the by-product include B2O3; The first cleaning solution and the third cleaning solution are BOE buffered oxide etching solutions; The second cleaning solution comprises H3PO4; The first cleaning temperature and the third cleaning temperature are 20°C to 25°C; The second cleaning temperature is 160°C to 190°C.

4. The diffusion doping method according to claim 3, characterized in that: The second cleaning liquid and the third cleaning liquid are isotropically corrosive; The composition of the first cleaning solution and the third cleaning solution is NH4F:HF=7.5:1; The corrosion rate of the first cleaning process The second cleaning process is an over-etching process of 120%.

5. The diffusion doping method according to claim 1, characterized in that: The step of doping the oxide layer and the silicon wafer with a doping source from the diffusion window, and forming a doping layer on a side of the silicon wafer facing the oxide layer comprises: The oxide layer and the silicon wafer are isotropically doped using a doping source from the diffusion window to form a doping layer on a side of the silicon wafer facing the oxide layer; the doping layer is a whole-surface continuous structure.

6. The diffusion doping method according to claim 5, characterized in that: The doping source simultaneously diffuses downward longitudinally and diffuses laterally to the surroundings in the oxide layer and the silicon wafer; The lateral diffusion rate V1 is smaller than the longitudinal diffusion rate V2; On a cross section perpendicular to the surface of the silicon wafer, the lateral diffusion distance X is greater than the diffusion depth Y; The width A of the isolation layer between adjacent diffusion windows is less than or equal to the distance X of the lateral diffusion and greater than the diffusion depth Y.

7. The diffusion doping method according to claim 6, characterized in that: The lateral diffusion rate V1=0.7V2~0.8V2; The lateral diffusion distance X=1.4Y~1.6Y; The width A of the isolation layer between adjacent diffusion windows is 1.2Y to 1.6Y.

8. The diffusion doping method according to claim 7, characterized in that: The diffusion window is a groove with a square cross section; The width of the diffusion window is 5 μm to 15 μm; The diffusion depth Y is 40 μm; The width A of the isolation layer between adjacent diffusion windows is 50 μm to 64 μm.

9. The diffusion doping method according to claim 5, characterized in that: The step of isotropically doping the oxide layer and the silicon wafer through the diffusion window and forming a doping layer on a side of the silicon wafer facing the oxide layer comprises: Taking BN as the doping source, O2 and H2 are introduced at the first diffusion temperature and maintained for a certain time to activate BN; at the second diffusion temperature, the introduction of H2 is stopped, and only O2 is introduced and maintained for a certain time to convert BN into B2O3 to complete pre-doping; the first diffusion temperature is 400°C to 550°C; the second diffusion temperature is 600°C to 800°C; Allowing B2O3 to penetrate and diffuse into the oxide layer to form a mixed doping source; N2 and O2 are introduced at a third diffusion temperature, so that the mixed doping source precipitates B atoms, and the B atoms are diffused into the silicon wafer to form a B-doped P-type doping layer; the third diffusion temperature is 1200°C to 1280°C.

10. The diffusion doping method according to claim 1, characterized in that: The material of the oxide layer is silicon dioxide; the material of the isolation layer is Si3N4; The thickness of the oxide layer is The thickness of the isolation layer is The doping concentration of the doping layer is greater than or equal to E20 / cm 3 ; The roughness of the doping layer is less than 0.5.

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