Preparation method of semiconductor device
By forming an epitaxial layer on the silicon carbide substrate and performing high-temperature ion implantation, combined with ion implantation on the second surface to release internal stress, the warping problem caused by high-temperature ion implantation is solved and the lithography accuracy is improved.
Patent Information
- Application Number
- CN202411335698.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-24
- Publication Date
- 2025-04-18
AI Technical Summary
During semiconductor device manufacturing process, high-temperature ion implantation will destroy the lattice structure of the silicon carbide wafer, resulting in an increase in internal stress and an increase in warpage, affecting the photolithography accuracy.
An epitaxial layer is formed on the silicon carbide substrate and ion implanted in a high temperature state to form a functional area. Then ion implantation is performed on the second surface, destroying its lattice structure to release internal stress and reduce warpage.
By releasing the internal stress generated by high-temperature ion implantation, the warpage of the silicon carbide wafer is reduced, the photolithography accuracy is improved, and the smoothness of the device structure and the uniformity of the photoresist are ensured.
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Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor device. Background Art
[0002] The photolithography process for silicon carbide wafers is one of the important process flows for forming semiconductor devices. In the manufacturing process of semiconductor devices, there are also a large number of high-temperature ion implantation processes. High-temperature ion implantation will destroy the lattice structure of the silicon carbide wafer and cause the silicon carbide wafer to produce large internal stress, causing the surface of the epitaxial layer of the silicon carbide wafer to warp, thereby affecting the epitaxial layer and the silicon carbide substrate, as well as the lithography accuracy of the device structure arranged on the epitaxial layer. Summary of the invention
[0003] The present application proposes a method for preparing a semiconductor device, aiming to improve the lithography accuracy of a silicon carbide wafer.
[0004] In a first aspect, an embodiment of the present application provides a method for preparing a semiconductor device, the method comprising forming an epitaxial layer on a silicon carbide substrate, the epitaxial layer comprising a first surface away from the silicon carbide substrate, the silicon carbide substrate comprising a second surface away from the epitaxial layer, performing ion implantation on the first surface to form a functional area, forming a protective layer covering the first surface, then performing ion implantation on the second surface, and then removing the protective layer.
[0005] In some embodiments, the functional region is a well region. After the well region is formed, a protective layer covering the first surface is formed, ions are implanted into the second surface, and the protective layer is removed.
[0006] In some embodiments, after removing the protective layer, the preparation method also includes forming a mask layer on the first surface, forming a photoresist layer, the photoresist layer being located on a side of the mask layer away from the silicon carbide substrate, exposing and developing the photoresist layer, forming a first opening in the photoresist layer, etching the mask layer through the first opening, forming a second opening in the mask layer, and performing ion implantation on the first surface through the second opening to form a contact area.
[0007] In some embodiments, the functional region is a contact region. After the contact region is formed, a protection layer covering the first surface is formed, and then ions are implanted into the second surface, and then the protection layer is removed.
[0008] In some embodiments, after removing the protective layer, the preparation method also includes forming a gate conductive layer on the first surface, forming a photoresist layer, the photoresist layer being located on a side of the gate conductive layer away from the silicon carbide substrate, exposing and developing the photoresist layer, forming a third opening in the photoresist layer, and etching the gate conductive layer through the third opening to form a gate.
[0009] In some embodiments, after forming the gate, the preparation method further includes forming a source electrode, the source electrode is located on a side of the gate away from the first surface, grinding the second surface, and forming a drain electrode on the second surface.
[0010] In some embodiments, the orthographic projection of the ion-implanted region of the second surface on the first surface covers the ion-implanted region of the first surface.
[0011] In some embodiments, the ions implanted into the second surface are of the same conductivity type as the material of the silicon carbide substrate.
[0012] In some embodiments, the conductivity type of the material of the silicon carbide substrate is N-type, and the conductivity type of the ions implanted into the second surface is N-type.
[0013] In some embodiments, forming the protection layer includes depositing a dielectric material on the first surface to form the protection layer.
[0014] In an embodiment of the present application, ion implantation is performed on the first surface of the epitaxial layer at a high temperature, causing the first surface to warp. After the ion implantation is performed on the first surface, a protective layer covering the first surface is formed, and then ion implantation is performed on the second surface. The protective layer can protect the first surface during the ion implantation of the second surface to prevent scratches from being formed on the first surface. The ion implantation performed on the second surface can destroy the lattice structure of the second surface and release the internal stress generated by multiple ion implantations performed on the first surface, thereby reducing the warpage of the first surface and improving the lithography accuracy of the silicon carbide substrate, the epitaxial layer, and the device structure arranged on the epitaxial layer.
[0015] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] In order to more clearly illustrate the technical solutions in the present application, the following is a brief introduction to the drawings required for use in some embodiments of the present application. Obviously, the drawings described below are only drawings of some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the products involved in the embodiments of the present application, the actual process of the method, etc.
[0017] Figure 1 A flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application;
[0018] Figure 2 to Figure 16 for Figure 1 A diagram of the steps in preparing a semiconductor device;
[0019] Fig.17 A flow chart of another method for preparing a semiconductor device provided in an embodiment of the present application;
[0020] Figure 18 to Figure 21 for Fig.17 A diagram of the steps in preparing a semiconductor device;
[0021] Fig. 22 A flow chart of another method for preparing a semiconductor device provided in an embodiment of the present application;
[0022] Figure 23 to Figure 25 for Fig. 22 A diagram of the steps in preparing a semiconductor device. DETAILED DESCRIPTION
[0023] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.
[0024] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.
[0025] In the description of the present application, “plurality” means two or more.
[0026] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.
[0027] In the existing semiconductor manufacturing process, there are a large number of high-temperature ion implantation processes to form ion implantation areas such as well areas and source areas on silicon carbide wafers. These areas determine the electrical properties of semiconductor devices. However, the process of high-temperature ion implantation will destroy the lattice structure of the silicon carbide wafer, and cause the silicon carbide wafer to bear greater stress inside, resulting in an increase in the warpage of the silicon carbide wafer surface. As the number of high-temperature ion implantations increases, the warpage of the silicon carbide wafer surface will also increase. A subsequent photolithography process is required. During the exposure of the photoresist, due to the increase in the warpage of the silicon carbide wafer surface, the light irradiation of the covering photoresist is uneven, which in turn deteriorates the alignment accuracy of the photolithography machine, affecting the critical dimension (Critical Dimension, CD), thereby affecting the photolithography accuracy of the device structure on the silicon carbide wafer.
[0028] In order to solve the above problems, the present invention provides a method for preparing a semiconductor device. Figure 1 A flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application, Figure 2 to Figure 16 1 is a diagram of the steps of preparing a semiconductor device in an embodiment of the present application. Figure 1 As shown, the preparation method includes the following steps S1 to S14:
[0029] Step S1: Figure 2 As shown, an epitaxial layer 10b is formed on a silicon carbide substrate 10a to obtain a silicon carbide wafer 10, the conductivity type of the silicon carbide wafer 10 is a first conductivity type, the epitaxial layer 10b includes a first surface 101 away from the silicon carbide substrate 10a, and the silicon carbide substrate 10a includes a second surface 102 away from the epitaxial layer 10b, that is, the silicon carbide wafer 10 includes a first surface 101 and a second surface 102 that are arranged opposite to each other.
[0030] Step S2: performing ion implantation on the first surface 101 to form a functional area.
[0031] In some embodiments, Figure 3 As shown, the functional area is a well region 11, and the conductivity type of the well region 11 is different from that of the silicon carbide wafer 10, that is, a second conductivity type. For example, the conductivity type of the silicon carbide wafer 10 is N-type, and P-type ions are implanted into the first surface 101 to obtain the well region 11, and the well region 11 can be called a "P-type well region (P-well)".
[0032] Step S3: Figure 4 As shown, a protection layer 12 is formed to cover the first surface 101 .
[0033] In some embodiments, the specific step of forming the protective layer 12 is to deposit a dielectric material on the first surface 101 and then form the protective layer 12. The protective layer 12 can be used to protect the first surface 101 of the silicon carbide wafer 10 to prevent scratches on the first surface 101 during the process of transporting the silicon carbide wafer 10. Exemplarily, the dielectric material can be silicon oxide.
[0034] Step S4: Figure 5 As shown, the silicon carbide wafer 10 is turned over to invert the silicon carbide wafer 10, and ions are implanted into the second surface 102 to form an ion implantation area 10c. The protective layer 12 can be used as a carrier, so that during the ion implantation process of the second surface 102, the protective layer 12 can support and protect the silicon carbide wafer 10.
[0035] During the ion implantation process of the first surface 101 in the above step S2 , the high temperature ion implantation destroys part of the lattice structure in the silicon carbide wafer 10 , and generates a large internal stress in the silicon carbide wafer 10 , which causes a certain degree of warping of the first surface 101 .
[0036] In some embodiments, by setting the orthographic projection of the ion-implanted region of the second surface 102 on the first surface 101 to cover the ion-implanted region of the first surface 101, a large area of ion implantation is performed on the second surface 102 of the silicon carbide wafer 10, so that the lattice structure of the second surface 102 is destroyed, and the stress existing in the well region 11 corresponding to the second surface 102 in the Z direction is released. The orthographic projection of the ion-implanted region of the second surface 102 on the first surface 101 covers the ion-implanted region of the first surface 101, that is, the orthographic projection area of the ion implantation region 10c on the first surface 101 is larger than the orthographic projection area of the well region 11 on the first surface 101, ensuring that the stress generated by ion implantation to form the well region 11 is fully released, so that the warpage of the silicon carbide wafer 10 is reduced to the greatest extent.
[0037] In some embodiments, the conductivity type of the material of the silicon carbide substrate 10a and the epitaxial layer 10b is N-type, and the conductivity type of the ions implanted into the second surface 102 is also N-type. The ions implanted into the second surface 102 are consistent with the conductivity type of the material of the silicon carbide wafer 10, so that the stress generated by the first ion implantation in the silicon carbide wafer 10 can be released, and in the subsequent process of manufacturing the semiconductor, after the second surface 102 of the silicon carbide wafer 10 is polished, the conductivity type of the second surface 102 will not be changed regardless of whether there is a residue of the ion implantation area 10c on the second surface 102.
[0038] Step S5: Figure 6As shown, the protective layer 12 is removed. The protective layer 12 can be removed by any one of wet etching, dry etching and chemical vapor etching, which can achieve the effect of completely removing silicon oxide.
[0039] In some embodiments, after removing the protective layer 12, the preparation method further includes the following steps S6 to S9:
[0040] Step S6: Figure 7 As shown, a mask layer 14 is formed on the first surface 101. Exemplarily, the material of the mask layer 14 can be any one of silicon oxide, polysilicon, and a composite film layer of silicon oxide and polysilicon.
[0041] Step S7: Figure 8 As shown, photoresist is coated on the side of the mask layer 14 away from the silicon carbide substrate 10 a to form a photoresist layer 15 , and then the photoresist layer 15 is exposed and developed to form a first opening 151 in the photoresist layer 15 .
[0042] In the process of exposing the photoresist layer 15, since the above steps perform ion implantation on the second surface 102, the lattice structure of the second surface 102 is destroyed, so that the internal stress of the first surface 101 is released, the warpage of the first surface 101 is reduced, and the flatness of the silicon carbide wafer 10 is improved, which is conducive to the leveling of the photoresist on the first surface 101, and the thickness uniformity of each region of the photoresist is improved, so as to improve the uniformity of light irradiation received by each region of the photoresist, thereby increasing the flatness of the photoresist layer 15. Since the flatness of the photoresist layer 15 is increased, the alignment accuracy of the photolithography system is effectively improved in the process of forming the first opening 151, and the control of the key size is more accurate.
[0043] Step S8: Fig. 9 As shown, the mask layer 14 is etched through the first opening 151 to form a second opening 141 in the mask layer 14 .
[0044] Step S9: Fig.10 As shown, ions are implanted into the first surface 101 through the second opening 141 to form a contact region. Exemplarily, the contact region is an N+ contact region 130. After the contact region is formed, the mask layer 14 is etched away.
[0045] After completing step S9, Fig.11 As shown, ion implantation is continued on the first surface 101 through a photolithography process to form a P+ contact region 131 , thereby forming a complete functional region.
[0046] In some embodiments, after completing the above steps, the preparation method further includes the following steps S10 to S14:
[0047] Step S10: Fig.12 As shown, a gate oxide is deposited on the first surface 101, and after a photoresist is coated on the side of the gate oxide away from the silicon carbide wafer 10, the photoresist is exposed and developed to obtain a third opening, and the gate oxide is etched through the third opening to obtain a gate oxide layer 18 to isolate the gate and the N+ contact area 130 to prevent the semiconductor device from short circuiting.
[0048] Step S11: Fig.13 As shown, a gate conductive layer is deposited on the side of the gate oxide layer 18 away from the silicon carbide wafer 10, and after photoresist is coated on the side of the gate conductive layer away from the silicon carbide wafer 10, the photoresist is exposed and developed to obtain a fourth opening, and the gate conductive layer is etched through the fourth opening to obtain the gate 16.
[0049] Step S12: Fig.14 As shown, a layer of dielectric is deposited on the side of the gate 16 away from the silicon carbide wafer 10, and after the dielectric is coated with photoresist on the side of the dielectric away from the silicon carbide wafer 10, the photoresist is exposed and developed to obtain a fifth opening, and the dielectric is etched through the fifth opening to obtain a dielectric layer 19.
[0050] Step S13: Fig.15 As shown, a source conductive layer is deposited on the side of the dielectric layer 19 away from the silicon carbide wafer 10, and after the side of the source conductive layer away from the silicon carbide wafer 10 is coated with photoresist, the photoresist is exposed and developed to obtain a sixth opening, and the source conductive layer is etched through the sixth opening to obtain the source 17.
[0051] In the process of forming the gate 16 and the source 17 in steps S10 to S13, since the second surface 102 is ion implanted in steps S3 to S5, the lattice structure of the second surface 102 is destroyed, so that the internal stress of the first surface 101 is released, the warping of the silicon carbide wafer 10 is reduced, and the flatness of the silicon carbide wafer 10 is improved. In the process of exposing the photoresist, the light exposure to each part of the photoresist is more uniform, so that the accuracy of the photolithography is improved, and thus the photolithography accuracy of the gate 16, the source 17, the gate oxide layer 18 and the dielectric layer 19 is also improved.
[0052] Step S14: Fig.16As shown, the second surface 102 is ground and a drain 20 is formed on the second surface 102. In the process of grinding and thinning the second surface 102, due to the process of ion implantation on the second surface 102 in step S3, the conductivity type of the second surface 102 does not change, so even if the second ion implantation area 10c is not completely thinned and removed in this step, it will not affect the crystal quality of the silicon carbide wafer 10. After the second surface 102 is ground and thinned, a drain 20 is formed on the second surface 102, and finally the preparation of the semiconductor device 1 is completed, wherein the semiconductor device 1 is a silicon carbide metal oxide semiconductor field effect transistor (SiC MOSFET).
[0053] The embodiment of the present application also provides another method for preparing a semiconductor device, and this method can also complete the preparation of the semiconductor device 1. Fig.17 A flow chart of another method for preparing a semiconductor device provided in an embodiment of the present application, Figure 18 to Figure 21 for Fig.17 The steps of the preparation method are shown in FIG. Fig.17 As shown, the preparation method includes the following steps S1 to S6:
[0054] Step S1: As above Figure 2-Figure 3 In the illustrated embodiment, ion implantation is performed on the first surface 101 of the silicon carbide wafer 10 to form a well region 11 .
[0055] Step S2: Fig.18 As shown, ion implantation is performed on the first surface 101 to form an N+ contact region 130 , and the N+ contact region 130 has the same conductivity type as the material of the silicon carbide wafer 10 .
[0056] The two high-temperature ion implantations performed on the first surface 101 of the silicon carbide wafer 10 in steps S1 to S2 destroy part of the lattice structure in the silicon carbide wafer 10 and generate large internal stress in the silicon carbide wafer 10, which causes a certain degree of warping of the first surface 101.
[0057] Step S3: Fig.19 As shown, a dielectric material is deposited on the first surface 101 to form a protective layer 12 covering the first surface 101. The protective layer 12 can be used to protect the first surface 101 of the silicon carbide wafer 10 to prevent scratches on the first surface 101 during the process of transporting the silicon carbide wafer 10. Exemplarily, the dielectric material can be silicon oxide.
[0058] Step S4: Fig. 20As shown, the silicon carbide wafer 10 is flipped over so that the silicon carbide wafer 10 is inverted, and the protective layer 12 is used as a carrier to support and protect the silicon carbide wafer 10, and then ions are implanted into the second surface 102 to form an ion implantation area 10c, and the conductivity type of the ion implantation area 10c is the same as the conductivity type of the material of the silicon carbide wafer 10.
[0059] In an embodiment of the present application, a large area of ion implantation is performed on the second surface 102 of the silicon carbide wafer 10, so that the lattice structure of the second surface 102 is destroyed, thereby releasing the stress of the well region 11 and the N+ contact region 130 corresponding to the second surface 102 in the Z direction, and the orthographic projection of the ion-implanted area of the second surface 102 on the first surface covers the ion-implanted area of the first surface 101, ensuring that the stress generated by the two ion implantations on the first surface 101 is fully released, thereby minimizing the warping of the silicon carbide wafer 10.
[0060] Step S5: Fig.21 As shown, the protective layer 12 is removed. The protective layer 12 can be removed by any one of wet etching, dry etching and chemical vapor etching, which can achieve the effect of completely removing silicon oxide.
[0061] Step S6: As above Figures 11 to 16 In the embodiment shown, the first surface 101 is subjected to a third ion implantation to form a P+ contact region 131, a gate oxide layer 18, a gate 16, a dielectric layer 19 and a source 17 are sequentially formed on the first surface 101, and finally the second surface 102 is ground and a drain 20 is formed on the second surface 102, thereby finally forming a semiconductor device 1.
[0062] Among them, since the ion implantation is performed on the second surface 102 in the above steps S3 to S5, the stress generated by the high-temperature ion implantation on the first surface 101 is released, and the warpage of the silicon carbide wafer 10 is effectively reduced. Not only the accuracy of the implantation window for the ion implantation required to form the P+ contact area 131 is improved, but also the flatness of each structure arranged on the first surface 101 is improved, so that the photoresist layer 15 on each structure is easier to level. In the process of exposing the photoresist layer 15, since the flatness of the photoresist layer 15 is increased, the light exposure of each part of the photoresist is more uniform, the alignment accuracy of the photolithography system is effectively improved, and the control of the key size is more accurate.
[0063] In the process of forming the gate oxide layer 18, the gate 16, the dielectric layer 19 and the source 17, the photolithography process is applied multiple times. Due to the reduction of the warpage of the silicon carbide wafer 10, the flatness of the device structure arranged on the first surface 101 during the deposition process is improved, so that during the exposure process of the photoresist, the light exposure of each part of the photoresist is more uniform, thereby improving the photolithography accuracy of the gate 16, the source 17, the gate oxide layer 18 and the dielectric layer 19.
[0064] The embodiment of the present application also provides another method for preparing a semiconductor device, and this method can also complete the preparation of the semiconductor device 1. Fig. 22 A flow chart of another method for preparing a semiconductor device provided in an embodiment of the present application, Figure 23 to Figure 25 for Fig. 22 The steps of the preparation method are shown in FIG. Fig. 22 As shown, the preparation method includes the following steps S1 to S5:
[0065] Step S1: As above Figure 2 , Figure 3 as well as Fig.18 In the embodiment shown in the figure, a well region 11 and an N+ contact region 130 are formed on the first surface 101 of the silicon carbide wafer 10, and then Fig.23 As shown, the P+ contact area 131 is further formed on the first surface 101. Among them, the conductivity type of the well area 11 and the P+ contact area 131 is the same, both are P-type, and the conductivity type of the silicon carbide wafer 10 and the N+ contact area 130 is the same, both are N-type. The above three high-temperature ion implantation processes on the first surface 101 of the silicon carbide wafer 10 destroy part of the lattice structure in the silicon carbide wafer 10, and generate a large internal stress in the silicon carbide wafer 10, which will cause a certain degree of warping of the first surface 101.
[0066] Step S2: Fig.24 As shown, a dielectric material is deposited on the first surface 101 to form a protective layer 12 covering the first surface 101 . The protective layer 12 can be used to protect the first surface 101 of the silicon carbide wafer 10 to prevent scratches on the first surface 101 during the process of transferring the silicon carbide wafer 10 .
[0067] Step S3: Fig.25 As shown, the silicon carbide wafer 10 is turned over to invert the silicon carbide wafer 10, and ions are implanted into the second surface 102 to form an ion implantation area 10c. The protective layer 12 can be used as a carrier, so that during the ion implantation process of the second surface 102, the protective layer 12 can support and protect the silicon carbide wafer 10.
[0068] Step S4: Remove the protective layer 12 to obtain Fig.11The structure shown.
[0069] After completing the three ion implantations, a protective layer 12 is formed on the first surface 101, and then the silicon carbide wafer 10 is inverted, and ion implantation is performed on the second surface 102. The protective layer is then removed. This process allows the stress generated in the silicon carbide wafer 10 due to the three ion implantations to be completely released, and the warping of the first surface 101 of the silicon carbide wafer 10 is greatly reduced, thereby improving the lithography accuracy of the gate oxide layer 18, the gate 16, the dielectric layer 19 and the source 17 subsequently formed on the first surface 101.
[0070] Step S5: As above Figure 12 to Figure 16 In the illustrated embodiment, a gate oxide layer 18 , a gate 16 , a dielectric layer 19 and a source 17 are sequentially formed on the first surface 101 , and finally the second surface 102 is ground and a drain 20 is formed on the second surface 102 to form a semiconductor device 1 .
[0071] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.
Claims
1. A method for preparing a semiconductor device, characterized in that: include: forming an epitaxial layer on a silicon carbide substrate, wherein the epitaxial layer includes a first surface away from the silicon carbide substrate, and the silicon carbide substrate includes a second surface away from the epitaxial layer; Performing ion implantation on the first surface to form a functional area; forming a protective layer covering the first surface; performing ion implantation on the second surface; The protective layer is removed.
2. The preparation method according to claim 1, characterized in that: The functional region is a well region. After the well region is formed, forming a protective layer covering the first surface; performing ion implantation on the second surface; The protective layer is removed.
3. The preparation method according to claim 2, characterized in that: After removing the protective layer, the preparation method further comprises: forming a mask layer on the first surface; forming a photoresist layer, wherein the photoresist layer is located on a side of the mask layer away from the silicon carbide substrate; exposing and developing the photoresist layer to form a first opening in the photoresist layer; etching the mask layer through the first opening to form a second opening in the mask layer; Ions are implanted into the first surface through the second opening to form a contact region.
4. The preparation method according to claim 1, characterized in that: The functional area is a contact area. After the contact area is formed, forming a protective layer covering the first surface; performing ion implantation on the second surface; The protective layer is removed.
5. The preparation method according to claim 4, characterized in that: After removing the protective layer, the preparation method further comprises: forming a gate conductive layer on the first surface; forming a photoresist layer, wherein the photoresist layer is located on a side of the gate conductive layer away from the silicon carbide substrate; exposing and developing the photoresist layer to form a third opening in the photoresist layer; The gate conductive layer is etched through the third opening to form a gate.
6. The preparation method according to claim 5, characterized in that: After forming the gate, the preparation method further includes: forming a source electrode, wherein the source electrode is located on a side of the gate electrode away from the first surface; The second surface is ground, and a drain electrode is formed on the second surface.
7. The preparation method according to claim 1, characterized in that: The orthographic projection of the ion-implanted region of the second surface on the first surface covers the ion-implanted region of the first surface.
8. The preparation method according to claim 1, characterized in that: The ions implanted into the second surface are of the same conductivity type as the material of the silicon carbide substrate.
9. The preparation method according to claim 8, characterized in that: The conductivity type of the material of the silicon carbide substrate is N-type, and the conductivity type of the ions implanted into the second surface is N-type.
10. The preparation method according to claim 1, characterized in that: Forming the protective layer includes: A dielectric material is deposited on the first surface to form the protection layer.