Manufacturing method of semiconductor device

Abstract

The invention relates to a manufacturing method of a semiconductor device. According to the manufacturing method, after the metal layer and the titanium nitride layer are stacked on the surface of the semiconductor substrate, the tungsten layer is deposited firstly, then annealing is carried out, the metal silicification reaction is carried out on the metal layer and the silicon-containing conductive region, and the situation that the compactness of the titanium nitride layer becomes poor due to advanced annealing can be avoided; the barrier effect of the titanium nitride layer on the process gas in the tungsten layer deposition process is ensured, fluorine or other halogens contained in the process gas are prevented from corroding the lower layer material, and therefore the volcanic defect can be effectively avoided. According to the manufacturing method, the process window for manufacturing the titanium nitride layer is widened, the yield of the device can be improved, the thickness of the titanium nitride layer can be set to be thin, and the problems of tungsten filling and connection resistance increase of the tungsten layer and the silicon-containing conductive region caused by key size reduction can be solved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit manufacturing, and in particular to a method for manufacturing a semiconductor device. Background Art

[0002] The technology of depositing tungsten (W) using chemical vapor deposition (CVD) has been widely used in semiconductor manufacturing processes. This technology deposits a tungsten layer by reducing a tungsten-containing precursor such as tungsten hexafluoride (WF6) using a reducing agent such as hydrogen (H2) through a chemical vapor deposition process.

[0003] The above process can be used to form a tungsten plug to connect a device formed on the surface of a semiconductor substrate with a metal layer formed above the semiconductor substrate. In order to reduce the contact resistance between the tungsten plug and the active area of ​​the substrate, a self-aligned silicide layer is usually formed between the tungsten plug and the corresponding active area.

[0004] In an existing process, a metal layer for forming metal silicide and a titanium nitride layer (TiN) are sequentially deposited on the surface of a semiconductor substrate, followed by annealing to allow the metal layer to undergo a silicidation reaction with the silicon-containing conductive region of the substrate active region, followed by a tungsten deposition process, wherein the titanium nitride layer is used, on the one hand, to enhance tungsten adhesion to avoid tungsten peeling (Wpeeling), and on the other hand, to prevent fluorine free radicals from attacking the underlying layer (F attack) during the tungsten deposition process to produce volcano defects (volcano defects).

[0005] With the development of technology, the critical dimension (CD) of semiconductor devices has shrunk, and the thickness limit of the above-mentioned titanium nitride layer has become more stringent. The increase in the thickness of the titanium nitride layer is likely to cause the deterioration of the hole-filling ability of tungsten and the increase in the connection resistance between tungsten and the silicon-containing conductive area. However, the reduction in the thickness of the titanium nitride layer will make the ability to resist fluorine weaker. After the tungsten deposition is completed using the above-mentioned process, volcano defects are likely to occur, resulting in a very small process window for making the titanium nitride layer. Summary of the invention

[0006] In order to avoid fluorine or other halogens contained in the process gas from corroding the underlying material and generating volcano defects when depositing a tungsten layer using a chemical vapor deposition process, to broaden the process window for producing a titanium nitride layer and to facilitate reducing the thickness of the titanium nitride layer, the present invention provides a method for producing a semiconductor device.

[0007] The method for manufacturing a semiconductor device provided by the present invention comprises the following steps:

[0008] providing a semiconductor substrate having a silicon-containing conductive region with a top surface exposed;

[0009] A metal layer and a titanium nitride layer are sequentially stacked on the surface of the semiconductor substrate, wherein the metal layer is used to perform a metal silicidation reaction with the silicon-containing conductive region;

[0010] Depositing a tungsten layer on the surface of the titanium nitride layer; and

[0011] Annealing is performed to cause a metal silicidation reaction between the metal layer and the silicon-containing conductive region, and a self-aligned silicide layer is formed on the top of the silicon-containing conductive region.

[0012] Optionally, the semiconductor substrate comprises:

[0013] a substrate including an active region; and

[0014] A MOS transistor formed on the surface of the active region, the MOS transistor comprising a gate formed on the active region and a source region and a drain region formed in the active region and located on both sides of the gate, respectively, the silicon-containing conductive region comprising at least one of the source region and the drain region;

[0015] An interlayer dielectric layer covers the substrate and the MOS transistor, and a through hole exposing the silicon-containing conductive region is formed in the interlayer dielectric layer.

[0016] Optionally, sequentially stacking a metal layer and a titanium nitride layer on the surface of the semiconductor substrate comprises:

[0017] forming the metal layer on the upper surface of the interlayer dielectric layer and the inner surface of the through hole;

[0018] The titanium nitride layer is conformally formed along the surface of the metal layer.

[0019] Optionally, when the tungsten layer is deposited on the surface of the titanium nitride layer, the tungsten layer fills the through hole and covers the titanium nitride layer outside the through hole.

[0020] Optionally, when the tungsten layer is deposited on the surface of the titanium nitride layer, a chemical vapor deposition process is adopted, and the process gas includes a reducing agent and a tungsten precursor containing a halogen element.

[0021] Optionally, the tungsten precursor containing halogen elements is at least one of tungsten hexafluoride (WF6), tungsten hexachloride (WCl6) and tungsten pentachloride (WCl5).

[0022] Optionally, before forming the metal layer, a process of removing the natural oxide layer is performed.

[0023] Optionally, the metal layer includes at least one of titanium, tantalum, cobalt and nickel.

[0024] Optionally, the thickness of the titanium nitride layer is

[0025] Optionally, the annealing temperature ranges from 300°C to 800°C.

[0026] In the method for manufacturing a semiconductor device provided by the present invention, after a metal layer and a titanium nitride layer are stacked on the surface of the semiconductor substrate, a tungsten layer is then deposited on the surface of the titanium nitride layer, and then annealing is performed to cause a metal silicide reaction between the metal layer and the silicon-containing conductive area, thereby avoiding the deterioration of the density of the titanium nitride layer due to early annealing, ensuring the barrier effect of the titanium nitride layer on the process gas in the process of depositing the tungsten layer, and avoiding the fluorine or other halogens contained in the process gas from corroding the underlying material, thereby effectively avoiding the generation of volcano defects. The manufacturing method broadens the process window for manufacturing the titanium nitride layer, reduces the impact on the device quality when the thickness of the titanium nitride layer is limited, helps to improve the device yield, and the thickness of the titanium nitride layer can be set to be thinner, thereby further helping to solve the problems of tungsten filling and increased connection resistance between the tungsten layer and the silicon-containing conductive area caused by the reduction of the critical dimension. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic diagram of the effect of depositing a composite layer of a titanium layer and titanium nitride on a semiconductor substrate and performing an annealing process on the curvature of a wafer.

[0028] Figure 2 It is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0029] FIG. 3A to FIG. 3E is a schematic cross-sectional view of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0030] Figure 4 These are device photos obtained by different annealing methods when forming a titanium layer, a titanium nitride layer, and a tungsten layer. DETAILED DESCRIPTION

[0031] The following is a further detailed description of the method for manufacturing a semiconductor device of the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be understood that the drawings of the specification are all in a very simplified form and are all in non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It should be noted that the order of the steps in the method presented herein is not necessarily the only order for performing these steps, and some of the steps described may be omitted and / or some other steps not described herein may be added to the method. It should be understood that spatial relative terms are intended to include different orientations in use or operation in addition to the orientation of the device described in the figure. For example, if the structure in the accompanying drawings is inverted or positioned in other different ways (such as rotation), the exemplary term "on..." may also include "under..." and other orientation relationships.

[0032] In order to solve the problem of volcano defects as described in the background art, the inventors studied the effects of the deposition of metal layers and titanium nitride layers and the annealing process on the curvature of semiconductor substrates. In the experiment, a titanium nitride layer was deposited on a test substrate, and the curvature of the substrate was measured before and after the deposition of the titanium nitride layer, followed by annealing, and the curvature of the substrate after annealing was measured. Figure 1 As shown, compared with not depositing the titanium nitride layer, the change in substrate curvature caused by depositing the titanium nitride layer is a first change BOW1 (experimental calculation value: -1.005), indicating that the titanium nitride layer will form compressive stress on the test substrate; compared with depositing the titanium nitride layer but not annealing, the change in substrate curvature caused by annealing is a second change BOW2 (experimental calculation value: -3.009); compared with not depositing the titanium nitride layer, the change in substrate curvature caused by depositing the titanium nitride layer and annealing is a third change BOW3 (experimental calculation value: -4.014). It can be seen that the third change BOW3 is greater than the first change BOW1 and the second change BOW2.

[0033] According to the above research, annealing immediately after the titanium nitride layer is deposited will result in greater compressive stress in the substrate, so that the weaker titanium nitride layer area is easily damaged. If the tungsten deposition process is then performed, the fluorine free radicals in the process gas will easily pass through the damaged titanium nitride layer area and come into contact with the underlying material (such as titanium) and react chemically, resulting in the formation of volcano defects. The chemical reaction formula of tungsten hexafluoride and titanium is shown in the following formula (1) and formula (2):

[0034] 2WF6+3Ti——>2W+3TiF4↑ (1)

[0035] WF6+2Ti——>W+2TiF3 (2)

[0036] After the above research, in this application, in order to avoid the deterioration of the film quality of the titanium nitride layer between the metal layer and the tungsten layer after annealing and to ensure that the titanium nitride layer has better barrier properties in the tungsten deposition process, the annealing process for generating the metal silicide reaction is performed after the tungsten deposition process. Figures 2 to 3E A method for manufacturing a semiconductor device according to an embodiment of the present invention is described.

[0037] Reference Figure 2 as well as Figure 3A , performing step S1, providing a semiconductor substrate, the semiconductor substrate having a silicon-containing conductive region 101 with an exposed top surface. In this embodiment, a self-aligned silicide layer is formed on the top of the silicon-containing conductive region 101, and a subsequently formed tungsten layer is electrically connected to the silicon-containing conductive region through the self-aligned silicide layer.

[0038] The semiconductor substrate may include a substrate 100, such as a silicon substrate, an SOI (Silicon On Insulator) substrate or other substrates having a silicon-containing conductive region. The substrate 100 may be provided with an active region and an isolation region for isolating the active region. The substrate 100 may also be implanted with certain doping ions to change electrical parameters according to design requirements. The semiconductor substrate may also include electronic components formed on the surface of the active region, such as a MOS transistor. The MOS transistor may include a gate dielectric layer and a gate stacked on the surface of the corresponding active region, and a source region and a drain region formed in the active region and respectively located on both sides of the gate. The silicon-containing conductive region 101 may include at least one of the source region and the drain region. When the gate is a polysilicon gate, the silicon-containing conductive region 101 may also include a polysilicon gate. Figure 3A Only a portion of the semiconductor substrate is shown.

[0039] As an example, Figure 3A As shown, the silicon-containing conductive region 101 may include a germanium-silicon epitaxial layer. The germanium-silicon epitaxial layer is formed by an epitaxial process in a trench formed at the position corresponding to the source region and the drain region of the PMOS transistor, and serves as the source region and the drain region of the PMOS transistor.

[0040] The semiconductor substrate may further include an interlayer dielectric layer 110 , which covers the semiconductor substrate and has a through hole 110 a formed therein to expose the silicon-containing conductive region 101 . The through hole 110 a is used to subsequently form a tungsten plug electrically connected to the silicon-containing conductive region 101 .

[0041] Since the surface of the silicon-containing conductive region 101 is exposed, a natural oxide layer 102 will be formed in the exposed region during the waiting time for the subsequent process. The natural oxide layer 102 will affect the subsequent metal silicidation reaction and contact resistance of the region. Therefore, according to the formation of the natural oxide layer 102, before the subsequent steps are performed, a process of removing the natural oxide layer 102 can be performed first. For example, the natural oxide layer 102 can be removed by wet cleaning or dry etching. After removing the natural oxide layer 102, the following is obtained: Figure 3B The semiconductor substrate is shown.

[0042] Reference Figure 2 as well as Figure 3C , perform step S2, stack a metal layer 120 and a titanium nitride layer 130 on the surface of the semiconductor substrate in sequence, the metal layer 120 is used to perform a metal silicidation reaction with the silicon-containing conductive area 101. Specifically, the metal layer 120 can be first formed on the upper surface of the interlayer dielectric layer 110 and the inner wall of the through hole 110a, and then the titanium nitride layer 130 is conformally formed along the surface of the metal layer 120. The metal layer 120 includes, for example, at least one of titanium, tantalum, cobalt and nickel, but other suitable materials such as NiPt alloy or TiAl alloy can also be used. As an example, the present invention forms a composite layer of a titanium layer and a titanium nitride layer 130 in step S2, wherein the titanium layer is the metal layer 120, which is used to perform a metal silicidation reaction with the silicon-containing conductive area 101, and the titanium layer also has the function of adhering the titanium nitride layer 130 to the semiconductor substrate. The titanium nitride layer 130 may be deposited by chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), plasma enhanced ALD (PEALD) or other suitable deposition processes. The thickness of the titanium nitride layer 130 is, for example, In this embodiment, in order to avoid the increase of compressive stress caused by high temperature and the increase of curvature of the semiconductor substrate, the deposition temperature of the titanium nitride layer 130 can be controlled to be in a relatively low range, for example, the temperature of the titanium nitride layer 130 is in the range of 200°C to 500°C.

[0043] Refer to 2 and Figure 3D , step S3 is performed to deposit a tungsten layer 140 on the surface of the titanium nitride layer 130. In this embodiment, the tungsten layer 140 is used to form a tungsten plug, for example, and the tungsten layer 140 fills the through hole 110a and covers the titanium nitride layer 130 outside the through hole 110a.

[0044] The semiconductor substrate formed with the titanium nitride layer 130 can be exposed to an atmosphere including a reducing agent and a tungsten precursor containing a halogen element, and a tungsten layer 140 can be deposited by a chemical vapor deposition process. The tungsten precursor containing a halogen element can be at least one of tungsten hexafluoride (WF6), tungsten hexachloride (WCl6) and tungsten pentachloride (WCl5), and the reducing agent can be hydrogen (H2), silane (SiH4), disilane (Si2H6) or other suitable materials. During the deposition of the tungsten layer 140, the temperature can be set within a certain range to avoid the high temperature causing an increase in the compressive stress of the substrate and an increase in the curvature of the semiconductor substrate, which affects the barrier performance of the titanium nitride layer 130. As an example, the temperature for depositing the tungsten layer 140 is, for example, in the range of 200°C to 500°C, more specifically, for example, about 250°C to 350°C.

[0045] Reference Figure 2 as well as Figure 3E , perform step S4, perform annealing, so that the metal layer 120 and the corresponding silicon-containing conductive region 101 undergo metal silicide reaction, and form a self-aligned silicide layer 150 on the top of the silicon-containing conductive region 101. The annealing can be, for example, at least one of soak annealing, spike annealing, and laser annealing. The temperature range of the annealing is, for example, 300° C. to 800° C.

[0046] In the present embodiment, since no annealing is performed before the tungsten deposition process, the compressive stress in the semiconductor substrate is small, the curvature of the substrate is small, and the titanium nitride layer 130 has good flatness and density. This can effectively prevent fluorine or other halogen radicals from passing through the titanium nitride layer 130 and corroding the underlying metal layer 120 and the semiconductor substrate during the deposition of the tungsten layer 140, thereby avoiding the formation of volcano defects.

[0047] Figure 4 Shown are device photos obtained by different annealing methods when forming the above-mentioned titanium layer, titanium nitride layer 130 and tungsten layer 140. (a), (c) and (e) show cross-sectional photos of the tungsten plug formation area, (b), (d) and (f) show planar photos of the CPI (chip package interaction) test structure area, (a) and (b) correspond to the method of annealing before tungsten deposition, (c) and (d) correspond to the method of not annealing, (e) and (f) correspond to the method of annealing after tungsten deposition, and other experimental conditions are the same.

[0048] Reference Figure 4In (a) and (b), when annealing is performed first and then a tungsten deposition process is performed after forming the composite layer of the titanium layer and the titanium nitride layer 130, a volcano defect will be generated in the top surface area of ​​the titanium nitride layer 130 (as shown in the area outlined by the white dotted line in (a) and (b)).

[0049] Reference Figure 4 In (c) and (d), when no annealing is performed after forming the composite layer of the titanium layer and the titanium nitride layer 130 and no annealing is performed after the tungsten deposition process, the device photograph shows that no volcano defects are formed, indicating that the volcano defects shown in (a) and (b) are related to the annealing before the tungsten deposition process.

[0050] Reference Figure 4 In (e) and (f), after forming the composite layer of the titanium layer and the titanium nitride layer 130, annealing is not performed first, but a tungsten deposition process is performed next. After the tungsten deposition process is completed, annealing is performed to form the metal silicide layer 150. At this time, the device photo shows that no volcano defect is formed, indicating that annealing after the tungsten deposition process will not cause volcano defects. Moreover, if Figure 4 As shown in (e), after the annealing process after the tungsten deposition process, the tungsten layer 140 can achieve grain repair and regrowth, which helps to reduce the connection resistance between the tungsten layer 140 and the corresponding silicon-containing conductive region 101.

[0051] In the method for manufacturing a semiconductor device described in the above embodiment, after stacking a metal layer 120 and a titanium nitride layer 130 on the surface of the semiconductor substrate, a tungsten layer 140 is then deposited on the surface of the titanium nitride layer 130 using a chemical vapor deposition process, and then annealing is performed to allow the metal layer 120 to undergo a metal silicidation reaction with the silicon-containing conductive region 101. This can avoid the deterioration of the density of the titanium nitride layer 130 due to premature annealing, ensure the barrier effect of the titanium nitride layer 130 on the process gas in the process of depositing the tungsten layer 140, and avoid the fluorine or other halogens contained in the process gas from corroding the underlying material, thereby effectively avoiding the generation of volcano defects.

[0052] In addition, the manufacturing method broadens the process window for manufacturing the titanium nitride layer 130, reduces the impact on device quality when the thickness of the titanium nitride layer 130 is limited, and helps to improve the device yield. The thickness of the titanium nitride layer 130 can be set thinner, which further helps to solve the problems of tungsten plug filling and increased connection resistance between the tungsten plug and the corresponding silicon-containing conductive area 101 caused by the reduction of critical dimensions.

[0053] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any technical personnel in this field can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: providing a semiconductor substrate having a silicon-containing conductive region with a top surface exposed; A metal layer and a titanium nitride layer are sequentially stacked on the surface of the semiconductor substrate, wherein the metal layer is used to perform a metal silicidation reaction with the silicon-containing conductive region; Depositing a tungsten layer on the surface of the titanium nitride layer; as well as Annealing is performed to cause a metal silicidation reaction between the metal layer and the silicon-containing conductive region, and a self-aligned silicide layer is formed on the top of the silicon-containing conductive region.

2. The method according to claim 1, characterized in that: The semiconductor substrate comprises: a substrate including an active region; and a MOS transistor formed on the surface of the active region, the MOS transistor comprising a gate formed on the active region, and a source region and a drain region formed in the active region and located at both sides of the gate, respectively, the silicon-containing conductive region comprising at least one of the source region and the drain region; and An interlayer dielectric layer covers the substrate and the MOS transistor, and a through hole exposing the silicon-containing conductive region is formed in the interlayer dielectric layer.

3. The method according to claim 2, characterized in that: Sequentially stacking a metal layer and a titanium nitride layer on the surface of the semiconductor substrate comprises: forming the metal layer on the upper surface of the interlayer dielectric layer and the inner surface of the through hole; The titanium nitride layer is conformally formed along the surface of the metal layer.

4. The method according to claim 3, characterized in that: When the tungsten layer is deposited on the surface of the titanium nitride layer, the tungsten layer fills the through hole and covers the titanium nitride layer outside the through hole.

5. The method according to claim 1, characterized in that: When the tungsten layer is deposited on the surface of the titanium nitride layer, a chemical vapor deposition process is adopted, and the process gas includes a reducing agent and a tungsten precursor containing a halogen element.

6. The method according to claim 5, characterized in that: The tungsten precursor containing halogen elements is at least one of tungsten hexafluoride, tungsten hexachloride and tungsten pentachloride.

7. The method according to claim 1, characterized in that: Before forming the metal layer, a process of removing the natural oxide layer is performed.

8. The method according to claim 1, characterized in that: The metal layer includes at least one of titanium, tantalum, cobalt and nickel.

9. The method according to claim 1, characterized in that: The thickness of the titanium nitride layer is 10. The production method according to any one of claims 1 to 9, characterized in that: The temperature range of the annealing is 300°C to 800°C.

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