Semiconductor structure and forming method thereof

Abstract

A method of forming a semiconductor structure includes forming a metal pad, depositing a passivation layer on the metal pad, and planarizing the passivation layer such that the passivation layer includes a planar top surface. The method further includes etching the passivation layer to form an opening in the passivation layer, where the metal pad is exposed to the opening, and forming a conductive via including a lower portion in the opening and an upper portion higher than the passivation layer. A polymer layer is then dispensed to cover the conductive vias. The embodiment of the invention also provides a semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to semiconductor structures and methods of forming the same. Background Art

[0002] In the formation of an integrated circuit, an integrated circuit device such as a transistor is formed at the surface of a semiconductor substrate in a wafer. An interconnect structure is then formed above the integrated circuit device. A metal pad is formed above the interconnect structure, and the metal pad is electrically coupled to the interconnect structure. A passivation layer and a first polymer layer are formed above the metal pad, and the metal pad is exposed through openings in the passivation layer and the first polymer layer. The first polymer layer has a function of buffering stress.

[0003] Metal vias may then be formed to connect to the top surface of the metal pads, followed by forming a second polymer layer over the redistribution lines. Summary of the invention

[0004] Some embodiments of the present disclosure provide a method for forming a semiconductor structure, the method comprising: forming a metal pad; depositing a passivation layer on the metal pad; planarizing the passivation layer so that the passivation layer includes a flat top surface; etching the passivation layer to form an opening in the passivation layer, wherein the metal pad is exposed to the opening; forming a conductive via, the conductive via comprising a lower portion located in the opening and an upper portion higher than the passivation layer; and dispensing a polymer layer covering the conductive via.

[0005] Other embodiments of the present disclosure provide a semiconductor structure comprising: a metal pad; a passivation layer comprising a first portion overlapping the metal pad and a second portion offset from the metal pad, wherein top surfaces of the first portion and the second portion are coplanar; a conductive via comprising: a lower portion located in the passivation layer; and an upper portion located above the passivation layer; and a dielectric layer, wherein the upper portion of the conductive via is located in the dielectric layer.

[0006] Another embodiment of the present disclosure provides a semiconductor structure, which includes: a first metal pad and a second metal pad; at least one dielectric layer, including a passivation layer, wherein the passivation layer includes: a first portion overlapping the first metal pad; a second portion overlapping the second metal pad; and a third portion connecting the first portion to the second portion, wherein top surfaces of the first portion, the second portion, and the third portion are coplanar; and a conductive via, including: a lower portion located in the passivation layer; and an upper portion located above the passivation layer, wherein the upper portion forms a horizontal interface with the top surface of the first portion of the at least one dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, aspects of the present disclosure can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figures 1 to 9 A cross-sectional view of an intermediate stage in forming a device die is shown in accordance with some embodiments.

[0009] Figures 10 to 16 A cross-sectional view is shown of an intermediate stage in forming a package including a device die in accordance with some embodiments.

[0010] Fig.17 An integrated fan-out package is shown in accordance with some embodiments.

[0011] Fig.18A , Fig.18B and Fig. 18C A package and corresponding wire and copper vias are shown in accordance with some embodiments.

[0012] Fig.19 A process flow for forming a package according to some embodiments is shown. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for implementing the different components of the present application. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the individual embodiments and / or configurations discussed.

[0014] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0015] A package including a device die and a method for forming the same are provided, wherein the device die includes a passivation layer having a flat top surface. According to some embodiments of the present disclosure, a passivation layer is deposited on a metal pad, and the passivation layer is flattened in a flattening process to have a flat top surface. The passivation layer is then patterned, and line vias and column vias are formed to penetrate the passivation layer. By flattening the passivation layer to have a flat top surface, the thickness of the passivation layer is reduced. In addition, the patterning process is performed by a photolithography process, so that the pitch of the line vias and the column vias is reduced to meet the requirements of advanced integrated circuits.

[0016] The embodiments discussed herein are intended to provide examples to enable the manufacture or use of the subject matter of the present disclosure, and those of ordinary skill in the art will readily appreciate the modifications that may be made while remaining within the intended scope of the different embodiments. Throughout the various views and illustrative embodiments, similar reference numerals are used to represent similar elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0017] Figures 1 to 16 1 shows a cross-sectional view of an intermediate stage in forming a package according to some embodiments of the present disclosure. Fig.19 The corresponding process is also schematically reflected in the process flow shown.

[0018] Figure 1 A cross-sectional view of a (integrated circuit) device 20 is shown. According to some embodiments of the present disclosure, the device 20 is or includes a device wafer, which includes active devices and possible passive devices represented as integrated circuit devices 26. A plurality of chips (device dies) 20' may be included in the device 20, of which one of the chips 20' is shown. According to an optional embodiment of the present invention, the device 20 is an interposer wafer, which has no active devices and may or may not include passive devices. According to another optional embodiment of the present invention, the device 20 is or includes a package substrate strip, which includes a coreless package substrate or a cored package substrate having a core therein. In the subsequent discussion, the device wafer is used as an example of the device 20, and the device 20 may also be referred to as a wafer 20. Embodiments of the present invention may also be applied to interposer wafers, package substrates, packages, and the like.

[0019] According to some embodiments of the present disclosure, the wafer 20 includes a semiconductor substrate 24 and components formed at a top surface of the semiconductor substrate 24. The semiconductor substrate 24 may be formed of or include crystalline silicon, crystalline germanium, silicon germanium, carbon-doped silicon, or a III-V compound semiconductor (such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, etc.). A shallow trench isolation (STI) region (not shown) may be formed in the semiconductor substrate 24 to isolate active regions in the semiconductor substrate 24.

[0020] According to some embodiments of the present disclosure, wafer 20 includes integrated circuit devices 26 formed on a top surface of semiconductor substrate 24. According to some embodiments, integrated circuit devices 26 may include complementary metal oxide semiconductor (CMOS) transistors, resistors, capacitors, diodes, etc. Details of integrated circuit devices 26 are not described herein. According to an optional embodiment, wafer 20 is used to form an interposer (which has no active devices).

[0021] An interlayer dielectric (ILD) 28 is formed over the semiconductor substrate 24 and fills the spaces between the gate stacks of transistors (not shown) in the integrated circuit device 26. According to some embodiments, the ILD 28 is formed of silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), etc. The ILD 28 may be formed using spin coating, flowable chemical vapor deposition (FCVD), etc. According to some embodiments of the present disclosure, the ILD 28 may also be formed using deposition methods such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), etc.

[0022] The contact plug 30 is formed in the ILD 28 and is used to electrically connect the integrated circuit device 26 to the metal lines and vias above. According to some embodiments of the present disclosure, the contact plug 30 is formed of a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, their alloys and / or their multilayers, or the contact plug 30 includes a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, their alloys and / or their multilayers. The formation of the contact plug 30 may include forming a contact opening in the ILD 28, filling the conductive material into the contact opening, and performing a planarization process (such as a chemical mechanical polishing (CMP) process or a mechanical grinding process) to make the top surface of the contact plug 30 flush with the top surface of the ILD 28.

[0023] An interconnect structure 32 is formed above the integrated circuit device 26. The interconnect structure 32 includes metal lines 34 and vias 36, which are formed in a dielectric layer 38 (also referred to as an intermetallic dielectric (IMD)) and an etch stop layer (not shown). Metal lines at the same level are collectively referred to as metal layers below. According to some embodiments of the present disclosure, the interconnect structure 32 includes a plurality of metal layers, which include metal lines 34 interconnected by vias 36. The metal lines 34 and vias 36 may be formed of copper or a copper alloy, and the metal lines 34 and vias 36 may also be formed of other metals.

[0024] According to some embodiments of the present disclosure, dielectric layer 38 is formed of a low-k dielectric material. For example, the dielectric constant (k value) of the low-k dielectric material may be lower than about 3.5. Dielectric layer 38 may include a carbon-containing low-k dielectric material, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), etc. An etch stop layer is formed under the corresponding dielectric layer 38, and the etch stop layer may be formed of aluminum nitride, aluminum oxide, silicon oxycarbide, silicon nitride, silicon carbide, silicon oxynitride, etc., or a multilayer thereof, or the etch stop layer may include aluminum nitride, aluminum oxide, silicon oxycarbide, silicon nitride, silicon carbide, silicon oxynitride, etc., or a multilayer thereof.

[0025] The formation of metal line 34 and via 36 may include a single damascene process and / or a dual damascene process. In a single damascene process for forming a metal line or via, a trench or via opening is first formed in one dielectric layer of dielectric layer 38, and then the trench or via opening is filled with a conductive material. A planarization process, such as a chemical mechanical polishing (CMP) process, is then performed to remove the excess portion of the conductive material above the top surface of the dielectric layer, thereby leaving a metal line or via in the corresponding trench or via opening. In a dual damascene process, both a trench and a via opening are formed in the dielectric layer, and the via opening is located below the trench and connected to the trench. Then a conductive material is filled into the trench and the via opening to form a metal line and a via, respectively. The conductive material may include a diffusion barrier layer and a copper-containing metal material located above the diffusion barrier layer. The diffusion barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0026] Metal lines 34 include top conductive (metal) features (designated as 34T), such as metal lines, metal pads, or vias, in a top dielectric layer (designated as dielectric layer 38T), which is a top layer of dielectric layer 38. According to some embodiments, dielectric layer 38T is formed of a low-k dielectric material similar to the material of the lower dielectric layers of dielectric layer 38. Metal features 34T in top dielectric layer 38T may also be formed of copper or a copper alloy, and may have a dual damascene structure or a single damascene structure.

[0027] According to some embodiments, an etch stop layer (not shown) may be deposited on the top dielectric layer 38T and the top metal layer. The etch stop layer may be formed of silicon nitride, silicon oxide, silicon oxycarbide, silicon oxynitride, etc., or the etch stop layer may include silicon nitride, silicon oxide, silicon oxycarbide, silicon oxynitride, etc.

[0028] A passivation layer 42 (sometimes referred to as passivation-1 or pass-1) is formed over the etch stop layer. According to some embodiments, the passivation layer 42 is formed of a non-low-k dielectric material having a dielectric constant equal to or greater than the dielectric constant of silicon oxide. The passivation layer 42 may be formed of or include an inorganic dielectric material, which may include a material selected from, but not limited to, undoped silicate glass (USG), silicon nitride (SiN), silicon oxide (SiO2), silicon oxynitride (SiON), silicon oxycarbide (SiOC), etc., combinations thereof, and / or multilayers thereof. According to some embodiments, the top surfaces of the top dielectric layer 38T and the metal line 34T are flush with each other. Accordingly, the passivation layer 42 may be a planar layer.

[0029] According to some embodiments, vias 44 are formed in passivation layer 42 to electrically connect to the underlying top metal feature 34T. Metal pads 46 are also formed over vias 44. The corresponding process is described in detail in detail below. Fig.19 The process flow 200 is shown as process 202. According to some embodiments, metal pad 46 includes aluminum, aluminum copper, copper, etc. According to some embodiments, metal pad 46 may have a thickness of about to about The thickness T1 is within the range.

[0030] According to some embodiments, via 44 and metal pad 46 are formed in the same process. The formation process may include etching passivation layer 42 to form an opening, depositing a metal layer, the metal layer including a first portion extending into the opening and a second portion located above passivation layer 42, and patterning the metal layer to form via 44 and metal pad 46. According to an optional embodiment, the formation process may include depositing a metal seed layer, forming a patterned plating mask, and plating a metal layer over the metal seed layer and extending into the opening. The patterned plating mask is then removed, followed by etching the portion of the metal seed layer previously covered by the plating mask. According to yet another optional embodiment, via 44 and metal pad 46 are formed separately, via 44 is formed in a single damascene process, and metal pad 46 is formed by deposition and patterning.

[0031] refer to Figure 2 According to some embodiments, a pre-layer 48 is deposited. The corresponding process is Fig.19The process flow 200 is shown as process 204. Pre-layer 48 can be formed of a material that has good adhesion to the metal pad 46 and passivation layer 42 below. Pre-layer 48 can also serve as a barrier to prevent the material of metal pad 46 from diffusing outward. Therefore, pre-layer 48 can also be referred to as an adhesion layer or barrier. For example, pre-layer 48 can be formed of a nitride-based dielectric material (such as silicon nitride, silicon oxynitride, silicon carbonitride, etc.), or pre-layer 48 can include a nitride-based dielectric material (such as silicon nitride, silicon oxynitride, silicon carbonitride, etc.). Pre-layer 48 is formed using a conformal deposition process (such as atomic layer deposition (ALD), chemical vapor deposition (CVD), etc.).

[0032] According to an alternative embodiment, pre-layer 48 is not formed, and subsequently formed passivation layer 50 is in direct contact with metal pad 46 and passivation layer 42. Accordingly, pre-layer 48 is shown using a dotted line to indicate that pre-layer 48 may or may not be formed. According to some embodiments, when pre-layer 48 is formed, pre-layer 48 may have a thickness of about to about The thickness T2 is within the range between.

[0033] Next, as Figure 2 As shown, a passivation layer 50 (sometimes referred to as passivation-2 or pass-2) is formed. The corresponding process is Fig.19 The process flow 200 is shown as process 206. According to some embodiments, the passivation layer 50 is formed of or includes a dielectric material, which may include an oxide-based dielectric material, such as undoped silicate glass (USG), spin-on glass (SOG), silicon oxide, etc. According to alternative embodiments, the passivation layer 50 is formed of or includes a nitride-based dielectric material, such as silicon nitride, silicon carbonitride, silicon oxynitride, etc.

[0034] According to yet another optional embodiment, the passivation layer 50 is formed of a polymer that is dispensed in a flowable form and then cured into a solid. According to these embodiments, the passivation layer 50 may be formed of a photosensitive polymer (such as polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), etc.) or a non-photosensitive polymer. As will be discussed in detail in subsequent paragraphs, when the passivation layer 50 is formed of a photosensitive polymer, the passivation layer 50 will be patterned by etching (using a photoresist as an etching mask) rather than by an exposure and development process. According to some embodiments, the passivation layer 50 is baked until the passivation layer 50 is cross-linked so that it is not subsequently used to pattern the photoresist 54 ( Figure 5 ) is patterned by an exposure and development process.

[0035] According to some embodiments, the passivation layer 50 is a single layer, and the entire passivation layer 50 is formed of a homogeneous material. According to an optional embodiment, the passivation layer 50 is a composite layer including two or more sublayers. The materials of adjacent sublayers in the sublayers are different from each other, and the material can be selected from the candidate materials discussed above. The passivation layer 50 can be formed by spin coating or deposition methods (such as CVD, high density plasma (HDP) CVD, plasma enhanced CVD (PECVD) and the like).

[0036] According to some embodiments, passivation layer 50 has a non-planar top surface. According to some embodiments, a portion of passivation layer 50 directly above metal pad 46 has a top surface greater than about The thickness T3 may be about to about The lowest portion of the top surface of passivation layer 50 is still higher than the top surface of metal pad 46 by a difference, so that after the subsequent planarization process, the flat top surface of passivation layer 50 is higher than the top surface of metal pad 46 by a portion having a sufficient thickness.

[0037] refer to Figure 3 , for example, a planarization process is performed by a CMP process or a mechanical grinding process. The corresponding process is Fig.19 The process flow 200 is shown as process 208. Therefore, the entire top surface of the passivation layer 50 is flat. According to some embodiments, the portion of the passivation layer 50 directly above the metal pad 46 has a thickness T4, which may be about to about in the range between.

[0038] According to some embodiments, due to the CMP process, the top surface of the passivation layer includes CMP scratches, which are shallow scratches caused by sand particles in the polishing pad and slurry. The shallow scratches are an indication of the planarization process. In comparison, if the planarization process is not performed, there are no scratches. The CMP scratches may include a first plurality of traces parallel to each other. In addition, a second plurality of traces intersecting the first plurality of traces may be included, wherein the second plurality of traces are parallel to each other but not parallel to the first plurality of traces.

[0039] The first plurality of traces and the second plurality of traces may be curved, or may be straight.

[0040] According to some embodiments where the passivation layer 50 includes a plurality of sub-layers, after the planarization process, the top sub-layer is polished, and the lower sub-layers below the top sub-layer may or may not be exposed. Figure 3An exemplary embodiment is shown in which the passivation layer 50 includes a lower sublayer 50A and an upper layer 50B, which are conformal layers when deposited. According to some embodiments, after the planarization process, the lower sublayer 50A may have some exposed portions, while some other portions are covered by the upper layer 50B. According to an optional embodiment, after the planarization process, the entire lower sublayer 50A is covered by the polished upper layer 50B.

[0041] refer to Figure 4 , a dielectric cap layer 52 is deposited on the passivation layer 50. The corresponding process is Fig.19 The process flow 200 is shown as process 210. According to some embodiments, the dielectric cap layer 52 is also formed of a material that has good adhesion to the underlying layers and the overlying layers. For example, the dielectric cap layer 52 can be formed of or include a nitride-based dielectric material, such as silicon nitride, silicon oxynitride, silicon carbonitride, etc. The dielectric cap layer 52 is formed using a conformal deposition process, such as ALD, CVD, etc. The entire dielectric cap layer 52 can be flat. According to some embodiments, the thickness T5 of the dielectric cap layer 52 can be about 1000 mm / s. to about in the range between.

[0042] refer to Figure 5 , forming and patterning an etching mask 54. The corresponding process is Fig.19 The process flow 200 is shown as process 212. According to some embodiments, the etching mask 54 includes a photoresist, and the patterning of the photoresist includes placing a photolithography mask (not shown) over the etching mask 54, wherein the photolithography mask includes an opaque pattern and a transparent portion. Then, an exposure process is performed to expose some portions of the photoresist, followed by a development process to remove some portions of the photoresist, thereby forming a Figure 5 Openings 56 are formed in etch mask 54 .

[0043] The etching mask 54 may also (or may not) have a single layer structure, a double layer structure, or a triple layer structure, which includes an anti-reflective coating. The anti-reflective coating can help reduce reflection and can further reduce the width, spacing, and pitch of the resulting openings.

[0044] According to some embodiments in which the passivation layer 50 includes a photosensitive material such as polyimide, PBO, BCB, etc., when the etching mask 54 (photoresist) is exposed and patterned, the passivation layer 50 has been fully baked, and thus the passivation layer 50 is cross-linked. Accordingly, even if the passivation layer 50 may receive light for exposure and may be exposed to chemicals for developing the etching mask 54 (in the case where the opening 56 extends to the passivation layer 50), the passivation layer 50 is not developed, and the opening 56 stops on the top surface of the passivation layer 50.

[0045] In a subsequent process, dielectric cap layer 52, passivation layer 50 and pre-layer 48 (when pre-layer 48 is formed) are patterned in an anisotropic etching process. Therefore, opening 56 extends downward to penetrate dielectric cap layer 52, passivation layer 50 and pre-layer 48, and metal pad 46 is exposed to opening 56. The corresponding process is Fig.19 This is shown as process 214 in illustrated process flow 200. According to some embodiments, width W1 of opening 56 is greater than about 2 μm, and may be in a range between about 2 μm and about 10 μm.

[0046] According to some embodiments in which the passivation layer 50 includes a photosensitive material such as polyimide, PBO, BCB, etc., the opening 56 is formed in the passivation layer 50 by etching rather than by exposure and development. The photolithography process using a photoresist as an etching mask has the advantage of reducing the pitch and spacing of patterned components. In addition, the etching mask 54 can adopt a double-layer structure or a three-layer structure, so that the width and spacing of the opening 56 can be further reduced. Accordingly, the width W1 of the opening 56 and the spacing S1 between adjacent openings 56 are both reduced, for example, to a range between about 2 μm and about 10 μm.

[0047] In comparison, in the prior art, a polyimide layer may be distributed as a stress buffer layer and formed on the metal pad 46, and the polyimide layer is not planarized by CMP or mechanical grinding. Accordingly, in order to have a relatively flat top surface, the polyimide layer is very thick, and the polyimide layer may have a thickness in the range of about 4 μm to about 6 μm. The patterning of the polyimide layer is by exposure and development (rather than etching by using the photoresist patterned above). Therefore, the width and spacing of the opening cannot be reduced to meet the specifications of advanced integrated circuits. For example, the width and spacing of the opening may be disadvantageously limited to greater than 10 μm. This significantly reduces the number of through holes that can be formed.

[0048] After the opening 56 is formed, the etching mask 54 is removed, for example, in an ashing process or an etching process, and the resulting structure is as shown. Figure 6 shown. Figure 7 and Figure 8 The formation of through holes (pillars) is shown in FIG. Fig.19 This is shown in the illustrated process flow 200 as process 216 . Figure 7 1 shows the formation of a metal seed layer 60A, which may be deposited by physical vapor deposition (PVD) according to some embodiments. The metal seed layer 60A may include a titanium layer and a copper layer located above the titanium layer. A plating mask 62 is formed on the metal seed layer 60A, and the plating mask 62 is patterned, with some portions overlapping the through-hole opening 56 ( Figure 6). Then, metal material 60B is deposited. According to some embodiments, the deposition is performed by plating. Metal material 60B may include copper, nickel, tungsten, cobalt, etc., combinations thereof, and / or multilayers thereof.

[0049] The plating mask 62 is then removed, exposing some portions of the metal seed layer 60A. The exposed portions of the metal seed layer 60A are then removed by etching using the metal material 60B as an etching mask. The remaining portions of the metal material 60B and the metal seed layer 60A are collectively referred to as vias 64. Figure 8 According to some embodiments, vias 64 include line vias 64A, which have a line shape (elongated) when viewed in a top view, and may be connected to more than one metal pad 46. Vias 64 also include post vias 64B, which have a post shape and are less elongated when viewed in a top view.

[0050] According to some embodiments, Figure 8 As shown, the line via 64A has a lateral dimension LD1 (length and width) that is greater than the lateral dimension (LD2) of the post via 64B. The spacing between adjacent line vias 64A may also be greater than the spacing between adjacent post vias 64B.

[0051] Fig.18A Schematic top view of device die 20' is shown in accordance with some embodiments. A plurality of regions 66A, 66B, and 66C are schematically shown, showing where vias 64 may be located. In accordance with some embodiments, line via 64A ( Fig.18B ) may be located in one of regions 66A, 66B, and 66C, while column through hole 64B ( Fig. 18C ) may be located in another one of regions 66A, 66B, and 66C.

[0052] Fig.18B A top view of a wire via 64A according to some embodiments is shown. In the example shown, the wire via 64A is formed to have a grid pattern, wherein the lines in the wire via 64A include horizontal lines and vertical lines. According to these embodiments, the grid-like wire vias can be used for electrical grounding, electromagnetic shielding, heat dissipation, etc. According to an optional embodiment, instead of forming a grid, the wire via 64A can be an elongated strip when viewed in a top view. Fig. 18C A top view of a plurality of post through-holes 64B is shown, which may be arranged in an array.

[0053] In subsequent processes, such as Fig. 9 As shown, a dielectric layer 65 is formed to embed a through hole 64 therein. The corresponding process is Fig.19The process flow 200 is shown as process 218. According to some embodiments, the dielectric layer 65 is formed of polyimide, PBO, BCB, etc., or the dielectric layer 65 includes polyimide, PBO, BCB, etc. The top surface of the dielectric layer 65 is higher than the top surface of the through hole 64, and thus the through hole 64 is covered. Then, the wafer 20 is singulated, for example, sawed, into a plurality of discrete dies 20'. The corresponding process is Fig.19 This is shown as process 220 in the illustrated process flow 200. During the sawing process, the wafer 20 may be fixed on a dicing tape (not shown), which is further fixed on a frame (not shown).

[0054] See also Fig.10 , a carrier 70 is provided, on which a release film 72 is coated. The carrier 70 may be a glass carrier, a silicon wafer, an organic carrier, etc. The release film 72 may be formed of a polymer-based material and / or an epoxy-based thermal release material (such as an LTHC material). A dielectric buffer layer (not shown), such as a PBO layer, may be formed on the release film 72.

[0055] A metal pillar 76 is formed above the carrier 70, for example on a dielectric buffer layer (not shown). The corresponding process is Fig.19 This is shown as process 222 in illustrated process flow 200. According to some embodiments, formation of metal pillars 76 includes depositing a metal seed layer, forming a plating mask, plating metal pillars 76 in openings of the plating mask, removing the plating mask, and etching portions of the metal seed layer previously covered by the plating mask.

[0056] The device die 20' is also attached to the carrier 70 by a die attach film 74, which is an adhesive film. The corresponding process is Fig.19 This is shown as process 224 in the illustrated process flow 200 . Although only one device die 20 ′ is shown, there may be multiple device dies 20 ′ attached to the carrier 70 .

[0057] Next, the device die 20' and the metal pillar 76 are sealed in an encapsulant 78, such as Fig.11 The corresponding process is Fig.19The process flow 200 shown is shown as process 226. The sealant 78 fills the gaps between adjacent metal pillars 76 and the gaps between the metal pillars 76 and the device die 20'. The sealant 78 may include a molding compound, a molding bottom filler, an epoxy resin and / or a resin. The top surface of the sealant 78 is higher than the top of the through hole 64. The molding compound may include a base material and filling particles (not shown) located in the base material, and the base material may be a polymer, a resin, an epoxy resin, etc. The filling particles may be dielectric particles such as SiO2, Al2O3, quartz, etc., and the filling particles may have a spherical shape. In addition, the spherical filling particles may have the same or different diameters.

[0058] like Fig.12 As shown, a planarization process (such as a CMP process or a mechanical grinding process) is performed to thin the sealant 78 and the dielectric layer 65 until the metal pillar 76 and the via 64 are all exposed. Fig.19 This is shown as process 228 in the illustrated process flow 200. The metal pillar 76 is referred to as a through-hole via 76 hereinafter.

[0059] Fig.13 FIG. 4 shows the formation of a front side redistribution structure 81, which includes a dielectric layer 80 and an RDL 82. The corresponding process is Fig.19 The process flow 200 is shown as process 230. According to some embodiments, the dielectric layer 80 may be formed of a polymer such as PBO, polyimide, etc. The formation of the dielectric layer 80 may include coating the dielectric layer 80 in a flowable form, and then curing the dielectric layer 80. According to an optional embodiment of the present disclosure, the dielectric layer 80 is formed of an inorganic dielectric material such as silicon nitride, silicon oxide, etc. The formation method may include CVD, ALD, plasma enhanced chemical vapor deposition (PECVD) or other applicable deposition methods.

[0060] The RDL 82 is formed to be electrically connected to the device die 20' and the via 76. Each RDL 82 includes a via portion formed in the corresponding underlying dielectric layer 80 and a trace portion (metal line) located above the corresponding dielectric layer 80. According to some embodiments of the present disclosure, each layer of RDL 82 is formed in a plating process that includes depositing a metal seed layer (not shown), forming a photoresist (not shown) over the metal seed layer and patterning the photoresist, and plating a metal material (e.g., copper and / or aluminum) over the metal seed layer. The patterned photoresist is then removed, followed by etching of the portion of the metal seed layer previously covered by the patterned photoresist.

[0061] Also like Fig.13As shown, electrical connector 84 is formed. The formation of electrical connector 84 may include placing a solder ball on the exposed portion of RDL 82, and then reflowing the solder ball, and thus electrical connector 84 is a solder area. According to an optional embodiment of the present disclosure, the formation of electrical connector 84 includes performing a plating step to form a solder layer above RDL 82, and then reflowing the solder layer. Electrical connector 84 may also include a non-solder metal column or a metal column and a solder cap located above the non-solder metal column, and electrical connector 84 may also be formed by plating. Throughout the description, the structure above release film 72 is referred to as a reconstructed wafer 100.

[0062] Fig.13 Also shown is the bonding of device 86 to redistribution structure 81. In accordance with some embodiments, device 86 includes an independent passive device (IPD), such as a capacitor die, an inductor die, or the like.

[0063] Next, refer to Fig.14 , reconstructed wafer 100 is placed on tape 88, which is attached to a frame (not shown). According to some embodiments of the present disclosure, electrical connector 84 is in contact with tape 88. Next, the structure on layer 72 is debonded from carrier 70, also as shown. Fig.14 The corresponding process is Fig.19 This is shown as process 232 in the illustrated process flow 200. During the debonding process, a light beam is projected onto the release film 72, and the light beam penetrates the transparent carrier 70. According to some embodiments, the light beam is a laser beam, and the laser beam scans the entire release film 72.

[0064] Due to the exposure (eg, laser scanning), the carrier 70 may be peeled off from the release film 72 , and thus the reconstructed wafer 100 is debonded (detached) from the carrier 70 .

[0065] Fig.15 1 shows the formation of an electrical connector 92 according to some embodiments, which may include a solder region. The corresponding process is Fig.19 The process flow 200 is shown as process 234. In a subsequent process, the reconstructed wafer 100 is sawn into a plurality of packages 100'. The corresponding process is Fig.19 This is shown in the illustrated process flow 200 as process 236 .

[0066] Fig.16 Also shown is the bonding of package 100' to package assembly 94, thereby forming package 110. The corresponding process is Fig.19The process flow 200 is shown as process 238. The bonding is performed through the solder region 92, which bonds the via 76 to the metal pad of the package component 94. According to some embodiments, the package component 94 may include a package substrate, an interposer, a printed circuit board, a package, etc. An underfill 96 is disposed between the package 100' and the package component 94.

[0067] Fig.17 Package 110 is shown including device die 20' in accordance with some embodiments. Region 114 shows the area where passivation layer 50 (with a planarized surface) and vias 64 are formed. In accordance with some embodiments, package 110 includes two device dies 20'.

[0068] In the above embodiments, some processes and features for forming three-dimensional (3D) packages are discussed according to some embodiments of the present disclosure. Other components and processes may also be included. For example, a test structure may be included to assist in verification testing of 3D packages or 3DIC devices. For example, the test structure may include a test pad formed in a redistribution layer or on a substrate, the test pad allowing testing of the 3D package or 3DIC, the use of probes and / or probe cards, and the like. Verification testing may be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein may be used in conjunction with a test method that combines intermediate verification of known good dies to increase yield and reduce costs.

[0069] Embodiments of the present disclosure have some advantageous features. By forming a passivation layer and planarizing the passivation layer, there is no need to form a thick polyimide layer with a relatively flat top surface as a stress buffer layer. A photolithography process is performed using a patterned photolithography mask to pattern the passivation layer. Therefore, the pitch, width and spacing of the through holes are reduced. In addition, by planarizing and thinning the passivation layer, the thickness of the passivation layer is reduced.

[0070] According to some embodiments of the present disclosure, a method includes forming a metal pad; depositing a passivation layer on the metal pad; planarizing the passivation layer so that the passivation layer includes a flat top surface; etching the passivation layer to form an opening in the passivation layer, wherein the metal pad is exposed to the opening; forming a conductive via, the conductive via including a lower portion located in the opening and an upper portion higher than the passivation layer; and dispensing a polymer layer covering the conductive via.

[0071] In an embodiment, the method further comprises sawing the wafer including the conductive vias and the polymer layer to separate a plurality of device dies in the wafer; sealing the device dies in the plurality of device dies in an encapsulant; and polishing the encapsulant and the device dies to expose the conductive vias. In an embodiment, the method further comprises forming an additional metal pad when forming the metal pad, wherein the conductive via is a line via that electrically connects the metal pad to the additional metal pad. In an embodiment, the method further comprises depositing a pre-layer on the metal pad using a conformal deposition process before forming the passivation layer.

[0072] In an embodiment, the method further comprises depositing a capping layer on the metal pad after planarizing the passivation layer and before etching the passivation layer. In an embodiment, etching the passivation layer comprises forming a patterned photoresist over the passivation layer, wherein the passivation layer is etched using the patterned photoresist as an etch mask. In an embodiment, depositing the passivation layer comprises depositing an inorganic dielectric layer.

[0073] In an embodiment, depositing the passivation layer comprises depositing an additional polymer layer. In an embodiment, depositing the passivation layer comprises depositing a homogenous material, and the entire passivation layer is formed of the homogenous material. In an embodiment, depositing the passivation layer comprises depositing a plurality of sub-layers comprising different dielectric materials.

[0074] According to some embodiments of the present disclosure, a structure includes a metal pad; a passivation layer, including a first portion overlapping the metal pad and a second portion offset from the metal pad, wherein top surfaces of the first portion and the second portion are coplanar; a conductive via, including a lower portion located in the passivation layer; and an upper portion located above the passivation layer; and a dielectric layer, wherein the upper portion of the conductive via is located in the dielectric layer.

[0075] In an embodiment, the structure further comprises a pre-layer located between the metal pad and the passivation layer, wherein the pre-layer comprises a vertical portion and a horizontal portion having the same thickness. In an embodiment, the structure further comprises a dielectric cover layer located above the passivation layer, wherein the lower portion of the conductive via is also located in the dielectric cover layer. In an embodiment, the entire dielectric cover layer is flat. In an embodiment, the passivation layer comprises an inorganic dielectric material. In an embodiment, the passivation layer comprises an organic dielectric material. In an embodiment, the conductive via and the dielectric layer are included in the device die, and the structure further comprises: an encapsulant, in which the device die is encapsulated; and a redistribution structure, comprising a plurality of redistribution lines, wherein the plurality of redistribution lines are located above the device die and electrically coupled to the device die. In an embodiment, the structure further comprises a through hole located in the encapsulant, wherein the through hole is electrically coupled to one of the plurality of redistribution lines.

[0076] According to some embodiments of the present disclosure, a structure includes a first metal pad and a second metal pad; at least one dielectric layer including a passivation layer, wherein the passivation layer includes a first portion overlapping the first metal pad; a second portion overlapping the second metal pad; and a third portion connecting the first portion to the second portion, wherein top surfaces of the first portion, the second portion, and the third portion are coplanar; and a conductive via including a lower portion located in the passivation layer; and an upper portion located above the passivation layer, wherein the upper portion forms a horizontal interface with a top surface of the first portion of the at least one dielectric layer.

[0077] In an embodiment, the top surface includes a plurality of scratch marks. In an embodiment, the structure further includes a dielectric cover layer located above the passivation layer, wherein the lower portion of the conductive via is also located in the dielectric cover layer. In an embodiment, the structure further includes a pre-layer located below the passivation layer, wherein the lower portion of the conductive via is also located in the pre-layer. In an embodiment, the structure further includes: an encapsulant in contact with opposite sidewalls of at least one dielectric layer; a through hole penetrating the encapsulant; and a plurality of redistribution lines located above and electrically coupled to the conductive via and the through hole.

[0078] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor structure, comprising: forming a metal pad; depositing a passivation layer on the metal pad; planarizing the passivation layer so that the passivation layer includes a planar top surface; etching the passivation layer to form an opening in the passivation layer, wherein the metal pad is exposed in the opening; forming a conductive via, the conductive via comprising a lower portion located in the opening and an upper portion higher than the passivation layer; and A polymer layer is dispensed covering the conductive vias.

2. The method according to claim 1, further comprising: sawing the wafer including the conductive vias and the polymer layer to separate a plurality of device dies in the wafer; encapsulating a device die of the plurality of device dies in an encapsulant; as well as The encapsulant and the device die are polished to expose the conductive vias.

3. The method according to claim 1, further comprising forming an additional metal pad when forming the metal pad, wherein The conductive via is a line via that electrically connects the metal pad to the additional metal pad. 4 . The method of claim 1 , further comprising depositing a pre-layer on the metal pad using a conformal deposition process before forming the passivation layer. 5 . The method of claim 1 , further comprising depositing a capping layer on the metal pad after planarizing the passivation layer and before etching the passivation layer.

6. The method according to claim 1, wherein: Etching the passivation layer comprises: A patterned photoresist is formed over the passivation layer, wherein the passivation layer is etched using the patterned photoresist as an etch mask.

7. The method according to claim 1, wherein: Depositing the passivation layer includes depositing an inorganic dielectric layer.

8. The method according to claim 1, wherein: Depositing the passivation layer includes depositing an additional polymer layer.

9. A semiconductor structure comprising: Metal pads; a passivation layer comprising a first portion overlapping the metal pad and a second portion offset from the metal pad, wherein top surfaces of the first portion and the second portion are coplanar; Conductive vias, including: a lower portion located in the passivation layer; and an upper portion located above the passivation layer; and A dielectric layer, wherein the upper portion of the conductive via is located in the dielectric layer.

10. A semiconductor structure comprising: a first metal pad and a second metal pad; at least one dielectric layer, including a passivation layer, wherein the passivation layer comprises: a first portion overlapping the first metal pad; a second portion overlapping the second metal pad; and a third portion connecting the first portion to the second portion, wherein top surfaces of the first portion, the second portion, and the third portion are coplanar; and Conductive vias, including: a lower portion located in the passivation layer; and An upper portion is located above the passivation layer, wherein the upper portion forms a horizontal interface with a top surface of the first portion of the at least one dielectric layer.

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