Dielectric layer in magnetic molding compound inductor package

Abstract

The invention relates to a dielectric layer in a magnetic molding compound inductor package. In an example, a semiconductor package (500) includes a semiconductor die (501) and an inductor (400) coupled to the semiconductor die. The inductor includes a first metal coil having a first end coupled to the semiconductor die and a second end; a second metal coil vertically spaced apart from the first metal coil and having a third end coupled to the second end and a fourth end coupled to the semiconductor die; a magnetic molding compound MMC between the first metal coil and the second metal coil, the MMC including conductive ions; and an insulating layer between the first metal coil and the second metal coil.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 590,486, filed on October 16, 2023, entitled "METHOD OF BUILDING HIGH Q INDUCTORS IN SUBSTRATES WITH MMC," and the U.S. Provisional Patent Application is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure relates to semiconductors. Background Art

[0004] A semiconductor wafer is a circular piece of semiconductor material, such as silicon, used to make semiconductor chips. Typically, complex manufacturing processes are used to form many integrated circuits on a single wafer. Forming such circuits on a wafer is called fabrication. After wafer fabrication, the wafer is cut into multiple pieces, called semiconductor dies, each of which contains a circuit. Cutting or sawing the wafer into individual dies is called singulation. The individual dies are then coupled to die pads and to conductive terminals, sometimes called "leads." The resulting structure is then covered with a molding compound to produce a package. Summary of the invention

[0005] In an example, a semiconductor package includes a semiconductor die and an inductor coupled to the semiconductor die. The inductor includes: a first metal coil having a first end and a second end coupled to the semiconductor die; a second metal coil vertically spaced apart from the first metal coil and having a third end coupled to the second end and a fourth end coupled to the semiconductor die; a magnetic mold compound (MMC) located between the first metal coil and the second metal coil, the MMC including conductive ions; and an insulating layer located between the first metal coil and the second metal coil.

[0006] In an example, a method for manufacturing a semiconductor package includes: plating a first metal coil on a carrier; covering the first metal coil with a first magnetic molding compound (MMC) layer; grinding the first MMC layer to reduce the thickness of the first MMC layer; covering the first MMC layer with an insulating layer having a thickness in a range of 10 microns to 40 microns; forming a first orifice and a second orifice in the insulating layer; plating a second metal coil on a first surface of the insulating layer opposite to a second surface of the insulating layer facing the first metal coil, the first metal coil and the second metal coil being coupled by a through hole extending through the first orifice; covering the second metal coil with a second MMC layer; grinding the second MMC layer to reduce the thickness of the second MMC layer; removing the carrier; coupling a semiconductor die to the first metal coil and the second metal coil; and covering the semiconductor die and the first metal coil and the second metal coil with molding compound. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figures 1A1 to 1L3 are cross-sectional, top, and perspective views of a process flow for manufacturing a magnetic mold compound (MMC) inductor package with a dielectric layer according to various examples.

[0008] Figure 2 is a flow chart of a method for manufacturing a semiconductor package including an MMC inductor package having a dielectric layer according to various examples.

[0009] Figures 3A to 3C are perspective views, top views, and cross-sectional views of coils and vias in an MMC inductor package with a dielectric layer according to various examples.

[0010] Figures 4A to 4C are perspective views, top views, and cross-sectional views of an MMC inductor package having a dielectric layer according to various examples.

[0011] Figures 5A to 5C are outline cross-sectional views, top views, and perspective views of a semiconductor package including an MMC inductor package having a dielectric layer according to various examples. DETAILED DESCRIPTION

[0012] Semiconductor packages typically include a semiconductor die. Some semiconductor packages may include components other than the semiconductor die. For example, some packages may include passive components, such as inductors. In a package containing an inductor, one or more metal coils may be coupled to the semiconductor die, which uses the one or more metal coils as part of a circuit. In addition, some inductor packages may include a specialized type of molding compound, such as a magnetic molding compound (MMC). MMC uses ferromagnetic particles (such as iron or ferrite) to manage magnetic flux, thereby improving efficiency. MMC acts as a shield against electromagnetic interference, thereby protecting adjacent components and reducing external interference. The MMC also dissipates heat and provides mechanical support, thereby improving the reliability of inductors in electronic circuits.

[0013] Some types of inductor packages are manufactured using an iterative process, in which a coil is formed, an MMC layer is applied to cover the coil, the MMC layer is ground to reduce the thickness of the MMC layer, and then a second coil is formed on the ground MMC layer. This technique for manufacturing an inductor package may be disadvantageous because the grinding process mentioned above exposes metal ions (e.g., iron ions) in the MMC layer. When the second coil is then plated on the MMC, the second coil contacts the exposed metal ions, making different parts or sections of the second coil susceptible to accidental short circuits caused by the metal ions exposed by the grinding process. This electrical short circuit renders the inductor package useless. In order to reduce the risk of this type of electrical short circuit, the coil can be enlarged in the horizontal plane so that the gaps between adjacent sections of the coil are too far apart and will not be short-circuited by the exposed metal ions. However, this method inappropriately increases the package size and manufacturing costs while reducing manufacturing efficiency. In addition, the risk of short circuits limits the flexibility of the coil architecture, which means that additional coil turns may not be achieved without significantly increasing the risk of electrical short circuits.

[0014] The present disclosure describes a semiconductor package manufacturing technology that reduces the risk of electrical short circuits described above. In some examples, the semiconductor package manufacturing technology includes: plating a first metal coil on a carrier; covering the first metal coil with a first magnetic mold compound (MMC) layer; and grinding the first MMC layer to reduce the thickness of the first MMC layer. The method also includes covering the first MMC layer with an insulating layer having a thickness in the range of 10 microns to 40 microns, forming a first orifice and a second orifice in the insulating layer, and plating a second metal coil on a first surface of the insulating layer opposite to the second surface of the insulating layer facing the first metal coil. The first metal coil and the second metal coil are coupled by a through hole extending through the first orifice. The method further includes: covering the second metal coil with a second MMC layer; grinding the second MMC layer to reduce the thickness of the second MMC layer; removing the carrier; and coupling the semiconductor die to the first metal coil and the second metal coil. The method also includes covering the semiconductor die and the first metal coil and the second metal coil with a mold compound. In addition, by reducing the risk of short circuits without enlarging the coils, the package size and manufacturing costs are kept low, and the manufacturing efficiency is kept high. Furthermore, the coil geometry is flexible, meaning that the number of coil turns can be freely increased and decreased without increasing the risk of electrical shorts caused by exposed metal ions.

[0015] Figures 1A1 to 1L3 are cross-sectional, top, and perspective views of a process flow for manufacturing a magnetic mold compound (MMC) inductor package with a dielectric layer according to various examples. Figure 2 is a flow chart of a method 200 for manufacturing a semiconductor package including an MMC inductor package having a dielectric layer according to various examples. Therefore, the following will now be described in parallel with each other. Figures 1A1 to 1L2 and 2.

[0016] The method 200 begins by plating a first coil and vias on a carrier (202). Figure 1A1A profile cross-sectional view of a carrier 100 on which a coil 102 is plated (e.g., by electroplating or electroless plating) is depicted. The carrier 100 may include any suitable material that provides properties such as chemical inertness, thermal stability, and mechanical strength, such as plastic, quartz, or ceramic. The coil 102 may include any suitable type of conductive material, such as a suitable metal or metal alloy (e.g., an alloy based on copper, aluminum, silver, gold, ferrite). The coil 102 may have any suitable number of windings, regardless of the specific number of windings shown in the drawings of the present disclosure. The physical dimensions of the coil 102 may have any suitable size. In addition to the coil 102, through holes 104 and 106 are plated on specific portions of the coil 102. For example, the through hole 104 may be plated on the outermost section of the coil 102, such as on the first end of the coil 102. The through hole 106 may be plated on the innermost section of the coil 102, such as on the center of the coil 102. As described in more detail below, vias 104 and 106 may be suitable for forming conductive terminals that enable a semiconductor die or other device to provide electrical power to an inductor of which coil 102 is a part. Figure 1A2 According to each instance Figure 1A1 Top view of the structure. Figure 1A3 According to each instance Figure 1A1 perspective view of the structure.

[0017] Method 200 includes applying a first MMC layer to the structure formed by step 202 (204). The MMC may include various components, such as iron, which has a high magnetic permeability; ferrites, which may include iron oxide and / or other metal oxides, such as manganese, nickel, or zinc; and amorphous or nanocrystalline alloys, such as iron-silicon-boron or iron-nickel, which exhibit desired magnetic properties, including high magnetic permeability and low core loss. In addition, the MMC layer may include a non-magnetic binder, such as a polymer resin, which is suitable for holding magnetic powder particles together to form a cohesive structure and may include epoxy resins, phenolic resins, polyamide resins, and polyester resins. The MMC layer may also include non-magnetic fillers and additives to adjust properties such as viscosity, thermal conductivity, and mechanical strength. Various processing aids may also be included in the MMC, such as solvents, dispersants, and / or curing agents. Figure 1B1 yes Figure 1A1 1, except that an MMC layer 108 containing iron ions 110 is applied. The depiction of the iron ions 110 is illustrative; in examples, the specific number, size, distribution, and other characteristics of the iron ions 110 may vary. The MMC layers described herein (such as MMC layer 108) are mold compounds in which metal (e.g., iron) particles are distributed throughout the mold compound (which can be distinguished from a mold compound having a single magnetic core). Figure 1B2 According to each instance Figure 1B1 Top view of the structure. Figure 1B3According to each instance Figure 1B1 perspective view of the structure.

[0018] The method 200 includes grinding the first MMC layer to thin the first MMC layer ( 206 ). The first MMC layer is thinned to remove excess thickness of the first MMC layer such that top surfaces of the underlying vias 104 , 106 are exposed. Fig.1C1 yes Figure 1B1 A profile cross-sectional view of the structure of , except that the MMC layer 108 has been thinned by grinding to expose the top surfaces of the vias 104 and 106, as shown. Fig.1C1 The resulting structure is shown in FIG. 1 having a top surface 112 including vias 104, 106, MMC layer 108, and one or more iron ions 110. After grinding, the thickness of the MMC layer 108 is in the range of 60 microns to 115 microns, where the lower limit represents a manufacturing tolerance limit, and where thicknesses exceeding the upper limit increase cost and result in reduced coupling and quality factor of the inductor coil. Fig.1C2 According to each instance Fig.1C1 Top view of the structure. Fig.1C3 According to each instance Fig.1C1 perspective view of the structure.

[0019] The method 200 includes applying a first insulating layer on the ground first MMC layer (208). Figure 1D1 yes Fig.1C1 1 , wherein an insulating layer 114 is added to the top surface 112. The insulating layer 114 can be a dielectric layer such as silicon dioxide, silicon nitride, polyimide, epoxy, benzocyclobutene, fluoropolymer, or another suitable type of material such as an organic polymer (e.g., polyethylene, polypropylene, polyethylene terephthalate). The dielectric can include a solder mask, a prepreg, or a built-up film (e.g., The thickness of the insulating layer 114 is in the range of 10 microns to 40 microns, where the lower limit of this range is critical because manufacturing tolerances do not allow thicknesses below this range, and where the upper limit of this range is critical because thicknesses above this range result in reduced coupling and quality factor of the inductor coil. The insulating layer 114 covers all areas of the top surface 112 to ensure that no inadvertent inductance is applied to the inductor coil. Figures 1A1 to 1L3 A short circuit is established between various conductive features of the package formed in FIG. Figure 1D2 According to each instance Figure 1D1 Top view of the structure. Fig.1D3 According to each instance Figure 1D1 perspective view of the structure.

[0020] The method 200 includes forming an aperture in a first insulating layer and plating a through hole in the aperture (210). Figure 1E1 yes Figure 1D1 104, 106, except that an aperture 116 is formed in the insulating layer 114. For example, an aperture 116 is formed to be vertically aligned with the through-holes 104, 106, which means that a vertical line extends through the center of the through-hole 104 and a corresponding one of the aperture 116, and another vertical line extends through the center of the through-hole 106 and another one of the aperture 116. The aperture 116 must not expose any MMC layer 108, because doing so may cause an unintentional short circuit of the type described in detail above. The aperture 116 exposes the top surface of the through-holes 104, 106, so that the through-holes 104, 106 can be freely accessed through the aperture 116, as shown. Figure 1E2 According to each instance Figure 1E1 Top view of the structure. Figure 1E3 According to each instance Figure 1E1 perspective view of the structure.

[0021] Figure 1F1 yes Figure 1E1 104, 106, except that the through holes 117, 118 are plated in the apertures 116 formed above the corresponding through holes 104, 106. The through holes 117, 118 can be formed by electroplating or electroless plating or by any other suitable technique. As shown, the through holes 117, 118 fill their respective apertures 116. In an example, the top surfaces of the through holes 117, 118 and the top surface of the insulating layer 114 are all approximately flush with each other (i.e., within + / - 5 microns). The through holes 117, 118 can be composed of any suitable metal or alloy, such as copper, gold or silver. Figure 1F2 According to each instance Figure 1F1 Top view of the structure. Figure 1F3 According to each instance Figure 1F1 perspective view of the structure.

[0022] The method 200 includes plating a second coil (212) on the first insulating layer. Figure 1G1 yes Figure 1F1 A profile cross-sectional view of the structure of FIG. 1 is shown, except that a coil 124 is added on the insulating layer 114, as shown. The coil 124 may have any number of turns and may be made of any suitable material. The description provided above for the coil 102 also applies to the coil 124, but the coils 102 and 124 do not necessarily share any physical dimensions, material composition, location, etc. The coil 124 may be formed by electroplating, electroless plating, or any other suitable technique. Figure 1G2 According to each instance Figure 1G1 Top view of the structure. Figure 1G3 According to each instance Figure 1G1 perspective view of the structure.

[0023] The method 200 includes applying a second MMC layer to a second coil (213). Figure 1H1 yes Figure 1G1 1, except for the addition of an MMC layer 126 containing a plurality of iron ions 128. The description provided above for MMC layer 108 also applies to MMC layer 126, but MMC layers 108 and 126 need not be identical or have any shared properties. Figure 1H2 According to each instance Figure 1H1 Top view of the structure. Figure 1H3 According to each instance Figure 1H1 perspective view of the structure.

[0024] The method 200 includes grinding the second MMC layer (214). Fig.1I1 yes Figure 1H1 1, except that the MMC layer 126 has been thinned by grinding. The grinding exposes the top surface of the coil 124 and exposes the top surface of the iron ions 128. Fig.1I1 The structure has a top surface 130, to which the coil 124, at least one of the iron ions 128, and the MMC layer 126 are exposed, as shown. The thickness of the ground MMC layer 126 is in the range of 60 microns to 115 microns, wherein the lower end of this range represents a manufacturing tolerance limit, and wherein thicknesses above this range are disadvantageous due to increased cost and reduced coupling and quality factor of the inductor coil. Fig.1I2 According to each instance Fig.1I1 Top view of the structure. Fig.1I3 According to each instance Fig.1I1 perspective view of the structure.

[0025] The method 200 includes applying a second insulating layer (216) on the ground second MMC layer. Figure 1J1 yes Fig.1I1 1, except that an insulating layer 132 is added on top surface 130. The thickness of insulating layer 132 is in the range of 10 microns to 40 microns, where thicknesses below this range are difficult or impossible due to manufacturing tolerances, and where thicknesses above this range are disadvantageous because of increased cost without any performance advantage. The description of the material composition of insulating layer 114 provided above also applies to insulating layer 132, but insulating layers 114, 132 do not necessarily share any properties. Figure 1J2 According to each instance Figure 1J1 Top view of the structure. Figure 1J3 According to each instance Figure 1J1 perspective view of the structure.

[0026] The method 200 includes removing the carrier and applying a third insulating layer on the first coil (218). The method 200 also includes forming an aperture in the third insulating layer and plating a through hole in the aperture, thereby forming an inductor package (220). Figure 1K1 yes Figure 1J1 100, except that the carrier 100 has been removed, the structure has been rotated 180 degrees in the vertical plane (i.e., inverted), and a third insulating layer 133 is applied to the coil 102 and the MMC layer 108, as shown. The description provided above for the first insulating layer 114 and the second insulating layer 132 also applies to the third insulating layer 133, but the insulating layers 114, 132, 133 do not have to share the same characteristics, such as physical dimensions, material composition, etc. The thickness of the third insulating layer 133 is in the range of 10 microns to 40 microns, wherein a thickness above this range is disadvantageous because of increased cost without any performance advantage; and wherein a thickness below this range is disadvantageous because of manufacturing tolerance limitations. Aperture 134 is formed in third insulating layer 133 in vertical alignment with through-hole 104 and the section of coil 102 closest to through-hole 104, as shown, meaning that a vertical line extends through one of through-hole 104 and aperture 134, and another vertical line extends through the other of the section of coil 102 closest to through-hole 104 and aperture 134. As with aperture 116, aperture 134 exposes coil 102 so that coil 102 can be directly accessed through aperture 134, but aperture 134 must not allow exposure of MMC layer 108, as this increases the risk of unintentional electrical shorting described above. Figure 1K2 According to each instance Figure 1K1 Top view of the structure. Figure 1K3 According to each instance Figure 1K1 perspective view of the structure.

[0027] Figure 1L1 yes Figure 1K1 104, 117, and 136 are collectively referred to herein as through-holes 142. Through-holes 106, 118 are collectively referred to herein as through-holes 140. Figure 1L2 According to each instance Figure 1L1 Top view of the structure. Figure 1L3 According to each instance Figure 1L1 perspective view of the structure.

[0028] Figure 3A1 is a perspective view of coils 102, 124 and through holes 140, 142. Coils 102 and 124 are in different horizontal planes, which means that coils 102 and 124 are vertically separated from each other. Although coils 102, 124 are represented as rectangular, other shapes such as circular coils are also considered and included within the scope of the present disclosure. Through hole 138 is coupled to the first end of coil 102 and extends vertically from the horizontal plane of coil 102. The second end of coil 102 is located at the center of coil 102 and is coupled to through hole 140, which extends vertically downward toward coil 124. Through hole 140 is coupled to the first end of coil 124, and the second end of coil 124 is coupled to through hole 142. Through hole 142 extends vertically toward the horizontal plane of coil 102. Through hole 142 has a distal tip 300. The top surface of through hole 138 is roughly coplanar with distal tip 300 (i.e., within + / - 5 microns). In other words, the top surface of the through hole 138 and the distal tip 300 are approximately equidistant from the coil 102 . Figure 3B According to each instance Figure 3A Top view of the structure. Figure 3C According to each instance Figure 3A A cross-sectional view of the structure.

[0029] Figure 4A is based on the method 200 and Figures 1A1 to 1L3 A perspective view of a process flow for forming an inductor package 400 is shown. Figure 4B According to each instance Figure 4A Top view of the structure. Figure 4C According to each instance Figure 4A A cross-sectional view of the structure.

[0030] Reference again Figure 2 The method 200 includes coupling an inductor package to a semiconductor die (222), and covering the inductor package and the semiconductor die with a molding compound to form a semiconductor package (224). Figure 5A5 is an outline cross-sectional view of a semiconductor package 500 that includes a semiconductor die 501 coupled to a substrate 502 by means of conductive terminals 504 (e.g., solder bumps). For example, the conductive terminals 504 may be coupled to conductive traces on the substrate 502. The inductor package 400 is coupled to the substrate 502, such as to the conductive traces described above. In this manner, the semiconductor die 501 and the inductor package 400 are coupled to each other so that the semiconductor die 501 is configured to use the inductor package 400. A molding compound 506 covers the semiconductor die 501, the conductive terminals 504, the substrate 502, and the inductor package 400. The molding compound 506 does not directly contact any coil within the inductor package 400, at least because the insulating layers described above (e.g., the insulating layers 114, 132, 133, such as dielectric layers) prevent such direct contact. Figure 5B According to each instance Figure 5A Top view of the structure. Figure 5C According to each instance Figure 5A perspective view of the structure.

[0031] Although method 200 depicts forming two layers in inductor package 400, the scope of the present disclosure is not limited in this regard. Method 200 may be extended to fabricating inductor package 400 having any suitable number of layers, ranging from one layer and upwards.

[0032] In this specification, the term "coupled" may encompass connections, communications, or signal paths that achieve a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B through a direct connection; or (b) in a second instance, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not change the functional relationship between device A and device B, so that device B is controlled by device A via the control signal generated by device A.

[0033] In this specification, unless otherwise stated, "about," "approximately," or "substantially" preceding a parameter means within a + / -10% range of the parameter. Modifications may be made in the described examples, and other examples may be made within the scope of the claims.

Claims

1. A semiconductor package, comprising: semiconductor die; and an inductor coupled to the semiconductor die, the inductor comprising: a first metal coil having a first end coupled to the semiconductor die and a second end; a second metal coil vertically spaced apart from the first metal coil and having a third end coupled to the second end and a fourth end coupled to the semiconductor die; a magnetic molding compound MMC located between the first metal coil and the second metal coil, the MMC including conductive ions; and An insulating layer is located between the first metal coil and the second metal coil. 2 . The package of claim 1 , wherein the insulating layer insulates a first portion and a second portion of the second metal coil from making electrical contact with each other by means of at least one of the conductive ions of the MMC. The package of claim 1 , wherein the conductive ions are iron ions. The package of claim 1 , wherein the insulating layer is a dielectric layer.

5. The package of claim 4, wherein the dielectric layer is selected from the group consisting of: solder resist, prepreg, polyimide, and build-up film. 6 . The package of claim 1 , wherein the insulating layer includes an aperture through which the first metal coil and the second metal coil are coupled to each other. 7 . The package of claim 1 , wherein the insulating layer has a thickness in a range of 10 microns to 40 microns.

8. The package of claim 1, wherein the inductor is coupled to the semiconductor die by means of a conductive layer in a substrate of the package.

9. A semiconductor package, comprising: An inductor comprising: A first metal coil having a first end and a second end, wherein the first end can be accessed by a device external to the inductor; a second metal coil having a third end and a fourth end; a magnetic molding compound MMC located between the first metal coil and the second metal coil; a dielectric layer located between the first metal coil and the second metal coil, the dielectric layer contacting the first coil but not contacting the second coil; a first via coupling the second end and the third end through a first aperture in the dielectric layer; and A second via is coupled to the fourth end and extends vertically through the second aperture in the dielectric layer to terminate at a fifth end, the first end and the fifth end being substantially equidistant from the first coil in a vertical direction.

10. The package of claim 9, further comprising a semiconductor die coupled to the first end and the fifth end, and a molding compound covering the semiconductor die and the inductor.

11. The package of claim 9, further comprising a second dielectric layer, the first metal coil being located between the first dielectric layer and the second dielectric layer.

12. The package of claim 9, wherein the MMC comprises iron ions.

13. A method for manufacturing a semiconductor package, comprising: Plating a first metal coil on a carrier; covering the first metal coil with a first magnetic molding compound MMC layer; grinding the first MMC layer to reduce the thickness of the first MMC layer; covering the first MMC layer with an insulating layer having a thickness in a range of 10 micrometers to 40 micrometers; forming a first aperture and a second aperture in the insulating layer; a second metal coil plated on a first surface of the insulating layer opposite to a second surface of the insulating layer facing the first metal coil, the first metal coil and the second metal coil being coupled via a through hole extending through the first aperture; covering the second metal coil with a second MMC layer; grinding the second MMC layer to reduce the thickness of the second MMC layer; removing the carrier; coupling a semiconductor die to the first metal coil and the second metal coil; and The semiconductor die and the first and second metal coils are covered with a molding compound.

14. The method of claim 13, further comprising: forming a second through hole extending vertically from the second metal coil toward the first metal coil; A third through hole is formed extending vertically away from the first metal coil, wherein a first end of the second through hole and a second end of the third through hole are substantially equidistant from the first metal coil. The method of claim 13 , wherein the MMC layer comprises conductive ions. The method of claim 15 , wherein the conductive ions include iron ions. The method of claim 13 , wherein the insulating layer is a dielectric layer.

18. The method of claim 17, wherein the dielectric layer is selected from the group consisting of: solder resist, prepreg, polyimide, and build-up film.

19. The method of claim 13, wherein the molding compound does not directly contact the second metal coil.

20. The method of claim 13, further comprising covering the second MMC layer with a second dielectric layer.

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