Vertical cavity surface emitting laser device with current blocking reflector

Abstract

The invention relates to a vertical cavity surface emitting laser device with a current blocking reflector. A transmitter includes: a substrate; a current blocking distributed Bragg reflector (DBR) disposed on the substrate, where the current blocking DBR includes a plurality of p-n junctions vertically connected in series to form a bidirectional current blocking structure; a bottom contact layer disposed on the current blocking DBR; a bottom DBR disposed on the bottom contact layer; a top DBR disposed on the bottom DBR; an active region configured to generate laser light, where the active region is disposed between the bottom DBR and the top DBR; a top contact layer disposed on the top DBR; and an optical output disposed over the top DBR, where the emitter is configured to emit laser light via the optical output.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to U.S. Patent Application No. 63 / 590,865, filed on October 17, 2023, entitled “VERTICAL CAVITY SURFACE EMITTING LASER DEVICE WITH CURRENT-BLOCKING REFLECTOR”. The disclosure of the prior application is considered a part of and incorporated by reference into this patent application. Technical Field

[0003] The present disclosure generally relates to a transmitter device having a current blocking reflector. Background Art

[0004] A vertical cavity surface emitting laser (VCSEL) is a type of semiconductor laser diode (e.g., laser resonator) in which the laser beam is emitted perpendicular to the top or bottom surface of the device. A VCSEL typically includes two distributed Bragg reflector (DBR) mirrors arranged parallel to the wafer surface, wherein the active region is arranged between the two DBR mirrors. The active region includes one or more quantum wells for generating laser light. VCSELs are widely used in various applications such as data communications, sensing, and optical interconnects due to their advantages over other types of lasers. For example, VCSELs typically have lower power consumption (e.g., VCSELs require much lower power than other types of lasers to operate, making them more energy-efficient and cost-effective), are capable of high-speed operation (e.g., making VCSELs ideal for data communications and other applications requiring fast signal transmission), have narrow beam divergence (e.g., the narrow beam divergence of VCSELs allows high coupling efficiency with optical fibers and other components, making VCSELs easier to integrate into optical systems), and have high reliability (e.g., VCSELs have long operating lifetimes and are less prone to failure than other types of lasers).

[0005] Different applications, such as three-dimensional sensing and data communications, can use semiconductor lasers that emit in different wavelength bands. For example, short-range communications can use VCSELs that emit at about 850 nanometers (nm), while long-range communications can use VCSELs that emit above 1.3 micrometers (μm) or even above 1.5 μm. Three-dimensional sensing applications, such as light detection and ranging (LiDAR), can use VCSELs that emit at different wavelengths, such as 905nm and 940nm, to achieve various functions.

[0006] A typical VCSEL has a sandwich structure, which is mainly composed of a top distributed Bragg reflector (DBR), a bottom DBR and an active region (e.g., an active layer) arranged between the top DBR and the bottom DBR. Each DBR is composed of a plurality of alternating high-refractive index layers and low-refractive index layers, and each layer has an optical thickness of an odd integer of 1 / 4λ (1 / 4, 3 / 4, ...), where the optical thickness of one λ is the length of a wavelength divided by the refractive index. A high refractive index refers to a relatively high optical refractive index value, while a low refractive index refers to a relatively low optical refractive index value. Optionally, the DBR may include a gradient layer that provides a smoother transition between different energy bands corresponding to a high-refractive index semiconductor material and a low-refractive index semiconductor material. The top DBR, the active region, and the bottom DBR form an optical cavity with a gain material. Summary of the invention

[0007] In some embodiments, an emitter includes: a substrate; a current blocking DBR arranged on the substrate, wherein the current blocking DBR includes a plurality of pn junctions connected vertically in series to form a bidirectional current blocking structure; a bottom contact layer arranged on the current blocking DBR; a bottom DBR arranged on the bottom contact layer; a top DBR arranged on the bottom DBR; an active region configured to generate laser light, wherein the active region is arranged between the bottom DBR and the top DBR; a top contact layer arranged on the top DBR; and an optical output arranged above the top DBR, wherein the emitter is configured to emit laser light via the optical output.

[0008] In some embodiments, an emitter array includes: a substrate; a first emitter arranged on the substrate, wherein the first emitter includes: a first current blocking DBR arranged on the substrate, wherein the first current blocking DBR includes a first plurality of pn junctions connected in series vertically to form a first bidirectional current blocking structure; a first bottom contact layer arranged on the first current blocking DBR and associated with a first current; a first bottom DBR arranged on the first bottom contact layer; a first top DBR arranged on the first bottom DBR; a first active region configured to generate a first laser, wherein the first active region is arranged between the first bottom DBR and the first top DBR; a first top contact layer arranged on the first top DBR and associated with the first current; and a first optical output arranged above the first top DBR, wherein the first emitter is configured to emit a first laser via the first optical output; a second emitter arranged on the substrate, wherein the second emitter is adjacent to the first emitter, and wherein the second emitter includes The invention discloses a bidirectional current blocking structure comprising: a second current blocking DBR arranged on a substrate, wherein the second current blocking DBR includes a second plurality of pn junctions connected in series vertically to form a second bidirectional current blocking structure; a second bottom contact layer arranged on the second current blocking DBR and associated with a second current; a second bottom DBR arranged on the second bottom contact layer; a second top DBR arranged on the second bottom DBR; a second active region configured to generate a second laser, wherein the second active region is arranged between the second bottom DBR and the second top DBR; a second top contact layer arranged on the second top DBR and associated with the second current; and a second optical output arranged above the second top DBR, wherein a second emitter is configured to emit a second laser via the second optical output; and an isolation region configured to electrically isolate a first emitter from a second emitter, wherein the isolation region is laterally arranged between the first bottom contact layer and the second bottom contact layer, and is laterally arranged between the first current blocking DBR and the second current blocking DBR.

[0009] In some embodiments, a method of manufacturing an emitter includes: forming a current blocking DBR on a substrate, wherein the current blocking DBR includes multiple pn junctions connected vertically in series to form a bidirectional current blocking structure; forming a bottom contact layer on the current blocking DBR, wherein the current blocking DBR is configured to electrically isolate the substrate from the bottom contact layer; forming a bottom DBR on the bottom contact layer; forming an active region on the bottom DBR, wherein the active region is configured to generate laser light; forming a top DBR on the active region; forming a top contact layer on the top DBR; and forming an optical output above the top DBR, wherein the optical output is configured to emit laser light from the emitter. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A and Figure 1B 2 are diagrams depicting a top view of an example emitter and a cross-sectional view of an example emitter along line XX, respectively.

[0011] Figure 2 A cross-sectional view of a transmitter is shown in accordance with one or more embodiments.

[0012] Figure 3 An example of reverse vertical series connection of pn junctions to form a current blocking structure is shown according to one or more embodiments.

[0013] Figure 4 A current blocking DBR according to one or more embodiments is shown.

[0014] Figure 5 A current blocking DBR according to one or more embodiments is shown.

[0015] Figure 6 A current blocking DBR according to one or more embodiments is shown.

[0016] Figure 7 A current blocking DBR according to one or more embodiments is shown.

[0017] Figure 8 A current blocking DBR according to one or more embodiments is shown.

[0018] Fig. 9 An addressable emitter array is shown in accordance with one or more implementations.

[0019] Fig.10 An addressable emitter array is shown in accordance with one or more implementations.

[0020] Fig.11 is a flow chart of an example process associated with a vertical cavity surface emitting laser apparatus. DETAILED DESCRIPTION

[0021] The following detailed description of example embodiments refers to the accompanying drawings.The same reference numbers in different drawings may identify the same or similar elements.

[0022] In the past few years, VCSEL arrays have achieved widespread market applications in both consumer mobile devices for 3D sensing at short range (less than a few meters) and LiDAR for longer range detection. In addition, multi-junction schemes achieve high peak power density and reduce the operating current for the desired optical power. This higher voltage and lower operating current make LiDAR modules more efficient. Given that VCSEL arrays offer the possibility of LiDAR scanning without moving parts, the emitter array (such as an emitter stripe array or an emitter array matrix) should be matrix addressable. In other words, each emitter in the emitter array should be selectively activated / deactivated.

[0023] Vertical emitters (such as VCSELs) and vertical emitter arrays are typically manufactured using epitaxial structures grown on conductive substrates (typically n-type substrates) that have better quality than semi-insulating (SI) type substrates. Conductive substrates make it challenging to produce matrix-addressable emitter arrays. Some emitter arrays may use SI substrates or electrical isolation structures (such as NPN (or PNP) schemes) to isolate different emitters (e.g., different VCSELs) in an emitter array. However, SI substrates typically have higher defect densities than conductive substrates (e.g., GaAs or InP substrates). Subsequent epitaxial structures grown on SI substrates may have lower quality than epitaxial structures grown on conductive substrates. Another approach may utilize an isolation layer or multiple isolation layers that are used to block current crosstalk between each individual emitter in an emitter array in an emitter chip. The isolation layer may include a PNP layer, an NPN layer, a PNPN layer, an NPNP layer, and / or an undoped layer (e.g., an intrinsic layer, i-type). The epitaxy of the additional isolation layer causes the entire epitaxial structure to increase in epitaxial thickness. Adding an isolation layer increases the complexity and cost of VCSEL manufacturing. In addition, high optical power density LiDAR using multi-junction VCSELs may require high voltage operation, so that isolation with a high voltage range of more than 10V is required between the substrate and the emitter, between the emitter to the emitter, or between the subarray to the subarray. Higher operating voltages typically require thicker isolation layers to meet the isolation requirements for normal operation, which in turn increases the cost of VCSEL manufacturing. Higher complexity, higher cost, and thicker devices are generally undesirable.

[0024] Some embodiments disclosed herein provide a current blocking DBR to provide electrical isolation. For example, the current blocking DBR may be incorporated into the bottom DBR of an emitter (e.g., of a VCSEL), or may be provided as an additional DBR adjacent to a substrate (e.g., a conductive substrate such as an n-type substrate) on which the current blocking DBR is formed.

[0025] The current blocking DBR may include alternating p-type doped layers and n-type doped layers, which form a series of pnpn junctions or pinipin junctions to block or isolate current. For example, a portion of a layer stack of a high refractive index layer and a low refractive index layer may be alternately or periodically p-doped or n-doped. For example, the high refractive index layer may be p-type, and the low refractive index layer may be n-type, or vice versa. In some embodiments, the current blocking DBR may include an intrinsic layer (i layer) between the p-type doped layer and the n-type doped layer. Therefore, this portion of the layer stack may be configured for current blocking while also performing optical reflection on light in the optical cavity. In other words, the current blocking DBR has a current blocking layer that is also performed as an optical reflector layer. The active region may be a single junction including a quantum well or may include a multi-junction, which includes a plurality of junctions connected by a tunnel junction, wherein each junction may have a quantum well. Therefore, DBR reflection may be combined with current blocking to simplify the epitaxial structure of the emitter. Furthermore, the electrical isolation using a certain number of current blocking DBR pairs can be enhanced without adding extra thickness compared to conventional PNP or NPN isolation.

[0026] Figure 1A and Figure 1B 1 and 2 are diagrams depicting a top view of an example transmitter 100 and a cross-sectional view 150 of an example transmitter 100 along line XX, respectively. Figure 1A As shown, transmitter 100 may include a collection of transmitter layers constructed in a transmitter architecture. In some embodiments, transmitter 100 may correspond to one or more vertical transmission devices described herein.

[0027] like Figure 1A As shown, in this example, the emitter 100 may include an implant protection layer 102 having a circular shape. In some embodiments, the implant protection layer 102 may have another shape, such as an elliptical shape, a polygonal shape, etc. The implant protection layer 102 is defined based on the space between the segments (not shown) of the implant material included in the emitter 100.

[0028] like Figure 1AAs shown in the medium gray area and the dark gray area in , the emitter 100 includes an ohmic metal layer 104 (e.g., a P-type ohmic metal layer or an N-type ohmic metal layer) constructed into a partial ring shape (e.g., having an inner radius and an outer radius). As described below, the medium gray area shows the area of ​​the ohmic metal layer 104 covered by the protective layer (e.g., a dielectric layer or a passivation layer) of the emitter 100, while the dark gray area shows the area of ​​the ohmic metal layer 104 exposed by the via 106. As shown, the ohmic metal layer 104 overlaps the implant protection layer 102. For example, in the case of a P-type upper / top emitting emitter 100, this configuration can be used. In the case of a bottom emitting emitter 100, the configuration can be adjusted as needed.

[0029] Figure 1A Not shown in the figure, the emitter 100 includes a protective layer in which a via 106 is formed (e.g., etched). The dark gray area shows the area of ​​the ohmic metal layer 104 that is exposed by the via 106 (e.g., the shape of the dark gray area can be a result of the shape of the via 106), while the medium gray area shows the area of ​​the ohmic metal layer 104 that is covered by some of the protective layer. The protective layer can cover all of the emitter except the via. As shown, the via 106 is formed as a partial ring (e.g., similar to the ohmic metal layer 104) and is formed above the ohmic metal layer 104 so that the metallization on the protective layer contacts the ohmic metal layer 104. In some embodiments, the via 106 and / or the ohmic metal layer 104 can be formed into another shape, such as a full ring or a split ring.

[0030] As further shown, the emitter 100 includes an optical aperture 108 in a portion of the emitter 100 within the inner radius of the partial annular shape of the ohmic metal layer 104. The emitter 100 emits a laser beam via the optical aperture 108. As further shown, the emitter 100 also includes a current limiting aperture 110 (e.g., an oxide aperture (not shown) formed by an oxide layer of the emitter 100). The current limiting aperture 110 is formed below the optical aperture 108.

[0031] like Figure 1A As further shown, the emitter 100 includes a collection of trenches 112 (e.g., oxide trenches) spaced apart (e.g., equally spaced, unequally spaced) around the circumference of the implant protection layer 102. How closely the trenches 112 can be positioned relative to the optical aperture 108 depends on the application and is generally limited by the implant protection layer 102, the ohmic metal layer 104, the vias 106, and manufacturing tolerances.

[0032] Figure 1A The number and arrangement of layers shown are provided as examples. In practice, transmitter 100 may include more Figure 1AThe layers shown may be more layers, fewer layers, different layers, or layers arranged in a different manner. For example, while emitter 100 includes a set of six grooves 112, in practice, other configurations are possible, such as a compact emitter including five grooves 112, seven grooves 112, or another number of grooves. In some embodiments, the grooves 112 may surround emitter 100 to form a mesa structure dt. As another example, while emitter 100 is a circular emitter design, in practice, other designs may be used, such as a rectangular emitter, a hexagonal emitter, an elliptical emitter, etc. Additionally or alternatively, a set of layers (e.g., one or more layers) of emitter 100 may each perform one or more functions described as being performed by another set of layers of emitter 100.

[0033] It is worth noting that while the design of emitter 100 is described as including a VCSEL, other implementations are possible. For example, the design of emitter 100 may be applied in the context of another type of optical device, such as a light emitting diode (LED), or another type of vertical emitting (e.g., top emitting or bottom emitting) optical device. Additionally, the design of emitter 100 may be applied to emitters of any wavelength, power level, and / or emission profile. In other words, emitter 100 is not specific to an emitter having given performance characteristics.

[0034] like Figure 1B As shown, the example cross-sectional view may represent a cross section of the emitter 100 through or between a pair of grooves 112 (eg, as shown in FIG. 1 ). Figure 1A ). As shown, the emitter 100 may include a back cathode layer 128, a substrate layer 126, a bottom mirror 124, an active region 122, an oxide layer 120, a top mirror 118, an implanted isolation material 116, a protective layer 114 (e.g., a dielectric passivation / mirror layer), and an ohmic metal layer 104. As shown, the emitter 100 may have an overall height of, for example, approximately 10 μm.

[0035] The back cathode layer 128 may include a layer that makes electrical contact with the substrate layer 126. For example, the back cathode layer 128 may include an annealed metallization layer, such as a AuGeNi layer, a PdGeAu layer, or the like.

[0036] The substrate layer 126 may include a base substrate layer on which an epitaxial layer is grown. For example, the substrate layer 126 may include a semiconductor layer, such as a GaAs layer, an InP layer, and / or another type of semiconductor layer.

[0037] The bottom mirror 124 may include a bottom reflector layer of the emitter 100. For example, the bottom mirror 124 may include a DBR. A portion of the bottom mirror 124 may include a current blocking DBR including alternating p-type doped layers and n-type doped layers. In some embodiments, the current blocking DBR may include an intrinsic layer (i-layer) between the p-type doped layer and the n-type doped layer.

[0038] The active region 122 may include a layer that confines electrons and defines the emission wavelength of the emitter 100. For example, the active region 122 may be a quantum well.

[0039] The oxide layer 120 may include an oxide layer that provides optical and electrical confinement to the emitter 100. In some embodiments, the oxide layer 120 may be formed due to wet oxidation of an epitaxial layer. For example, the oxide layer 120 may be an Al2O3 layer formed due to oxidation of an AlAs or AlGaAs layer. The trench 112 may include an opening that allows oxygen (e.g., dry oxygen, wet oxygen) to enter the epitaxial layer that forms the oxide layer 120.

[0040] The current confining aperture 110 may include an optically active aperture defined by an oxide layer 120. The size of the current confining aperture 110 may range from, for example, about 4 μm to about 20 μm. In some embodiments, the size of the current confining aperture 110 may depend on the distance between the trenches 112 surrounding the emitter 100. For example, the trenches 112 may be etched to expose the epitaxial layer forming the oxide layer 120. Here, before forming (e.g., depositing) the protective layer 114, the oxidation of the epitaxial layer may be increased toward the center of the emitter 100 at a certain distance (e.g., at about 100°). Figure 1B The symbol is d o ), thereby forming an oxide layer 120 and a current confining aperture 110. In some embodiments, the current confining aperture 110 may include an oxide aperture. Additionally or alternatively, the current confining aperture 110 may include an aperture associated with another type of current confinement technology (such as an etched mesa, a region without ion implantation, a lithographically defined intracavity mesa and regrowth, etc.).

[0041] The top mirror 118 may include a top reflector layer of the emitter 100. For example, the top mirror 118 may include a DBR.

[0042] The implant isolation material 116 may include a material that provides electrical isolation. For example, the implant isolation material 116 may include an ion implant material (such as a hydrogen / proton implant material or similar implant elements) to reduce electrical conductivity. In some embodiments, the implant isolation material 116 may define an implant protection layer 102.

[0043] The protective layer 114 may include a layer that acts as a protective passivation layer and may act as an additional DBR. For example, the protective layer 114 may include one or more sublayers (e.g., a dielectric passivation layer and / or a mirror layer, a SiO2 layer, a Si3N4 layer, an Al2O3 layer, or other layers) deposited (e.g., by chemical vapor deposition, atomic layer deposition, or other techniques) on one or more other layers of the emitter 100.

[0044] As shown, the protective layer 114 may include one or more vias 106 that provide an electrical path to the ohmic metal layer 104. For example, the vias 106 may be formed as etched portions of the protective layer 114 or stripped sections of the protective layer 114. The optical aperture 108 may include a portion of the protective layer 114 above the current confining aperture 110 through which light may be emitted.

[0045] The ohmic metal layer 104 may include a layer for making electrical contact, through which current may flow. For example, the ohmic metal layer 104 may include a Ti and Au layer, a Ti and Pt layer, and / or an Au layer, etc., through which current may flow (e.g., by contacting a bonding pad (not shown) of the ohmic metal layer 104 via the via 106). The ohmic metal layer 104 may be P-type ohmic, N-type ohmic, or other forms known in the art. The selection of a particular type of ohmic metal layer 104 may depend on the architecture of the emitter and is well within the knowledge of those skilled in the art. The ohmic metal layer 104 may provide an ohmic contact between a metal and a semiconductor and / or may provide a non-rectifying electrical junction and / or may provide a low resistance contact. In some embodiments, a series of steps may be used to manufacture the emitter 100. For example, the bottom mirror 124, the active region 122, the oxide layer 120, and the top mirror 118 may be epitaxially grown on the substrate layer 126, after which the ohmic metal layer 104 may be deposited on the top mirror 118. Next, trenches 112 may be etched to expose oxide layer 120 for oxidation. Implant isolation material 116 may be produced via ion implantation, after which protective layer 114 may be deposited. Vias 106 may be etched in protective layer 114 (e.g., to expose ohmic metal layer 104 for contact). Electroplating, seeding, and etching may be performed, after which substrate layer 126 may be thinned and / or ground to a target thickness. Finally, back cathode layer 128 may be deposited on the bottom side of substrate layer 126.

[0046] Figure 1B The number, arrangement, thickness, order, symmetry, etc. of layers shown are provided as examples. In practice, transmitter 100 may include more than Figure 1BThe layers shown may be more layers, fewer layers, different layers, layers constructed differently, or layers arranged differently. Additionally or alternatively, a collection of layers (e.g., one or more layers) of transmitter 100 may be described as one or more functions performed by another collection of layers of transmitter 100, and any layer may include more than one layer.

[0047] Figure 2 A cross-sectional view of an emitter 200 according to one or more embodiments is shown. The emitter 200 may be a VCSEL device (e.g., a VCSEL emitter), and the emitter 200 includes: a substrate 202; a current blocking DBR 204 disposed on the substrate 202; a bottom contact layer 206 disposed on the current blocking DBR 204; a bottom DBR 208 disposed on the bottom contact layer 206; a top DBR 210 disposed on the bottom DBR 208; an active region 212 disposed between the bottom DBR 208 and the top DBR 210; an oxide layer 214 defining a current limiting aperture 216 and providing optical and electrical confinement to the emitter 200; a top contact layer 218 disposed on the top DBR 210; and an optical output end 220 disposed on the top DBR 210 for light output. Active region 212 can generate laser light, and emitter 200 can be configured to emit laser light via optical output 220. In some implementations, active region 212 can be a quantum well active region.

[0048] Additionally, the emitter 200 may include a protection layer 222 disposed on the top DBR 210. For example, the protection layer 222 may be a passivation layer.

[0049] In some embodiments, the transmitter 200 may include a spacer DBR 224 disposed between the current blocking DBR 204 and the bottom contact layer 206 (e.g., above the current blocking DBR 204 and below the bottom contact layer 206). The spacer DBR 224 may include a doped layer or an undoped layer. In some embodiments, the spacer DBR 224 may be part of the current blocking DBR 204.

[0050] In some embodiments, the emitter 200 can include an implant isolation region 226 for electrical isolation. The implant isolation region 226 can include an implant isolation material. In some embodiments, the implant isolation region 226 can be implanted into an edge region of the top DBR 210.

[0051] The top contact layer 218 may include a metal contact or contact pad configured to make contact with a metal layer, such as an ohmic metal layer. In some embodiments, the bottom contact layer 206 may be a contact buffer layer for a cathode electrical connection, and the top contact layer 218 may be an anode contact layer for an anode electrical connection. Alternatively, the bottom contact layer 206 may be an anode buffer layer for an anode electrical connection, and the top contact layer 218 may be a cathode contact layer for a cathode electrical connection. The bottom contact layer 206 and the top contact layer 218 may be configured to allow current to flow between the bottom contact layer 206 and the top contact layer 218 for generating laser light at the active region 212. For example, a voltage may be applied across the bottom contact layer 206 and the top contact layer 218 to activate the emitter 200 and generate current.

[0052] The substrate may be a GaAs, InP, InGaAs, GaSb, Si, Ge, GaP, GaN, ZnO or sapphire substrate, which is used to grow an epitaxial structure on top. The substrate may be an n-type, p-type, semi-insulating, insulating or conductive type. The current blocking DBR 204 may be formed directly on the substrate 202 (e.g., in direct contact with it). The current blocking DBR 204 includes a plurality of pn junctions connected vertically in series to form a bidirectional current blocking structure. For example, a plurality of pn junctions may be equivalent to a series of current blocking diodes arranged in series relative to each other. The current blocking DBR 204 may electrically isolate the substrate 202 from the bottom contact layer 206 (e.g., by providing current isolation between the bottom contact layer 206 and the substrate 202). For example, the current blocking DBR 204 may prevent leakage current from flowing from the bottom contact layer 206 to the substrate 202, and vice versa. Thus, current blocking DBR 204 can be used to electrically isolate emitter 200 from other emitters and / or other current sources to ensure that active region 212 produces laser light only when needed. In addition, current blocking DBR 204 is an optical reflector configured to reflect a portion of the laser light generated by active region 212 toward optical output 220. Thus, current blocking DBR 204 provides dual functionality by providing both electrical isolation and optical reflection.

[0053] The current blocking DBR 204 may include a plurality of alternatingly stacked high refractive index layers and low refractive index layers, wherein the high refractive index layers are p-type doped and the low refractive index layers are n-type doped, or the high refractive index layers are n-type doped and the low refractive index layers are p-type doped. Thus, alternating p-type doped layers and n-type doped layers may be formed within the current blocking DBR 204 to form a plurality of pn junctions.

[0054] In some embodiments, a first portion of each high refractive index layer is p-type doped, and a second portion of each high refractive index layer is n-type doped, so that multiple pn junctions are formed with the low refractive index layer. Additionally or alternatively, a first portion of each low refractive index layer is p-type doped, and a second portion of each low refractive index layer is n-type doped, so that multiple pn junctions are formed with the high refractive index layer.

[0055] In some embodiments, the plurality of pn junctions may include a plurality of pin junctions. For example, an intrinsic layer (e.g., an undoped layer or an i-layer) may be provided between a p-type doped layer and an n-type doped layer forming a pn junction. Each intrinsic layer may be thin enough and / or the doping concentrations of the p-type doped layer and the n-type doped layer may be high enough to form a pn junction (e.g., a depletion region is formed between the p-type doped layer and the n-type doped layer). Therefore, the current blocking DBR 204 may include a plurality of intrinsic layers, wherein each intrinsic layer is arranged between respective pairs of p-type doped layers and n-type doped layers of the current blocking DBR 204. In some embodiments, each of the plurality of intrinsic layers is part of a corresponding high refractive index layer of the current blocking DBR 204, or part of a corresponding low refractive index layer of the current blocking DBR 204. In other words, the first portion of each high refractive index layer may be doped, while the second portion of each high refractive index layer may be undoped (intrinsic), and / or the first portion of each low refractive index layer may be doped, while the second portion of each low refractive index layer may be undoped (intrinsic). Thus, each high refractive index layer may have a doped sublayer and an undoped intrinsic sublayer, and / or each low refractive index layer may have a doped sublayer and an undoped intrinsic sublayer.

[0056] In some embodiments, the current blocking DBR 204 may include a plurality of gradient layers. Each gradient layer may be disposed between a respective pair of high refractive index layers and a low refractive index layer of the current blocking DBR 204. Additionally, each gradient layer may have a corresponding intermediate refractive index value between a high refractive index value and a low refractive index value of a respective pair of high refractive index layers and low refractive index layers.

[0057] In some embodiments, the plurality of gradient layers can provide a gradual semiconductor bandgap change or a stepped semiconductor bandgap change between high refractive index materials and low refractive index materials of the alternating stacks of high refractive index layers and low refractive index layers.

[0058] In some embodiments, the current blocking DBR 204 may include a plurality of high refractive index layers and low refractive index layers that are alternately stacked. Each low refractive index layer may include a first plurality of gradient sublayers that provide a first transition of refractive index across a low refractive index range. In addition, each high refractive index layer may include a second plurality of gradient sublayers that provide a second transition of refractive index across a high refractive index range. Therefore, the refractive index of the current blocking DBR 204 may have a periodicity that vertically changes from a minimum refractive index value to a maximum refractive index value. The high refractive index layer may be p-type doped and the low refractive index layer may be n-type doped, or the high refractive index layer may be n-doped and the low refractive index layer may be p-type doped.

[0059] In some embodiments, the current blocking DBR 204 may include a plurality of alternately stacked high refractive index layers and low refractive index layers forming a plurality of DBR pairs. Each DBR pair may include respective adjacent and paired high refractive index layers and low refractive index layers. In addition, the plurality of DBR pairs may be alternately p-type doped and n-type doped to form a plurality of pn junctions. For example, both the high refractive index layer and the low refractive index layer of the first DBR pair may be p-type doped, while both the high refractive index layer and the low refractive index layer of the second DBR pair may be n-type doped. The first DBR pair and the second DBR pair may be arranged to form one pn junction in the pn junction of the current blocking DBR 204. For example, the first DBR pair and the second DBR pair may be adjacent DBR pairs. In some embodiments, each DBR pair may include an intrinsic layer arranged between respective adjacent and paired high refractive index layers and low refractive index layers. Therefore, each DBR may include a high refractive index layer, an intrinsic layer, and a low refractive index layer. In some embodiments, each DBR pair may include one or more gradient layers arranged between respective adjacent and paired high refractive index layers and low refractive index layers. Thus, each DBR pair may include a high refractive index layer, one or more gradient layers, and a low refractive index layer. In some embodiments, each DBR pair may be separated by an intrinsic layer.

[0060] In some embodiments, the current blocking DBR 204 and the bottom DBR 208 may be different sections of the same DBR. In some embodiments, the current blocking DBR 204 and the bottom DBR 208 may be different DBRs. However, for simplicity, the current blocking DBR 204 may be considered as a first DBR, the bottom DBR 208 may be considered as a second DBR, and the top DBR 210 may be considered as a third DBR. Therefore, the transmitter 200 may include at least three DBRs, wherein the DBR in contact with the substrate 202 or arranged closest to the substrate 202 is the current blocking DBR 204. In some embodiments, the spacer DBR 224 may be a fourth DBR, or may be part of the current blocking DBR 204 and / or the bottom DBR 208.

[0061] In order to form a PNPN junction (e.g., a PNPN diode) or a NPNP junction (e.g., an NPNP diode) in a DBR, the high refractive index layer of the DBR may be p-type doped, and the low refractive index layer of the DBR may be n-type doped. Alternatively, the high refractive index layer of the DBR may be n-type doped, and the low refractive index layer of the DBR may be p-type doped. N-type doping may use silicon (Si), sulfur (S), selenium (Se) and / or tellurium (Te) as dopants. P-type doping may use carbon (C), zinc (Zn), beryllium (Be) and / or magnesium (Mg) as dopants.

[0062] The current blocking DBR 204 may be configured to perform optical reflection on light within the optical cavity of the transmitter 200. In other words, the current blocking DBR 204 may have a current blocking structure formed by a (counter-doped) optical reflector layer. The top DBR 210, the active region 212, and the bottom DBR 208 and the current blocking DBR 204 may form an optical cavity with a gain material.

[0063] From the perspective of optical reflection, the current blocking DBR 204 used to block the current can be a DBR, a DBR-like optical reflector, or an optical reflector that includes multiple layers and provides a certain amount of optical reflection. In addition, the current blocking layer can be a set of DBR layers, or only part of the current blocking layer can be a set of DBR layers. The current blocking reflector can include additional spacer layers, intermediate layers, gradient layers, buffer layers, and / or cavity layers.

[0064] In addition, one or more aspects may be included in the above embodiments, including: (1) the multi-junction VCSEL described in the context of this article can have one, two, three or more junctions; (2) the electrical polarity of the VCSEL from top to bottom can be a pin structure or a nip structure. The top semiconductor contact or cap can be a p-type semiconductor or an n-type semiconductor. In addition, by using a tunnel junction, all or part of the p-DBR can be replaced by an n-DBR, and vice versa; (3) the oxide-limited VCSEL can have one, two or more oxide layers on the p-side or n-side; (4) using the optical aperture layer in the VCSEL as current and mode confinement is optional and can be replaced with different approaches (such as implant passivation, mesa or trench isolation or buried tunnel junction); (5) the substrate can be a GaAs, InP, InGaAs, GaSb, Si, Ge, GaP, GaN, ZnO or sapphire substrate, which is used to grow an epitaxial structure on the top. The substrate can be n-type, p-type, semi-insulating, insulating or conductive. Even when epitaxy is used on a semi-insulating substrate or an insulating substrate, embodiments described herein may improve electrical isolation, for example, in cases where the vertical isolation regions do not extend completely down to the substrate.

[0065] As indicated above, Figure 2 are provided as examples. Other examples may differ from those described herein. Figure 2 The content described.

[0066] Figure 3 An example 300A of a schematic diagram of a reverse series connected pnpn diode is shown, which can be formed by a current blocking DBR having alternating p-type high refractive index layers and n-type low refractive index layers. Additionally, Figure 3 An example 300B is shown of a schematic diagram of an anti-series connected npnp diode that may be formed from a current blocking DBR having alternating n-type high refractive index layers and p-type low refractive index layers.

[0067] Figure 3 are provided as examples. Other examples may differ from those described herein. Figure 3 The content described.

[0068] Figure 4 A current blocking DBR 400 is shown according to one or more embodiments. The current blocking DBR 400 may be implemented as the current blocking DBR 204 of the emitter 200. The current blocking DBR 400 includes alternating p-type high refractive index layers 401 and n-type low refractive index layers 402.

[0069] In addition, the current blocking DBR 400 may include one or more gradient layers (not shown) between adjacent and paired high and low refractive index layers. For example, one or more gradient layers may be provided between each adjacent and paired high and low refractive index layers of the current blocking DBR 400. The one or more gradient layers may be n-type doped or p-type doped, or n-type doped in a portion and p-type doped in the remaining portion.

[0070] Adjacent and paired high refractive index layers and low refractive index layers (i.e., DBR pairs) can include two oppositely doped layers, wherein the complete section of the high refractive index layer 401 is p-type doped, and the complete section of the low refractive index layer 402 is n-type doped. Other different configurations or schemes may exist. For example, a portion of the high refractive index layer 401 and / or an adjacent portion of the low refractive index layer 402 may be p-type doped, and the remaining portion of the high refractive index layer 401 and / or an adjacent portion of the low refractive index layer 402 may be n-type doped. Therefore, each high refractive index layer 401 may be formed by two or more high refractive index sublayers, and the two or more high refractive index sublayers may have the same doping type or opposite doping types. Two or more high refractive index sublayers may have the same refractive index or different refractive indices to form a refractive index gradient. Additionally, each low refractive index layer 402 may be formed by two or more low refractive index sublayers, and the two or more low refractive index sublayers may have the same type of doping or opposite doping. The two or more low-refractive-index sub-layers may have the same refractive index or different refractive indices to form a refractive-index gradient.

[0071] For example, DBR pair #1 can be p-type doped (or n-type doped), while DBR pair #2 can be n-type doped (or p-type doped). DBR pair #N can be oppositely doped relative to the adjacent DBR pair, and N can be an integer greater than two. In other words, the high refractive index layer 401 and the low refractive index layer 402 of DBR pair #1 can be p-type (or n-type) doped, while the high refractive index layer 401 and the low refractive index layer 402 of DBR pair #2 can be n-type (or p-type) doped. Therefore, adjacent DBR pairs can have opposite doping. Therefore, the current blocking junction can be formed by alternating p-doped structures and n-doped structures within the current blocking DBR 400.

[0072] In addition, the current blocking DBR 400 may include one or more gradient layers between the high refractive index layer and the low refractive index layer. Figure 4 The graded layer may be n-doped, p-doped, undoped, or n-doped in one portion and p-doped in the remaining portion.

[0073] The current blocking DBR 400 can provide excellent current blocking performance due to several identical or similar pn junctions which can also be heterojunctions. Heterojunctions are formed by different semiconductor materials with different energy bands. For example, an AlGaAs DBR based on GaAs can have a higher aluminum component in the low refractive index layer and a lower aluminum component in the high refractive index layer, so that the two adjacent layers form a heterojunction.

[0074] Figure 4 are provided as examples. Other examples may differ from those described herein. Figure 4 The content described.

[0075] Figure 5 A current blocking DBR 500 is shown according to one or more embodiments. The current blocking DBR 500 may be implemented as the current blocking DBR 204 of the emitter 200. The current blocking DBR 500 includes alternating n-type high refractive index layers 501 and p-type low refractive index layers 502.

[0076] In addition, the current blocking DBR 500 may include one or more gradient layers (not shown) between adjacent and paired high and low refractive index layers. For example, one or more gradient layers may be provided between adjacent and paired high and low refractive index layers of the current blocking DBR 500. The one or more gradient layers may be n-type doped or p-type doped, or n-type doped in a portion and p-type doped in the remaining portion.

[0077] Adjacent and paired high refractive index layers and low refractive index layers (i.e., DBR pairs) can include two oppositely doped layers, wherein the complete section of the high refractive index layer 501 is n-type doped, and the complete section of the low refractive index layer 502 is p-type doped. Other different configurations or schemes may exist. For example, a portion of the high refractive index layer 501 and / or an adjacent portion of the low refractive index layer 502 may be n-type doped, while the remaining portion of the high refractive index layer 501 and / or an adjacent portion of the low refractive index layer 502 may be p-type doped. Therefore, each high refractive index layer 501 may be formed by two or more high refractive index sublayers, and the two or more high refractive index sublayers may have the same doping type or opposite doping types. Two or more high refractive index sublayers may have the same refractive index or different refractive indices to form a refractive index gradient. Additionally, each low refractive index layer 502 may be formed by two or more low refractive index sublayers, and the two or more low refractive index sublayers may have the same type of doping or opposite doping. The two or more low-refractive-index sub-layers may have the same refractive index or different refractive indices to form a refractive-index gradient.

[0078] For example, DBR pair #1 can be p-type doped (or n-type doped), while DBR pair #2 can be n-type doped (or p-type doped). DBR pair #N can be oppositely doped relative to an adjacent DBR pair. In other words, both the high refractive index layer 501 and the low refractive index layer 502 of DBR pair #1 are p-type (or n-type) doped, while both the high refractive index layer 501 and the low refractive index layer 502 of DBR pair #2 are n-type (or p-type) doped. Therefore, adjacent DBR pairs can have opposite doping. Therefore, the current blocking junction can be formed by alternating p-type doping structures and n-type doping structures within the current blocking DBR 500.

[0079] In addition, the current blocking DBR 500 may include one or more gradient layers between the high refractive index layer and the low refractive index layer. Figure 5 The graded layer may be n-doped, p-doped, undoped, or n-doped in one portion and p-doped in the remaining portion.

[0080] The current blocking DBR 500 can provide excellent current blocking performance due to several identical or similar pn junctions which can also be heterojunctions. Heterojunctions are formed by different semiconductor materials with different energy bands. For example, an AlGaAs DBR based on GaAs can have a higher aluminum component in the low refractive index layer and a lower aluminum component in the high refractive index layer, so that the two adjacent layers form a heterojunction.

[0081] Figure 5 are provided as examples. Other examples may differ from those described herein. Figure 5 The content described.

[0082] Figure 6 A current blocking DBR 600 is shown according to one or more embodiments. The current blocking DBR 600 may be implemented as the current blocking DBR 204 of the transmitter 200. The current blocking DBR 600 includes alternating p-type high refractive index layers 601 and n-type low refractive index layers 602. In addition, the current blocking DBR 600 includes an undoped layer 603 (e.g., an intermediate layer or an intrinsic layer) between each pair of high refractive index layers and low refractive index layers. Thus, each DBR pair includes at least one undoped layer 603. Each DBR pair may include three differently doped layers (e.g., a p-type doped layer, an n-type doped layer, and an undoped (intrinsic) layer arranged between the p-type doped layer and the n-type doped layer).

[0083] There may be other different configurations or schemes. For example, a portion of the high refractive index layer 601, an adjacent portion of the undoped layer 603, and / or the low refractive index layer 602 may be p-type doped (or n-type doped). Additionally, a portion of the undoped layer 603 or a portion of the high refractive index layer 601 (or the low refractive index layer 602) may be undoped. Additionally, the remaining portion of the high refractive index layer 601, an adjacent portion of the undoped layer 603, and / or the low refractive index layer 602 may be n-type doped (or p-type doped), respectively. For example, a portion of the DBR pair #1 or a portion of the DBR pair #1 may be p-type doped (or n-type doped), a portion of the DBR pair #2 or a portion of the DBR pair #2 may be undoped, and a portion of the DBR pair #3 or a portion of the DBR pair #3 may be n-type doped (or p-type doped), respectively. Therefore, adjacent DBR pairs may form a pn junction. In some embodiments, each DBR pair may include one or more pn junctions.

[0084] In some embodiments, the undoped layer 603 can be a gradient layer having an intermediate refractive index value between the high refractive index value of the high refractive index layer 601 and the low refractive index value of the low refractive index layer 602. For example, the undoped layer 603 of DBR pair #1 can have an intermediate refractive index value between the high refractive index value of the high refractive index layer 601 of DBR pair #1 and the low refractive index value of the low refractive index layer 602 of DBR pair #1. Therefore, the undoped layer 603 of DBR pair #1 can provide a gradual semiconductor bandgap change or a step-like semiconductor bandgap change between the high refractive index material and the low refractive index material of DBR pair #1. The undoped layer 603 of DBR pair #2 can have an intermediate refractive index value between the high refractive index value of the high refractive index layer 601 of DBR pair #2 and the low refractive index value of the low refractive index layer 602 of DBR pair #2. Thus, the undoped layer 603 of DBR pair #2 can provide a gradual semiconductor bandgap change or a stepped semiconductor bandgap change between the high refractive index material and the low refractive index material of DBR pair #2. In some embodiments, two or more undoped layers 603 can be provided between the high refractive index layer and the low refractive index layer of the DBR pair. The two or more undoped layers 603 can be gradient layers, each of which has a different intermediate refractive index value between the high refractive index value of the high refractive index layer 601 and the low refractive index value of the low refractive index layer 602, so as to provide a gradual transition or a stepped transition between the high refractive index value of the high refractive index layer 601 and the low refractive index value of the low refractive index layer 602.

[0085] In some embodiments, one or more undoped layers 603 may be provided between adjacent DBR pairs. In some embodiments, one or more undoped layers 603 provided between adjacent DBR pairs may be gradient layers, each of which has a different intermediate refractive index value between a high refractive index value of an adjacent high refractive index layer 601 and a low refractive index value of an adjacent low refractive index layer 602, so as to provide a gradual transition or a stepped transition between a high refractive index value of the high refractive index layer 601 and a low refractive index value of the low refractive index layer 602.

[0086] Due to several identical or similar pin junctions that may also be heterojunctions, the current blocking DBR 600 may deliver excellent current blocking performance.

[0087] Figure 6 are provided as examples. Other examples may differ from those described herein. Figure 6 The content described.

[0088] Figure 7 A current blocking DBR 700 is shown according to one or more embodiments. The current blocking DBR 700 may be implemented as the current blocking DBR 204 of the transmitter 200. The current blocking DBR 700 includes alternating p-type high refractive index layers 701 and n-type low refractive index layers 702. In addition, the current blocking DBR 700 includes an undoped layer 703 (e.g., an intermediate layer or an intrinsic layer) between each pair of high refractive index layers and low refractive index layers. Thus, each DBR pair includes at least one undoped layer 703. Each DBR pair may include three differently doped layers (e.g., a p-type doped layer, an n-type doped layer, and an undoped (intrinsic) layer arranged between the p-type doped layer and the n-type doped layer). The current blocking DBR 700 is similar to the current blocking DBR 600, except that the high refractive index layer 701 is n-doped and the low refractive index layer 702 is p-doped. Additionally, the undoped layer 703 may be a graded layer with an intermediate refractive index value, which may provide a gradual or stepped semiconductor bandgap change between high and low refractive index materials of the alternating stacks of high and low refractive index layers.

[0089] Other different configurations or schemes may exist. For example, a portion of the high refractive index layer, an adjacent portion of the gradient layer and / or a low refractive index layer may be p-type doped (or n-type doped). Additionally, a portion of the gradient layer or a portion of the high refractive index (or low refractive index) layer may be undoped. Additionally, the remainder of the high refractive index layer, an adjacent portion of the gradient layer and / or a low refractive index layer may be n-type doped (or p-type doped), respectively. For example, DBR pair #1 or a portion of DBR pair #1 may be p-type doped (or n-type doped), DBR pair #2 or a portion of DBR pair #2 may be undoped, and DBR pair #3 or a portion of DBR pair #3 may be n-type doped (or p-type doped), respectively.

[0090] Figure 7 are provided as examples. Other examples may differ from those described herein. Figure 7 The content described.

[0091] Figure 8 A current blocking DBR 800 is shown according to one or more embodiments. The current blocking DBR 800 can be implemented as the current blocking DBR 204 of the transmitter 200. The current blocking DBR 800 includes alternating high refractive index layers 801 and low refractive index layers 802. The high refractive index layer 801 can have a high refractive index value n1 (e.g., a maximum or local maximum refractive index value), and the low refractive index layer 802 can have a low refractive index value n4 (e.g., a minimum or local minimum refractive index value), where n1>n4. The high refractive index layer 801 can be p-type doped and the low refractive index layer 802 can be n-type doped, or the high refractive index layer 801 can be n-type doped and the low refractive index layer 802 can be p-type doped. Adjacent and paired high refractive index layers and low refractive index layers can form a DBR pair (e.g., DBR pair #1, ... and DBR pair #N) including two oppositely doped layers. In some embodiments, an intrinsic layer can be arranged between adjacent DBR pairs.

[0092] In addition, each DBR pair (e.g., DBR pair #1, ..., and DBR pair #N) may include two or more gradient layers (e.g., multiple gradient layers), including a first gradient layer 803 (e.g., a high refractive index gradient layer) and a second gradient layer 804 (e.g., a low refractive index gradient layer). One of the first gradient layers 803 may be arranged between the high refractive index layer 801 and the second gradient layer 804 of the corresponding DBR pair. One of the second gradient layers 804 may be arranged between the low refractive index layer 802 and the first gradient layer 803 of the corresponding DBR pair. In some embodiments, the high refractive index layer 801 may be arranged between the two first gradient layers 803, and the low refractive index layer 802 may be arranged between the two second gradient layers 804.

[0093] The first gradient layer 803 may have an intermediate refractive index value n2 (e.g., a first intermediate refractive index value) that is smaller than the high refractive index value n1. The second gradient layer 804 may have an intermediate refractive index value n3 (e.g., a second intermediate refractive index value) that is larger than the low refractive index value n4 and smaller than the intermediate refractive index value n2. Therefore, the refractive index value of the DBR pair may transition between the high refractive index value n1 and the low refractive index value n4 according to the following conditions: n1>n2>n3>n4. The refractive index values ​​n2 and n3 may be referred to as intermediate refractive index values. The gradient layer may provide a gradual or stepped transition between the high refractive index value n1 of the high refractive index layer 801 and the low refractive index value n4 of the low refractive index layer 802. Therefore, the gradient layer of the current blocking DBR 800 may provide a gradual semiconductor bandgap change or a stepped semiconductor bandgap change between the high refractive index material and the low refractive index material of the alternatingly stacked high refractive index layer 801 and the low refractive index layer 802.

[0094] In some embodiments, the first gradient layer 803 and the second gradient layer 804 may be intrinsic layers. Alternatively, in some embodiments, the first gradient layer 803 and the second gradient layer 804 may be doped layers. For example, the first gradient layer 803 may have the same doping type as the high refractive index layer 801, and the second gradient layer 804 may have the same doping type as the low refractive index layer 802. In some embodiments, the second gradient layer 804 and the low refractive index layer 802 may be oppositely doped, and the first gradient layer 803 and the high refractive index layer 801 may be oppositely doped.

[0095] In some embodiments, the low refractive index layer 802 and the second gradient layer 804 of the DBR pair are sublayers of the low refractive index layer. Therefore, the low refractive index layer can be formed by the low refractive index layer 802 and the second gradient layer 804. In other words, the low refractive index layer 802 itself can be a gradient layer. Therefore, each low refractive index layer can include a first plurality of gradient sublayers (e.g., layer 802 and layer 804), and the first plurality of gradient sublayers provide a first transition of refractive index across a low refractive index range (e.g., across a range of n3 to n4). The first plurality of gradient sublayers constituting the low refractive index layer may include three or more gradient layers of different refractive indices. The first plurality of gradient sublayers may have the same doping type. Therefore, the second gradient layer 804 may have the same doping type as the low refractive index layer 802.

[0096] In some embodiments, the high refractive index layer 801 and the first gradient layer 803 of the DBR pair are sublayers of the high refractive index layer. Therefore, the high refractive index layer can be formed by the high refractive index layer 801 and the first gradient layer 803. In other words, the high refractive index layer 801 itself can be a gradient layer. Therefore, each high refractive index layer can include a second plurality of gradient sublayers (e.g., layer 801 and layer 803), and the second plurality of gradient sublayers provide a second transition of refractive index across a high refractive index range (e.g., across the range of n1 to n2). The second plurality of gradient sublayers constituting the high refractive index layer can include three or more gradient layers of different refractive indices. The second plurality of gradient sublayers can have the same doping type. Therefore, the first gradient layer 803 can have the same doping type as the high refractive index layer 801.

[0097] In some embodiments, the first plurality of gradient sublayers may have alternating doping types, and the second plurality of gradient sublayers may have alternating doping types. For example, the second gradient layer 804 and the low refractive index layer 802 may be oppositely doped, and the first gradient layer 803 and the high refractive index layer 801 may be oppositely doped.

[0098] Figure 8 are provided as examples. Other examples may differ from those described herein. Figure 8 The content described.

[0099] Fig. 9 An addressable emitter array 900 is shown in accordance with one or more embodiments. The addressable emitter array 900 may include a plurality of addressable emitters (e.g., addressable VCSEL devices). Thus, the addressable emitter array 900 may be an addressable VCSEL or vertical emitter array. For example, the addressable emitter array 900 may include a plurality of emitters (e.g., a plurality of emitters 200) arranged on a common substrate 902 (e.g., substrate 202). Fig. 9 Two laterally adjacent emitters of addressable emitter array 900 are shown in FIG.

[0100] The addressable emitter array 900 may include a common substrate 902, a first emitter 200a disposed on the common substrate 902, and a second emitter 200b disposed on the common substrate 902. The first emitter 200a and the second emitter 200b are selectively addressable. In some embodiments, the first emitter 200a and the second emitter 200b may be independently enabled and disabled. The first emitter 200a and the second emitter 200b each have a Figures 2 to 8The first emitter 200a may include a first current blocking DBR 204a disposed on the common substrate 902; a first bottom contact layer 206a disposed on the first current blocking DBR 204a and associated with a first current; a first bottom DBR 208a disposed on the first bottom contact layer 206a; a first top DBR 210a disposed on the first bottom DBR 208a; a first active region 212a configured to generate a first laser, wherein the first active region 212a is disposed between the first bottom DBR 208a and the first top DBR 210a; a first oxide layer 214a defining a current limiting aperture 216a; a first top contact layer 218a disposed on the first top DBR 210a and associated with the first current; and a first optical output 220a disposed on the first top DBR 210a, wherein the first emitter 200a is configured to emit a first laser via a first optical output 220a. In addition, the first emitter 200a may include a contact pad 904a in electrical contact with the first bottom contact layer 206a. The first current blocking DBR 204a includes a first plurality of pn junctions connected in series vertically to form a first bidirectional current blocking structure. In addition, the first current blocking DBR 204a is a first optical reflector configured to reflect a portion of the first laser generated by the first active region 212a toward the first optical output 220a.

[0101] The second emitter 200b may include: a second current blocking DBR 204b, which is arranged on the common substrate 902; a second bottom contact layer 206b, which is arranged on the second current blocking DBR 204b and is associated with a second current; a second bottom DBR 208b, which is arranged on the second bottom contact layer 206b; a second top DBR 210b, which is arranged on the second bottom DBR 208b; a second active region 212b, which is configured to generate a second laser, wherein the second active region 212b is arranged between the second bottom DBR 208b and the second top DBR 210b; a second oxide layer 214b, which defines a current limiting aperture 216b; a second top contact layer 218b, which is arranged on the second top DBR 210b and is associated with the second current; and a second optical output 220b, which is arranged on the second top DBR 210b, wherein the second emitter 200b is configured to emit a second laser via a second optical output 220b. In addition, the second emitter 200b may include a contact pad 904b that is electrically in contact with the second bottom contact layer 206b. The second current blocking DBR 204b includes a second plurality of pn junctions connected vertically in series to form a second bidirectional current blocking structure. In addition, the second current blocking DBR 204b is a second optical reflector configured to reflect a portion of the second laser generated by the second active region 212b toward the second optical output 220b.

[0102] The first emitter 200a and the second emitter 200b may be at least partially separated by a vertical trench 906. The vertical trench 906 may extend vertically downward from the uppermost layers of the first emitter 200a and the second emitter 200b to at least the first bottom contact layer 206a and the second bottom contact layer 206b. Thus, the vertical trench 906 may provide lateral separation and electrical isolation between the first emitter 200a and the second emitter 200b.

[0103] In addition, the addressable emitter array 900 may include a vertical isolation region between each laterally adjacent emitter. The vertical isolation region may extend vertically through the bottom contact buffer layer and the current blocking DBR to the common substrate 902. For example, the addressable emitter array 900 may include an isolation region 908 configured to electrically isolate the first emitter 200a and the second emitter 200b. The isolation region 908 may be laterally disposed between the first bottom contact layer 206a and the second bottom contact layer 206b, and laterally disposed between the first current blocking DBR 204a and the second current blocking DBR 204b.

[0104] The first bottom contact layer 206a and the second bottom contact layer 206b may be formed by a contact buffer layer. In other words, the first bottom contact layer 206a and the second bottom contact layer 206b may be formed by a common contact layer. In addition, the first current blocking DBR 204a and the second current blocking DBR 204b may be formed by a common current blocking DBR. The isolation region 908 may be an injection isolation region formed by injection, which vertically extends through the contact buffer layer and the common current blocking DBR to the common substrate 902 or partially extends into the common substrate 902 so as to electrically isolate the first bottom contact layer 206a and the second bottom contact layer 206b. Therefore, the isolation region 908 may prevent current leakage between the first emitter 200a and the second emitter 200b. In addition, the first current blocking DBR 204a may electrically isolate the common substrate 902 from the first bottom contact layer 206a, and the second current blocking DBR 204b may electrically isolate the common substrate 902 from the second bottom contact layer 206b. Thus, the first current blocking DBR 204a, the second current blocking DBR 204b, and the isolation region 908 may provide electrical isolation between the first transmitter 200a and the second transmitter 200b.

[0105] The addressable emitter array 900 can be an array of emitter stripes or a matrix addressable array. A matrix addressable array can be configured for two-dimensional (grid-type) addressing. Alternatively, more complex addressing of current or voltage can be used, including sub-array addressing or addressing a specific pattern / distribution of emitters.

[0106] For a top emitting matrix addressable VCSEL array, in addition to separating the top contact layer, it may be necessary to add vertical isolation in the current blocking DBR to separate the bottom contact layer between different emitters or sub-arrays. For example, to electrically isolate two emitters or two sub-arrays, the addressable emitter array 900 may include an implant isolation region to electrically isolate the bottom contact layers of laterally adjacent emitters. The depth of the implant isolation region may extend downward through a portion of the common current blocking DBR, or further downward onto or into the common substrate 902. To make electrical contact with the bottom contact layer, a trench or moat may be etched to expose the bottom contact buffer layer.

[0107] In some embodiments, there may be additional passivation / isolation layers such as SiOx, SiNx, atomic layer deposition (ALD) layers, polymers, polyamides, and / or another type of dielectric or ceramic material on and / or between the cathode and anode.

[0108] In addition, one or more aspects may be included in the above embodiments, including: (1) the multi-junction VCSEL described in the context of this article can have one, two, three or more junctions; (2) the electrical polarity of the VCSEL from top to bottom can be a pin structure or a nip structure. The top semiconductor contact or cap can be a p-type semiconductor or an n-type semiconductor. In addition, by using a tunnel junction, all or part of the p-DBR can be replaced by an n-DBR, and vice versa; (3) the oxide-limited VCSEL can have one, two or more oxide layers on the p-side or n-side; (4) using the optical aperture layer in the VCSEL as current and mode confinement is optional and can be replaced by different approaches (such as implant passivation, mesa or trench isolation or buried tunnel junction); (5) the substrate can be a GaAs, InP, InGaAs, GaSb, Si, Ge, GaP, GaN, ZnO or sapphire substrate, which is used to grow an epitaxial structure on the top. The substrate can be n-type, p-type, semi-insulating, insulating or conductive. Even when epitaxy is used on a semi-insulating substrate or an insulating substrate, the above-described embodiments may improve electrical isolation, for example, in cases where the vertical isolation regions do not extend completely down to the substrate.

[0109] In some embodiments, a buffer layer can be arranged on the substrate 902, vertically arranged between the substrate 902 and the common current blocking DBR. For example, a thin buffer layer of GaAs can be grown on the substrate 902 (e.g., a GaAs substrate) to provide a clean surface to start growing the DBR layer of the common current blocking DBR. The thin buffer layer can be undoped or lowly doped to provide high resistance. The isolation region 908 can extend at least to the buffer layer. For example, the isolation region 908 can extend to the buffer layer, partially extend through the buffer layer, or completely extend through the buffer layer to the substrate 902. The substrate 902 can be a high resistance substrate that provides electrical isolation between the emitters in the addressable emitter array 900.

[0110] Fig. 9 are provided as examples. Other examples may differ from those described herein. Fig. 9 The content described.

[0111] Fig.10An addressable emitter array 1000 is shown in accordance with one or more embodiments. The addressable emitter array 1000 is similar to the addressable emitter array 900, except that the isolation region 908 is an isolation trench, which can be an extension of the vertical trench 906. The isolation trench can extend vertically through the contact buffer layer and the common current blocking DBR to separate the first bottom contact layer 206a and the second bottom contact layer 206b, and to separate the first current blocking DBR 204a and the second current blocking DBR 204b. The isolation trench can extend vertically to the common substrate 902 or partially extend into the common substrate 902 to electrically isolate the first bottom contact layer 206a and the second bottom contact layer 206b.

[0112] Therefore, the isolation region 908 can prevent current leakage between the first emitter 200a and the second emitter 200b. In addition, the first current blocking DBR 204a can electrically isolate the common substrate 902 from the first bottom contact layer 206a, and the second current blocking DBR 204b can electrically isolate the common substrate 902 from the second bottom contact layer 206b. Therefore, the first current blocking DBR 204a, the second current blocking DBR 204b and the isolation region 908 can provide electrical isolation between the first emitter 200a and the second emitter 200b.

[0113] In some embodiments, a buffer layer can be arranged on the substrate 902, arranged vertically between the substrate 902 and the common current blocking DBR. For example, a thin buffer layer of GaAs can be grown on a GaAs substrate to provide a clean surface to start growing the DBR layer of the common current blocking DBR. The thin buffer layer can be undoped or lowly doped to provide high resistance. The isolation region 908 can extend at least to the buffer layer. For example, the isolation region 908 can extend to the buffer layer, partially extend through the buffer layer, or completely extend through the buffer layer to the substrate 902. The substrate 902 can be a high resistance substrate that provides electrical isolation between the emitters in the addressable emitter array 1000.

[0114] Fig.10 are provided as examples. Other examples may differ from those described herein. Fig.10 The content described.

[0115] Fig.11 is a flow chart of an example process 1100 associated with a vertical cavity surface emitting laser device. In some embodiments, the method / process (including epitaxy and wafer fabrication) is performed Fig.11 In some embodiments, one or more process blocks of the present invention are used to form an electrically isolated VCSEL or vertical emitter array having a current blocking DBR and having a vertical isolation region (e.g., implant isolation or trench isolation). Fig.11One or more process blocks of are performed by a device, a group of devices, or one or more manufacturing systems.

[0116] like Fig.11 As shown, process 1100 may include: forming a current blocking DBR on a substrate (block 1110). As described above, the current blocking DBR may include a plurality of pn junctions connected vertically in series to form a bidirectional current blocking structure.

[0117] like Fig.11 As further shown, process 1100 may include forming a bottom contact layer on the current blocking DBR (block 1120). As described above, the current blocking DBR may electrically isolate the substrate from the bottom contact layer.

[0118] like Fig.11 As further shown, process 1100 may include forming a bottom DBR on the bottom contact layer (block 1130 ).

[0119] like Fig.11 As further shown, process 1100 may include forming an active region on the bottom DBR (block 1140). As described above, the active region may be configured to generate lasing.

[0120] like Fig.11 As further shown, process 1100 may include forming a top DBR on the active area (block 1150 ).

[0121] like Fig.11 As further shown, process 1100 may include forming a top contact layer on the top DBR (block 1160).

[0122] like Fig.11 As further shown, process 1100 may include forming an optical output above the top DBR (block 1170). As described above, the optical output may be configured to emit laser light from an emitter.

[0123] When forming an addressable emitter array (such as addressable emitter array 900 or addressable emitter array 1000), process 1100 can be performed for each emitter. In addition, as described above, process 1100 can include forming vertical trenches (e.g., vertical trenches 906) between adjacent emitters. In addition, as described above, process 1100 can include forming isolation regions (e.g., isolation regions 908) between adjacent emitters.

[0124] Process 1100 may include additional implementations, such as any single implementation or any combination of implementations described below and / or in combination with one or more other processes described elsewhere herein.

[0125] although Fig.11An example block diagram of process 1100 is shown, but in some implementations, process 1100 includes Fig.11 The depicted blocks may be more blocks, fewer blocks, different blocks than the depicted blocks, or blocks arranged in a different manner. Additionally or alternatively, two or more of the blocks of process 1100 may be performed in parallel.

[0126] The foregoing disclosure provides illustrations and descriptions, but is not intended to be exhaustive or to limit the embodiments to the precise forms disclosed. Modifications and variations may be made in light of the foregoing disclosure, or these modifications and variations may be obtained from the practice of the embodiments. In addition, unless the foregoing disclosure explicitly provides a reason why one or more embodiments may not be combined, any embodiment described herein may be combined.

[0127] It is apparent that the systems and / or methods described herein may be implemented in various forms of hardware, firmware, or a combination of hardware and software. The actual dedicated control hardware or software code used to implement these systems and / or methods does not limit these implementations. Therefore, the operation and behavior of the systems and / or methods are described herein without reference to specific software code - it should be understood that software and hardware can be designed to implement the systems and / or methods based on the description herein.

[0128] Even though specific combinations of features are referenced in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of the various embodiments. In fact, many of these features may be combined in ways that are not explicitly referenced in the claims and / or disclosed in the specification. Although each dependent claim listed below may only directly depend on one claim, the disclosure of the various embodiments includes each dependent claim in combination with each other claim in the claim set. As used herein, a phrase referring to "at least one" in a list of items refers to any combination of these items, including single members. As an example, "at least one of a, b, or c" is intended to cover any combination of a, b, c, ab, ac, bc, and abc, as well as multiple identical items.

[0129] When a component or one or more components (e.g., a laser emitter or one or more laser emitters) is described or claimed (either within a single claim or across multiple claims) as performing multiple operations or being configured to perform multiple operations, such language is intended to broadly cover a variety of architectures and environments. For example, unless otherwise expressly stated (e.g., via the use of "first component" and "second component" or other language in the claim that distinguishes components), such language is intended to cover a single component that performs or is configured to perform all operations, a group of components that collectively perform or are configured to perform all operations, a first component that performs or is configured to perform a first operation and a second component that performs or is configured to perform a second operation, or any combination of components that perform or are configured to perform operations. For example, when a claim is of the form: "One or more components are configured to: perform X; perform Y; and perform Z," the claim should be interpreted as "One or more components are configured to perform X; one or more (possibly different) components are configured to perform Y; and one or more (possibly different) components are configured to perform Z."

[0130] Unless clearly described as such, any element, action or instruction used herein should not be interpreted as critical or necessary. In addition, as used herein, the articles "one" and "an" are intended to include one or more items, and can be used interchangeably with "one or more". In addition, as used herein, the article "the" is intended to include one or more items related to the article "the", and can be used interchangeably with "one or more". In addition, as used herein, the term "set" is intended to include one or more items (such as related items, unrelated items or a combination of related items and unrelated items), and can be used interchangeably with "one or more". If only one item is intended to be used, phrase "only one" or similar language is used. In addition, as used herein, the term "has", "have", "containing (having)" etc. are intended to be open terms. In addition, unless otherwise expressly stated, the phrase "based on" is intended to represent "based at least in part". In addition, as used herein, unless otherwise expressly stated (e.g., when used in conjunction with "any one of" or "only one of"), the term "or" when used in series is intended to be inclusive and may be used interchangeably with "and / or". In addition, for ease of description, spatially relative terms such as "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or feature to another (or more) element(s) or feature(s) as illustrated in the figures. In addition to the orientations depicted in the figures, spatially relative terms are intended to cover different orientations of devices, equipment, and / or elements in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Claims

1. A transmitter, comprising: substrate; a current-blocking distributed Bragg reflector DBR disposed on the substrate, wherein the current-blocking DBR comprises a plurality of pn junctions connected in series vertically to form a bidirectional current-blocking structure; A bottom contact layer is disposed on the current blocking DBR; a bottom DBR disposed on the bottom contact layer; a top DBR disposed on the bottom DBR; an active region configured to generate laser light, wherein the active region is disposed between the bottom DBR and the top DBR; A top contact layer disposed on the top DBR; as well as An optical output is disposed above the top DBR, wherein the emitter is configured to emit the laser light via the optical output. 2 . The transmitter of claim 1 , wherein the current blocking DBR is configured to electrically isolate the substrate from the bottom contact layer.

3. The transmitter of claim 1, wherein the current blocking DBR is an optical reflector configured to reflect a portion of the laser light generated by the active region toward the optical output. The emitter of claim 1 , wherein the plurality of pn junctions comprises a plurality of pin junctions.

5. The emitter according to claim 1, wherein the current blocking DBR comprises a plurality of alternatingly stacked high refractive index layers and low refractive index layers, The high refractive index layer is p-type doped and the low refractive index layer is n-type doped, or the high refractive index layer is n-type doped and the low refractive index layer is p-type doped.

6. The transmitter of claim 5, wherein the current blocking DBR comprises a plurality of gradient layers, wherein each of the plurality of gradient layers is arranged between respective pairs of high refractive index layers and low refractive index layers of the current blocking DBR, and Each of the plurality of gradient layers has a corresponding intermediate refractive index value between the high refractive index value and the low refractive index value of the respective pair of high refractive index layer and low refractive index layer.

7. The emitter of claim 5, wherein the current blocking DBR comprises a plurality of gradient layers providing a gradual semiconductor bandgap change or a stepped semiconductor bandgap change between high refractive index materials and low refractive index materials of the alternatingly stacked high refractive index layers and low refractive index layers.

8. The emitter of claim 5, wherein a first portion of each high refractive index layer is p-type doped and a second portion of each high refractive index layer is n-type doped such that the plurality of pn junctions are formed with the low refractive index layer.

9. The emitter of claim 5, wherein a first portion of each low refractive index layer is p-type doped and a second portion of each low refractive index layer is n-type doped such that the plurality of pn junctions are formed with the high refractive index layer.

10. The transmitter of claim 5, wherein the current blocking DBR comprises a plurality of intrinsic layers, Each of the plurality of intrinsic layers is arranged between a respective pair of p-type doped layers and n-type doped layers of the current blocking DBR.

11. The emitter of claim 10, wherein each of the plurality of intrinsic layers is part of a corresponding high refractive index layer of the current blocking DBR or is part of a corresponding low refractive index layer of the current blocking DBR.

12. The emitter of claim 1, wherein the current blocking DBR comprises a plurality of alternatingly stacked high refractive index layers and low refractive index layers, wherein each low refractive index layer comprises a first plurality of gradient sub-layers providing a first transition of refractive index across the low refractive index range, and Each high refractive index layer comprises a second plurality of gradient sub-layers providing a second transition of refractive index across the high refractive index range.

13. The emitter of claim 12, wherein the high refractive index layer is p-type doped and the low refractive index layer is n-type doped, or the high refractive index layer is n-type doped and the low refractive index layer is p-type doped.

14. The emitter of claim 1, wherein the current blocking DBR comprises a plurality of alternatingly stacked high refractive index layers and low refractive index layers, wherein the plurality of alternately stacked high refractive index layers and low refractive index layers form a plurality of DBR pairs, Each DBR pair includes a respective adjacent and paired high refractive index layer and low refractive index layer, and The plurality of DBR pairs are alternately p-type doped and n-type doped to form the plurality of pn junctions.

15. The emitter of claim 14, wherein each DBR pair comprises an intrinsic layer disposed between respective adjacent pairs of high and low refractive index layers.

16. A transmitter array comprising: substrate; A first emitter is arranged on the substrate, wherein the first emitter comprises: a first current-blocking distributed Bragg reflector DBR disposed on the substrate, wherein the first current-blocking DBR comprises a first plurality of pn junctions connected vertically in series to form a first bidirectional current-blocking structure; a first bottom contact layer disposed on the first current blocking DBR and associated with a first current; a first bottom DBR disposed on the first bottom contact layer; a first top DBR disposed on the first bottom DBR; a first active region configured to generate a first laser, wherein the first active region is disposed between the first bottom DBR and the first top DBR; a first top contact layer disposed on the first top DBR and associated with a first current; and a first optical output disposed above the first top DBR, wherein the first emitter is configured to emit the first laser light via the first optical output; a second emitter disposed on the substrate, wherein the second emitter is adjacent to the first emitter, and wherein the second emitter comprises: a second current blocking DBR disposed on the substrate, wherein the second current blocking DBR comprises a second plurality of pn junctions connected vertically in series to form a second bidirectional current blocking structure; a second bottom contact layer disposed on the second current blocking DBR and associated with a second current; a second bottom DBR disposed on the second bottom contact layer; a second top DBR disposed on the second bottom DBR; a second active region configured to generate a second laser, wherein the second active region is disposed between the second bottom DBR and the second top DBR; a second top contact layer disposed on the second top DBR and associated with the second current; and a second optical output disposed above the second top DBR, wherein the second emitter is configured to emit the second laser light via the second optical output; and An isolation region is configured to electrically isolate the first emitter from the second emitter, wherein the isolation region is laterally disposed between the first bottom contact layer and the second bottom contact layer and laterally disposed between the first current blocking DBR and the second current blocking DBR.

17. The emitter array of claim 16, wherein the first bottom contact layer and the second bottom contact layer are formed of a contact buffer layer, and The isolation region is an isolation trench that vertically extends through the contact buffer layer to separate the first bottom contact layer and the second bottom contact layer, and The isolation trench vertically extends to the substrate or partially extends into the substrate so as to electrically isolate the first bottom contact layer from the second bottom contact layer.

18. The emitter array of claim 16, wherein the first bottom contact layer and the second bottom contact layer are formed of a contact buffer layer, wherein the first current blocking DBR and the second current blocking DBR are formed by a common current blocking DBR, and The isolation region is an injection isolation region, which vertically extends through the contact buffer layer and the common current blocking DBR to the substrate or partially extends into the substrate so as to electrically isolate the first bottom contact layer from the second bottom contact layer.

19. The emitter array of claim 16, wherein the isolation region is configured to electrically isolate the first bottom contact layer from the second bottom contact layer.

20. The emitter array of claim 16, wherein the first current blocking DBR is configured to electrically isolate the substrate from the first bottom contact layer, and The second current blocking DBR is configured to electrically isolate the substrate from the second bottom contact layer.

21. The emitter array of claim 16, wherein the first current blocking DBR is a first optical reflector configured to reflect a portion of the first laser light generated by the first active region toward the first optical output, and Wherein the second current blocking DBR is a second optical reflector configured to reflect a portion of the second laser light generated by the second active region toward the second optical output.

22. The emitter array of claim 16, wherein the first emitter and the second emitter are selectively addressable.

23. A method of manufacturing a transmitter, the method comprising: forming a current-blocking distributed Bragg reflector (DBR) on a substrate, wherein the current-blocking DBR comprises a plurality of pn junctions connected in series vertically to form a bidirectional current-blocking structure; forming a bottom contact layer on the current blocking DBR, wherein the current blocking DBR is configured to electrically isolate the substrate from the bottom contact layer; forming a bottom DBR on the bottom contact layer; forming an active region on the bottom DBR, wherein the active region is configured to generate lasing; forming a top DBR on the active area; forming a top contact layer on the top DBR; as well as An optical output is formed over the top DBR, wherein the optical output is configured to emit the laser light from the emitter.

Images