Gallium nitride transistor and gallium arsenide VCSEL heterogeneous three-dimensional integrated device structure and manufacturing method

Abstract

The invention discloses a gallium nitride transistor and gallium arsenide VCSEL heterogeneous three-dimensional integrated device structure and a manufacturing method, and belongs to the technical field of semiconductors. The device structure comprises bottom layer metal, an N-face reflector, a VCSEL light-emitting region, a P-face reflector, VCSEL bonding metal, gallium nitride device bonding metal, a gallium nitride substrate layer, a gallium nitride epitaxial layer, a metal through hole, a gallium nitride transistor electrode source electrode, a gallium nitride transistor electrode grid electrode and a gallium nitride transistor electrode drain electrode from bottom to top. According to the device, three-dimensional heterogeneous vertical integration is realized based on metal bonding, so that a gallium nitride device and gallium arsenide VCSEL three-dimensional integrated material structure and a device structure are obtained, and a feasible preparation method is provided.

Description

Technical Field

[0001] The invention relates to a gallium nitride transistor and gallium arsenide VCSEL heterogeneous three-dimensional integrated device structure and a manufacturing method, belonging to the technical field of semiconductors. Background Art

[0002] Gallium arsenide VCSEL (Vertical-Cavity Surface-Emitting Laser) is a new generation of semiconductor laser. The laser forms a resonant cavity in the vertical direction of the substrate and emits laser in the vertical direction. It has the characteristics of small temperature drift, low threshold, easy coupling with optical fiber, low power consumption, and good dynamic single-mode performance. It is widely used in optical communication, optical storage, optical interconnection and other fields, and is suitable for various application scenarios such as vehicle-mounted lidar, face recognition, 3D sensing, etc.

[0003] In recent years, with the rapid development of technologies such as 5G networks, the Internet, and AR / VR, we have entered an information age centered on big data and the Internet of Everything.

[0004] Therefore, people's demand for information transmission speed and communication capacity is increasing.

[0005] Optical interconnection technology using optical fiber as transmission link is becoming more and more mature and is rapidly occupying a large market share.

[0006] As a third-generation semiconductor, gallium nitride has excellent properties such as large bandgap, high electron mobility, and high electron saturation velocity. It has broad application potential in the fields of next-generation radio frequency devices, power electrical devices, etc.

[0007] Gallium nitride-based devices have the characteristics of high breakdown voltage, high efficiency, high switching frequency and short switching time, while gallium arsenide-based devices have advantages in realizing red light, infrared LEDs, lasers, etc.

[0008] Therefore, if high-density micro-nano heterogeneous integration of GaN-driven and GaAs-luminescent chips can be achieved, it will be of great significance for the development of optoelectronic equipment systems such as high-end displays, lidars, optical communication modules, etc. with more functions, smaller size and higher performance.

[0009] However, there are still many difficulties in terms of material compatibility, process compatibility, etc.

[0010] Based on the above-mentioned deficiencies, a gallium nitride transistor and gallium arsenide VCSEL heterogeneous three-dimensional integrated device structure and a manufacturing method are needed to improve the above-mentioned deficiencies. Summary of the invention

[0011] The main purpose of the present invention is to provide a gallium nitride transistor and gallium arsenide VCSEL heterogeneous three-dimensional integrated device structure and a manufacturing method.

[0012] The purpose of the present invention can be achieved by adopting the following technical solutions:

[0013] A gallium nitride transistor and gallium arsenide VCSEL heterogeneous three-dimensional integrated device structure and a manufacturing method. The device structure comprises, from bottom to top, gallium arsenide VCSEL N-electrode metal, gallium arsenide VCSEL N-pole reflector, gallium arsenide VCSEL light-emitting area, gallium arsenide VCSEL P-pole reflector, gallium arsenide VCSEL P-electrode metal, gallium arsenide VCSEL bonding metal, gallium nitride device bonding metal, gallium nitride device back and through-hole metal, gallium nitride substrate layer, gallium nitride epitaxial layer, metal through-hole, gallium nitride transistor electrode source, gallium nitride transistor electrode gate and gallium nitride transistor electrode drain.

[0014] The GaAs VCSEL N-electrode metal, GaAs VCSEL N-pole reflector, GaAs VCSEL light-emitting area, GaAs VCSEL P-pole reflector, GaAs VCSEL P-electrode metal, and GaAs VCSEL bonding metal constitute the GaAs VCSEL device. The GaAs VCSEL light-emitting area realizes photon lasing, and the light beam is emitted from the back.

[0015] The gallium nitride device bonding metal, the back side and through-hole metal of the gallium nitride device, the gallium nitride substrate layer, the gallium nitride epitaxial layer, the metal through-hole, the gallium nitride transistor electrode source, the gallium nitride transistor electrode gate and the gallium nitride transistor electrode drain constitute a gallium nitride transistor. The gallium nitride epitaxial layer is a group III nitride material and can be one or a combination of several of GaN, AlN and InN. A conductive channel is formed in the gallium nitride epitaxial layer and is regulated by the gallium nitride transistor electrode gate. When working, the current flows from the gallium nitride transistor electrode drain to the gallium nitride transistor electrode source.

[0016] GaN transistor and GaAs VCSEL; through metal bonding, three-dimensional vertical integration is achieved. The current flows from the GaN transistor electrode drain, through the GaN transistor electrode source, the GaN device back and through-hole metal, the GaN device bonding metal, the GaAs VCSEL P-electrode metal, and the GaAs VCSEL bonding metal to the GaAs VCSEL P-pole reflector, providing holes to the GaAs VCSEL light-emitting area and electrons provided by the GaAs VCSEL N-electrode metal for composite light emission, thereby achieving the regulation of the GaN transistor electrode gate on the GaAs VCSEL light emission.

[0017] This structure can use the characteristics of high breakdown voltage, high efficiency, high switching frequency and short switching time of GaN transistors to provide drive for GaAs VCSEL. The proposed integration scheme enables GaN transistors and GaAs VCSELs to have a smaller spatial spacing, reduce chip volume, reduce chip weight, and improve chip integration; reduce the loss of long-distance package transmission signals at high frequencies and the influence of parasitic parameters such as inductance, improve the high-frequency performance of the system; reduce the package shell and package leads in the traditional scheme, and reduce the cost of the entire system.

[0018] Preferably, the gallium nitride substrate may be absent, and the back side of the gallium nitride device is in direct contact with the through-hole metal and the gallium nitride epitaxial layer;

[0019] Preferably, the material of the gallium nitride substrate can be one of silicon carbide, silicon, and sapphire substrates, with a thickness of 100-1500 μm; the material of the gallium nitride device epitaxial layer is a group III nitride semiconductor material, which is a compound formed by one or more of gallium nitride, aluminum nitride, and indium nitride. The gallium nitride device epitaxial layer includes a nitride nucleation layer, a nitride transition layer, a nitride buffer layer, a nitride channel layer, and a nitride barrier layer. The material of the nitride nucleation layer is aluminum nitride with a thickness of 50-300nm; the material of the nitride transition layer is graded aluminum gallium nitride, or aluminum nitride / aluminum gallium nitride superlattice, with a thickness of 500-1000nm; the material of the nitride buffer layer is gallium nitride with a thickness of 100-1000nm; the material of the nitride channel layer is gallium nitride, or indium gallium nitride, or aluminum gallium nitride, with a thickness of 50-500nm; the material of the nitride barrier layer is aluminum gallium nitride, or indium aluminum nitride, with a thickness of 5-30nm. A two-dimensional electron gas is formed between the nitride channel layer and the nitride barrier layer as a conductive channel of the gallium nitride radio frequency device.

[0020] Preferably, the bottom layer of the material of the gallium nitride transistor electrode gate is Ni, or Ti, or TiN, or TaN, and the second layer or the material above the second layer is one or more of Al, Au, Ti, Ta, Pt, TiN, TaN, W, and Cu.

[0021] The bottom two layers of the material of the source electrode of the gallium nitride transistor are Ti, Al, or Ta, Al, or Mo, Al from bottom to top; the metals of other layers include one or more of Ti, Al, Ni, Au, Mo, Pt, and W.

[0022] The bottom two layers of the material of the GaN transistor electrode drain are Ti, Al, or Ta, Al, or Mo, Al from bottom to top; the metals of other layers include one or more of Ti, Al, Ni, Au, Mo, Pt, and W.

[0023] The back side and through hole metals of the gallium nitride device are Ti, Cu, Au, or W.

[0024] Preferably, a layer of the GaAs VCSEL N-electrode metal material contacting the N-type arsenide material is Ni or Mo, and the other layers of materials are Ge, Au, Ni or a combination of several of them.

[0025] The GaAs VCSEL P-electrode metal material has a layer of Ti in contact with the P-type arsenide material, and the other layers of materials are one or a combination of Pt, Au, and Zn.

[0026] The material of the GaAs VCSEL bonding metal and the GaN device bonding metal is one or a combination of Ti, Ni, Au, Cu, etc.;

[0027] Preferably, the GaAs VCSEL N-pole reflector and the GaAs VCSEL P-pole reflector adopt a distributed Bragg reflector (DBR), the material of which is one or several periodic material structures of multiple pairs of AlAs / GaAs, AlGaAs / GaAs, AlGaAs / InGaP, and AlAs;

[0028] Preferably, the VCSEL light emitting region includes an active region and an electrical confinement layer; the active region comprises a quantum well component.

[0029] Preferably, a gallium nitride transistor and gallium arsenide VCSEL heterogeneous three-dimensional integrated device structure and a manufacturing method include the following steps:

[0030] Step S1: Select a GaAs epitaxial wafer to prepare a GaAs VCSEL;

[0031] Step S2: selecting a gallium nitride epitaxial wafer and preparing a gallium nitride transistor, including substrate thinning, metal through-hole preparation, and back and through-hole metal preparation of the gallium nitride device;

[0032] Step S3: depositing GaAs VCSEL bonding metal and GaN device bonding metal on the GaAs VCSELP electrode metal and on the back side of the GaN device and the through-hole metal respectively;

[0033] Step S4: the gallium nitride transistor and the gallium arsenide VCSEL are metal-bonded by using the gallium arsenide VCSEL bonding metal and the gallium nitride device bonding metal.

[0034] Beneficial technical effects of the present invention:

[0035] The present invention provides a gallium nitride transistor and gallium arsenide VCSEL heterogeneous three-dimensional integrated device structure and a manufacturing method.

[0036] 1. Using the characteristics of high breakdown voltage, high efficiency, high switching frequency and short switching time of GaN transistors, it can provide drive for GaAs VCSELs to meet the requirements of high laser modulation rate in some application scenarios such as LiDAR;

[0037] 2. The proposed integration scheme enables GaN transistors and GaAs VCSELs to have a smaller spatial spacing, reducing chip volume, reducing chip weight, and improving chip integration;

[0038] 3. Reduce the loss of long-distance package image transmission signals at high frequencies and the influence of parasitic parameters such as inductance, thereby improving the high-frequency performance of the system;

[0039] 4. The package tube shell and package leads in the traditional solution are reduced, reducing the cost of the entire system. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 It is a schematic structural diagram (cross-sectional view) of a device of heterogeneous vertical integration of a gallium nitride device and a gallium arsenide VCSEL provided in Example 1 of the present invention;

[0041] Figure 2 A schematic flow chart of a method for manufacturing a device for heterogeneous vertical integration of a gallium nitride device and a gallium arsenide VCSEL provided in an embodiment of the present invention.

[0042] In the figure: 2. GaAs VCSEL N-pole reflector; 3. GaAs VCSEL light-emitting area; 4. GaAs VCSEL P-pole reflector; 5. GaAs VCSEL bonding metal; 6. GaN device bonding metal; 7. GaN substrate layer; 8. GaN epitaxial layer; 10. Metal via; 11. GaAs VCSEL N-electrode metal; 12. GaAs VCSEL N-electrode metal; 41. GaAs VCSEL P-electrode metal; 9. GaN device back and via metal; 91. GaN transistor electrode source; 92. GaN transistor electrode gate; 93. GaN transistor electrode drain. DETAILED DESCRIPTION

[0043] In order to make the technical solution of the present invention more clear and specific to those skilled in the art, the present invention is further described in detail below in conjunction with embodiments and drawings, but the implementation manner of the present invention is not limited thereto.

[0044] like Figure 1 - Figure 2As shown, the present embodiment provides a gallium nitride transistor and gallium arsenide VCSEL heterogeneous three-dimensional integrated device structure and a manufacturing method, wherein the device structure includes, from bottom to top: gallium arsenide VCSEL N-electrode metals 11, 12, gallium arsenide VCSEL N-pole reflector 2, gallium arsenide VCSEL light-emitting area 3, gallium arsenide VCSEL P-pole reflector 4, gallium arsenide VCSELP electrode metal 41, gallium arsenide VCSEL bonding metal 5, gallium nitride device bonding metal 6, gallium nitride device back and through-hole metal 9, gallium nitride substrate layer 7, gallium nitride epitaxial layer 8, metal through-hole 10, gallium nitride transistor electrode source 91, gallium nitride transistor electrode gate 92 and gallium nitride transistor electrode drain 93.

[0045] GaAs VCSEL N-electrode metal 1112, GaAs VCSEL N-pole reflector 2, GaAs VCSEL light-emitting area 3, GaAs VCSEL P-pole reflector 4, GaAs VCSEL P-electrode metal 41, and GaAs VCSEL bonding metal 5 constitute a GaAs VCSEL device. The GaAs VCSEL light-emitting area realizes photon lasing, and the light beam is emitted from the back.

[0046] The gallium nitride device bonding metal 6, the gallium nitride device back and through-hole metal 9, the gallium nitride substrate layer 7, the gallium nitride epitaxial layer 8, the metal through-hole 10, the gallium nitride transistor electrode source 91, the gallium nitride transistor electrode gate 92 and the gallium nitride transistor electrode drain 93 constitute a gallium nitride transistor, and the gallium nitride epitaxial layer 8 is a group III nitride material, which can be one or a combination of GaN, AlN and InN;

[0047] A conductive channel is formed in the GaN epitaxial layer 8 and is regulated by the GaN transistor electrode gate 92 . During operation, current flows from the GaN transistor electrode drain 93 to the GaN transistor electrode source 91 .

[0048] GaN transistor and GaAs VCSEL: Three-dimensional vertical integration is achieved by metal bonding. Current flows from GaN transistor electrode drain 93, through GaN transistor electrode source 91, GaN device back and through-hole metal 9, GaN device bonding metal 6, GaAs VCSEL P-electrode metal 41, GaAs VCSEL bonding metal 5 to GaAs VCSEL P-pole reflector 4, providing holes to GaAs VCSEL light-emitting area 3, and electrons provided by GaAs VCSEL N-electrode metal 11, 12 for combined light emission. GaN transistor electrode gate 92 is used to control the light emission of GaAs VCSEL.

[0049] This structure can utilize the characteristics of high breakdown voltage, high efficiency, high switching frequency and short switching time of GaN transistors to provide drive for GaAs VCSEL. The proposed integration scheme enables GaN transistors and GaAs VCSELs to have a smaller spatial spacing, reduce chip volume, reduce chip weight, and improve chip integration; reduce the loss of long-distance package impression transmission signals at high frequencies and the influence of parasitic parameters such as inductance, thereby improving the high-frequency performance of the system; reduce the package shell and package leads in the traditional scheme, thereby reducing the cost of the entire system.

[0050] The gallium nitride substrate 7 may be absent, and the back side of the gallium nitride device is in direct contact with the through-hole metal 9 and the gallium nitride epitaxial layer 8;

[0051] The material of the gallium nitride substrate 7 can be one of silicon carbide, silicon, and sapphire substrates, with a thickness of 100-1500 μm; the material of the gallium nitride device epitaxial layer 8 is a group III nitride semiconductor material, which is a compound formed by one or more of gallium nitride, aluminum nitride, and indium nitride. The gallium nitride device epitaxial layer 3 includes a nitride nucleation layer, a nitride transition layer, a nitride buffer layer, a nitride channel layer, and a nitride barrier layer. The material of the nitride nucleation layer is aluminum nitride with a thickness of 50-300nm; the material of the nitride transition layer is graded aluminum gallium nitride, or aluminum nitride / aluminum gallium nitride superlattice, with a thickness of 500-1000nm; the material of the nitride buffer layer is gallium nitride with a thickness of 100-1000nm; the material of the nitride channel layer is gallium nitride, or indium gallium nitride, or aluminum gallium nitride, with a thickness of 50-500nm; the material of the nitride barrier layer is aluminum gallium nitride, or indium aluminum nitride, with a thickness of 5-30nm. A two-dimensional electron gas is formed between the nitride channel layer and the nitride barrier layer as a conductive channel of the gallium nitride radio frequency device.

[0052] The bottom layer of the material of the gallium nitride transistor electrode gate 92 is Ni, or Ti, or TiN, or TaN, and the second layer or the material above the second layer is one or more of Al, Au, Ti, Ta, Pt, TiN, TaN, W, and Cu.

[0053] The bottom two layers of the material of the gallium nitride transistor electrode source 91 are Ti, Al, or Ta, Al, or Mo, Al from bottom to top; the metals of other layers include one or more of Ti, Al, Ni, Au, Mo, Pt, and W.

[0054] The bottom two layers of the material of the GaN transistor electrode drain 93 are Ti, Al, or Ta, Al, or Mo, Al from bottom to top; the metals of other layers include one or more of Ti, Al, Ni, Au, Mo, Pt, and W.

[0055] The back side of the GaN device and the through-hole metal 9 are Ti, Cu, Au, or W.

[0056] The GaAs VCSEL N-electrode metal 1112 material has a layer of Ni or Mo in contact with the N-type arsenide material, and the other layers of materials are Ge, Au, Ni or a combination of Ge, Au, Ni, or a combination of the two or more layers.

[0057] The GaAs VCSEL P-electrode metal 41 material has a layer of Ti in contact with the P-type arsenide material, and the other layers of materials are one or a combination of Pt, Au, and Zn.

[0058] The material of the GaAs VCSEL bonding metal 5 and the GaN device bonding metal 6 is one or a combination of Ti, Ni, Au, Cu, etc.;

[0059] The GaAs VCSEL N-pole reflector 2 and the GaAs VCSEL P-pole reflector 4 use distributed Bragg reflectors DBR, and the materials thereof are one or several periodic material structures among multiple pairs of AlAs / GaAs, AlGaAs / GaAs, AlGaAs / InGaP, and AlAs;

[0060] The VCSEL light emitting area 3 includes an active area and an electrical confinement layer; the active area comprises a quantum well component.

[0061] like Figure 1 - Figure 2 As shown, the working process of a gallium nitride transistor and gallium arsenide VCSEL heterogeneous three-dimensional integrated device structure and manufacturing method provided in this embodiment is as follows:

[0062] Step S1: Select a GaAs epitaxial wafer to prepare a GaAs VCSEL;

[0063] Step S2: selecting a gallium nitride epitaxial wafer and preparing a gallium nitride transistor, including substrate thinning, metal through hole 10 preparation, and gallium nitride device back and through hole metal 9 preparation; Step S3: depositing gallium arsenide VCSEL bonding metal 5 and gallium nitride device bonding metal 6 on the gallium arsenide VCSEL P electrode metal 41 and on the gallium nitride device back and through hole metal 9 respectively;

[0064] Step S4: the gallium nitride transistor and the gallium arsenide VCSEL are metal-bonded via the gallium arsenide VCSEL bonding metal 5 and the gallium nitride device bonding metal.

[0065] Example

[0066] like Figure 1 - Figure 2As shown, the gallium arsenide epitaxial wafer is selected to prepare the gallium arsenide VCSEL, and the gallium nitride epitaxial wafer is selected to prepare the gallium nitride transistor, including substrate thinning, metal through-hole 10 preparation and gallium nitride device back and through-hole metal 9 preparation, gallium arsenide VCSEL bonding metal 5 and gallium nitride device bonding metal 6 are deposited on the gallium arsenide VCSEL P electrode metal 41 and the gallium nitride device back and through-hole metal 9, respectively, and the gallium nitride transistor and the gallium arsenide VCSEL are metal-bonded through the gallium arsenide VCSEL bonding metal 5 and the gallium nitride device bonding metal 6;

[0067] Taking advantage of the high breakdown voltage, high efficiency, high switching frequency, and short switching time of GaN transistors, it provides drive for GaAs VCSELs to meet the requirements of high laser modulation rate in some application scenarios such as LiDAR.

[0068] The proposed integration scheme enables GaN transistors and GaAs VCSELs to have a smaller spatial spacing, reducing chip size, reducing chip weight, and improving chip integration;

[0069] Reduces the loss of long-distance package image transmission signals at high frequencies and the influence of parasitic parameters such as inductance, thus improving the high-frequency performance of the system;

[0070] The package tube shell and package leads in the traditional solution are reduced, thereby reducing the cost of the entire system.

[0071] The above description is only a further embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical solutions and concepts of the present invention within the scope disclosed by the present invention, which belong to the protection scope of the present invention.

Claims

1. A gallium nitride transistor and gallium arsenide VCSEL heterogeneous three-dimensional integrated device structure and manufacturing method, characterized in that: The device structure comprises, from bottom to top, gallium arsenide VCSEL N-electrode metal (11) (12), gallium arsenide VCSEL N-pole reflector (2), gallium arsenide VCSEL light-emitting area (3), gallium arsenide VCSEL P-pole reflector (4), gallium arsenide VCSEL P-electrode metal (41), gallium arsenide VCSEL bonding metal (5), gallium nitride device bonding metal (6), gallium nitride device back and through-hole metal (9), gallium nitride substrate layer (7), gallium nitride epitaxial layer (8), metal through-hole (10), gallium nitride transistor electrode source (91), gallium nitride transistor electrode gate (92) and gallium nitride transistor electrode drain (93). A gallium arsenide VCSEL device is composed of gallium arsenide VCSEL N-electrode metal (11), (12), gallium arsenide VCSEL N-pole reflector (2), gallium arsenide VCSEL light-emitting area (3), gallium arsenide VCSEL P-pole reflector (4), gallium arsenide VCSEL P-electrode metal (41), and gallium arsenide VCSEL bonding metal (5). The gallium arsenide VCSEL light-emitting area realizes photon lasing, and the light beam is emitted from the back. A gallium nitride transistor is composed of a gallium nitride device bonding metal (6), a gallium nitride device back and through-hole metal (9), a gallium nitride substrate layer (7), a gallium nitride epitaxial layer (8), a metal through-hole (10), a gallium nitride transistor electrode source (91), a gallium nitride transistor electrode gate (92) and a gallium nitride transistor electrode drain (93). The gallium nitride epitaxial layer (8) is a group III nitride material and can be one or a combination of several of GaN, AlN and InN. A conductive channel is formed in the gallium nitride epitaxial layer (8) and is regulated by the gallium nitride transistor electrode gate (92). When working, current flows from the gallium nitride transistor electrode drain (93) to the gallium nitride transistor electrode source (91). Gallium nitride transistor and gallium arsenide VCSEL; three-dimensional vertical integration is achieved by metal bonding, and current flows from the gallium nitride transistor electrode drain (93), through the gallium nitride transistor electrode source (91), the gallium nitride device back and through-hole metal (9), the gallium nitride device bonding metal (6), the gallium arsenide VCSEL P-electrode metal (41), and the gallium arsenide VCSEL bonding metal (5) to the gallium arsenide VCSEL P-pole reflector (4), providing holes to the gallium arsenide VCSEL light-emitting area (3) and electrons provided by the gallium arsenide VCSEL N-electrode metal (11) (12) for combined light emission. The gallium nitride transistor electrode gate (92) is used to control the light emission of the gallium arsenide VCSEL.

2. The gallium nitride transistor and gallium arsenide VCSEL heterogeneous three-dimensional integrated device structure and manufacturing method according to claim 1, characterized in that: The gallium nitride substrate (7) may be absent, and the back side of the gallium nitride device is in direct contact with the through-hole metal (9) and the gallium nitride epitaxial layer (8).

3. The gallium nitride transistor and gallium arsenide VCSEL heterogeneous three-dimensional integrated device structure and manufacturing method according to claim 2, characterized in that: The material of the gallium nitride substrate (7) can be one of silicon carbide, silicon, and sapphire substrates, with a thickness of 100-1500 μm; the material of the gallium nitride device epitaxial layer (8) is a group III nitride semiconductor material, which is a compound formed by one or more of gallium nitride, aluminum nitride, and indium nitride. The gallium nitride device epitaxial layer (3) includes a nitride nucleation layer, a nitride transition layer, a nitride buffer layer, a nitride channel layer, and a nitride barrier layer. The material of the nitride nucleation layer is aluminum nitride, with a thickness of 50-300nm; the material of the nitride transition layer is gradient aluminum gallium nitride, or aluminum nitride / aluminum gallium nitride superlattice, with a thickness of 500-1000nm; the material of the nitride buffer layer is gallium nitride, with a thickness of 100-1000nm; the material of the nitride channel layer is gallium nitride, or indium gallium nitride, or aluminum gallium nitride, with a thickness of 50-500nm; the material of the nitride barrier layer is aluminum gallium nitride, or indium aluminum nitride, with a thickness of 5-30nm, and a two-dimensional electron gas is formed between the nitride channel layer and the nitride barrier layer as a conductive channel of the gallium nitride radio frequency device.

4. The gallium nitride transistor and gallium arsenide VCSEL heterogeneous three-dimensional integrated device structure and manufacturing method according to claim 3, characterized in that: The bottom layer of the material of the gallium nitride transistor electrode gate (92) is Ni, or Ti, or TiN, or TaN, and the second layer or the second layer above the second layer is one or more of Al, Au, Ti, Ta, Pt, TiN, TaN, W, and Cu; The bottom two layers of the material of the gallium nitride transistor electrode source (91) are Ti, Al, or Ta, Al, or Mo, Al from bottom to top; the metals of other layers include one or more of Ti, Al, Ni, Au, Mo, Pt, and W; The bottom two layers of the material of the gallium nitride transistor electrode drain (93) are Ti, Al, or Ta, Al, or Mo, Al from bottom to top; the metals of other layers include one or more of Ti, Al, Ni, Au, Mo, Pt, and W. The back side and through hole metal (9) of the gallium nitride device are Ti, Cu, Au or W. The back surface and through-hole metal (9) of the gallium nitride device are Ti, Cu, Au or W.

5. The gallium nitride transistor and gallium arsenide VCSEL heterogeneous three-dimensional integrated device structure and manufacturing method according to claim 4, characterized in that: The GaAs VCSEL N-electrode metal (11) (12) material has a layer of Ni or Mo in contact with the N-type arsenide material, and the other layers of materials are one or a combination of Ge, Au, and Ni; The GaAs VCSEL P-electrode metal (41) material has a layer of Ti in contact with the P-type arsenide material, and the other layers of materials are one or a combination of Pt, Au, and Zn; The materials of the gallium arsenide VCSEL bonding metal (5) and the gallium nitride device bonding metal (6) are one or a combination of Ti, Ni, Au, Cu and the like.

6. The gallium nitride transistor and gallium arsenide VCSEL heterogeneous three-dimensional integrated device structure and manufacturing method according to claim 5, characterized in that: The gallium arsenide VCSEL N-pole reflector (2) and the gallium arsenide VCSEL P-pole reflector (4) adopt a distributed Bragg reflector (DBR), the material of which is one or several periodic material structures of multiple pairs of AlAs / GaAs, AlGaAs / GaAs, AlGaAs / InGaP, and AlAs.

7. A gallium nitride transistor and gallium arsenide VCSEL heterogeneous three-dimensional integrated device structure and manufacturing method according to claim 6, characterized in that: The VCSEL light-emitting region (3) comprises an active region and an electrical confinement layer; the active region comprises a quantum well component.

8. The gallium nitride transistor and gallium arsenide VCSEL heterogeneous three-dimensional integrated device structure and manufacturing method according to claim 7, characterized in that: The following steps are also included: Step S1: Select a GaAs epitaxial wafer to prepare a GaAs VCSEL; Step S2: selecting a gallium nitride epitaxial wafer and preparing a gallium nitride transistor, including substrate thinning, preparation of metal through holes (10), and preparation of the back side and through hole metal (9) of the gallium nitride device; Step S3: depositing a gallium arsenide VCSEL bonding metal (5) and a gallium nitride device bonding metal (6) on the gallium arsenide VCSEL P electrode metal (41) and on the back of the gallium nitride device and the through-hole metal (9) respectively; Step S4: The gallium nitride transistor and the gallium arsenide VCSEL are metal-bonded via the gallium arsenide VCSEL bonding metal (5) and the gallium nitride device bonding metal.

Images