High-voltage line turn-to-turn protection method and device and computer equipment

Abstract

The invention is suitable for the technical field of relay protection, and provides a high-voltage line turn-to-turn protection method and device and computer equipment. The method comprises the following steps: judging whether a non-full-phase coincidence action condition is met or not according to a circuit breaker on-off state, a line side three-phase alternating voltage vector and a reactor head end zero-sequence current vector; if a non-full-phase coincidence action condition is met, performing turn-to-turn protection by adopting a floating zero-sequence direction action element criterion and a floating negative-sequence direction action element criterion; otherwise, adopting a conventional zero sequence direction action element criterion and a conventional negative sequence direction action element criterion to carry out turn-to-turn protection; the floating zero-sequence direction action element criterion and the floating negative-sequence direction action element criterion both comprise floating coefficients, the floating coefficients are reduced along with time from the non-full-phase coincidence moment based on an initial value, and the minimum value is the value of a conventional coefficient. According to the method, the floating criterion is adopted under the condition that the non-full-phase coincidence action condition is met, so that the inter-turn protection misoperation risk is reduced.

Description

Technical Field

[0001] The present application belongs to the field of relay protection technology, and in particular, relates to a high-voltage line turn-to-turn protection method, device and computer equipment. Background Art

[0002] In the high-voltage lines of 220kV and above in the power system, more than 70% of the faults are single-phase grounding faults, and more than 80% of them are transient faults. For transient single-phase faults, the line protection generally chooses single-phase tripping and single-phase automatic reclosing mode. Figure 1 A non-full-phase closing process of a line is shown, which specifically includes: when a single-phase fault occurs in the line, the line protection phase selection trips the single-phase circuit breaker or the circuit breaker trips the single-phase circuit breaker, and the line will be in a full-phase operation state (i.e. Figure 1 three-phase operation state) into a short-term non-full-phase operation state (i.e. Figure 1 After non-full-phase operation, the line protection sends a circuit breaker reclosing command through the automatic reclosing logic. At this time, it is in the non-full-phase reclosing (abbreviated as non-full-phase reclosing) state.

[0003] In order to limit the operating overvoltage of the ultra-high voltage long-distance transmission line system and absorb the capacitive reactive power of the line, it is necessary to install a three-phase shunt reactor on the transmission line. Due to the inductive characteristics of the shunt reactor, a large non-periodic transient inrush current will be generated during the non-full-phase reclosing period on the line side. Figure 2 The waveforms of voltage and current during non-full-phase overlap are shown, where UC is the phase voltage during non-full-phase overlap, and IHC is the phase current during non-full-phase overlap. Figure 2 It can be seen from the IHC current waveform that during the non-full-phase reclosing period, the instantaneous phase current decays from the maximum value of 1.531A in the first cycle after the reclosing time 0, that is, the moment when the DL_HZ switch channel is set to 1, to the normal value of 0.516A over time, and the non-full-phase closing phase current presents a waveform state that decays over time. The duration of transient inrush current will vary due to differences in equipment factory processes. In this non-full-phase reclosing situation, the inter-turn protection that originally used compensated zero-sequence or negative-sequence power direction protection may be affected by the transient inrush current and malfunction. Summary of the invention

[0004] The embodiments of the present application provide a method, an apparatus and a computer device for high-voltage line turn-to-turn protection, which reduce the risk of false operation of turn-to-turn protection by adopting a floating criterion when the non-full-phase coincidence action conditions are met.

[0005] In a first aspect, an embodiment of the present application provides a high-voltage line turn-to-turn protection method, comprising:

[0006] Determine whether the non-full-phase coincidence action conditions are met according to the circuit breaker switch state, the three-phase AC voltage vector on the line side, and the zero-sequence current vector at the first end of the reactor;

[0007] If the non-full-phase coincidence action conditions are met, the floating zero-sequence directional action element criteria and the floating negative-sequence directional action element criteria are used for turn-to-turn protection; otherwise, the conventional zero-sequence directional action element criteria and the conventional negative-sequence directional action element criteria are used for turn-to-turn protection;

[0008] The above-mentioned conventional zero-sequence direction action element criterion and the above-mentioned floating zero-sequence direction action element criterion are calculated based on the zero-sequence current vector of the first end of the reactor and the zero-sequence voltage vector on the line side; the above-mentioned conventional negative-sequence direction action element criterion and the above-mentioned floating negative-sequence direction action element criterion are calculated based on the negative-sequence current vector of the first end of the reactor and the negative-sequence voltage vector on the line side; the above-mentioned conventional zero-sequence direction action element criterion and the above-mentioned conventional negative-sequence direction action element criterion both include conventional coefficients; the above-mentioned floating zero-sequence direction action element criterion and the above-mentioned floating negative-sequence direction action element criterion both include floating coefficients, and the above-mentioned floating coefficients decrease with time based on the initial value starting from the moment of non-full-phase coincidence, and the minimum value is the value of the above-mentioned conventional coefficients.

[0009] In a second aspect, an embodiment of the present application provides a high-voltage line turn-to-turn protection device, comprising:

[0010] A condition judgment module is used to judge whether the non-full-phase coincidence action condition is met according to the switch state of the circuit breaker, the three-phase AC voltage vector on the line side, and the zero-sequence current vector at the first end of the reactor;

[0011] A criterion selection module is used to adopt the floating zero-sequence direction action element criterion and the floating negative-sequence direction action element criterion for turn-to-turn protection when the non-all-phase coincidence action conditions are met; otherwise, the conventional zero-sequence direction action element criterion and the conventional negative-sequence direction action element criterion are adopted for turn-to-turn protection;

[0012] A criterion calculation module is used to calculate the above-mentioned conventional zero-sequence direction action element criterion and the above-mentioned floating zero-sequence direction action element criterion according to the above-mentioned zero-sequence current vector at the first end of the inductor and the zero-sequence voltage vector on the line side, and to calculate the above-mentioned conventional negative-sequence direction action element criterion and the above-mentioned floating negative-sequence direction action element criterion according to the negative-sequence current vector at the first end of the inductor and the negative-sequence voltage vector on the line side; the above-mentioned conventional zero-sequence direction action element criterion and the above-mentioned conventional negative-sequence direction action element criterion both include conventional coefficients; the above-mentioned floating zero-sequence direction action element criterion and the above-mentioned floating negative-sequence direction action element criterion both include floating coefficients, and the above-mentioned floating coefficients decrease with time based on an initial value starting from the moment of non-full-phase coincidence, and the minimum value is the value of the above-mentioned conventional coefficient.

[0013] In a third aspect, an embodiment of the present application provides a computer device, including:

[0014] The method comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the method according to the first aspect is implemented.

[0015] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program, and when the computer program is executed by a processor, it implements the steps in the method described in the first aspect.

[0016] In a fifth aspect, an embodiment of the present application provides a computer program product, which, when executed on a computer device, enables the computer device to execute the method described in the first aspect.

[0017] It can be understood that the beneficial effects of the second to fifth aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here.

[0018] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0019] 1) In the early stage of non-full-phase reclosing, there is the greatest braking characteristic. In the later stage, as time goes by, the braking characteristic gradually decreases and finally returns to the normal state. This application adopts the floating zero-sequence direction action element criterion and the floating negative-sequence direction action element criterion for turn-to-turn protection in the non-full-phase reclosing state. Both of these floating criteria contain floating coefficients that decrease over time, thereby fitting the current inrush characteristics generated by non-full-phase reclosing to the greatest extent, and can effectively reduce the risk of false operation of turn-to-turn protection during non-full-phase reclosing;

[0020] 2) The method provided in this application is an improvement and upgrade of the turn-to-turn protection algorithm, and there is no need to change the original product structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 This is a schematic diagram of a non-full-phase closing process of a line provided by an embodiment of the present application;

[0023] Figure 2 It is a waveform diagram of voltage and current during non-full-phase coincidence provided by an embodiment of the present application;

[0024] Figure 3 It is a schematic diagram of an application scenario provided by an embodiment of the present application;

[0025] Figure 4 This is a flow chart of a high-voltage line turn-to-turn protection method provided by an embodiment of the present application;

[0026] Figure 5 It is a judgment logic diagram of each criterion provided in an embodiment of the present application;

[0027] Figure 6 This is a schematic diagram of non-full-phase coincidence judgment logic provided by an embodiment of the present application;

[0028] Figure 7 It is a structural block diagram of a high-voltage line turn-to-turn protection device provided in one embodiment of the present application;

[0029] Figure 8 It is a structural diagram of a computer device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0030] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0031] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0032] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0033] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0034] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0035] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0036] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0037] The embodiment of the present application provides a high-voltage line turn-to-turn protection method, which improves the action conditions of the high-voltage shunt reactor turn-to-turn protection, can effectively identify the non-full-phase coincidence action conditions of the high-voltage line reactor and adopt a floating criterion, thereby improving the action accuracy of the high-voltage shunt reactor turn-to-turn protection under different operating conditions.

[0038] To understand the above method, first combine Figure 3 The "non-full phase overlap" state is explained. Figure 3 A schematic diagram of an application scenario to which the present application is applicable is shown. Figure 3 10, 20, 30, 40 respectively represent the three-phase current CT at the head end of the shunt reactor, the three-phase voltage PT of the high-voltage line, the A-phase circuit breaker in the three-phase circuit breaker on the line side, and the instantaneous fault of the A-phase of the line. The three-phase circuit breaker on the line side refers to the circuit breaker installed on one side of the power line, which is used to control and protect the power line. This circuit breaker can independently control each phase in the three-phase circuit, such as the A-phase circuit breaker 30 used to control and protect the A-phase of the line; the three-phase current at the head end of the shunt reactor refers to the current of the three phases (A, B, C phases) at the input end (head end) of the shunt reactor, which can be measured by the current transformer (Current Transformer, CT); the three-phase voltage of the high-voltage line refers to the voltage of the three phases (A, B, C phases) in the high-voltage transmission line, which can be measured by the voltage transformer (Power Transformer, PT).

[0039] When the instantaneous fault 40 of phase A of the line disappears, the phase A circuit breaker 30 is reclosed due to line protection control, and at this time, it is in a non-full-phase reclosing state.

[0040] Combine the following Figure 4 The high-voltage line turn-to-turn protection method provided in the embodiment of the present application is described in detail.

[0041] Figure 4 4 is a flow chart of a high-voltage line turn-to-turn protection method provided in an embodiment of the present application. In some embodiments, the method can be applied to a device such as a microcomputer relay protection device or a computer device. The process includes steps S401, S402 and S403, which are as follows:

[0042] S401, judging whether the non-full-phase coincidence action condition is met according to the circuit breaker switch state, the line side three-phase AC voltage vector and the reactor head end zero-sequence current vector. If the non-full-phase coincidence action condition is met, executing step S402, otherwise executing step S403.

[0043] Among them, the circuit breaker switching state, the three-phase AC voltage vector on the line side and the zero-sequence current vector at the first end of the reactor can be obtained through existing methods, and this application does not limit this.

[0044] In one embodiment, it is possible to determine whether the non-full-phase operation mark condition is met based on the circuit breaker switch state and the zero-sequence current vector at the first end of the reactor, and then determine whether the non-full-phase coincidence action condition is met based on the non-full-phase operation mark and the three-phase AC voltage vector on the line side.

[0045] When determining whether the non-full-phase coincidence action condition is met, in one embodiment, when a phase voltage recovers from a non-full-phase state to a normal state, it is determined that the non-full-phase coincidence action condition is met. Specifically, when any phase voltage recovers from less than 20V to 0.9 times the rated voltage, it is determined that the non-full-phase coincidence action condition is met.

[0046] S402, using floating zero-sequence directional action element criteria and floating negative-sequence directional action element criteria to perform turn-to-turn protection.

[0047] S403, using conventional zero-sequence direction action element judgment criteria and conventional negative-sequence direction action element judgment criteria to perform turn-to-turn protection.

[0048] In the above steps S402 and S403, the conventional zero-sequence direction action element criterion and the floating zero-sequence direction action element criterion can be calculated based on the zero-sequence current vector at the first end of the reactor and the zero-sequence voltage vector on the line side; the conventional negative-sequence direction action element criterion and the floating negative-sequence direction action element criterion can be calculated based on the negative-sequence current vector at the first end of the reactor and the negative-sequence voltage vector on the line side.

[0049] Among them, the conventional zero-sequence direction action element criterion and the conventional negative-sequence direction action element criterion (hereinafter referred to as the conventional criterion) both include conventional coefficients; the floating zero-sequence direction action element criterion and the floating negative-sequence direction action element criterion (hereinafter referred to as the floating criterion) both include floating coefficients, and the floating coefficients decrease with time from the non-full-phase coincidence moment based on the initial value, and the minimum value is the value of the conventional coefficient. Among them, the non-full-phase coincidence moment is the moment when the non-full-phase coincidence action conditions are judged to be met. Through the setting of the floating coefficient, the floating coefficient decreases from the non-full-phase coincidence moment and gradually approaches the conventional coefficient over time. In the initial stage of the non-full-phase coincidence state, it has the greatest braking characteristics for parameters such as current and voltage. In the later stage, as time goes by, the braking characteristics are gradually reduced and finally restored to the normal state. Through the setting of the floating coefficient, the floating criterion of the inter-turn protection can be more in line with the characteristics of the non-full-phase coincidence state, thereby effectively reducing the risk of false operation of the inter-turn protection during the non-full-phase coincidence period.

[0050] In one embodiment, when the non-all-phase coincidence condition return condition is met, the floating criterion can be changed to the conventional criterion.

[0051] In one example, within the 500ms widening time after it is determined that the non-full-phase coincidence action condition is met, the floating zero-sequence direction action element criterion and the floating negative-sequence direction action element criterion are used. After reaching the widening time of 500ms, it is determined that the non-full-phase coincidence condition return condition is met, and the conventional zero-sequence direction action element criterion and the conventional negative-sequence direction action element criterion are used instead. Alternatively, before reaching the widening time of 500ms, in order to avoid misjudgment of non-full-phase coincidence during line oscillation, after the widening time of 20ms after it is determined that the non-full-phase coincidence action condition is met, if the voltage meets the voltage return condition, it is determined that the non-full-phase coincidence condition return condition is met, and the conventional zero-sequence direction action element criterion and the conventional negative-sequence direction action element criterion are used instead, thereby terminating the use of the floating criterion in advance. Specifically, after the widening time of 20ms, if the three-phase minimum phase voltage is lower than 50V, it can be determined that the voltage return condition is met.

[0052] In another example, in order to prevent the misjudgment of non-full-phase reclosing when a single-phase fault is not cleared, when the maximum phase voltage of the three-phase is greater than 80V, the return condition of the non-full-phase reclosing condition is judged to be met, and the conventional zero-sequence direction action element judgment criteria and the conventional negative-sequence direction action element judgment criteria are adopted.

[0053] So far, the Figure 4 Description of the process shown, by Figure 4 The process shown can achieve the following technical effects:

[0054] 1) This application adopts floating zero-sequence direction action element criteria and floating negative-sequence direction action element criteria for turn-to-turn protection in the non-full-phase overlap state. Both floating criteria include floating coefficients that decrease over time, thereby better fitting the current inrush characteristics generated by non-full-phase overlap, and can effectively reduce the risk of false operation of turn-to-turn protection during non-full-phase overlap;

[0055] 2) The method provided in this application is an improvement and upgrade of the turn-to-turn protection algorithm, and there is no need to change the original product structure.

[0056] To facilitate understanding of the high-voltage line turn-to-turn protection method provided in the embodiment of the present application, the above steps are described in more detail below.

[0057] First, let's take an example to illustrate how to obtain the parameters in the above method:

[0058] In one embodiment, the secondary rated impedance ZL1 of the main reactor and the secondary rated impedance ZL2 of the small reactor can be calculated according to the system parameters of the shunt reactor. s0 And the zero-sequence impedance ZL0 of the reactor. Specifically, the shunt reactor system parameters include: three-phase rated capacity S n , Rated voltage U n , Line voltage transformer PT ratio N v , the first-end current transformer CT ratio N a And the neutral point reactance primary rated impedance Z n The secondary rated impedance of the main reactance is ZL1, and the secondary rated impedance of the small reactance is ZL s0 The zero-sequence impedance ZL0 of the reactor can be calculated by the following formula:

[0059] according to Calculate the secondary rated impedance ZL1 of the main reactance;

[0060] According to the formula Z n ×N a / N v Calculate the secondary rated impedance ZL of the small reactance s0 ;

[0061] According to the formula ZL1+3ZL s0 Calculate the zero-sequence impedance ZL0 of the reactor.

[0062] In one embodiment, the following six vectors can be calculated and determined using the sampling information: the three-phase AC voltage vector of the line side of the shunt reactor, the three-phase AC current vector of the reactor head end, the zero-sequence voltage vector of the line side, the zero-sequence current vector of the reactor head end, the negative-sequence voltage vector of the line side, and the negative-sequence current vector of the reactor head end. Specifically, the analog quantity information can be collected separately by the sampling plug-in and transmitted to the protection module by the data bus, and the original sampling values ​​are stored in the protection module, and then the above six vectors are calculated and determined using the original sampling values. In one example, collecting analog quantity information and transmitting it to the protection module by the data bus may include: collecting the three-phase AC voltage U a , U b , U c And the three-phase AC current I at the first end of the shunt reactor ha ,I hb ,I hc The data is transmitted to the protection module via the data bus, and the protection module stores the original sampled values. The calculation process of the above 6 vectors based on the original sampled values ​​is as follows:

[0063] The real part, imaginary part and square amplitude of the three-phase AC current vector at the head end of the reactor can be calculated from the original sampling value through the Fourier full-cycle fundamental wave formula. Among them, the formula for Fourier full-cycle fundamental wave operation is as follows:

[0064]

[0065] Where N is the number of sampling points, p is the sampling pointer (the current sampling point number), i(n) is the original sampling data of the analog channel, and I Re is the real part of the current vector, I Im is the imaginary part of the current vector, is the square of the current vector amplitude. The calculation ideas of the real part, imaginary part and square of the three-phase AC voltage vector on the line side are the same, so they will not be repeated here.

[0066] Furthermore, the zero-sequence current vector at the first end of the reactor and the negative-sequence current vector at the first end of the reactor can be calculated from the three-phase current vector at the first end of the reactor. The specific formula is as follows:

[0067] I 0_Re =I A_Re +I B_Re +I C_Re (4)

[0068] I 0_Im =I A_Im +I B_Im +I C_Im (5)

[0069]

[0070]

[0071]

[0072] Among them I A_Re ,I B_Re ,I C_Re is the real part of the current of phase A, phase B, and phase C at the first end of the reactor, I A_Im ,I B_Im ,I C_Im is the imaginary part of the current of phase A, phase B, and phase C at the first end of the reactor, I 0_Re is the real part of the zero-sequence current vector at the first end of the reactor, I 0_Im is the imaginary part of the zero-sequence current vector at the first end of the reactor, is the square of the magnitude of the zero-sequence current vector at the first end of the reactor, I 2_Re is the real part of the negative sequence current vector at the first end of the reactor, I 2_Im is the imaginary part of the negative sequence current vector at the first end of the reactor, is the square of the magnitude of the negative sequence current vector at the first end of the reactor. The calculation ideas of the line side zero sequence voltage vector and the line side negative sequence voltage vector are the same, which will not be repeated here.

[0073] The following is an example of how to calculate the conventional criterion and the floating criterion:

[0074] In one example, according to the reactor zero-sequence impedance value ZL0, the line-side zero-sequence voltage vector and the reactor head-end zero-sequence current vector, the conventional zero-sequence direction action element criterion can be calculated, and the specific calculation is as follows:

[0075]

[0076] in, are the zero-sequence voltage vector on the line side and the zero-sequence current vector at the first end of the reactor respectively, and ZL0 is the zero-sequence impedance value of the reactor.

[0077] In an example, according to the reactor secondary rated impedance value ZL1, the line side negative sequence voltage vector and the reactor head end negative sequence current vector, the conventional negative sequence direction action element criterion can be calculated, and the specific calculation is as follows:

[0078]

[0079] in, and They are the negative sequence voltage vector on the line side and the negative sequence current vector at the first end of the reactor respectively, and ZL1 is the secondary rated impedance value of the reactor.

[0080] In one example, when calculating the floating criterion, it is necessary to first calculate the floating coefficient ΔK. Since the surge saturation characteristics show a decay characteristic when the non-full-phase overlap occurs, the floating coefficient ΔK adopts a sinusoidal characteristic with time as the horizontal axis, and its characteristic formula is as follows:

[0081]

[0082] Among them, T is the floating time of the comprehensive blocking value set by the program; t is the non-full-phase coincidence counter, which decreases from the non-full-phase coincidence moment to 0, 0≤t≤T. When the non-full-phase coincidence moment 0 is ΔK=1, ΔK gradually approaches the conventional coefficient 0.9 as time goes by.

[0083] According to the floating coefficient ΔK, the reactor zero-sequence impedance ZL0, the line-side zero-sequence voltage vector and the reactor head-end zero-sequence current vector calculated above, the floating zero-sequence direction action element criterion is calculated according to the following formula:

[0084]

[0085] in, is the zero-sequence voltage vector on the line side and the zero-sequence current vector at the first end of the reactor, and ZL0 is the zero-sequence impedance value of the reactor.

[0086] According to the floating coefficient ΔK calculated above, the secondary rated impedance value ZL1 of the reactor, the negative sequence voltage vector on the line side and the negative sequence current vector at the first end of the reactor, the floating negative sequence direction action element criterion is calculated according to the following formula:

[0087]

[0088] in, is the negative sequence voltage vector at the line side and the negative sequence current vector at the first end of the reactor, and ZL1 is the secondary rated impedance value of the reactor.

[0089] In one example, when performing inter-turn protection, in addition to the conventional criterion and floating criterion described above, the zero-sequence impedance action element criterion can also be calculated according to the zero-sequence impedance ZL0, the line-side zero-sequence voltage vector, and the reactor head-end zero-sequence current vector according to the following formula:

[0090] jXL0>0.6×ZL0(15)

[0091] in, is the zero-sequence voltage vector on the line side and the zero-sequence current vector at the first end of the reactor, and ZL0 is the zero-sequence impedance value of the reactor.

[0092] The judgment logic based on the above criteria can be referred to Figure 5 As shown. Among them, the zero-sequence impedance action element criterion is the gate criterion of the zero-sequence directional element and the negative-sequence directional element in the main logic direction, and each directional element criterion is AND logic with the criterion.

[0093] The following is an example of non-full phase coincidence judgment:

[0094] Figure 6 A schematic diagram of non-full phase coincidence judgment logic is shown. Figure 6 As shown in the figure, when the switch position of the circuit breaker is closed and one phase is tripped (i.e. single-phase tripped), and the zero-sequence current amplitude of the reactor head end is greater than the fixed value I set When it is judged as non-full-phase state, the non-full-phase operation flag is set to 1 and the Tset time is extended.

[0095] During the 1S time when the non-full-phase operation mark changes from 1 to 0, the phase voltage recovers from the non-full-phase state to the normal state, that is, the phase voltage recovers from less than 20V to 0.9U n Rated voltage is judged to meet the non-full-phase coincidence action conditions, and the extension time is 500ms.

[0096] After the non-full-phase coincidence action condition is met, if the minimum phase voltage of the three phases is lower than 50V after the extension time of 20ms, it is judged that the non-full-phase coincidence condition return condition is met; or, when the action extension time of 500ms is reached, it is judged that the non-full-phase coincidence condition return condition is met; or, when the maximum phase voltage of the three phases is greater than 80V, it is judged that the non-full-phase coincidence condition return condition is met. After the non-full-phase coincidence condition return condition is judged to be met, the floating criterion is changed to the conventional criterion.

[0097] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0098] Corresponding to the high-voltage line turn-to-turn protection method described in the above embodiment, Figure 7 A structural block diagram of a high-voltage line turn-to-turn protection device provided in an embodiment of the present application is shown. For ease of explanation, only the parts related to the embodiment of the present application are shown.

[0099] Reference Figure 7 The device comprises: a condition judgment module 701, a criterion selection module 702 and a criterion calculation module 703. Among them:

[0100] The condition judgment module 701 is used to judge whether the non-full-phase coincidence action condition is met according to the switch state of the circuit breaker, the three-phase AC voltage vector on the line side and the zero-sequence current vector at the first end of the reactor.

[0101] The criterion selection module 702 is used to use the floating zero-sequence direction action element criterion and the floating negative-sequence direction action element criterion to perform turn-to-turn protection when the non-all-phase coincidence action condition is met; otherwise, use the conventional zero-sequence direction action element criterion and the conventional negative-sequence direction action element criterion to perform turn-to-turn protection;

[0102] The criterion calculation module 703 is used to calculate the conventional zero-sequence direction action element criterion and the floating zero-sequence direction action element criterion according to the zero-sequence current vector at the first end of the inductor and the zero-sequence voltage vector on the line side, and to calculate the conventional negative-sequence direction action element criterion and the floating negative-sequence direction action element criterion according to the negative-sequence current vector at the first end of the inductor and the negative-sequence voltage vector on the line side; the conventional zero-sequence direction action element criterion and the conventional negative-sequence direction action element criterion both include conventional coefficients; the floating zero-sequence direction action element criterion and the floating negative-sequence direction action element criterion both include floating coefficients, and the floating coefficient decreases with time based on the initial value starting from the non-full-phase coincidence moment, and the minimum value is the value of the conventional coefficient.

[0103] It should be noted that the information interaction, execution process, etc. between the above-mentioned devices / units / modules are based on the same concept as the method embodiment of the present application. Their specific functions and technical effects can be found in the method embodiment part and will not be repeated here.

[0104] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0105] An embodiment of the present application also provides a computer device, which includes: at least one processor, a memory, and a computer program stored in the memory and executable on the at least one processor, wherein the processor implements the steps of any of the above-mentioned method embodiments when executing the computer program.

[0106] An embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0107] An embodiment of the present application provides a computer program product. When the computer program product is run on a computer device, the computer device can implement the steps in the above-mentioned method embodiments when executing the computer device.

[0108] Figure 8 This is a schematic diagram of the structure of a computer device provided in one embodiment of the present application. Figure 8 As shown, the computer device of this embodiment includes: at least one processor 80 ( Figure 8 Only one is shown), a memory 81, and a computer program 82 stored in the memory 81 and executable on the at least one processor 80, wherein when the processor 80 executes the computer program 82, the steps of any of the above-mentioned visual programming method embodiments are implemented.

[0109] The computer device may include, but is not limited to, a processor 80 and a memory 81. Those skilled in the art will appreciate that Figure 8 It is only an example of a computer device and does not constitute a limitation of the computer device. It may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, it may also include input and output devices, network access devices, etc.

[0110] The processor 80 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0111] In some embodiments, the memory 81 may be an internal storage unit of the computer device, such as a hard disk or memory of the computer device. In other embodiments, the memory 81 may also be an external storage device of the computer device, such as a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), etc. equipped on the computer device. Further, the memory 81 may also include both an internal storage unit of the computer device and an external storage device. The memory 81 is used to store an operating system, an application program, a boot loader (BootLoader), data, and other programs, such as the program code of the computer program. The memory 81 may also be used to temporarily store data that has been output or is to be output.

[0112] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, which can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may at least include: any entity or device that can carry the computer program code to the device / computer device, a recording medium, a computer memory, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), an electric carrier signal, a telecommunication signal, and a software distribution medium. For example, a USB flash drive, a mobile hard disk, a magnetic disk or an optical disk. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electric carrier signals and telecommunication signals.

[0113] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0114] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0115] In the embodiments provided in the present application, it should be understood that the disclosed apparatus / computer equipment and methods can be implemented in other ways. For example, the apparatus / computer equipment embodiments described above are merely schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of the apparatus or unit, which can be electrical, mechanical or other forms.

[0116] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0117] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A high voltage line turn-to-turn protection method, characterized in that: include: Determine whether the non-full-phase coincidence action conditions are met according to the circuit breaker switch state, the three-phase AC voltage vector on the line side, and the zero-sequence current vector at the first end of the reactor; If the non-full-phase coincidence action conditions are met, the floating zero-sequence directional action element criteria and the floating negative-sequence directional action element criteria are used for turn-to-turn protection; otherwise, the conventional zero-sequence directional action element criteria and the conventional negative-sequence directional action element criteria are used for turn-to-turn protection; The conventional zero-sequence direction action element criterion and the floating zero-sequence direction action element criterion are calculated based on the zero-sequence current vector of the reactor head end and the zero-sequence voltage vector of the line side; The conventional negative-sequence direction action element criterion and the floating negative-sequence direction action element criterion are calculated based on the negative-sequence current vector at the first end of the reactor and the negative-sequence voltage vector on the line side; the conventional zero-sequence direction action element criterion and the conventional negative-sequence direction action element criterion both include conventional coefficients; the floating zero-sequence direction action element criterion and the floating negative-sequence direction action element criterion both include floating coefficients, and the floating coefficient decreases with time based on an initial value starting from the moment of non-full-phase overlap, and the minimum value is the value of the conventional coefficient.

2. The method according to claim 1, characterized in that The method of using floating zero-sequence direction action element criterion and floating negative-sequence direction action element criterion to perform turn-to-turn protection includes: After the non-full-phase coincidence action conditions are met, the floating zero-sequence direction action element criteria and the floating negative-sequence direction action element criteria are used to perform turn-to-turn protection within the 500ms extension time. The method further comprises: After reaching the expansion time of 500ms, it is judged that the non-full-phase coincidence condition return condition is met, and the conventional zero-sequence direction action element criterion and the conventional negative-sequence direction action element criterion are used instead for turn-to-turn protection; or, after the expansion time of 20ms after it is judged that the non-full-phase coincidence action condition is met, if the three-phase minimum phase voltage is less than 50V, it is judged that the non-full-phase coincidence condition return condition is met, and the conventional zero-sequence direction action element criterion and the conventional negative-sequence direction action element criterion are used instead for turn-to-turn protection.

3. The method according to claim 1, characterized in that The method further comprises: When the maximum three-phase phase voltage is greater than 80V, it is determined that the non-full-phase coincidence condition return condition is met, and the conventional zero-sequence direction action element criterion and the conventional negative-sequence direction action element criterion are adopted.

4. The method according to claim 1, characterized in that The determining whether the non-full-phase coincidence action condition is met includes: When the voltage of any phase recovers from below 20V to 0.9 times the rated voltage, it is judged that the non-full-phase coincidence action conditions are met.

5. The method according to claim 1, characterized in that The floating zero-sequence direction action element criterion is: The floating negative sequence direction action element judgment criteria are: Among them, ΔK is the floating coefficient, and is the zero-sequence voltage vector at the line side and the zero-sequence current vector at the first end of the reactor, ZL0 is the zero-sequence impedance of the reactor, and is the negative sequence voltage vector on the line side and the negative sequence current vector at the first end of the reactor, and ZL1 is the secondary rated impedance of the main reactor.

6. The method according to claim 5, characterized in that The method further comprises: The zero-sequence impedance ZL0 of the reactor and the secondary rated impedance ZL1 of the main reactor are calculated according to the system parameters of the shunt reactor.

7. The method according to any one of claims 1 to 6, characterized in that: The method further comprises: The analog quantity information is collected through the sampling plug-in and transmitted to the protection module through the data bus, and the original sampling value is stored in the protection module; The original sampling values ​​are used to calculate and determine the line-side three-phase AC voltage vector of the shunt reactor, the line-side zero-sequence voltage vector, the reactor head-end zero-sequence current vector, the line-side negative-sequence voltage vector, and the reactor head-end negative-sequence current vector.

8. A high voltage line turn-to-turn protection device, characterized in that: include: A condition judgment module is used to judge whether the non-full-phase coincidence action condition is met according to the switch state of the circuit breaker, the three-phase AC voltage vector on the line side, and the zero-sequence current vector at the first end of the reactor; A criterion selection module is used to adopt the floating zero-sequence direction action element criterion and the floating negative-sequence direction action element criterion for turn-to-turn protection when the non-all-phase coincidence action conditions are met; otherwise, the conventional zero-sequence direction action element criterion and the conventional negative-sequence direction action element criterion are adopted for turn-to-turn protection; A criterion calculation module is used to calculate the conventional zero-sequence direction action element criterion and the floating zero-sequence direction action element criterion according to the zero-sequence current vector at the first end of the inductor and the zero-sequence voltage vector on the line side, and to calculate the conventional negative-sequence direction action element criterion and the floating negative-sequence direction action element criterion according to the negative-sequence current vector at the first end of the inductor and the negative-sequence voltage vector on the line side; the conventional zero-sequence direction action element criterion and the conventional negative-sequence direction action element criterion both include conventional coefficients; the floating zero-sequence direction action element criterion and the floating negative-sequence direction action element criterion both include floating coefficients, and the floating coefficients decrease with time based on an initial value starting from the moment of non-full-phase coincidence, and the minimum value is the value of the conventional coefficient.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the method according to any one of claims 1 to 7 is implemented.

10. A computer program product, characterized in that When the computer program product is executed on a computer device, the computer device is caused to execute the method according to any one of claims 1 to 7.

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