Power oscillation suppression method and system suitable for multi-VSG converter parallel system

Abstract

The invention discloses a power oscillation suppression method and system suitable for a multi-VSG converter parallel system, and the method comprises two parts: error power low-pass filtering feed-forward compensation and error power differential feed-forward compensation, and the error power low-pass filtering feed-forward compensation employs a low-pass filtering link containing a virtual inertia and a damping coefficient to construct an active feed-forward item; the suppression of low-frequency power oscillation is realized by adjusting feed-forward parameters; according to error power differential feed-forward compensation, an active feed-forward item is constructed by using a generalized second-order integrator (SOGI), and suppression of synchronous oscillation is realized by adjusting a differential coefficient. According to the invention, coordinated suppression of low-frequency oscillation and synchronous oscillation of the multi-VSG converter parallel system is realized, and safe and stable operation of the multi-VSG converter parallel system is guaranteed.

Description

Technical Field

[0001] The present invention relates to the technical field of power oscillation suppression of a multi-VSG parallel system, and in particular to a power oscillation suppression method and system suitable for a multi-VSG converter parallel system. Background Art

[0002] Distributed power sources such as electric vehicles are an important part of the construction of a new energy system, which can effectively alleviate the problems of environmental pollution and shortage of traditional energy. The high proportion of large-scale distributed resources connected to the power grid will lead to a decrease in the inertia of the entire power grid, a faster frequency change speed, and an increased difficulty in regulation, which will affect the safe and stable operation of the power grid. If distributed resources such as electric vehicles can be converted into a voltage source that supports the stable operation of the power grid through cutting-edge power conversion technology, it can play a role in rapid frequency and voltage regulation, increase inertia, and realize active support for the power grid, which can effectively reduce the additional construction of energy storage power stations and save costs. In response to this, virtual synchronous machine technology came into being.

[0003] Virtual synchronous generator technology simulates the characteristics of synchronous machines by introducing virtual inertia and damping, and can provide the necessary frequency and voltage support for the power grid. However, similar to traditional synchronous machines, VSGs also have power oscillations. When there is a step in the VSG power command or a disturbance in the grid frequency, there are large oscillations in the VSG output active power and output frequency. Especially in a multi-VSG parallel system, the power oscillation phenomenon caused by grid frequency disturbances is more severe. What's worse is that the VSG's overcurrent capacity is much smaller than that of traditional synchronous generators, so it is easy for power oscillations to cause equipment damage and disconnection from the grid.

[0004] Existing research on output power oscillation suppression is mostly focused on a single VSG. Although most research methods can effectively suppress single-machine power oscillations, their oscillation suppression effect is limited when multiple VSGs are connected in parallel. In addition, existing research is mostly focused on single oscillation types such as low-frequency power oscillation or synchronous power oscillation, and has not suppressed both low-frequency power oscillation and synchronous power oscillation at the same time, which has certain limitations. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a power oscillation suppression method and system suitable for a multi-VSG converter parallel system in view of the shortcomings of the existing technology, so as to achieve coordinated suppression of low-frequency oscillation and synchronous oscillation of the multi-VSG parallel supercharging system, and ensure the safe and stable operation of the multi-VSG parallel supercharging system.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is: a power oscillation suppression method applicable to a multi-VSG converter parallel system, comprising the following steps:

[0007] S1, sample the VSG grid-connected voltage and VSG grid-connected current, and calculate the VSG output active power P e and reactive power Q e ;

[0008] S2, VSG active power command value P ref The VSG output active and reactive power value P e Subtract the active power error ΔP and subtract the VSG reactive power command value Q ref and reactive power value Q e Subtract the active power error ΔP and the reactive power error ΔQ to obtain the effective value E0 and the phase angle θ0 of the potential inside the VSG;

[0009] S3, introduce an error power low-pass filter feedforward compensation branch at the active power error ΔP to generate a compensation phase angle θ1; introduce an error power differential feedforward compensation branch at the active power error ΔP, and convert the output ΔP of SOGI into β Multiply by the coefficient k d3 Then generate the compensation phase angle θ2;

[0010] S4, adding the phase angle θ0 to the compensation phase angle θ1 and the compensation phase angle θ2 to obtain the final phase angle θ of the VSG;

[0011] S5, the effective value of the potential E0 and the phase angle θ in the VSG are modulated by PWM, and the VSG switch tube drive signal K is output. PWM .

[0012] The present invention is directed to a multi-VSG parallel supercharging system, and a power oscillation suppression method suitable for a multi-VSG parallel supercharging system based on an error power feedforward compensation design can effectively suppress power oscillations between parallel VSGs; this scheme has no additional communication means, and is a feedforward compensation scheme without differential operations, so it is suitable for a homogeneous multi-VSG parallel supercharging system, which does not require additional communication means and differential operations, and does not affect the steady-state averaging effect of the fast charging system; due to the error power low-pass filter feedforward compensation, it uses a virtual inertia J and a primary frequency modulation parameter D p An active feedforward term is constructed in the low-pass filtering link, and the ability of the fast charging system to suppress low-frequency power oscillations is improved by adjusting the feedforward parameters, which is equivalent to increasing the damping coefficient in the transient process and reducing the inertia coefficient in the transient process. Therefore, the present invention suppresses both low-frequency power oscillations and synchronous power oscillations at the same time, and can achieve coordinated suppression of low-frequency oscillations and synchronous oscillations in a multi-VSG parallel supercharging system, thereby ensuring the safe and stable operation of a multi-VSG parallel supercharging system.

[0013] VSG internal potential effective value ΔU=U n -U e, U n , U e They are the VSG output voltage reference command value and the actual value of the output voltage amplitude respectively.

[0014] VSG phase angle ω n is the rated angular velocity of the multi-VSG converter parallel system, D p is the damping coefficient and J is the inertia coefficient.

[0015] The transfer function G of the feedforward branch is f (s) is expressed as:

[0016] G f (s)=(k d1 s+k d2 ) / [(0.1Js 2 +3D p s+D p )(Js+D p )ω n ];

[0017] Among them, k d1 and k d2 is the feedforward parameter, J is the inertia coefficient, D p is the damping coefficient, s is a complex parameter, s = jω, j is an imaginary unit, ω n is the rated angular velocity of the multi-VSG converter parallel system.

[0018] k d1 =J-1, k d2 =-2D p .

[0019] The transfer function G of the feedforward SOGI branch is q (s) is:

[0020]

[0021] Where Q(s) is the output side ΔP of the feedforward SOGI branch β The transfer function of ΔP on the input side, k s is the feedforward SOGI branch gain coefficient, k d3 is the differential coefficient.

[0022] Error power differential feedforward compensation uses a generalized second-order integrator (SOGI) to construct an active feedforward term to achieve synchronous frequency power oscillation suppression, while filtering out high-frequency harmonics and reducing the interference of high-frequency harmonic components in the control link. In SOGI, when k s =1, for ω=ω n signal, Q(s) is equivalent to -s / ω n, plays a differential role; for ω<ω n The amplitude of the input and output signals remains unchanged; for ω>ω n The signal Q(s) plays a filtering role, which can reduce the interference of high-frequency harmonic components in the control link. In this scheme, k can be set s =1, so it has a differential effect on the synchronous frequency component, and the introduction of the differential effect can move the synchronous oscillation pole away from the 0 axis, thereby suppressing the synchronous oscillation.

[0023]

[0024] As an inventive concept, the present invention also provides a power oscillation suppression system suitable for a multi-VSG converter parallel system, comprising a memory, a processor and a computer program stored in the memory; the processor executes the computer program to implement the steps of the above method.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] 1. The present invention is directed to a multi-VSG parallel supercharging system, and a power oscillation suppression method suitable for a multi-VSG parallel supercharging system based on an error power feedforward compensation design can effectively suppress power oscillations between parallel VSGs;

[0027] 2. The present invention is applicable to a homogeneous multi-VSG parallel supercharging system, which does not require additional communication means and differential operations, and does not affect the steady-state balancing effect of the fast charging system.

[0028] 3. The present invention suppresses low-frequency power oscillation and synchronous power oscillation simultaneously, and can achieve coordinated suppression of low-frequency oscillation and synchronous oscillation of a multi-VSG parallel supercharging system, thereby ensuring safe and stable operation of the multi-VSG parallel supercharging system. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 This is a schematic diagram of a multi-frequency power oscillation suppression method for a multi-VSG parallel supercharging system according to an embodiment of the present invention;

[0030] Figure 2 It is a SOGI control block diagram of an embodiment of the present invention;

[0031] Figure 3 Schematic diagram of power oscillation simulation of multi-VSG parallel supercharging system under traditional VSG control;

[0032] Figure 4 Schematic diagram of power oscillation simulation of a multi-VSG parallel supercharging system using the oscillation suppression method of an embodiment of the present invention. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0034] Example 1

[0035] This embodiment provides a method for suppressing multi-frequency power oscillations in a multi-VSG parallel supercharging system.

[0036] like Figure 1 As shown, the power oscillation suppression method applicable to the parallel system of multiple VSG converters in this embodiment includes two parts: error power low-pass filter feedforward compensation and error power differential feedforward compensation. The error power low-pass filter feedforward compensation uses a low-pass filter link to construct an active feedforward term, which can achieve low-frequency power oscillation suppression; the error power differential feedforward compensation uses a generalized second-order integrator to construct an active feedforward term, which can achieve synchronous oscillation suppression. The power oscillation suppression method applicable to the parallel system of multiple VSG converters includes the following steps:

[0037] 1) VSG grid-connected voltage u gabc and VSG grid-connected current i gabc Sampling is performed and the instantaneous power is calculated to obtain the VSG output active power P e and reactive power Q e ;

[0038] 2) Set the VSG active and reactive power command value P ref and reactive power command value Q ref Respectively with the VSG output active and reactive power values ​​P e And reactive power value Q e Subtracting them, we get the active power error ΔP and reactive power error ΔQ, and then we get the effective value E0 and phase angle θ0 of the potential inside the VSG through traditional VSG control. ΔU=U n -U e , U n , U e They are the VSG output voltage reference command value and the actual value of the output voltage amplitude;

[0039] 3) Introduce error power low-pass filter feedforward compensation in the VSG control loop, that is, introduce feedforward G at the active power error ΔP f (s) branch generates compensation phase angle θ1, θ1 = G f (s)ΔP;

[0040] 4) Introduce error power differential feedforward compensation in the VSG control loop, that is, introduce a feedforward SOGI branch at the active power error ΔP, and convert the output ΔP of SOGI into β , multiplied by the coefficient k d3 Then generate the compensation phase angle θ2, θ2 = G q (s)ΔP;

[0041] 5) Add the phase angle θ0 obtained by traditional VSG control to the compensation phase angle θ1 output by the error power low-pass filter feedforward compensation and the compensation phase angle θ2 output by the error power differential feedforward compensation to obtain the final phase angle θ of the VSG;

[0042] 6) The effective value of the potential E0 and the phase angle θ in the VSG are output through the PWM controller as the VSG switch tube drive signal K PWM .

[0043] The error power low-pass filter feedforward compensation uses a virtual inertia J and a damping coefficient D p The low-pass filter link constructs the active feedforward term, and adjusts the feedforward parameter k d1 and k d2 To improve the ability of the fast charging system to suppress low-frequency power oscillations. The error power low-pass filter feedforward compensation does not require additional communication means and differential operations, and does not affect the steady-state averaging effect of the fast charging system. f (s) The transfer function is:

[0044] G f (s)=(k d1 s+k d2 ) / [(0.1Js 2 +3D p s+D p )(Js+D p )ω n ] (1)

[0045] In the formula, k d1 and k d2 is the feedforward parameter, k d1 =J-1, k d2 =-2D p .

[0046] The error power differential feedforward compensation uses a generalized second-order integrator (SOGI) to construct an active feedforward term and adjusts the differential coefficient k d3 To achieve the suppression of synchronous oscillation, high-frequency harmonics can be filtered out at the same time, reducing the interference of high-frequency harmonic components in the control link. The error power differential feedforward branch transfer function G q (s) is:

[0047]

[0048] Where, Q(s) is the ΔP at the output side of SOGI β The transfer function of ΔP on the input side, k s is the SOGI gain coefficient, k d3 is the differential coefficient, k d3 = -1e-6. The SOGI gain coefficient, its value k s = 1. When k s =1, for the frequency is the grid frequency ω n signal, Q(s) is equivalent to -s / ω n , plays a differential role; for frequency <ω n The amplitude of the input and output signals remains unchanged; for frequencies > ω n The signal Q(s) acts as a filter, which can reduce the interference of high-frequency harmonic components in the control link.

[0049] like Figure 2 As shown in the block diagram of SOGI control in the error power differential feedforward compensation of this embodiment, ΔP is the SOGI input, ΔP α and ΔP β is the output, Q(s) is the ΔP at the output side of SOGI β The transfer function of ΔP on the input side, k s is the SOGI gain coefficient, the SOGI gain coefficient, its value k s = 1. When k s =1, for the frequency is the grid frequency ω n signal, Q(s) is equivalent to -s / ω n , plays a differential role; for frequency <ω n The amplitude of the input and output signals remains unchanged; for frequencies > ω n The signal Q(s) plays a filtering role, which can reduce the interference of high-frequency harmonic components in the control link. d3 is the differential coefficient, k d3 =-1e-6.

[0050] The phase angle θ includes three parts: phase angle θ0, compensation phase angle θ1 and compensation phase angle θ2. Phase angle θ=θ0+θ1+θ2. The compensation phase angles θ1 and θ2 are the outputs of error power low-pass filter feedforward compensation and error power differential feedforward compensation, respectively, and their values ​​are:

[0051]

[0052] The error power low-pass filter feedforward compensation and the error power differential feedforward compensation need to work together to achieve the coordinated suppression of low-frequency oscillation and synchronous oscillation of the multi-VSG parallel supercharging system.

[0053] like Figure 3 As shown, the multi-VSG parallel supercharging system in this embodiment adopts a power oscillation simulation schematic diagram under traditional VSG control. The simulation system is a 4VSG parallel supercharging system, and the power instruction changes from 200kW to 240kW. It can be seen from the figure that low-frequency oscillations and synchronous oscillations exist in the fast charging system at the same time. The maximum amplitude of the low-frequency oscillation is 84.5%, and the amplitude of the synchronous oscillation increases from 9kW to 13.5kW.

[0054] like Figure 4 As shown, a schematic diagram of power oscillation simulation of a multi-VSG parallel supercharging system using the oscillation suppression method of an embodiment of the present invention is shown. The simulation system is a 4VSG parallel supercharging system, and the power command changes from 200kW to 240kW. It can be seen from the figure that the maximum amplitude of low-frequency oscillation in the fast charging system is 22.7%, and the synchronous oscillation amplitude value increases from 6kW to 9kW. The results show that a multi-frequency power oscillation suppression method for a multi-VSG parallel supercharging system of this embodiment can indeed achieve coordinated suppression of low-frequency oscillations and synchronous oscillations of a multi-VSG parallel supercharging system.

[0055] Example 2

[0056] Embodiment 2 of the present invention provides a system corresponding to the above-mentioned embodiment 1, including a memory, a processor and a computer program stored in the memory; the processor executes the computer program in the memory to implement the steps of the method in the above-mentioned embodiment 1.

[0057] In some implementations, the memory may be a high-speed random access memory (RAM), and may also include a non-volatile memory, such as at least one disk memory.

[0058] In some other implementations, the processor may be a central processing unit (CPU), a digital signal processor (DSP), or other general-purpose processors of various types, which are not limited herein.

[0059] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0060] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A power oscillation suppression method applicable to a multi-VSG converter parallel system, characterized in that: The following steps are involved: S1, sample the VSG grid-connected voltage and VSG grid-connected current, and calculate the VSG output active power P e and reactive power Q e ; S2, VSG active power command value P ref The VSG output active and reactive power value P e Subtract and get the active power error ΔP; The VSG reactive power command value Q ref and reactive power value Q e Subtract the active power error ΔP and the reactive power error ΔQ to obtain the effective value E0 and the phase angle θ0 of the potential inside the VSG; S3, introduce a feedforward branch at the active power error ΔP to generate a compensation phase angle θ1; introduce a feedforward SOGI branch at the active power error ΔP, and convert the output ΔP of SOGI β Multiply by the coefficient k d3 Then generate the compensation phase angle θ2; S4, adding the phase angle θ0 to the compensation phase angle θ1 and the compensation phase angle θ2 to obtain the final phase angle θ of the VSG; S5, the effective value of the potential E0 and the phase angle θ in the VSG are modulated by PWM, and the VSG switch tube drive signal K is output. PWM .

2. The power oscillation suppression method applicable to a multi-VSG converter parallel system according to claim 1, characterized in that: VSG internal potential effective value ΔU=U n -U e , U n , U e are the VSG output voltage reference command value and the actual value of the output voltage amplitude, D q is the reactive loop damping coefficient, k q is the reactive power regulation coefficient.

3. The power oscillation suppression method applicable to a multi-VSG converter parallel system according to claim 1, characterized in that: VSG phase angle ω n is the rated angular velocity of the multi-VSG converter parallel system, D p is the damping coefficient and J is the inertia coefficient.

4. The power oscillation suppression method applicable to a multi-VSG converter parallel system according to claim 1, characterized in that: The transfer function G of the feedforward branch is f (s) is expressed as: G f (s)=(k d1 s+k d2 ) / [(0.1Js 2 +3D p s+D p )(Js+D p )ω n ]; Among them, k d1 and k d2 is the feedforward parameter, J is the inertia coefficient, D p is the damping coefficient, s is a complex parameter, s = jω, j is an imaginary unit, ω n is the rated angular velocity of the multi-VSG converter parallel system.

5. The power oscillation suppression method applicable to a multi-VSG converter parallel system according to claim 4, characterized in that: k d1 =J-1,k d2 =-2D p 。 6. The power oscillation suppression method applicable to a multi-VSG converter parallel system according to claim 1, characterized in that: The transfer function G of the feedforward SOGI branch is q (s) is: Where Q(s) is the output side ΔP of the feedforward SOGI branch β The transfer function of ΔP on the input side, k s is the feedforward SOGI branch gain coefficient, k d3 is the differential coefficient.

7. The power oscillation suppression method applicable to a multi-VSG converter parallel system according to claim 1, characterized in that:

8. A power oscillation suppression system for a multi-VSG converter parallel system, comprising a memory, a processor and a computer program stored in the memory; characterized in that: The processor executes the computer program to implement the steps of the method according to any one of claims 1 to 7.

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