A dead time circuit and GaN driver chip

Abstract

This application provides a dead-time circuit and a GaN driver chip, relating to the field of power transistor driver circuit technology. When the drive source signal of a power transistor changes from indicating off to indicating on, the current generation module charges the capacitor module. The threshold trigger module's output signal flips only when the charge reaches the threshold. The output signal of the threshold trigger module is connected to the gate of the power transistor, and the charging time to the threshold is the dead time. When the drive signals of the high-side and low-side power transistors flip, the inductor in the load module stores energy, causing the current generation module to generate current. When the inductance in the load module changes, the current generated by the current generation module changes, thereby changing the charging time and dead time; that is, the dead time can change with the inductance of the load module.

Description

1. Technical Field

[0001] This application relates to the field of power transistor drive circuit technology, and in particular to dead-time circuits and GaN drive chips. 2 Background Technology

[0002] The numerous advantages of GaN devices have spurred the development of high-frequency, high-efficiency, and high-performance GaN driver chips, leading to the widespread application of GaN in power electronics. A basic structure of an enhanced GaN driver chip includes two channels: a high-side channel and a low-side channel. In high-voltage drive circuits, the high-side and low-side channels require independent gate drive circuits. Furthermore, the high-side requires a high-voltage isolation structure during manufacturing. These factors can cause a mismatch in the delay paths of the gate input signals of the high-side and low-side power transistors.

[0003] When a mismatch occurs in the delay between the high-side and low-side channels of the drive circuit, shoot-through may occur during commutation of the high-side and low-side power transistors. Therefore, a dead time is usually inserted between the gate drive signals of the high-side and low-side power transistors to ensure safe and reliable commutation. Dead time refers to the delay between the effective gate input signals of the high-side and low-side power transistors, which is the time during which neither the high-side nor low-side power transistors are turned on.

[0004] If the dead time is too long, it will cause reverse conduction loss in the power transistor; if the dead time is too short, shoot-through may occur, which generates a large current, i.e., hard switching loss.

[0005] Ideally, the dead time setting should vary with load conditions. Different loads have different optimal dead times, and designing a dead time circuit that adaptively adjusts the dead time according to load changes is a design challenge. 3. Summary of the Invention

[0006] The purpose of this application is to provide a dead-time circuit and a GaN driver chip to solve the technical problem of how to design a dead-time circuit that adaptively adjusts the size of the dead time according to the load.

[0007] To achieve the above objectives, one or more embodiments of this application adopt the following technical solutions.

[0008] In a first aspect, this application provides a dead-time circuit applied to a power transistor circuit. The power transistor circuit includes a bus, a high-side power transistor, and a low-side power transistor, which are connected sequentially to ground. The connection point between the high-side power transistor and the low-side power transistor is used to connect a load module. The load module includes an inductor.

[0009] The dead-time circuit includes a bootstrap module, a first current generation module, a first signal relay module, a first capacitor module, and a first threshold trigger module;

[0010] The first end of the bootstrap module is connected to the connection point of the high-side power transistor and the low-side power transistor. The second end of the bootstrap module is connected to the positive power supply terminal of the first current generation module, and the negative power supply terminal of the first current generation module is grounded. The current output terminal of the first current generation module is connected to the first end of the first capacitor module through the first signal relay module, and the second end of the first capacitor module is grounded.

[0011] The input terminal of the first signal relay module is used to connect to the drive signal source of the high-side power transistor;

[0012] The output terminal of the first signal relay module is connected to the first terminal of the first capacitor module;

[0013] The first terminal of the first capacitor module is connected to the input terminal of the first threshold trigger module;

[0014] The output of the first threshold trigger module is used to connect to the gate of the high-side power transistor;

[0015] When the voltage at the first terminal of the bootstrap module increases, the voltage at the second terminal of the bootstrap module also increases; when the voltage at the second terminal of the bootstrap module increases, the current generated by the first current generating module increases.

[0016] When the drive signal source of the high-side power transistor sends a signal to turn on the high-side power transistor, the first signal relay module charges the first capacitor module with the current generated by the first current generation module; when the voltage of the first capacitor module reaches the threshold of the first threshold trigger module, the output signal of the first threshold trigger module flips.

[0017] When the drive signal source of the high-side power transistor sends a signal to turn off the high-side power transistor, the first signal relay module causes the first capacitor module to discharge to ground; when the first capacitor module discharges until the voltage reaches the threshold of the first threshold trigger module, the output signal of the first threshold trigger module flips.

[0018] The following example, using one implementation method, illustrates the beneficial effects from a principle perspective:

[0019] In this embodiment, a low-level drive signal indicates that the power transistor is turned off, and a high-level drive signal indicates that the power transistor is turned on. When the voltage of the first capacitor module is higher than the threshold of the first threshold trigger module, the first threshold trigger module triggers a high-level output; when the voltage of the first capacitor module is lower than the threshold of the first threshold trigger module, the first threshold trigger module triggers a low-level output. The connection point voltage between the high-side power transistor and the low-side power transistor is denoted as V. SW ;

[0020] Assume that the drive signal of the high-side power transistor is low and the drive signal of the low-side power transistor is high. At this time, the first current generation module generates a certain current to power the first signal relay module, and the first signal relay module turns the first capacitor module to ground. Since the voltage of the first capacitor module is small, the first threshold trigger module does not trigger a high-level output. Therefore, the first threshold trigger module outputs a low level, which is transmitted to the high-side power transistor through the transfer circuit, and the high-side power transistor is turned off.

[0021] When the drive signal for the low-side power transistor transitions from high to low, the low-side power transistor is quickly turned off. Due to the freewheeling current in the inductor of the load module, V... SW It will rise rapidly to the bus voltage, V SW When a positive dv / dt is formed, and the voltage at the first terminal of the bootstrap module increases, the voltage at the second terminal of the bootstrap module also increases simultaneously. The current generated by the first current generation module increases, and the signal input to the first signal relay module becomes high. The first signal relay module uses the current generated by the first current generation module to charge the first capacitor module. When the voltage of the first capacitor module reaches the threshold of the first threshold trigger module, the output signal of the first threshold trigger module flips. This charging time is the high-side dead time. The charging time is related to the charging current of the first capacitor module, and the charging current is related to V. SW Related, V SW This is related to the inductance in the load module; that is, changes in the inductance, current, etc., in the load module will cause adaptive changes in the high-side dead time of the high-side power transistor.

[0022] In a second aspect, this application provides a dead-time circuit applied to the power transistor circuit described in the first aspect. The dead-time circuit includes a second current generation module, a second signal relay module, a second capacitor module, and a second threshold trigger module.

[0023] The connection point of the high-side power transistor and the low-side power transistor is connected to the negative power supply terminal of the second current generation module. The positive power supply terminal of the second current generation module is connected to the power supply. The current output terminal of the second current generation module is connected to the first terminal of the second capacitor module through the second signal relay module. The second terminal of the second capacitor module is grounded.

[0024] The input terminal of the second signal relay module is used to connect to the drive signal source of the low-side power transistor;

[0025] The output of the second signal relay module is connected to the first terminal of the second capacitor module;

[0026] The first terminal of the second capacitor module is connected to the input terminal of the second threshold trigger module;

[0027] The output of the second threshold trigger module is used to connect to the gate of the low-side power transistor;

[0028] When the voltage at the connection point between the high-side power transistor and the low-side power transistor drops, the current generated by the second current generation module increases.

[0029] When the drive signal source of the low-side power transistor sends a signal to turn on the low-side power transistor, the second signal relay module charges the second capacitor module with the current generated by the second current generation module; when the voltage of the second capacitor module reaches the threshold of the second threshold trigger module, the output signal of the second threshold trigger module flips.

[0030] When the drive signal source of the low-side power transistor sends a signal to turn off the low-side power transistor, the second signal relay module causes the second capacitor module to discharge to ground; when the second capacitor module discharges until the voltage reaches the threshold of the second threshold trigger module, the output signal of the second threshold trigger module flips.

[0031] Regarding the beneficial effects, the principle is similar to that described in the first aspect:

[0032] When the drive signal for the high-side power transistor transitions from high to low, the high-side power transistor is quickly turned off. Due to the freewheeling current in the inductor of the load module, V... SW It will drop rapidly, V SW A negative dv / dt is formed, the current generated by the second current generation module increases, and the signal input to the second signal relay module becomes high. The second signal relay module uses the current generated by the second current generation module to charge the second capacitor module. When the voltage of the second capacitor module reaches the threshold of the second threshold trigger module, the output signal of the second threshold trigger module flips. This charging time is the low-side dead time. The charging time is related to the charging current of the second capacitor module, and the charging current is related to V. SW Related, V SW This is related to the inductance in the load module; that is, changes in the inductance, current, etc., in the load module will cause adaptive changes in the low-side dead time.

[0033] Thirdly, this application provides a GaN driver chip, which includes the dead-time circuit described in the first or second aspect. The load module includes an inductor, for example, the load module includes a Buck circuit, and the Buck circuit includes an inductor. 4. Attached Figure Descriptions

[0034] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a schematic diagram of a power transistor circuit;

[0036] Figure 2 A schematic diagram of a high-side dead-time circuit provided in an embodiment of this application;

[0037] Figure 3 A schematic diagram of a low-side dead-time circuit provided in an embodiment of this application;

[0038] Figure 4 A bootstrap module provided in this application embodiment includes a bootstrap capacitor C. Boot and bootstrap diode D Boot A schematic diagram;

[0039] Figure 5 A schematic diagram illustrating how the same PWM signal generates opposite drive signals, as provided in an embodiment of this application;

[0040] Figure 6 A schematic diagram of a cut-through protection module provided in an embodiment of this application;

[0041] Figure 7 This is a schematic diagram of a first current generating module provided in an embodiment of this application;

[0042] Figure 8 This is a schematic diagram of a second current generating module provided in an embodiment of this application;

[0043] Figure 9 A schematic diagram illustrating the principle of high-side dead time provided in an embodiment of this application;

[0044] Figure 10 This is a schematic diagram illustrating the principle of low-side dead time in an embodiment of this application. 5. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. The described embodiments are only some embodiments of this application, not all embodiments. The components of the embodiments of this application described in the accompanying drawings can generally be arranged and designed in various different configurations.

[0046] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0047] In the description of this application, it should be noted that:

[0048] Relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations;

[0049] "Connection" should be interpreted broadly. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium.

[0050] like Figure 1 , Figure 1 This paper demonstrates a power transistor circuit, which can be a structure in an enhanced GaN driver chip. The power transistor circuit includes a bus and a high-side power transistor M. H and low-side power transistor M L V in the diagram BUS For bus voltage, bus, high-side power transistor M H and low-side power transistor M L Connect GND and ground in sequence; high-side power transistor M H and low-side power transistor M L The connection point is denoted as the switch node, and the voltage at the switch node is denoted as V. SW The switching node is used to connect the load module; the load module includes an inductor and a load.

[0051] The dead-time circuit of this application is applied to power transistor circuits. Figure 2 A high-side dead-time circuit is shown, which includes a bootstrap module, a first current generation module, a first signal relay module, a first capacitor module, and a first threshold trigger module.

[0052] The first terminal of the bootstrap module is connected to the connection point of the high-side power transistor and the low-side power transistor. The second terminal of the bootstrap module is connected to the positive power supply terminal of the first current generation module, and the negative power supply terminal of the first current generation module is grounded. When the voltage at the first terminal of the bootstrap module increases, the voltage at the second terminal of the bootstrap module also increases.

[0053] The current output terminal of the first current generating module is connected to the first terminal of the first capacitor module via the first signal relay module. When the voltage at the second terminal of the bootstrap module increases, i.e., the voltage at the positive power supply terminal of the first current generating module increases, the current generated by the first current generating module increases. The second terminal of the first capacitor module is grounded.

[0054] The input terminal of the first signal relay module is used to connect to the drive signal source of the high-side power transistor and receive the drive signal HIN of the high-side power transistor; the output terminal of the first signal relay module is connected to the first terminal of the first capacitor module; when the drive signal source of the high-side power transistor sends a signal to turn on the high-side power transistor, the first signal relay module charges the first capacitor module with the current generated by the first current generation module, and the current generated by the first current generation module affects the charging speed of the first capacitor module.

[0055] The first terminal of the first capacitor module is connected to the input terminal of the first threshold trigger module. When the first capacitor module is charged until the voltage reaches the threshold of the first threshold trigger module, the output signal of the first threshold trigger module flips. Conversely, when the drive signal source of the high-side power transistor sends a signal to turn off the high-side power transistor, the first signal relay module causes the first capacitor module to discharge to ground. When the first capacitor module discharges until the voltage reaches the threshold of the first threshold trigger module, the output signal of the first threshold trigger module flips.

[0056] The output of the first threshold trigger module is used to connect to the gate of the high-side power transistor. The output of the first threshold trigger module can be connected to the gate of the high-side power transistor through the high-side drive module.

[0057] The following describes the beneficial effects from a principle perspective, using one implementation as an example. In this implementation, a low-level drive signal indicates that the power transistor is turned off, and a high-level drive signal indicates that the power transistor is turned on. When the voltage of the first capacitor module is higher than the threshold of the first threshold trigger module, the first threshold trigger module triggers a high-level output; when the voltage of the first capacitor module is lower than the threshold of the first threshold trigger module, the first threshold trigger module triggers a low-level output. In other implementations, the high and low levels may be reversed.

[0058] Assume that the drive signal of the high-side power transistor is low and the drive signal of the low-side power transistor is high. At this time, the first current generation module generates a certain current to power the first signal relay module, and the first signal relay module turns the first capacitor module to ground. Since the voltage of the first capacitor module is small, the first threshold trigger module does not trigger a high-level output. Therefore, the first threshold trigger module outputs a low level, which is transmitted to the high-side power transistor through the transfer circuit, and the high-side power transistor is turned off.

[0059] When the drive signal for the high-side power transistor transitions from low to high, the low-side power transistor quickly turns off. Due to the freewheeling current in the inductor of the load module, V... SW It will rise rapidly to the bus voltage, V SWWhen a positive dv / dt is formed, and the voltage at the first terminal of the bootstrap module increases, the voltage at the second terminal of the bootstrap module also increases simultaneously. The current generated by the first current generation module increases, and the signal input to the first signal relay module becomes high. The first signal relay module uses the current generated by the first current generation module to charge the first capacitor module. When the voltage of the first capacitor module reaches the threshold of the first threshold trigger module, the output signal of the first threshold trigger module flips. This charging time is the high-side dead time. The charging time is related to the charging current of the first capacitor module, and the charging current is related to V. SW Related, V SW This is related to the inductance in the load module; that is, changes in the inductance, current, etc., in the load module will cause adaptive changes in the high-side dead time of the high-side power transistor.

[0060] The above high-side dead time circuit can achieve adaptive changes in the high-side dead time. Figure 3 A low-side dead time circuit that enables adaptive variation of the low-side dead time is demonstrated. The low-side dead time circuit includes a second current generation module, a second signal relay module, a second capacitor module, and a second threshold trigger module.

[0061] The connection point between the high-side power transistor and the low-side power transistor is connected to the negative power supply terminal of the second current generation module. The positive power supply terminal of the second current generation module is connected to the power supply VDD. The power supply VDD can simultaneously power the first current generation module, the first signal relay module, the first threshold trigger module, the second current generation module, the second signal relay module, and the second threshold trigger module. When the voltage at the negative power supply terminal of the second current generation module decreases, the output current of the second current generation module increases.

[0062] The current output terminal of the second current generating module is connected to the first terminal of the second capacitor module via the second signal relay module, and the second terminal of the second capacitor module is grounded.

[0063] The input terminal of the second signal relay module is used to connect to the drive signal source of the low-side power transistor and receive the drive signal LIN of the low-side power transistor; the output terminal of the second signal relay module is connected to the first terminal of the second capacitor module; when the drive signal source of the low-side power transistor sends a signal to turn on the low-side power transistor, the second signal relay module charges the second capacitor module with the current generated by the second current generation module, and the current generated by the second current generation module affects the charging speed of the second capacitor module.

[0064] The first terminal of the second capacitor module is connected to the input terminal of the second threshold trigger module. When the second capacitor module is charged until the voltage reaches the threshold of the second threshold trigger module, the output signal of the second threshold trigger module flips. Conversely, when the drive signal source of the low-side power transistor sends a signal to turn off the low-side power transistor, the second signal relay module causes the second capacitor module to discharge to ground. When the second capacitor module discharges until the voltage reaches the threshold of the second threshold trigger module, the output signal of the second threshold trigger module flips.

[0065] The output of the second threshold trigger module is used to connect to the gate of the low-side power transistor. The output of the second threshold trigger module can be connected to the gate of the low-side power transistor through the low-side drive module.

[0066] Similar to the high-side dead-time circuit, the principle of the low-side dead-time circuit is as follows:

[0067] When the drive signal for the low-side power transistor transitions from low to high, the high-side power transistor is quickly turned off. Due to the freewheeling current in the inductor of the load module, V... SW It will drop rapidly, V SW A negative dv / dt is formed, the current generated by the second current generation module increases, and the signal input to the second signal relay module becomes high. The second signal relay module uses the current generated by the second current generation module to charge the second capacitor module. When the voltage of the second capacitor module reaches the threshold of the second threshold trigger module, the output signal of the second threshold trigger module flips. This charging time is the low-side dead time. The charging time is related to the charging current of the second capacitor module, and the charging current is related to V. SW Related, V SW This is related to the inductance in the load module; that is, changes in the inductance, current, etc., in the load module will cause adaptive changes in the low-side dead time.

[0068] The high-side dead time circuit and the low-side dead time circuit mentioned above can be combined and applied to the power transistor circuit simultaneously.

[0069] like Figure 4 The dead-time circuit module comprises a first current generation module, a first signal relay module, a first capacitor module, a first threshold trigger module, a second current generation module, a second signal relay module, a second capacitor module, and a second threshold trigger module. The high-side drive module may include a level shifter and a buffer, and the low-side drive module may also include a level shifter and a buffer. Figure 4 In this context, the bootstrap module may include a bootstrap capacitor C. Boot and bootstrap diode D Boot Bootstrap diode D Boot The anode can be connected to the power supply VDD, and the bootstrap capacitor C Boot and bootstrap diode DBoot The connection point is the high-side floating source VDDH, and the bootstrap capacitor C. Boot and bootstrap diode D Boot The connection point voltage can be greater than the power supply VDD.

[0070] like Figure 5 , Figure 5 In the high-side delay adjustment module, there are a first signal relay module, a first capacitor module, and a first threshold trigger module. The low-side delay adjustment module includes a second current generation module, a second signal relay module, a second capacitor module, and a second threshold trigger module. A shoot-through protection module can be added to the input positions of the first and second signal relay modules. This shoot-through protection module prevents simultaneous high-level inputs to both modules. The shoot-through protection module may include logic gates. For example... Figure 6 The anti-straight-through protection module may include an XOR gate (XOR1), an AND gate (AND1), and an AND gate (AND2), and the output signals A1_OUT and A2_OUT are not simultaneously high.

[0071] like Figure 5 The drive signal HIN and the drive signal LIN can be formed by the same PWM signal. The PWM signal is passed through an NOT gate to form opposite signals to prevent the first signal relay module and the second signal relay module from being input with a high level at the same time.

[0072] Figure 7 An implementation of a first current generating module is illustrated. The first current generating module may include a first current branch, a second current branch, and a first bias current source (the current of the first bias current source is I). SET The first current branch includes MOSFETs MP1, NLD1, and MN1. MOSFET NLD1 is a high-voltage MOSFET. The capacitor C in the diagram... P1 The parasitic capacitance of NLD1 is defined. The second current branch includes MOSFET MN2, and the third current branch includes MOSFETs MP2 and MP3. MOSFETs MN1 and MN2 form a current mirror. MOSFET MN2 is connected in parallel with the first bias current source and then in series with MOSFET MP2. MOSFETs MP2 and MP3 form a current mirror.

[0073] The second current branch replicates the current of the first current branch. The current of the third current branch is equal to the sum of the currents of the second current branch and the first bias current source, denoted as Itotal_H. The third current branch outputs Itotal_H, which is connected to the first terminal of the first capacitor module via the first signal relay module.

[0074] Figure 8 An implementation of a second current generation module is illustrated. The second current generation module may include a fourth current branch, a fifth current branch, a second bias current source, and a sixth current branch. The fourth current branch includes MOSFETs MP4, NLD2, and MN5. MOSFET NLD2 is a high-voltage MOSFET. Capacitor C is shown in the figure. P2 The parasitic capacitance of NLD2 is used. The fifth current branch includes MOSFETs MP5, MN3, and MN4. The second bias current source can be the same as the first bias current source. The sixth current branch includes MOSFETs MP6 and MP7. MOSFETs MP4 and MP5 form a current mirror, as do MOSFETs MN3 and MN4. MOSFET MN4 is connected in parallel with the second bias current source and then in series with MOSFET MP6. MOSFETs MP6 and MP7 form a current mirror.

[0075] The fifth current branch replicates the current of the fourth current branch. The current of the sixth current branch is equal to the sum of the currents of the fifth current branch and the second bias current source; the sum of the currents of the fifth current branch and the second bias current source is denoted as Itotal_L. The fourth current branch connects to the junction of the high-side power transistor and the low-side power transistor; the sixth current branch outputs Itotal_L, which is connected to the first terminal of the second capacitor module via the second signal relay module.

[0076] like Figure 9 The first signal relay module may include a first inverter INV1 and a second inverter INV2.

[0077] The input of the first inverter INV1 receives the output signal of the AND gate AND1, which is equivalent to the drive signal source for the high-side power transistor. The power supply terminal of the first inverter is connected to the power supply VDD, and the ground terminal of the first inverter is grounded.

[0078] The output terminal of the first inverter INV1 is connected to the input terminal of the second inverter INV2. The power supply terminal of the second inverter INV2 is connected to the current output terminal of the first current generating module. The ground terminal of the second inverter INV2 is grounded. The output terminal of the second inverter INV2 is connected to the first terminal of the first capacitor module C1.

[0079] like Figure 9 The first threshold triggering module may include a third inverter INV3 and a fourth inverter INV4. The inverters have threshold triggering characteristics.

[0080] The input terminal of the third inverter INV3 is the input terminal of the first threshold trigger module and is connected to the first terminal of the first capacitor module C1; the power supply terminal of the third inverter INV3 is used to connect to the power supply VDD; the ground terminal of the third inverter INV3 is grounded.

[0081] The output of the third inverter INV3 is connected to the input of the fourth inverter INV4.

[0082] The power supply terminal of the fourth inverter INV4 is connected to the power supply; the ground terminal of the fourth inverter INV4 is grounded; the output terminal of the fourth inverter INV4 is the output terminal of the first threshold trigger module, which is used to connect to the gate of the high-side power transistor.

[0083] like Figure 9 The principle of high-side dead time is as follows:

[0084] Assuming the initial conditions are that the drive signal HIN is low and the drive signal LIN is high, the first inverter INV1 outputs a high level. At this time, the low-side transistor in the second inverter INV2 is turned on, providing a discharge path from the first capacitor module C1 to ground. Therefore, the second inverter INV2 outputs a low level. After passing through the third inverter INV3 and the fourth inverter INV4, the final output signal DT_H is low, and the high-side power transistor is off. Similarly, when the signal DT_L is high, the low-side power transistor will be on. At this time, V... SW =0;

[0085] When the drive signal HIN goes low and the drive signal LIN goes high, the half-bridge switching state changes from low-side power transistor to low-side power transistor to high-side power transistor. Due to the reverse freewheeling effect of the inductor in the external load module of the half-bridge, after the low-side power transistor is turned off, the switching node voltage V... SW It will rise rapidly to the bus voltage V BUS V SW This results in a positive dv / dt. This is due to the bootstrap capacitance C. Boot The existence of V SW The positive dv / dt formed on the high-side floating source VDDH is rapidly coupled to it, thus forming a dv / dt of the same magnitude on the high-side floating source VDDH. Since the gate and source terminals of MOSFET NLD1 are shorted, MOSFET NLD1 is normally closed. When a positive dv / dt is formed on VDDH, due to the parasitic capacitance C of MOSFET NLD1... P1 The presence of this parasitic current I flowing through the drain-source terminals of MOSFET NLD1 causes the gate voltage change of MOSFET MP1 to lag behind the high-side floating source VDDH. P1 The output current Itotal_H increases (Itotal_H = I P1 +I SETSince the first inverter INV1 outputs a low level, the high-side transistor in the second inverter INV2 is turned on. Current Itotal_H charges the first capacitor module C1 through the high-side transistor of the second inverter INV2. When the voltage across the first capacitor module C1 is charged to the threshold voltage V of the third inverter INV3... th The charging time is: Where C1 is the capacitance value of the first capacitor module C1, and the output level of the third inverter INV3 is flipped. This charging time is the high-side dead time.

[0086] When the external load changes, the switching node voltage V SW The dv / dt changes accordingly, the total detection current Itotal_H changes, and the charging time of the first capacitor module C1 also changes, realizing different dead times, thereby achieving the effect of adaptive high-side dead time.

[0087] like Figure 10 The second signal relay module includes a fifth inverter (INV5) and a sixth inverter (INV6), with the same connection structure as the first signal relay module. The second threshold trigger module includes a seventh inverter (INV7) and an eighth inverter (INV8), with the same connection structure as the first threshold trigger module.

[0088] like Figure 10 The principle of low-side dead time is as follows:

[0089] Assuming the initial conditions are that the drive signal HIN is high and the drive signal LIN is low, then the fifth inverter INV5 outputs a high level. At this time, the low-side transistor in the sixth inverter INV6 is turned on, providing a discharge path from the second capacitor module C2 to ground. Therefore, the sixth inverter INV6 outputs a low level. After passing through the seventh inverter INV7 and the eighth inverter INV8, the final output signal DT_L is low, and the high-side power transistor is in the off state. Similarly, when the signal DT_H is high, the low-side power transistor will be turned on. At this time, V SW Bus voltage V BUS ;

[0090] When the drive signal HIN goes high and the drive signal LIN goes low, the half-bridge switching state changes from high-side power transistor to low-side power transistor to turn on. Due to the energy storage effect of the inductor in the external load module of the half-bridge, after the high-side power transistor is turned off, the switching node voltage V... SW It will quickly drop to 0, V SW This results in a negative dv / dt. Since the gate and source terminals of MOSFET NLD2 are shorted, MOSFET NLD2 is normally closed. When V... SW When a negative dv / dt is formed, due to the parasitic capacitance C of the MOS transistor NLD2... P2Due to the presence of the MOSFET MN5, the gate voltage change lags behind the switching node voltage V. SW This will generate a parasitic current I flowing through the drain-source terminals of the MOSFET NLD2. P2 The output current Itotal_L increases (Itotal_L = I P2 +I SET Since the output of the fifth inverter INV5 is low, the high-side transistor in the sixth inverter INV6 is turned on. The current Itotal_L charges the second capacitor module C2 through the high-side transistor of the sixth inverter INV6. When the voltage across the second capacitor module C2 is charged to the threshold voltage V of the seventh inverter INV7... th The charging time is: Where C2 is the capacitance value of the second capacitor module C2, and the output level of the seventh inverter INV7 is flipped. This charging time is the low-side dead time.

[0091] When the external load changes, the switching node voltage V SW The dv / dt changes accordingly, the total detection current Itotal_L changes, and the charging time of the second capacitor module C2 also changes, realizing different dead times, thereby achieving the effect of low-side dead time adaptation.

[0092] Based on the above embodiments, this application also provides a GaN driver chip, which includes any of the dead-time circuits described above. The load module includes an inductor, for example, a Buck circuit, which in turn includes an inductor. When the drive source signal of a power transistor changes from indicating off to indicating on, the current generation module charges the capacitor module. The threshold trigger module's output signal flips only when the charge reaches the threshold. The output signal of the threshold trigger module is connected to the gate of the power transistor, and the charging time to the threshold is the dead time. When the drive signals of the high-side and low-side power transistors flip, the inductor in the load module stores energy, causing the current generation module to generate current. When the inductance in the load module changes, the current generated by the current generation module changes, thereby changing the charging time and dead time; that is, the dead time can change with the inductance of the load module.

[0093] The apparatus and system embodiments described above are merely illustrative. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement these embodiments without any creative effort.

[0094] The above are merely preferred embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A dead-time circuit, characterized in that, This is applied to a power transistor circuit, which includes a bus, a high-side power transistor, and a low-side power transistor, wherein the bus, the high-side power transistor, the low-side power transistor, and ground are connected in sequence; the connection point between the high-side power transistor and the low-side power transistor is used to connect a load module; the load module includes an inductor. The dead-time circuit includes a bootstrap module, a first current generation module, a first signal relay module, a first capacitor module, and a first threshold trigger module. The first end of the bootstrap module is connected to the connection point of the high-side power transistor and the low-side power transistor. The second end of the bootstrap module is connected to the positive power supply terminal of the first current generation module, and the negative power supply terminal of the first current generation module is grounded. The current output terminal of the first current generation module is connected to the first end of the first capacitor module through the first signal relay module, and the second end of the first capacitor module is grounded. The input terminal of the first signal relay module is used to connect to the drive signal source of the high-side power transistor; The output terminal of the first signal relay module is connected to the first terminal of the first capacitor module; The first terminal of the first capacitor module is connected to the input terminal of the first threshold trigger module; The output of the first threshold trigger module is used to connect to the gate of the high-side power transistor; When the voltage at the first terminal of the bootstrap module increases, the voltage at the second terminal of the bootstrap module also increases; when the voltage at the second terminal of the bootstrap module increases, the current generated by the first current generating module increases. When the drive signal source of the high-side power transistor sends a signal to turn on the high-side power transistor, the first signal relay module charges the first capacitor module with the current generated by the first current generation module; when the voltage of the first capacitor module reaches the threshold of the first threshold trigger module, the output signal of the first threshold trigger module flips. When the drive signal source of the high-side power transistor sends a signal to turn off the high-side power transistor, the first signal relay module causes the first capacitor module to discharge to ground; when the first capacitor module discharges until the voltage reaches the threshold of the first threshold trigger module, the output signal of the first threshold trigger module flips.

2. The dead-time circuit as described in claim 1, characterized in that, The bootstrap module includes a bootstrap capacitor and a bootstrap diode; The anode of the bootstrap diode is used to connect to a power supply, which is used to power the first current generation module, the first signal relay module, and the first threshold trigger module. The cathode of the bootstrap diode is connected to the first terminal of the bootstrap capacitor; The second end of the bootstrap capacitor is connected to the connection point of the high-side power transistor and the low-side power transistor; The first end of the bootstrap capacitor is the second end of the bootstrap module, which is connected to the power supply terminal of the first current generating module.

3. The dead-time circuit as described in claim 1, characterized in that, The first current generation module includes a first current branch, a second current branch, a first bias current source, and a third current branch; The second current branch is used to replicate the current of the first current branch; The current in the third current branch is equal to the sum of the currents in the second current branch and the first bias current source. The first current branch is connected between the second terminal of the bootstrap module and ground; The third current branch provides the current output terminal of the first current generating module, which is connected to the first terminal of the first capacitor module via the first signal relay module.

4. The dead-time circuit as described in claim 1, characterized in that, The first signal relay module includes a first inverter and a second inverter; The input terminal of the first inverter is the input terminal of the first signal relay module, used to connect to the drive signal source of the high-side power transistor; the power supply terminal of the first inverter is used to connect to the power supply, which is used to power the first current generation module, the first signal relay module and the first threshold trigger module; the ground terminal of the first inverter is grounded. The output terminal of the first inverter is connected to the input terminal of the second inverter; The power supply terminal of the second inverter is connected to the current output terminal of the first current generating module; the ground terminal of the second inverter is grounded; the output terminal of the second inverter is connected to the first terminal of the first capacitor module.

5. The dead-time circuit as described in claim 1, characterized in that, The first threshold triggering module includes a third inverter and a fourth inverter; The input terminal of the third inverter is the input terminal of the first threshold trigger module and is connected to the first terminal of the first capacitor module; the power supply terminal of the third inverter is used to connect to the power supply, which is used to power the first current generation module, the first signal conversion module and the first threshold trigger module; the ground terminal of the third inverter is grounded. The output terminal of the third inverter is connected to the input terminal of the fourth inverter; The power supply terminal of the fourth inverter is connected to the power supply. The ground terminal of the fourth inverter is grounded; the output terminal of the fourth inverter is the output terminal of the first threshold trigger module, and is used to connect to the gate of the high-side power transistor.

6. A dead-time circuit, characterized in that, This is applied to a power transistor circuit, which includes a bus, a high-side power transistor, and a low-side power transistor, wherein the bus, the high-side power transistor, the low-side power transistor, and ground are connected in sequence; the connection point between the high-side power transistor and the low-side power transistor is used to connect a load module; the load module includes an inductor. The dead-time circuit includes a second current generation module, a second signal relay module, a second capacitor module, and a second threshold trigger module. The connection point of the high-side power transistor and the low-side power transistor is connected to the negative power supply terminal of the second current generation module. The positive power supply terminal of the second current generation module is connected to the power supply. The current output terminal of the second current generation module is connected to the first terminal of the second capacitor module through the second signal relay module. The second terminal of the second capacitor module is grounded. The input terminal of the second signal relay module is used to connect to the drive signal source of the low-side power transistor; The output terminal of the second signal relay module is connected to the first terminal of the second capacitor module; The first terminal of the second capacitor module is connected to the input terminal of the second threshold trigger module; The output of the second threshold trigger module is used to connect to the gate of the low-side power transistor; When the voltage at the connection point between the high-side power transistor and the low-side power transistor drops, the current generated by the second current generating module increases. When the drive signal source of the low-side power transistor sends a signal to turn on the low-side power transistor, the second signal relay module charges the second capacitor module with the current generated by the second current generation module; when the voltage of the second capacitor module reaches the threshold of the second threshold trigger module, the output signal of the second threshold trigger module flips. When the drive signal source of the low-side power transistor sends a signal to turn off the low-side power transistor, the second signal relay module causes the second capacitor module to discharge to ground; when the second capacitor module discharges until the voltage reaches the threshold of the second threshold trigger module, the output signal of the second threshold trigger module flips.

7. The dead-time circuit as described in claim 6, characterized in that, The second current generation module includes a fourth current branch, a fifth current branch, a second bias current source, and a sixth current branch; The fifth current branch is used to replicate the current of the fourth current branch; The current in the sixth current branch is equal to the sum of the currents in the fifth current branch and the second bias current source. The fourth current branch connects the connection point of the high-side power transistor and the low-side power transistor. The sixth current branch provides the current output terminal of the second current generating module, which is connected to the first terminal of the second capacitor module via the second signal relay module.

8. The dead-time circuit as described in claim 6, characterized in that, The second signal relay module includes a fifth inverter and a sixth inverter; The input terminal of the fifth inverter is the input terminal of the second signal relay module, used to connect to the drive signal source of the low-side power transistor; the power supply terminal of the fifth inverter is used to connect to the power supply, which supplies power to the second current generation module, the second signal relay module, and the second threshold trigger module; the ground terminal of the fifth inverter is grounded. The output terminal of the fifth inverter is connected to the input terminal of the sixth inverter; The power supply terminal of the sixth inverter is connected to the current output terminal of the second current generating module; the ground terminal of the sixth inverter is grounded; the output terminal of the sixth inverter is connected to the first terminal of the second capacitor module.

9. The dead-time circuit as described in claim 6, characterized in that, The second threshold triggering module includes a seventh inverter and an eighth inverter; The input terminal of the seventh inverter is the input terminal of the second threshold trigger module and is connected to the first terminal of the second capacitor module; the power supply terminal of the seventh inverter is used to connect to the power supply, which is used to power the second current generation module, the second signal conversion module and the second threshold trigger module; the ground terminal of the seventh inverter is grounded. The output terminal of the seventh inverter is connected to the input terminal of the eighth inverter; The power supply terminal of the eighth inverter is connected to the power supply. The ground terminal of the eighth inverter is grounded; the output terminal of the eighth inverter is the output terminal of the second threshold trigger module, which is used to connect to the gate of the low-side power transistor.

10. A GaN driver chip, characterized in that, The GaN driver chip includes the dead-time circuit described in any one of claims 1 to 9.

Images