Selectable conversion ratio DC-to-DC converter

Abstract

A single integrated circuit DC-to-DC conversion solution can be combined with a product design that requires at least two different DC-to-DC conversion ratios, in particular with a product design that requires both a 2-divided DC-to-DC buck conversion ratio and a 3-divided DC-to-DC buck conversion ratio or both a 2-multiplied DC-to-DC boost conversion ratio and a 3-multiplied DC-to-DC boost conversion ratio. Embodiments are reconfigurable between first and second Dixon converter configurations for achieving at least a first conversion ratio and a second conversion ratio different therefrom, the first Dixon converter configuration includes two non-parallel capacitors (any one of the two non-parallel capacitors may be off-chip) and an associated controlled multi-phase switch, the second Dixon converter configuration includes a smaller number of equivalent capacitors than the first circuit configuration (which may be achieved by paralleling at least two non-parallel capacitors of the first configuration) and an associated controlled multi-phase switch.

Description

[0001] This application is a divisional application of invention patent application No. 201980018753.6, whose application date is March 6, 2019, international application number is PCT / US2019 / 021007, and which entered the Chinese national phase on September 11, 2020, and whose invention name is “Selectable Conversion Ratio DC to DC Converter”.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims priority to the following patent application: U.S. patent application serial number 15 / 920,327, filed on March 13, 2018, entitled “Selectable Conversion Ratio DC-DC Converter,” which is assigned to the assignee of the present invention, and its entire contents are incorporated by reference. background (1) Technical field

[0005] The present invention relates to electronic circuits and, more particularly, to DC to DC converter circuits. (2) Background technology

[0006] Many electronic products use lithium-ion (Li-Ion) batteries as a power source, especially mobile computing and / or communication products (e.g., notebook computers, ultrabook computers, and tablet devices). Li-Ion batteries are usually in the form of two or three series-connected battery cells (including parallel groups of such series-connected battery cells) with a nominal open circuit voltage of about 3V to 5V per battery cell, which depends mainly on the battery chemistry. Commonly available 2-cell Li-Ion batteries can provide an output voltage range of about 6V DC to 10V DC, while commonly available 3-cell Li-Ion batteries can provide an output voltage range of about 9V DC to about 15V-16V DC.

[0007] Many battery-operated electronic systems require multiple voltage levels. For example, a radio transmitter power amplifier may require a relatively high voltage (e.g., 12V or higher), while logic circuits may require a fairly low voltage level (e.g., 1V to 2V). But other circuits may require intermediate voltage levels (e.g., 5V to 10V).

[0008] DC-to-DC converters are commonly used to generate lower DC voltages or higher DC voltages from a DC power source. DC-to-DC converters that generate intermediate voltage levels and / or lower voltage levels from a higher voltage DC power source are often referred to as step-down converters, so called because V OUT Less than V IN , and thus the converter "steps down" the input voltage. DC-to-DC converters that generate voltage levels higher than the DC supply are often called boost converters, because V OUT Greater than V IN There are many options for creating buck and boost converters, including inductive circuits, capacitive circuits, and linear regulators (including low dropout (LDO) regulators), with size and efficiency being important differences between these options. For a typical step-down DC-to-DC converter, a large drop in input voltage (e.g., from 15V to 1.8V) in a single step-down conversion step is typically inefficient. In the case of an inductive buck converter, the large conversion ratio would require a fairly large inductor, which is typically unacceptable for many applications, particularly mobile applications. For a linear converter, such a large conversion ratio would be unacceptably inefficient.

[0009] Although the most efficient DC to DC converters usually require inductors, smaller converters can be implemented based on switched capacitor (SC) designs. Switched capacitor DC to DC converters do not require inductors and are therefore very suitable for mobile battery-powered applications. Switched capacitor DC to DC converters are typically integrated circuits (ICs) that can have some external components (e.g., capacitors), and in some cases switched capacitor DC to DC converters are characterized by having a fixed integer-based conversion ratio (e.g., 2- or 3-partitions) rather than a fractional conversion ratio. Decompression step-down SC DC to DC converters usually work according to the following principle: charging capacitors in series and then switching the capacitors to other configurations (e.g., parallel) to create a desired output voltage based on charge sharing between different configurations. A specific type of SC DC to DC converter is a Dickson converter, which is compact and very suitable for mobile applications that require an initial integer-based step-down conversion such as a 2- or 3-partition. Previous Dickson converters were only able to provide a single integer voltage divider ratio, which limited flexibility and increased inventory requirements for manufacturers. A general discussion of Dickson converter operation can be found, for example, in Technical Report No. UCB / EECS-2011-94, entitled “Switched Capacitor DC-DC Converter: Superior where the Buck Converter has Dominated,” by Vincent Wai-Shan Ng and Seth R. Sanders of the Department of Electrical Engineering and Computer Science at the University of California, Berkeley, dated August 17, 2011 (see specifically, for example, pages 8 to 11).

[0010] Figure 1 1 is a block diagram 100 of a prior art 2-cell battery 102 and an electronic system including a switched capacitor 2-voltage divider DC to DC converter 102. The 2-cell battery 102 provides a DC output voltage V that can be applied to a higher voltage circuit 106. HI Such a circuit may include a suitable voltage regulator for providing a uniform internal voltage. For a 2-cell battery 102 using Li-Ion technology, V HI Typically about 6V to 10V. The 2-way SC DC to DC converter 104 converts V HI The voltage is converted into an intermediate voltage V that can be applied to the intermediate voltage circuit 108 INT For a 2-cell battery 102 using Li-Ion technology, V INT Typically around 3V to 5V.

[0011] The output of the 2-way SC DC-to-DC converter 104 may optionally be further down-converted by one or more secondary DC-to-DC converters 110 to an even lower output voltage V LOW , for example 1V to 1.8V. When the INT To V LOW When the step-down ratio of V is relatively low, the secondary DC to DC converter 110 can be almost any type of inductive step-down DC to DC converter, capacitive step-down DC to DC converter, or linear step-down DC to DC converter. LOW Can be generated by a voltage regulator circuit such as an analog LDO regulator; an LDO regulator can output any voltage, but is generally inefficient.

[0012] Figure 2 2 is a block diagram 200 of a prior art 3-cell battery 202 and an electronic system including a switched capacitor 3-voltage divider DC to DC converter 204. Figure 1 Very similar, but due to the higher voltage of the 3-cell battery 202 (typically about 9V to about 15V-16V for Li-Ion technology), a 3-way DC to DC converter 204 must be used to obtain the same Figure 1 The V of the 2-cell battery 102 system INT (ie, approximately 3V to 5V) the same level.

[0013] For all DC to DC converters, efficiency is key to extending battery life and reducing system cost and weight. In particular, low cost is critical for many electronic components and systems. In addition, manufacturers of electronic products often desire flexible components that can be applied to more than one design without substantially sacrificing efficiency or increasing cost, such as a battery management system that can handle a battery system with 2 cells or a battery system with 3 cells. However, as Figure 1 and Figure 2 As shown, the number of battery cells in the system imposes restrictions on manufacturers using 2-voltage SC DC to DC converter ICs or 3-voltage SC DC to DC converter ICs due to such converters based on discrete integer voltage division ratios. Therefore, for various products, manufacturers must obtain, stock and manage the deployment of two separate SC DC to DC converter components to accommodate both 2-cell battery sizes and 3-cell battery sizes, all of which increase manufacturing costs.

[0014] Therefore, what is needed is a single chip solution that can be used in conjunction with a product design that requires at least two different DC to DC step-down conversion ratios. It would be useful if such a product could also allow for at least two different DC to DC step-up conversion ratios. Such a single chip solution can make costs lower and the acquisition and management of components easier. The present invention addresses these and other needs. Summary of the invention

[0015] The present invention encompasses a single chip solution that can be used in conjunction with a product design that requires at least two different DC to DC conversion ratios, specifically a product design that requires both a 2-way DC to DC step-down conversion ratio and a 3-way DC to DC step-down conversion ratio or a 2-fold DC to DC step-up conversion ratio and a 3-fold DC to DC step-up conversion ratio. The single chip solution encompassed by the present invention enables lower costs and easier acquisition and management of components.

[0016] Preferred embodiments of the present invention encompass novel switched capacitor DC / DC converters that can maintain high efficiency while providing a selectable integer voltage division ratio (specifically, a step-down conversion ratio of 2 or 3).

[0017] Many different circuits are disclosed that provide at least two different DC to DC conversion ratios. Embodiments are reconfigurable between a first configuration for achieving a first conversion ratio, wherein the first configuration includes at least two non-parallel capacitors (either of the two non-parallel capacitors may be off-chip) and associated controlled multiphase switches, and a second configuration for achieving a second conversion ratio different from the first conversion ratio, wherein the second configuration includes a smaller number of equivalent capacitors than the first circuit configuration (which may be achieved by connecting the at least two non-parallel capacitors of the first configuration in parallel) and associated controlled multiphase switches.

[0018] More specifically, preferred embodiments of the present invention encompass novel switched capacitor DC / DC converters that can maintain high efficiency while providing a selectable integer voltage divider ratio (specifically, a step-down conversion ratio of 2 or 3). One embodiment of the novel DC to DC conversion integrated circuit includes: a first circuit configuration that is capable of operating as a Dickson converter circuit to convert an applied input voltage to a first output voltage having a first conversion ratio relative to the applied input voltage; a second circuit configuration that is capable of operating as a Dickson converter circuit to convert the applied input voltage to a second output voltage having a second conversion ratio relative to the applied input voltage; a configuration element that is used to selectively configure the DC to DC conversion circuit to one of the first circuit configuration or the second circuit configuration; and a configurable clock signal control circuit coupled to the first circuit configuration and the second circuit configuration, the configurable clock signal control circuit selectively outputting a first set of clock signals for operating the first circuit configuration and a second set of clock signals for operating the second circuit configuration.

[0019] In some embodiments, in a first configuration, the selectable clock signal control circuit outputs a first clock signal phase to at least one switch of the switch array, the first capacitor is not connected in parallel with the second capacitor, and the switch array operates in response to respective application of the first clock signal phase and the second clock signal phase to periodically charge and discharge the first capacitor and the second capacitor to provide an output voltage having a first ratio relative to an input voltage at an output voltage terminal. In a second configuration, the selectable clock signal control circuit outputs a second clock signal phase to at least one switch of the switch array, the first capacitor is connected in parallel with the second capacitor, and the switch array operates in response to respective application of the first clock signal phase and the second clock signal phase to periodically charge and discharge the first capacitor and the second capacitor in parallel (i.e., substantially as a single larger capacitor) to provide an output voltage having a second ratio relative to the input voltage at the output voltage terminal, the second ratio being different from the first ratio.

[0020] In other embodiments, in a first configuration, wherein the first capacitor and the second capacitor are coupled to the switch array, and the first capacitor is not connected in parallel with the second capacitor, the switch array operates in response to respective application of a first clock signal phase and a second clock signal phase to periodically charge and discharge the first capacitor and the second capacitor to provide an output voltage having a first ratio relative to an input voltage at an output voltage terminal. In a second configuration, only one of the first capacitor and the second capacitor is coupled to the switch array, and the switch array operates in response to respective application of the first clock signal phase or the second clock signal phase or the first logic state or the second logic state to periodically charge and discharge the one capacitor coupled to the switch array to provide an output voltage having a second ratio relative to the input voltage at the output voltage terminal, the second ratio being different from the first ratio. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will become apparent from the description and drawings, and from the claims.

[0022] Figure 1 is a block diagram of a prior art 2-cell battery and an electronic system including a switched capacitor 2-voltage divider DC to DC converter.

[0023] Figure 2 is a block diagram of a prior art 3-cell battery and an electronic system including a switched capacitor 3-way DC to DC converter.

[0024] Figure 3A is a schematic diagram of a 2-voltage Dickson converter of the prior art.

[0025] Figure 3B is with Figure 3A The circuit shown is used in conjunction with a timing diagram of a multi-phase clock signal having two phases.

[0026] Figure 4 is a schematic diagram of a prior art 3-voltage Dickson converter.

[0027] Figure 5 is a schematic diagram of a first embodiment of a selectable conversion ratio DC to DC converter.

[0028] Figure 6 is a schematic diagram of a variable phase clock generation circuit for generating a selectable clock signal Px.

[0029] Figure 7 is a schematic diagram of a second embodiment of a selectable conversion ratio DC to DC converter.

[0030] Fig. 8A is a schematic diagram of a third embodiment of a selectable conversion ratio DC to DC converter.

[0031] Figure 8B A simple circuit is shown that outputs either input clock phase Pn (ie, P1 or P2) or a logic "1" based on the state of the SELECT signal.

[0032] Figure 8C A simple circuit is shown that outputs either input clock phase Pn (ie, P1 or P2) or a logic "0" based on the state of the SELECT signal.

[0033] Fig.9A is a schematic diagram of a fourth embodiment of a selectable conversion ratio DC to DC converter in a 3-voltage divider Dickson converter configuration.

[0034] Fig. 9B yes Fig.9A Schematic diagram of a fourth embodiment of a selectable conversion ratio DC to DC converter, but in a 2-divider Dickson converter configuration.

[0035] Fig.10 is a process flow diagram depicting a first method for DC to DC conversion.

[0036] Fig.11 is a process flow diagram depicting a second method for DC to DC conversion.

[0037] Like reference numbers and designations in the various drawings indicate like elements. DETAILED DESCRIPTION

[0038] The present invention encompasses a single chip solution that can be used in conjunction with a product design that requires at least two different DC to DC conversion ratios, specifically a product design that requires both a 2-way DC to DC step-down conversion ratio and a 3-way DC to DC step-down conversion ratio or a 2-fold DC to DC step-up conversion ratio and a 3-fold DC to DC step-up conversion ratio. The single chip solution encompassed by the present invention enables lower costs and easier acquisition and management of components.

[0039] Preferred embodiments of the present invention encompass novel switched capacitor DC / DC converters that can maintain high efficiency while providing a selectable integer voltage divider ratio (specifically, a step-down conversion ratio of 2 or 3). One embodiment of the novel DC to DC conversion integrated circuit includes: a first circuit configuration that is capable of operating as a Dickson converter circuit to convert an applied input voltage to a first output voltage having a first conversion ratio relative to the applied input voltage; a second circuit configuration that is capable of operating as a Dickson converter circuit to convert the applied input voltage to a second output voltage having a second conversion ratio relative to the applied input voltage; a configuration element that is used to selectively configure the DC to DC conversion circuit to one of the first circuit configuration or the second circuit configuration; and a configurable clock signal control circuit coupled to the first circuit configuration and the second circuit configuration, the configurable clock signal control circuit selectively outputting a first set of clock signals for operating the first circuit configuration and a second set of clock signals for operating the second circuit configuration.

[0040] Since the architecture for embodiments of the present invention is a switched capacitor (SC) design based on a novel hybrid variation of the Dickson converter topology, a better understanding of the conventional Dickson converter topology will help in understanding how to make and use embodiments of the present invention.

[0041] 2-Divider Dickson Converter Topology

[0042] Figure 3A FIG. 1 is a schematic diagram of a prior art 2-way Dickson converter 300. The converter 300 shown includes a voltage source V coupled to the IN Two parallel cells 302a, 302b are connected to a reference potential 304, such as circuit ground. Each cell 302a, 302b includes four switches 306a1 to 306a4, 306b1 to 306b4 connected in series. Each switch can be, for example, one or more field effect transistors (FETs), such as one or more MOSFETs.

[0043] Each switch 306 a 1 to 306 a 4 , 306 b 1 to 306 b 4 is coupled to one of the two clock phases P 1 or P 2 . Figure 3B is with Figure 3A The circuit shown incorporates a timing diagram 350 for use with a multi-phase clock signal having two phases; generally, the pulses of phases P1 and P2 should not overlap.

[0044] focus on Figure 3AIn the left cell 302a shown, capacitor C1a is coupled between the upper alternating phase pair (P1, P2) switches 306a1, 306a2 and the lower alternating phase pair (P1, P2) switches 306a3, 306a4. In operation, when the P1 switch is closed, the pair is coupled to the output node V OUT The output capacitor C OUT The series capacitor C1a is charged. The capacitor C1a is charged until the intermediate voltage V INT =V IN -V OUT , and maintain at V INT When the P1 switch is turned off and the P2 switch is turned on, the capacitor C1a is connected to the V OUT The output capacitor C OUT placed in parallel; therefore, the charge on capacitor C1a is provided to the output node V OUT , so that C OUT This process is repeated with each full clock cycle. Applying Kirchhoff's Current Law (KCL) to the nodes of the arrangement shows that in the steady state, V OUT Will remain at V IN / 2 - that is, make V OUT The voltage at the input is converted to V IN The conversion ratio is 2:1.

[0045] In addition to the fact that the polarity of switches 306b1 to 306b4 of right unit 302b is 180° out of phase with respect to switches 306a1 to 306a4 of left unit 302a, Figure 3A The layout of the right cell 302b is shown to be substantially the same as the left cell 302a. Thus, for example, the clock signal applied to the switch 306b1 in the cell 302b is P2, while the clock signal applied to the switch 306a1 in the cell 302a is P1.

[0046] 3-Divider Dickson Converter Topology

[0047] Figure 4 is a schematic diagram of a prior art 3-way Dickson converter 400. The converter 400 shown is based on Figure 3A The converter 300 operates on the same principle, but each complementary unit 402a, 402b has three additional switches and one additional capacitor. More specifically, focus on Figure 4The left unit 402a shown, the unit 402a includes three switches 406a1 to 406a3 connected in series, the three switches 406a1 to 406a3 connected in series are coupled in series to a first branch, the first branch includes two switches 406a4 and 406a5 connected in series, and the three switches 406a1 to 406a3 connected in series are coupled in series to a second branch, the second branch includes two switches 406a4' and 406a5' connected in series. Each switch can include, for example, one or more FETs, the one or more FETs including one or more MOSFETs. Each switch is coupled to one of the two complementary clock phases P1 or P2.

[0048] The first capacitor C1a is coupled between the first upper alternating phase pair (P1, P2) switches 406a1, 406a2 and the first branch alternating phase pair (P1, P2) switches 406a4, 406a5. The second capacitor C2a is coupled between the second upper alternating phase pair (P2, P1) switches 406a2, 406a3 and the second branch alternating phase pair (P2, P1) switches 406a4', 406a5'.

[0049] In this example, the converter 400 is connected via three capacitors (eg, C1a, C2a, and C OUT ) V IN The voltage is divided into V OUT =V IN / 3 output voltage. In addition to the additional capacitor C2a charging in series with capacitor C1a, the operation is similar to Figure 3A The converter 300 is similar to the above, thereby increasing the voltage division ratio and reducing the output voltage to V IN / 3, the conversion ratio is 3:1.

[0050] Except that the polarity of the switches of the right unit 402b is 180° out of phase with respect to the switches of the left unit 402a, Figure 4 The layout of the right unit 402b is shown to be substantially the same as the left unit 402a (reference numerals in the right unit 402b have been omitted to avoid confusion).

[0051] DC to DC converter with selectable conversion ratio

[0052] It should be clear that Figure 3A The fixed 2-way Dickson converter 300 with Figure 4The fixed 3-way Dickson converter 400 is substantially different, and the fixed 2-way Dickson converter 300 and the fixed 3-way Dickson converter 400 are not interchangeable. An object of the present invention is to disclose a single circuit that can be operated in such a manner as to provide at least two different DC to DC conversion ratios, in particular, a single circuit that can be operated in such a manner as to provide integer-based conversion ratios, and more particularly, both a 2-way DC to DC step-down conversion ratio and a 3-way DC to DC step-down conversion ratio, or both a 2x DC to DC step-up conversion ratio and a 3x DC to DC step-up conversion ratio.

[0053] Many different circuits are disclosed that provide at least two different DC to DC conversion ratios. In the most general case, an embodiment is reconfigurable between a first configuration operated to achieve a first conversion ratio and a second configuration operated to achieve a second conversion ratio different from the first conversion ratio, wherein the first configuration includes at least two non-parallel capacitors (either of the two non-parallel capacitors can be off-chip) and associated controlled multiphase switches, and the second configuration includes a smaller number of equivalent capacitors than the first circuit configuration (which can be achieved by connecting at least two non-parallel capacitors of the first configuration in parallel) and associated controlled multiphase switches.

[0054] First embodiment

[0055] Figure 5 is a schematic diagram of a first embodiment of a selectable conversion ratio DC to DC converter 500. In particular, the specifically illustrated converter 500 can be selectively configured as a 2-way Dickson converter or a 3-way Dickson converter using the same basic circuit. The same converter 500 can be used for DC to DC boost conversion by inverting the voltage input and voltage output.

[0056] As shown, in addition to each unit 502a, 502b including the added corresponding configuration elements 504a, 504b and the alternative "DIV3" conductor and "DIV2" conductor (which have been omitted), Figure 4 In addition to the reference numerals in the figure to avoid confusion), the layout of the switch array controlled by the clock signals P1 and P2 and the layout of the capacitors C1a, C2a, C1b, C1b are similar to Figure 4 The 3-way Dickson converter 400 is substantially the same. In addition, in unit 502a, the voltage is directly coupled to V IN The switch 506a is controlled by the selectable clock signal Px, and in the complementary unit 502b, is directly coupled to V IN The switch 506b is selected by the complementary clock signal control.

[0057] When the configuration elements 504a, 504b are configured to couple the respective capacitors C1a, C1b to the corresponding DIV3 conductors, and the phase of the clock signal Px is set to be the same as P1 in the cell 502a, and the complementary clock signal When the phase of is set to be the same as P2 in unit 502b, the converter 500 is Figure 4 The conventional converter 400 operates in exactly the same manner as a 3-divider Dickson converter circuit; therefore, V OUT =V IN / 3.

[0058] When the configuration elements 504a, 504b are configured to couple the respective capacitors C1a, C1b to the corresponding DIV2 conductors, then the capacitor C1x is connected in parallel with the C2x capacitor of the other cell. Thus, in the example shown, the capacitor C1a in the cell 502a is coupled in parallel with the capacitor C2b in the cell 502b, and the capacitor C1b in the cell 502b is coupled in parallel with the capacitor C2a in the cell 502a. Furthermore, in the DIV2 configuration, the phase of the clock signal Px is set to be the same as P2 in the cell 502a (rather than the same as P1 in the DIV3 configuration), and the complementary clock signal The phase of is set to be the same as P1 in cell 502b (rather than the same as P2 in the DIV3 configuration). So configured, the parallel arrangement of two capacitors (e.g., C1a and C2b or C1b and C2a) effectively forms a single equivalent capacitor and thereby eliminates the need for a second independent capacitor in each cell 502a, 502b of the converter 500. Thus, the converter 500 is configured in the same manner as Figure 3A The conventional converter 300 operates in exactly the same manner as a 2-divider Dickson converter circuit, and therefore, V OUT =V IN / 2. Note that Figure 3A Compared to the conventional converter 300 , the 2-divider configuration of the illustrated embodiment has increased current capacity due to the parallel coupling of capacitors C1a and C2b and the parallel coupling of capacitors C1b and C2a.

[0059] Figure 6 FIG. 6 is a schematic diagram of a variable phase clock generation circuit 600 for generating a selectable clock signal Px. Complementary signals P1 and P2 (eg, Figure 3BThe SELECT signal is coupled to the other input of the AND gate 602 and the SELECT signal is coupled to the other input of the AND gate 604 after passing through the inverter 606. The outputs of the AND gates 602 and 604 are coupled to the OR gate 608, the output of which is Px; another inverter 610 generates a complementary When SELECT is a logic 1, then Px tracks the state of P1 (i.e., Px=0 when P1=0, and Px=1 when P1=1). Conversely, when SELECT is a logic 0, then Px tracks the state of P2 (i.e., Px=0 when P2=0, and Px=1 when P2=1). It should be clear that Figure 6 The circuit of is essentially a simple multiplexer, and there are many other ways to "swap" the P1 and P2 clock signals of switches 506a, 506b as needed for the DIV2 and DIV3 configurations of converter 500.

[0060] For a particular conversion configuration, the SELECT signal may be statically set (e.g., permanently connected to a voltage ground or to a circuit ground, not shown), or selectively set (e.g., using a mechanical switch or an electronic switch, not shown), or dynamically set under program control (circuitry not shown) for a particular implementation. Note that dynamically setting the SELECT signal requires that the circuit connection of the capacitors (e.g., C1a, C1b) may also be dynamically configured to a DIV2 or DIV3 configuration.

[0061] Refer again Figure 5 , in DIV2 configuration, coupled to V IN The switches 506a, 506b of the DIV3 configuration operate with a cycle opposite to that of the DIV3 configuration. Thus, for example, in the DIV3 configuration, for switch 506a, Px tracks P1, and for switch 506b, Tracks P2. Conversely, in the DIV2 configuration, for switch 506a, Px tracks P2, and for switch 506b, Tracking P1. Thus selectively changing the phase of switches 506a, 506b for DIV2 configuration substantially eliminates the independent directly connected series switches in their respective switch groups, since there are now two P1 or two P2 switches in series operating on the same clock phase. Thus, for example, focusing on Figure 5 In cell 502a, when Px tracks P2 for switch 506a, then switches 506a and 508a switch simultaneously and thus effectively operate as a single switch. Similarly, when Px tracks P2 for switch 506b, When tracking P1, switches 506b and 508b switch simultaneously and thus again effectively operate as a single switch.

[0062] Configuration elements 504a, 504b may be implemented as wired connections (e.g., jumpers or printed circuit board conductive traces disposed between pairs of externally accessible connection terminals of an integrated circuit—essentially zero-ohm resistors) so that converter 500 may be set to a particular DC-to-DC conversion ratio at system manufacturing time (e.g., when an IC including converter 500 is adhered to a printed circuit board, etc.). As an alternative, configuration elements 504a, 504b may be implemented as mechanical single-pole double-throw (SPDT) switches (including micro-electromechanical systems [MEMS] switches) so that the configuration of converter 500 may be manually selected. As another alternative, configuration elements 504a, 504b may be implemented as SPDTs implemented using transistor switching devices such as field effect transistors (FETs). While the case where configuration elements 504a, 504b may be implemented as SPDTs using transistor switching devices such as field effect transistors (FETs) would enable dynamic or programmed switching between conversion ratio configurations, the additional series impedance due to such switching devices may adversely affect efficiency.

[0063] It will be appreciated that by making two different configurations for coupling capacitors C1a and C2a, and by providing a selectable clock signal Px and its complement A single circuit can provide two different conversion ratios. Other combinations of voltage divider ratios can be used, such as 3-divider and 4-divider, and the concept can be extended to a single circuit that can provide more than two different conversion ratios.

[0064] The complementary phasing of the pair of cells 502a, 502b provides output ripple smoothing and additional current capacity. It should be clear that additional cells may be included to provide even greater current capacity. The complementary pair of additional cells may be controlled by a clock signal phase that is 180° apart and has a different phase than P1 or P2 to provide even greater output ripple smoothing (e.g., 45° or 60° - or multiples of 45° or 60° - out of phase with respect to P1 and P2). Thus, Figure 3B The two-phase clock of is just one example of a multi-phase clock.

[0065] Although directly coupled to V IN The switches 506a, 506b are shown as being driven by selectable clock signals Px and However, in a variant embodiment, other switches in each unit 502a, 502b can be replaced by selectable clock signals Px and Controls to achieve the same functionality.

[0066] Although Figure 5 An embodiment is shown in which the connections to capacitors C1a and C1b may be reconfigured, but the invention encompasses embodiments in which the connections to capacitors C2a and C2b may instead be reconfigured by making appropriate shifts in the phases of the clock signals applied to particular switches.

[0067] In an alternative embodiment, for the DIV2 configuration, capacitors C1a and C1b are not cross-connected to capacitors C2b and C2a, respectively. Instead, capacitors C1a and C1b are simply left disconnected—that is, configuration elements 504a, 504b present a single-pole single-throw (SPST) connection that connects or disconnects capacitors C1a and C1b in the DIV3 configuration. In this alternative embodiment, the selectable clock signal Px and Set to the corresponding configuration: DIV3 (when capacitors C1a and C1b are in the circuit) or DIV2 (when capacitors C1a and C1b are out of the circuit). However, when in the DIV2 configuration, if capacitors C1a and C1b are present, the efficiency of this alternative embodiment will be lower because capacitors C1a and C1b do not serve a purpose.

[0068] Second embodiment

[0069] Figure 7 is a schematic diagram of a second embodiment of a selectable conversion ratio DC to DC converter 700. In particular, the specifically illustrated converter 700 can be selectively configured to have a 2-way DC to DC step-down conversion ratio or a 3-way DC to DC step-down conversion ratio using the same circuit. The same converter 700 can be used for DC to DC step-up conversion by inverting the voltage input and voltage output.

[0070] As shown, each unit 502a, 502b includes a corresponding configuration element 704a, 704b added (instead of Figure 5 In addition to the configuration elements 504a, 504b shown in FIG. 1 and the alternative "DIV3" conductor and "DIV2" conductor, the layout of the switches controlled by the clock signals P1 and P2 and the layout of the capacitors C1a, C2a, C1b, C1b are similar to Figure 5 The converter 500 is substantially the same as the converter 500 of FIG. 502a. Focusing on the cell 502a, the capacitor C1a can be selectively coupled to the first branch 706a (for a 3-way voltage configuration) or to the second branch 708a (for a 2-way voltage configuration) by means of the configuration element 704a. In addition, the capacitor C1a is directly coupled to V IN The switch 506a is controlled by the selectable clock signal Px, and in unit 502b, is directly coupled to V INThe switch 506b is selected by the complementary clock signal Complementary cell 502b is similarly configured, but for the opposite clock phase.

[0071] In this alternative embodiment, in the DIV2 configuration, capacitor C1a is coupled in parallel with capacitor C2a within its own cell 502a, and there is no such a connection between cells 502a, 502b. Figure 5 However, in a variation of this embodiment, when in the DIV2 configuration, for better current distribution, as shown by the dotted curve, nodes ① and ③ should be interconnected, and nodes ② and ④ should be interconnected.

[0072] Although Figure 7 An embodiment is shown in which the connections to capacitors C1a and C1b may be reconfigured, but the invention encompasses embodiments in which the connections to capacitors C2a and C2b may instead be reconfigured by appropriate shifts in the phase of those control signals applied to particular switches.

[0073] Third embodiment

[0074] Fig. 8A is a schematic diagram of a third embodiment of a selectable conversion ratio DC to DC converter 800. In particular, the specifically illustrated converter 800 can be selectively configured to have a 2-way DC to DC step-down conversion ratio or a 3-way DC to DC step-down conversion ratio using the same circuit. The same converter 800 can be used for DC to DC step-up conversion by inverting the voltage input and voltage output.

[0075] In this example, in the DIV3 configuration, all capacitors (C1a, C2a, C1b, and C2b) are connected (or "mounted" if external to the IC). In this specific example, at least capacitors C2a and C2b are mounted to terminals 802a, 804a and 802b, 804b, respectively, which are externally accessible to the IC containing the rest of the DC to DC converter circuitry, including its switches. When in the DIV3 configuration, all switches are connected in a manner similar to the DIV3 configuration. Figure 5 The converter 500 responds to the P1 and P2 clock signals in the same manner (the two switches 810a, 810b are shown as closed, but this forced state is used for the DIV2 configuration described below).

[0076] For the DIV2 configuration, capacitors C2a and C2b are not mounted to respective terminals 802a, 804a and 802b, 804b. Alternatively, capacitor C2a may be coupled to one of respective terminals 802a, 804a instead of both terminals 802a, 804a, and capacitor C2b may be coupled to one of respective terminals 802b, 804b instead of both terminals 802b, 804b, thereby creating an open circuit and effectively switching the mounted capacitors out of the circuit. Additionally, in each cell 502a, 502b, switches 810a, 810b are forced closed (as shown), while one or both switches of branches 812a, 812b connected to terminals 804a, 804b, respectively, are forced open (as shown). Figure 5 and Figure 7 In contrast to the embodiment of the present invention, the circuit for directly connecting to V IN The switch is controlled by a clock signal.

[0077] Figure 8B A simple circuit is shown that outputs either input clock phase Pn (ie, P1 or P2) or a logic "1" based on the state of the SELECT signal. Figure 8C A simple circuit is shown that outputs either input clock phase Pn (ie, P1 or P2) or a logic "0" based on the state of the SELECT signal.

[0078] For example, you can use Figure 8B An example of a circuit of providing a clock signal to switch 810a by applying P1 to the input of AND gate 820 can be obtained by Figure 8B Another example of a circuit of the invention provides a clock signal to switch 810b by applying P2 to the input of AND gate 820. When the SELECT signal is set to "1" (i.e., the code assigned to the DIV3 configuration), then the output of the corresponding NOR gate 822 will track the state of the input, which is P1 in one case and P2 in another case. When the SELECT signal is set to "0" (i.e., the code assigned to the DIV2 configuration), then the inverter 824 will force the output of the NOR gate 822 of each such circuit example to a logic "1", thereby forcing the corresponding switches 810a, 810b to a closed state.

[0079] Similarly, we can use Figure 8CThe circuit provides a clock signal to one or both switches of branches 812a, 812b by applying the associated clock signal (P1 or P2) to the corresponding instance of the input of AND gate 830. When the SELECT signal is set to "1" (i.e., the code assigned to the DIV3 configuration), then the output of AND gate 830 will track the state of the input, which can be P1 or P2 as the case may be. When the SELECT signal is set to "0" (i.e., the code assigned to the DIV2 configuration), then the output of AND gate 830 of each such circuit instance is forced to a logic "0", thereby forcing the corresponding switch of branches 812a, 812b to an open state.

[0080] As with the above-described embodiments, for a particular configuration, the SELECT signal may be statically set (e.g., permanently connected to a voltage ground or to a circuit ground, not shown), or selectively set (e.g., using a mechanical switch or an electronic switch, not shown), or dynamically set under program control (circuitry not shown) for a particular embodiment.

[0081] Although Fig. 8A An embodiment is shown in which capacitors C2a and C2b may be omitted to create a DIV2 configuration, but a DIV2 configuration may also be created by maintaining capacitors C2a and C2b and omitting capacitors C1a and C1b instead by making appropriate changes with respect to which switches are forced open or closed.

[0082] Fourth embodiment

[0083] Fig.9A is a schematic diagram of a fourth embodiment of a selectable conversion ratio DC to DC converter 900 in a 3-way Dickson converter configuration. Fig. 9B yes Fig.9A Schematic diagram of a fourth embodiment of a selectable conversion ratio DC to DC converter 900 but in a 2-way Dickson converter configuration. Note that this fourth embodiment does not require changes to any off-chip (i.e., on-board) components or connections, nor does it require the use of additional switches to connect or disconnect components. This is a key advantage of this fourth embodiment compared to the above embodiments. In particular, the specifically shown converter 900 can be selectively configured to have a 2-way or 3-way DC to DC step-down conversion ratio using the same circuit and without any component changes at the board level. By reversing the voltage input and voltage output, the same converter 900 can be used for DC to DC step-up conversion. In the example shown, in addition to connecting all capacitors (C1a, C2a, C1b, C2b) (if external to the IC, all capacitors (C1a, C2a, C1b, C2b) are "installed"). Fig. 8A same.

[0084] exist Fig.9A In the DIV3 configuration, all switches are Fig. 8A 800 responds to the P1 and P2 clock signals in the same manner. Thus, focusing on the left cell 502a, switches S1, S3, S4, and S7 are controlled by the P1 clock signal, while switches S2, S5, and S6 are controlled by the P2 clock signal. The corresponding switches of the right cell 502b are completely opposite in configuration and clock signal phasing, and are essentially mirror images of the left cell 502a. Thus, the converter 900 operates as a 3-way Dickson converter circuit, where V OUT =V IN / 3. Note that the output voltage Vout is configured to be coupled to, for example, Figure 5 An external output capacitor (not shown) in (e.g., Cout).

[0085] In the DIV2 configuration, the phases of the P1 and P2 clock signals applied to switches S1, S4 and S6 in both cells 502a, 502b are inverted. Fig. 9B This is indicated in the left cell 502a by using a "P1" switch symbol for the S6 switch and a "P2" switch symbol for the S1 switch and the S4 switch. Note that this is only a change in the polarity of the clock signal applied to some of the switches, not a change in the physical switches. Figure 6 The variable phase clock generation circuit 600 is used, for example, to exchange P1 and P2 clock signals.

[0086] Thus, focusing on the left cell 502a, switches S1 and S4 respond to the P2 clock signal instead of the P1 clock signal, and the S6 switch responds to the P1 clock signal instead of the P2 clock signal. Thus, in the DIV2 configuration for the left cell 502a, switches S3, S6, and S7 are controlled by the P1 clock signal, while switches S1, S2, S4, and S5 are controlled by the P2 clock signal. Furthermore, the corresponding switches of the right cell 502b are completely opposite in configuration and clock signal phasing, essentially mirroring the left cell 502a. Thus, the converter 900 operates as a 2-divider Dickson converter circuit, where V OUT =V IN / 2.

[0087] Without changing any off-chip (ie, on-board) components or connections or without additional switches for connecting or disconnecting components, Fig.9A and Fig. 9B Described in Fig.9A The DIV3 converter is Fig. 9BThe switch and phase arrangement required to switch between the DIV2 converters of FIG. 1 and FIG. 2 is similar, but this implementation requires slightly more complexity in the clock signal generation and routing circuitry. The main problem arises from the fact that the switch driver circuits need to float along with the switches they drive - that is, the power supplies for the drivers of switches S1 and S4 may also need to be changed to ensure that the appropriate bias is supplied to these floating supplies.

[0088] As is known in the art, a typical driver circuit for a FET switch has V SS and V DD Voltage input. For Fig.9A The DIV3 circuit for the driver of switch S1 will make the driver's V SS The input is connected to the voltage at the top node 902 of capacitor C2b of cell 502b, and the driver for switch S4 will make the driver's V DD The input is connected to the voltage at the top node 904 of capacitor C1a ("top" refers to the orientation of schematic 900, with Vin at the top and ground at the bottom). However, when changing the phase of switches S1, S4, and S6 to Fig.9A The DIV3 configuration is changed to Fig. 9B The DIV2 configuration will adjust V SS and V DD Specifically, when the phase for switch S4 changes from P1 to P2 for DIV2 operation, V for the switch S4 driver DD The supply will need to be changed from the top node 904 of capacitor C1a to the top node 906 of capacitor C2a (while still being able to drive switch S4 "on" during the "on portion" of phase P2, of course). The same applies to switch S1, i.e., V for switch S1 drive SS The supply will need to be changed from the top node 902 of capacitor C2b to the top node 908 of capacitor C1b (while still being able to drive switch S1 "on" during the "on portion" of phase P1, of course).

[0089] Of course, the individual drivers for all other switches should also maintain appropriate levels of V SS and V DD To ensure correct operation of the drivers. The combination of these requirements may require selectable supplies for the various drivers (e.g., for switches S1 and S4). There may be other alternatives, such as an array of phase and voltage generators that can be switched to the various switches as needed.

[0090] Note that Fig. 9B DIV2 configuration, switch S2 can be shorted to avoid the R associated with this switch.ON losses, thereby improving the efficiency of DIV2 operation. More specifically, since switch S2 switches in phase with the rephasing switch S1, switch S2 is not required for DIV2 operation. Shorting switch S2 can be accomplished by connecting external (relative to the IC including the DIV3 / DIV2 circuit) shorts to nodes 904 and 906 and to nodes 902 and 908 (i.e., the top nodes of capacitors C1a and C2a and the top nodes of capacitors C1b and C2b, respectively). Switch S2 will have an R of typically a few milliohms. ON Similarly, an external short circuit may present a resistance of several milliohms. Therefore, the short circuit across switch S2 creates two low resistance paths in parallel with each other, making the effective R about switch S2 ON Minimum, and improve the overall efficiency of the circuit in the DIV2 configuration. In such a configuration, switch S2 can still be switched with or without an external parallel short circuit path. As will be appreciated by those skilled in the art, the advantage of this fourth embodiment is that there is no external component connection or conversion for switching between DIV2 and DIV3. The addition of the aforementioned external short circuit will improve efficiency, but requires external components.

[0091] By this fourth embodiment, it is not necessary to perform any off-chip physical transformation on how to connect the off-chip capacitor. Therefore, in any specific application, in the absence of a priori knowledge about whether to need fixed DIV2 or DIV3 configuration or to need selectable DIV2 / DIV3 configuration, the reconfiguration of DIV2 or DIV3 is fully realized by software control. This fourth embodiment also has the option for external short-circuit connection to improve the efficiency of DIV2 configuration. This flexibility can have high value for product developers, because single board layout and bill of materials ("BOM") can be used for any application, and can easily adapt to later design changes. This simplification provides advantages in cost, complexity, size and flexibility.

[0092] Boost conversion implementation

[0093] As described above, a DC / DC converter can either step down (“buck”) the input voltage or increase (“boost”) the input voltage. The above converter implementation is an example of a buck converter, where V OUT Less than V IN However, this converter implementation can be implemented by applying the supply voltage to V OUT node and from V IN The node gets the output voltage to become a boost converter. For example, refer to Figure 5 Converter 500, if the input voltage is applied to V OUT Node, then V INThe output voltage at the node is either twice (i.e., a conversion ratio of 2:1) or three times (i.e., a conversion ratio of 3:1) the applied voltage, depending on whether converter 500 is configured in “MULTIPLY3” mode (e.g., capacitor C1a is coupled to the DIV3 conductor) or in “MULTIPLY2” mode (e.g., capacitor C1a is coupled to the DIV2 conductor).

[0094] Integrated Circuit Implementation

[0095] A DC / DC converter typically includes an integrated circuit (IC) chip as well as external components and connecting wires. For example, the switches controlled by the P1 and P2 clock signals in the above embodiments (and variations of these embodiments) will typically be manufactured on the chip as components of the IC. However, the capacitors C1a, C2a, C1b, C2b and C2c used in conjunction with any of the above novel DC / DC converter embodiments are OUT This may be on-chip (i.e., as a manufactured component of the IC) or—perhaps more commonly—off-chip. Placing the capacitor off-chip enables different capacitors of potentially higher quality and different capacitance values ​​to be used with the same switch IC, thus increasing design flexibility and efficiency.

[0096] By splitting the functionality—on-chip switches, off-chip capacitors—configuration elements 504a, 504b, 704a, 704b are easily implemented as wired connections (e.g., jumpers or other conductors set between pairs of externally accessible connection terminals of the IC) so that converters 500, 700 can be set to a specific DC to DC conversion ratio when the system is manufactured (e.g., when an IC including the switching portion of converter 500, 700 is adhered to a printed circuit board, etc.).

[0097] So, for example, focus on Figure 5 In cell 502a, for the DIV3 configuration, a jumper is connected from one terminal of external capacitor C1a to an external terminal for the DIV3 conductor, and no external connection is made ("DNF" or "Not Installed") to an external terminal for the DIV2 conductor. Similarly, for the DIV2 configuration, a jumper is connected (installed) from one terminal of external capacitor C1a to an external terminal for the DIV2 conductor, and no external connection is made ("DNF" or "Not Installed") to an external terminal for the DIV3 conductor. As described above, in the DIV2 configuration, external capacitor C1a is therefore connected in parallel with external capacitor C2b, effectively forming a single equivalent capacitor with a greater total capacitance. Therefore, in the case of external connection changes for capacitors C1a and C2a, respectively, and in the case where variable phase clock generation circuit 600 controls Px and Px to switches 506a, 506b, respectively. (i.e., P1 or P2), the same IC chip can be configured as a DIV3 DC / DC Dickson buck converter or as a DIV2 DC / DC Dickson buck converter. More generally, the same DC / DC converter IC chip can be configured as a buck converter or as a boost converter, and can be configured to have at least one of a first conversion ratio or a second conversion ratio.

[0098] Features and advantages of embodiments of the present invention

[0099] As indicated in the above embodiments, a plurality of different circuits provide at least two different DC to DC conversion ratios. In some embodiments, in a first configuration, a selectable clock signal control circuit outputs a first clock signal phase to at least one switch of the switch array, the first capacitor is not connected in parallel with the second capacitor, and the switch array operates in response to respective application of the first clock signal phase and the second clock signal phase to periodically charge and discharge the first capacitor and the second capacitor to provide an output voltage having a first ratio relative to the input voltage at an output voltage terminal. In a second configuration, a selectable clock signal control circuit outputs a second clock signal phase to at least one switch of the switch array, the first capacitor is connected in parallel with the second capacitor, and the switch array operates in response to respective application of the first clock signal phase and the second clock signal phase to periodically charge and discharge the first capacitor and the second capacitor in parallel (i.e., essentially as a single larger capacitor) to provide an output voltage having a second ratio relative to the input voltage at an output voltage terminal, the second ratio being different from the first ratio.

[0100] In other embodiments, in a first configuration, wherein the first capacitor and the second capacitor are coupled to the switch array and the first capacitor is not connected in parallel with the second capacitor, the switch array operates in response to respective application of a first clock signal phase and a second clock signal phase to periodically charge and discharge the first capacitor and the second capacitor to provide an output voltage having a first ratio relative to an input voltage at an output voltage terminal. In a second configuration, only one of the first capacitor and the second capacitor is coupled to the switch array, and the switch array operates in response to respective application of the first clock signal phase or the second clock signal phase or the first logic state or the second logic state to periodically charge and discharge one capacitor (i.e., the first capacitor or the second capacitor) coupled to the switch array to provide an output voltage having a second ratio relative to the input voltage at the output voltage terminal, the second ratio being different from the first ratio.

[0101] The selectable conversion ratio DC to DC converter 500 of the first embodiment is particularly efficient, with the example circuit exhibiting less than half the losses of other embodiments encompassed by the present invention (eg, approximately 2% losses compared to approximately 4% losses).

[0102] Advantageously, the switches used in various embodiments of the present invention may be of the type of high voltage switching devices described in U.S. patent application Ser. No. 15 / 832,626, filed on Dec. 5, 2017, and entitled “High Breakdown Voltage Switching Device,” which is assigned to the assignee of the present invention and is incorporated herein by reference.

[0103] Advantages of various embodiments of the present invention include the following:

[0104] · A single IC can be used for product designs that require at least two different DC to DC conversion ratios, and specifically for product designs that require both a 2-way DC to DC step-down (buck conversion) ratio and a 3-way DC to DC step-down (buck conversion) ratio. Thus, a single chip solution can be used for mobile platform products with two-cell or three-cell Li-Ion batteries. o For example, according to the present invention, for a printed circuit board (PCB) on which the IC is mounted, a single external capacitor can be mounted per converter unit, and the IC can be configured as a 2-way Dickson buck converter.

[0105] o If the same PCB has two mounted capacitors per converter unit, the same IC can be configured as a 2-way Dickson buck converter or as a 3-way Dickson buck converter. In the 2-way configuration, two mounted capacitors are effectively utilized to increase current capacity.

[0106] Configuration changes can be made by using simple capacitor connection options in conjunction with logic control to change the phase or state of some switches in the IC based on the capacitor configuration.

[0107] Configuration changes may be made by installing or not installing off-chip capacitors to externally accessible terminals of the IC containing the DC-to-DC converter switch and / or by installing or not installing jumpers or conductive traces, etc. (i.e., essentially zero-ohm resistors) to externally accessible terminals of the IC containing the DC-to-DC converter switch.

[0108] A single IC solution can be used for both step-up and step-down conversion.

[0109] • Embodiments of the invention can be used with all types of DC voltage sources (not just batteries), and are particularly useful in conjunction with DC voltage sources that have a wide variation in output voltage.

[0110] • The single chip solution covered by the present invention makes the cost lower and enables easier acquisition and management of components.

[0111] method

[0112] Another aspect of the present invention includes various methods for DC to DC conversion. For example, Fig.10 is a process flow diagram illustrating a first method for DC to DC conversion, the method comprising configuring a first circuit to operate as a Dickson converter circuit to convert an applied input voltage to a first output voltage having a first conversion ratio relative to the applied input voltage (step 1002); configuring a second circuit to operate as a Dickson converter circuit to convert the applied input voltage to a second output voltage having a second conversion ratio relative to the applied input voltage (step 1004); selectively configuring the DC to DC conversion circuit to enable one of the first circuit or the second circuit (step 1006); and selectively providing a first set of clock signals for operating the first circuit and a second set of clock signals for operating the second circuit (step 1008). As an alternative to steps 1006 and 1008, the method may include selectively enabling the first circuit by providing the first set of clock signals, or selectively enabling the second circuit by providing the second set of clock signals.

[0113] As another example, Fig.11 is a process flow chart depicting a second method for DC-to-DC conversion, the method comprising providing a first circuit configuration, the first circuit configuration comprising at least two non-parallel capacitors and associated controlled multiphase switches, the first circuit configuration being operated to convert an applied input voltage to a first output voltage having a first conversion ratio relative to the applied input voltage (step 1102); providing a second circuit configuration, the second circuit configuration comprising a smaller number of equivalent capacitors and associated controlled multiphase switches than the first circuit configuration, the second circuit configuration being operated to convert the applied input voltage to a second output voltage having a second conversion ratio relative to the applied input voltage (step 1104); and selectively configuring the DC-to-DC conversion circuit to one of the first circuit configuration or the second circuit configuration (step 1106).

[0114] Another method for DC / DC conversion includes: providing an input voltage terminal configured to be coupled to a voltage source; providing an output voltage terminal; providing a selectable clock signal control circuit, the selectable clock signal control circuit selectively outputting a first clock signal phase or a second clock signal phase; providing a switch array including a plurality of switches directly or indirectly coupled to the input voltage terminal, each switch of the switch array being controlled by one of the first clock signal phase or the second clock signal phase, and at least one switch of the switch array being coupled to an output of the selectable clock signal control circuit; providing a configuration element, the configuration element being configured to selectively couple a first capacitor to one of at least two nodes of the switch array; and providing a connection line for coupling a second capacitor to the switch array; wherein, in a first configuration, (1) the first capacitor and the second capacitor are already coupled to the switch array, (2) an input voltage from the voltage source is already coupled to the input voltage terminal, and (3) the selectable clock signal control circuit couples the first clock signal phase to the second clock signal phase. The clock signal phase is output to at least one switch of the switch array, the first capacitor is not connected in parallel with the second capacitor, and the switch array operates in response to the respective application of the first clock signal phase and the second clock signal phase to charge and discharge the first capacitor and the second capacitor to provide a first output voltage having a first conversion ratio relative to the input voltage at the output voltage terminal; and wherein, in a second configuration, wherein (1) the first capacitor and the second capacitor are already coupled to the switch array, (2) the input voltage from the voltage source is already coupled to the input voltage terminal, and (3) the selectable clock signal control circuit outputs the second clock signal phase to at least one switch of the switch array, the first capacitor is connected in parallel with the second capacitor, and the switch array operates in response to the respective application of the first clock signal phase and the second clock signal phase to charge and discharge the first capacitor and the second capacitor to provide a second output voltage having a second conversion ratio relative to the input voltage at the output voltage terminal, the second conversion ratio being different from the first conversion ratio.

[0115] Another method for DC / DC conversion includes: providing an input voltage terminal configured to be coupled to a voltage source; providing an output voltage terminal; providing at least one first clock signal control circuit, the at least one first clock signal control circuit selectively outputting an applied clock signal phase or a first logic state; providing at least one second clock signal control circuit, the at least one second clock signal control circuit selectively outputting an applied clock signal phase or a second logic state; providing a switch array including a plurality of switches directly or indirectly coupled to the input voltage terminal, each switch of the switch array being controlled by one of the first clock signal phase or the second clock signal phase, and at least one switch of the switch array being coupled to an output of the first clock signal control circuit, and at least one switch of the switch array being coupled to an output of the second clock signal control circuit; providing a connection line for selectively coupling a first capacitor to the switch array; and providing a connection line for selectively coupling a second capacitor to the switch array; wherein, in a first configuration, (1) the first capacitor and the second capacitor are already coupled to the switch array, and (2) an input voltage from the voltage source is already coupled to the input voltage terminal. sub, and (3) each first clock signal control circuit and each second clock signal control circuit output a corresponding applied clock signal phase, the first capacitor is not connected in parallel with the second capacitor, and the switch array operates in response to the corresponding application of the first clock signal phase and the second clock signal phase to charge and discharge the first capacitor and the second capacitor to provide a first output voltage having a first conversion ratio relative to the input voltage at the output voltage terminal; and wherein, in a second configuration, wherein (1) only one of the first capacitor and the second capacitor has been coupled to the switch array, (2) an input voltage from a voltage source has been coupled to the input voltage terminal, and (3) each first clock signal control circuit outputs a first logic state, and each second clock signal control circuit outputs a second logic state, the switch array operates in response to the corresponding application of the first clock signal phase or the second clock signal phase or the first logic state or the second logic state to charge and discharge one of the first capacitor or the second capacitor coupled to the switch array to provide a second output voltage having a second conversion ratio relative to the input voltage at the output voltage terminal, the second conversion ratio being different from the first conversion ratio.

[0116] Other aspects of the above method include: the first output voltage and the second output voltage are less than the input voltage; the first output voltage and the second output voltage are greater than the input voltage; the first conversion ratio and the second conversion ratio are integer-based ratios; the first conversion ratio is 3:1 and the second conversion ratio is 2:1; the clock signal is generated by a two-phase clock and does not overlap; the method element is manufactured as an integrated circuit; at least one of the capacitors is manufactured as a component of the integrated circuit; the output voltage terminal is configured to be coupled to an external output capacitor; the configuration includes an "installed" or "not installed" connection.

[0117] Manufacturing Technologies and Options

[0118] As used in the present disclosure, the term "MOSFET" refers to any field effect transistor (FET) having an insulated gate and including metal or metalloid, insulator, and semiconductor structures. The term "metal" or "metalloid" includes at least one conductive material (e.g., aluminum, copper or other metals, or highly doped polysilicon, graphene or other electrical conductors), "insulator" includes at least one insulating material (e.g., silicon oxide or other dielectric materials), and "semiconductor" includes at least one semiconductor material.

[0119] It should be obvious to those skilled in the art that various embodiments of the present invention can be implemented to meet various specifications. Unless otherwise specified above, the selection of suitable component values ​​is a matter of design choice, and various embodiments of the present invention can be implemented in any suitable IC technology (including but not limited to MOSFET structure) or in the form of hybrid or discrete circuits. Integrated circuit implementation can be manufactured using any suitable substrate and process, including but not limited to standard body silicon, silicon on insulator (SOI) and silicon on sapphire (SOS). Unless otherwise specified above, the present invention can be implemented in other transistor technologies such as BCD (bipolar CMOSDMOS), bipolar, GaAs HBT, GaN HEMT, GaAs pHEMT and MESFET technology. The implementation of monolithic IC is particularly useful because parasitic capacitance can usually be kept low (or kept at a minimum, kept uniform on all units, allowing compensation) by careful design.

[0120] Voltage levels may be changed or voltage and / or logic signal polarity may be inverted depending on the particular specification and / or implementation technology (e.g., NMOS, PMOS, or CMOS, and enhancement or depletion mode transistor devices). Component voltage, current, and power handling capabilities may be adjusted as needed, such as by adjusting device size, "stacking" components (particularly FETs) in series to withstand greater voltages, and / or using multiple parallel components to handle greater currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and / or to provide additional functionality without significantly changing the functionality of the disclosed circuits.

[0121] in conclusion

[0122] A number of embodiments of the present invention have been described. It should be appreciated that various modifications may be made without departing from the spirit and scope of the present invention. For example, some of the above steps may be sequence independent and therefore may be performed in a sequence different from that described. In addition, some of the above steps may be optional. The various actions described with respect to the above identified methods may be performed in a repetitive, serial or parallel manner.

[0123] It should be understood that the foregoing description is intended to illustrate and not to limit the scope of the invention, which is defined by the scope of the appended claims and that other embodiments are also within the scope of the claims (note that parenthetical markings of claim elements are for convenience in referencing such elements and do not in themselves indicate a specific required order or enumeration of the elements; furthermore, such markings may be repeated in dependent claims as references to additional elements without being construed as causing a contradictory marking sequence).

[0124] Additionally, the present technology may also be configured as follows.

[0125] (1) A DC to DC conversion circuit, comprising:

[0126] (a) a configurable clock signal control circuit, the configurable clock signal control circuit selectively outputting a first phase clock signal, a second phase clock signal and a selectable phase clock signal;

[0127] (b) a first circuit configuration coupled to the configurable clock signal control circuit and operable as a Dickson converter circuit to convert an applied input voltage to a first output voltage having a first conversion ratio relative to the applied input voltage, the first circuit configuration having: at least one switch responsive to a first clock signal phase; at least one switch responsive to a second clock signal phase; and at least one switch responsive to the selectable phase clock signal; and

[0128] (c) a second circuit configuration coupled to the configurable clock signal control circuit and operable as a Dickson converter circuit to convert the applied input voltage to a second output voltage having a second conversion ratio relative to the applied input voltage, the second circuit configuration having: at least one switch responsive to a phase of the first clock signal; at least one switch responsive to a phase of the second clock signal; and at least one switch responsive to the selectable phase clock signal.

[0129] (2) The DC-to-DC conversion circuit according to (1), wherein the first output voltage and the second output voltage are lower than the input voltage.

[0130] (3) The DC-to-DC conversion circuit according to (1), wherein the first output voltage and the second output voltage are greater than the input voltage.

[0131] (4) The DC-to-DC conversion circuit according to (1), wherein the first conversion ratio and the second conversion ratio are ratios based on integers.

[0132] (5) The DC-to-DC conversion circuit according to (1), wherein the first conversion ratio is 3:1 and the second conversion ratio is 2:1.

[0133] (6) The DC-to-DC conversion circuit according to (1), wherein the output voltage is configured to be coupled to an external output capacitor.

[0134] (7) The DC to DC conversion circuit according to (1), wherein the DC to DC conversion circuit is manufactured as an integrated circuit.

[0135] (8) A DC to DC conversion circuit, comprising:

[0136] (a) a configurable clock signal control circuit, the configurable clock signal control circuit selectively outputting a first phase clock signal, a second phase clock signal and a selectable phase clock signal;

[0137] (b) a first circuit configuration coupled to the configurable clock signal control circuit and operable as a Dickson converter circuit to convert an applied input voltage to a first output voltage having a first conversion ratio relative to the applied input voltage, the first circuit configuration having: at least one switch responsive to a first clock signal phase; at least one switch responsive to a second clock signal phase; and at least one switch responsive to the selectable phase clock signal;

[0138] (c) a second circuit configuration coupled to the configurable clock signal control circuit and operable as a Dickson converter circuit to convert the applied input voltage to a second output voltage having a second conversion ratio relative to the applied input voltage, the second circuit configuration having: at least one switch responsive to the first clock signal phase; at least one switch responsive to the second clock signal phase; and at least one switch responsive to the selectable phase clock signal; and

[0139] (d) a configuration element for selectively configuring the DC-to-DC conversion circuit into one of the first circuit configuration or the second circuit configuration.

[0140] (9) The DC-to-DC conversion circuit according to (8), wherein the first output voltage and the second output voltage are lower than the input voltage.

[0141] (10) The DC-to-DC conversion circuit according to (8), wherein the first output voltage and the second output voltage are greater than the input voltage.

[0142] (11) The DC-to-DC conversion circuit according to (8), wherein the first conversion ratio and the second conversion ratio are ratios based on integers.

[0143] (12) The DC-to-DC conversion circuit according to (8), wherein the first conversion ratio is 3:1 and the second conversion ratio is 2:1.

[0144] (13) The DC-to-DC conversion circuit according to (8), wherein the output voltage is configured to be coupled to an external output capacitor.

[0145] (14) The DC-to-DC conversion circuit according to (8), wherein the DC-to-DC conversion circuit is manufactured as an integrated circuit.

[0146] (15) A DC to DC conversion circuit, comprising:

[0147] (a) a first circuit configuration comprising at least two non-parallel capacitors and associated controlled multi-phase switches, the first circuit configuration being operable to convert an applied input voltage to a first output voltage having a first conversion ratio relative to the applied input voltage;

[0148] (b) a second circuit configuration including a smaller number of equivalent capacitors and associated controlled multiphase switches than the first circuit configuration, the second circuit configuration being operative to convert the applied input voltage to a second output voltage having a second conversion ratio relative to the applied input voltage; and

[0149] (c) a configuration element for selectively configuring the DC-to-DC conversion circuit into one of the first circuit configuration or the second circuit configuration.

[0150] (16) The DC-to-DC conversion circuit according to (15), wherein the first output voltage and the second output voltage are smaller than the input voltage.

[0151] (17) The DC-to-DC conversion circuit according to (15), wherein the first output voltage and the second output voltage are greater than the input voltage.

[0152] (18) The DC-to-DC conversion circuit according to (15), wherein the first conversion ratio and the second conversion ratio are ratios based on integers.

[0153] (19) The DC-to-DC conversion circuit according to (15), wherein the first conversion ratio is 3:1 and the second conversion ratio is 2:1.

[0154] (20) The DC-to-DC conversion circuit according to (15), wherein the output voltage is configured to be coupled to an external output capacitor.

[0155] (21) The DC-to-DC conversion circuit according to (15), wherein the DC-to-DC conversion circuit is manufactured as an integrated circuit.

[0156] (22) A DC to DC conversion circuit with a selectable conversion ratio, comprising:

[0157] (a) an input voltage terminal configured to be coupled to a voltage source;

[0158] (b) output voltage terminal;

[0159] (c) a selectable clock signal control circuit that selectively outputs a first clock signal phase or a second clock signal phase;

[0160] (d) a switch array comprising a plurality of switches coupled directly or indirectly to the input voltage terminal, each switch of the switch array being controlled by one of the first clock signal phase or the second clock signal phase, and at least one switch of the switch array being coupled to an output of the selectable clock signal control circuit;

[0161] (e) a configuration element configured to selectively couple a first capacitor to one of at least two nodes of the switch array; and

[0162] (f) a connection line for coupling the second capacitor to the switch array;

[0163] wherein, in a first configuration, wherein (1) the first capacitor and the second capacitor are coupled to the switch array, and (2) an input voltage from the voltage source is coupled to the input voltage terminal, the first capacitor is not connected in parallel with the second capacitor, and the switch array is operated to charge and discharge the first capacitor and the second capacitor to provide a first output voltage having a first conversion ratio relative to the input voltage at the output voltage terminal; and

[0164] Wherein, in a second configuration, wherein (1) the first capacitor and the second capacitor are coupled to the switch array, and (2) an input voltage from the voltage source is coupled to the input voltage terminal, the first capacitor is connected in parallel with the second capacitor, and the switch array is operated to charge and discharge the first capacitor and the second capacitor to provide a second output voltage having a second conversion ratio relative to the input voltage at the output voltage terminal, the second conversion ratio being different from the first conversion ratio.

[0165] (23) The DC-to-DC conversion circuit according to (22), wherein the configuration element includes a mounted connection or a non-mounted connection between the first capacitor and the at least two nodes of the switch array.

[0166] (24) The DC-to-DC conversion circuit according to (22), wherein the first clock signal phase and the second clock signal phase are generated by a two-phase clock and the first clock signal phase and the second clock signal phase do not overlap.

[0167] (25) The DC-to-DC conversion circuit according to (22), wherein the DC-to-DC conversion circuit is manufactured as an integrated circuit, and wherein at least one of the first capacitor and the second capacitor is manufactured as a component of the integrated circuit.

[0168] (26) The DC-to-DC conversion circuit according to (22), wherein the first output voltage and the second output voltage are smaller than the input voltage.

[0169] (27) The DC-to-DC conversion circuit according to (22), wherein the first output voltage and the second output voltage are greater than the input voltage.

[0170] (28) The DC-to-DC conversion circuit according to (22), wherein the first conversion ratio and the second conversion ratio are ratios based on integers.

[0171] (29) The DC to DC conversion circuit according to (22), wherein the first conversion ratio is 3:1 and the second conversion ratio is 2:1.

[0172] (30) The DC-to-DC conversion circuit according to (22), wherein the output voltage is configured to be coupled to an external output capacitor.

[0173] (31) The DC to DC conversion circuit according to (22), wherein the DC to DC conversion circuit is manufactured as an integrated circuit.

[0174] (32) A DC to DC conversion circuit with a selectable conversion ratio, comprising:

[0175] (a) an input voltage terminal configured to be coupled to a voltage source;

[0176] (b) output voltage terminal;

[0177] (c) at least one first clock signal control circuit that selectively outputs an applied clock signal phase or a first logic state;

[0178] (d) at least one second clock signal control circuit that selectively outputs an applied clock signal phase or a second logic state;

[0179] (e) a switch array comprising a plurality of switches directly or indirectly coupled to the input voltage terminal, each switch of the switch array being controlled by one of a first clock signal phase and a second clock signal phase, and at least one switch of the switch array being coupled to an output of the first clock signal control circuit, and at least one switch of the switch array being coupled to an output of the second clock signal control circuit;

[0180] (f) a connection line for optionally coupling the first capacitor to the switch array; and

[0181] (g) a connection line for optionally coupling a second capacitor to the switch array;

[0182] wherein, in a first configuration, wherein (1) the first capacitor and the second capacitor are coupled to the switch array, and (2) an input voltage from the voltage source is coupled to the input voltage terminal, the first capacitor is not connected in parallel with the second capacitor, and the switch array is operated to charge and discharge the first capacitor and the second capacitor to provide a first output voltage having a first conversion ratio relative to the input voltage at the output voltage terminal; and

[0183] Wherein, in a second configuration, wherein (1) only one of the first capacitor and the second capacitor has been coupled to the switch array, and (2) an input voltage from the voltage source has been coupled to the input voltage terminal, the switch array is operated to charge and discharge one of the first capacitor or the second capacitor coupled to the switch array to provide a second output voltage having a second conversion ratio relative to the input voltage at the output voltage terminal, the second conversion ratio being different from the first conversion ratio.

[0184] (33) The DC-to-DC conversion circuit according to (32), wherein the first clock signal phase and the second clock signal phase are generated by a two-phase clock and the first clock signal phase and the second clock signal phase do not overlap.

[0185] (34) A DC-to-DC conversion circuit according to (32), wherein the DC-to-DC conversion circuit is manufactured as an integrated circuit, and wherein at least one of the first capacitor and the second capacitor is manufactured as a component of the integrated circuit.

[0186] (35) The DC-to-DC conversion circuit according to (32), wherein the first output voltage and the second output voltage are smaller than the input voltage.

[0187] (36) The DC-to-DC conversion circuit according to (32), wherein the first output voltage and the second output voltage are greater than the input voltage.

[0188] (37) The DC-to-DC conversion circuit according to (32), wherein the first conversion ratio and the second conversion ratio are ratios based on integers.

[0189] (38) A DC to DC conversion circuit according to (32), wherein the first conversion ratio is 3:1 and the second conversion ratio is 2:1.

[0190] (39) The DC-to-DC conversion circuit according to (32), wherein the output voltage is configured to be coupled to an external output capacitor.

[0191] (40) The DC-to-DC conversion circuit according to (32), wherein the DC-to-DC conversion circuit is manufactured as an integrated circuit.

[0192] (41). A method for DC to DC conversion, comprising:

[0193] (a) providing a configurable clock signal control circuit, wherein the configurable clock signal control circuit selectively outputs a first phase clock signal, a second phase clock signal, and a selectable phase clock signal;

[0194] (b) configuring a first circuit of the DC to DC conversion circuit to operate as a Dickson converter circuit to convert an applied input voltage to a first output voltage having a first conversion ratio relative to the applied input voltage, the first circuit configuration having: at least one switch responsive to a first clock signal phase; at least one switch responsive to a second clock signal phase; and at least one switch responsive to the selectable phase clock signal;

[0195] (c) configuring a second circuit of the DC-to-DC conversion circuit to operate as a Dickson converter circuit to convert the applied input voltage to a second output voltage having a second conversion ratio relative to the applied input voltage, the second circuit configuration having: at least one switch responsive to the phase of the first clock signal; at least one switch responsive to the phase of the second clock signal; and at least one switch responsive to the selectable phase clock signal; and

[0196] (d) selectively enabling the first circuit or selectively enabling the second circuit.

[0197] (42) The method according to (41) further includes manufacturing the DC to DC conversion circuit as an integrated circuit.

[0198] (43) The method according to (41), wherein the first output voltage and the second output voltage are less than the input voltage.

[0199] (44) The method according to (41), wherein the first output voltage and the second output voltage are greater than the input voltage.

[0200] (45) The method according to (41), wherein the first conversion ratio and the second conversion ratio are ratios based on integers.

[0201] (46) The method according to (41), wherein the first conversion ratio is 3:1 and the second conversion ratio is 2:1.

[0202] (47) The method according to (41) further includes configuring the output voltage to be coupled to an external output capacitor.

[0203] (48) A method for DC to DC conversion, comprising:

[0204] (a) providing a configurable clock signal control circuit, wherein the configurable clock signal control circuit selectively outputs a first phase clock signal, a second phase clock signal, and a selectable phase clock signal;

[0205] (b) configuring a first circuit of the DC to DC conversion circuit to operate as a Dickson converter circuit to convert an applied input voltage to a first output voltage having a first conversion ratio relative to the applied input voltage, the first circuit configuration having: at least one switch responsive to a first clock signal phase; at least one switch responsive to a second clock signal phase; and at least one switch responsive to the selectable phase clock signal;

[0206] (c) configuring a second circuit of the DC-to-DC conversion circuit to operate as a Dickson converter circuit to convert the applied input voltage to a second output voltage having a second conversion ratio relative to the applied input voltage, the second circuit configuration having: at least one switch responsive to the phase of the first clock signal; at least one switch responsive to the phase of the second clock signal; and at least one switch responsive to the selectable phase clock signal;

[0207] (d) selectively configuring the DC-to-DC conversion circuit to enable one of the first circuit or the second circuit; and

[0208] (e) selectively enabling the first circuit or selectively enabling the second circuit.

[0209] (49) The method according to (48) further includes manufacturing the DC to DC conversion circuit as an integrated circuit.

[0210] (50) The method according to (48), wherein the first output voltage and the second output voltage are less than the input voltage.

[0211] (51) The method according to (48), wherein the first output voltage and the second output voltage are greater than the input voltage.

[0212] (52) The method according to (48), wherein the first conversion ratio and the second conversion ratio are ratios based on integers.

[0213] (53) The method according to (48), wherein the first conversion ratio is 3:1 and the second conversion ratio is 2:1.

[0214] (54) The method according to (48) further includes configuring the output voltage to be coupled to an external output capacitor.

[0215] (55) A method for DC to DC conversion, the method comprising:

[0216] (a) providing a first circuit configuration, the first circuit configuration comprising at least two non-parallel capacitors and associated controlled multi-phase switches, the first circuit configuration being operable to convert an applied input voltage to a first output voltage having a first conversion ratio relative to the applied input voltage;

[0217] (b) providing a second circuit configuration including a smaller number of equivalent capacitors and associated controlled multiphase switches than the first circuit configuration, the second circuit configuration being operative to convert the applied input voltage to a second output voltage having a second conversion ratio relative to the applied input voltage; and

[0218] (c) selectively configuring a DC-to-DC conversion circuit into one of the first circuit configuration or the second circuit configuration.

[0219] (56) The method according to (55), wherein the first output voltage and the second output voltage are less than the input voltage.

[0220] (57) The method according to (55), wherein the first output voltage and the second output voltage are greater than the input voltage.

[0221] (58) The method according to (55), wherein the first conversion ratio and the second conversion ratio are ratios based on integers.

[0222] (59) The method according to (55), wherein the first conversion ratio is 3:1 and the second conversion ratio is 2:1.

[0223] (60) The method according to (55) further includes configuring the output voltage to be coupled to an external output capacitor.

[0224] (61) The method according to (55) further includes manufacturing the provided element into an integrated circuit.

[0225] (62) A method for DC / DC conversion, the method comprising:

[0226] (a) providing an input voltage terminal, wherein the input voltage terminal is configured to be coupled to a voltage source;

[0227] (b) providing an output voltage terminal;

[0228] (c) providing a selectable clock signal control circuit, the selectable clock signal control circuit selectively outputting a first clock signal phase or a second clock signal phase;

[0229] (d) providing a switch array, the switch array comprising a plurality of switches coupled directly or indirectly to the input voltage terminal, each switch of the switch array being controlled by one of the first clock signal phase or the second clock signal phase, and at least one switch of the switch array being coupled to an output of the selectable clock signal control circuit;

[0230] (e) providing a configuration element configured to selectively couple a first capacitor to one of at least two nodes of the switch array; and

[0231] (f) providing a connection line for coupling a second capacitor to the switch array;

[0232] wherein, in a first configuration, wherein (1) the first capacitor and the second capacitor are coupled to the switch array, and (2) an input voltage from the voltage source is coupled to the input voltage terminal, the first capacitor is not connected in parallel with the second capacitor, and the switch array is operated to charge and discharge the first capacitor and the second capacitor to provide a first output voltage having a first conversion ratio relative to the input voltage at the output voltage terminal; and

[0233] Wherein, in a second configuration, wherein (1) the first capacitor and the second capacitor are coupled to the switch array, and (2) an input voltage from the voltage source is coupled to the input voltage terminal, the first capacitor is connected in parallel with the second capacitor, and the switch array is operated to charge and discharge the first capacitor and the second capacitor to provide a second output voltage having a second conversion ratio relative to the input voltage at the output voltage terminal, the second conversion ratio being different from the first conversion ratio.

[0234] (63) The method of (62), wherein the configuration element comprises an installed connection or a non-installed connection between the first capacitor and the at least two nodes of the switch array.

[0235] (64) The method according to (62), wherein the first clock signal phase and the second clock signal phase are generated by a two-phase clock and the first clock signal phase and the second clock signal phase do not overlap.

[0236] (65) The method according to (62) further includes manufacturing the provided element as an integrated circuit, and manufacturing at least one of the first capacitor and the second capacitor as a component of the integrated circuit.

[0237] (66) The method according to (62), wherein the first output voltage and the second output voltage are less than the input voltage.

[0238] (67) The method according to (62), wherein the first output voltage and the second output voltage are greater than the input voltage.

[0239] (68) The method according to (62), wherein the first conversion ratio and the second conversion ratio are ratios based on integers.

[0240] (69) The method according to (62), wherein the first conversion ratio is 3:1 and the second conversion ratio is 2:1.

[0241] (70) The method according to (62), further comprising configuring the output voltage to be coupled to an external output capacitor.

[0242] (71) The method according to (62) further includes manufacturing the provided element into an integrated circuit.

[0243] (72) A method for DC / DC conversion, the method comprising:

[0244] (a) providing an input voltage terminal, wherein the input voltage terminal is configured to be coupled to a voltage source;

[0245] (b) providing an output voltage terminal;

[0246] (c) providing at least one first clock signal control circuit, the at least one first clock signal control circuit selectively outputting an applied clock signal phase or a first logic state;

[0247] (d) providing at least one second clock signal control circuit, the at least one second clock signal control circuit selectively outputting an applied clock signal phase or a second logic state;

[0248] (e) providing a switch array, the switch array comprising a plurality of switches directly or indirectly coupled to the input voltage terminal, each switch of the switch array being controlled by one of a first clock signal phase or a second clock signal phase, and at least one switch of the switch array being coupled to an output of the first clock signal control circuit, and at least one switch of the switch array being coupled to an output of the second clock signal control circuit;

[0249] (f) providing a connection line for optionally coupling the first capacitor to the switch array; and

[0250] (g) providing a connection line for optionally coupling a second capacitor to the switch array;

[0251] wherein, in a first configuration, wherein (1) the first capacitor and the second capacitor are coupled to the switch array, and (2) an input voltage from the voltage source is coupled to the input voltage terminal, the first capacitor is not connected in parallel with the second capacitor, and the switch array is operated to charge and discharge the first capacitor and the second capacitor to provide a first output voltage having a first conversion ratio relative to the input voltage at the output voltage terminal; and

[0252] Wherein, in a second configuration, wherein (1) only one of the first capacitor and the second capacitor has been coupled to the switch array, and (2) an input voltage from the voltage source has been coupled to the input voltage terminal, the switch array is operated to charge and discharge one of the first capacitor or the second capacitor coupled to the switch array to provide a second output voltage having a second conversion ratio relative to the input voltage at the output voltage terminal, the second conversion ratio being different from the first conversion ratio.

[0253] (73) The method according to (72), wherein the first clock signal phase and the second clock signal phase are generated by a two-phase clock and the first clock signal phase and the second clock signal phase do not overlap.

[0254] (74) The method according to (72) further includes manufacturing the provided element as an integrated circuit, and manufacturing at least one of the first capacitor and the second capacitor as a component of the integrated circuit.

[0255] (75) The method according to (72), wherein the first output voltage and the second output voltage are less than the input voltage.

[0256] (76) The method according to (72), wherein the first output voltage and the second output voltage are greater than the input voltage.

[0257] (77) The method according to (72), wherein the first conversion ratio and the second conversion ratio are ratios based on integers.

[0258] (78) The method according to (72), wherein the first conversion ratio is 3:1 and the second conversion ratio is 2:1.

[0259] (79) The method according to (72) further includes configuring the output voltage to be coupled to an external output capacitor.

[0260] (80) The method according to (72) further includes manufacturing the provided element into an integrated circuit.

[0261] (81) A DC to DC conversion circuit, the DC to DC conversion circuit being operable as a selectable conversion ratio Dickson converter circuit, comprising:

[0262] (a) a configurable clock signal control circuit, the configurable clock signal control circuit outputting a first phase clock signal, a second phase clock signal and a selectable phase clock signal;

[0263] (b) at least one switch responsive to a phase of a first clock signal;

[0264] (c) at least one switch responsive to a phase of a second clock signal; and

[0265] (d) at least one switch responsive to the selectable phase clock signal;

[0266] wherein, in a first circuit configuration for converting an applied input voltage to a first output voltage having a first conversion ratio relative to the applied input voltage, the selectable phase clock signal matches the phase of the first phase clock signal, and

[0267] Wherein, in a second circuit configuration for converting the applied input voltage into a second output voltage having a second conversion ratio relative to the applied input voltage, the selectable phase clock signal matches the phase of the second phase clock signal.

[0268] (82) The DC-to-DC conversion circuit according to (81), wherein the first clock signal phase and the second clock signal phase are generated by a two-phase clock and the first clock signal phase and the second clock signal phase do not overlap.

[0269] (83) A DC to DC conversion circuit according to (81), wherein the first output voltage and the second output voltage are smaller than the input voltage.

[0270] (84) A DC to DC conversion circuit according to (81), wherein the first output voltage and the second output voltage are greater than the input voltage.

[0271] (85) The DC to DC conversion circuit according to (81), wherein the first conversion ratio and the second conversion ratio are ratios based on integers.

[0272] (86) A DC to DC conversion circuit according to (81), wherein the first conversion ratio is 3:1 and the second conversion ratio is 2:1.

[0273] (87) A DC to DC conversion circuit according to (81), wherein the DC to DC conversion circuit is manufactured as an integrated circuit.

[0274] (88) A DC to DC conversion circuit, the DC to DC conversion circuit being operable as a selectable conversion ratio Dickson converter circuit, comprising:

[0275] (a) a configurable clock signal control circuit, the configurable clock signal control circuit outputting a first phase clock signal, a second phase clock signal, a selectable phase clock signal and an inverted selectable phase clock signal;

[0276] (b) at least one switch responsive to a phase of a first clock signal;

[0277] (c) at least one switch responsive to a phase of a second clock signal;

[0278] (d) at least one switch responsive to the selectable phase clock signal; and

[0279] (e) at least one switch responsive to the inverted selectable phase clock signal;

[0280] wherein, in a first circuit configuration for converting an applied input voltage to a first output voltage having a first conversion ratio relative to the applied input voltage, the selectable phase clock signal matches the phase of the first phase clock signal, and the inverted selectable phase clock signal matches the phase of the second phase clock signal, and

[0281] wherein, in a second circuit configuration for converting the applied input voltage to a second output voltage having a second conversion ratio relative to the applied input voltage, the selectable phase clock signal matches the phase of the second phase clock signal, and the inverted selectable phase clock signal matches the phase of the first phase clock signal.

[0282] (89) A DC to DC conversion circuit according to (88), wherein the first clock signal phase and the second clock signal phase are generated by a two-phase clock and the first clock signal phase and the second clock signal phase do not overlap.

[0283] (90) A DC to DC conversion circuit according to (88), wherein the first output voltage and the second output voltage are smaller than the input voltage.

[0284] (91) A DC to DC conversion circuit according to (88), wherein the first output voltage and the second output voltage are greater than the input voltage.

[0285] (92) The DC-to-DC conversion circuit according to (88), wherein the first conversion ratio and the second conversion ratio are ratios based on integers.

[0286] (93) A DC to DC conversion circuit according to (88), wherein the first conversion ratio is 3:1 and the second conversion ratio is 2:1.

[0287] (94) A DC to DC conversion circuit according to (88), wherein the DC to DC conversion circuit is manufactured as an integrated circuit.

[0288] (95) A DC to DC conversion circuit, comprising:

[0289] (a) a configurable clock signal control circuit, the configurable clock signal control circuit outputting a first phase clock signal, a second phase clock signal, a selectable phase clock signal and an inverted selectable phase clock signal;

[0290] (b) a first circuit configuration operable as a Dickson converter circuit to convert an applied input voltage to a first output voltage having a first conversion ratio relative to the applied input voltage, the first circuit configuration having: at least one switch responsive to a first clock signal phase; at least one switch responsive to a second clock signal phase; at least one switch responsive to the selectable phase clock signal; and at least one switch responsive to the inverted selectable phase clock signal; and

[0291] (c) a second circuit configuration operable as a Dickson converter circuit to convert the applied input voltage to a second output voltage having a second conversion ratio relative to the applied input voltage, the second circuit configuration having: at least one switch responsive to the phase of the first clock signal; at least one switch responsive to the phase of the second clock signal; at least one switch responsive to the selectable phase clock signal; and at least one switch responsive to the inverted selectable phase clock signal;

[0292] wherein, in the first circuit configuration, the selectable phase clock signal matches the phase of the first phase clock signal and the inverted selectable phase clock signal matches the phase of the second phase clock signal, and wherein, in the second circuit configuration, the selectable phase clock signal matches the phase of the second phase clock signal and the inverted selectable phase clock signal matches the phase of the first phase clock signal.

[0293] (96) A DC to DC conversion circuit according to (95), wherein the first clock signal phase and the second clock signal phase are generated by a two-phase clock and the first clock signal phase and the second clock signal phase do not overlap.

[0294] (97) A DC to DC conversion circuit according to (95), wherein the first output voltage and the second output voltage are smaller than the input voltage.

[0295] (98) A DC to DC conversion circuit according to (95), wherein the first output voltage and the second output voltage are greater than the input voltage.

[0296] (99) The DC to DC conversion circuit according to (95), wherein the first conversion ratio and the second conversion ratio are ratios based on integers.

[0297] (100) A DC to DC conversion circuit according to (95), wherein the first conversion ratio is 3:1 and the second conversion ratio is 2:1.

[0298] (101) A DC to DC conversion circuit according to (95), wherein the DC to DC conversion circuit is manufactured as an integrated circuit.

Claims

1. A DC to DC conversion circuit, comprising: (a) a configurable clock signal control circuit, the configurable clock signal control circuit selectively outputting a first phase clock signal, a second phase clock signal and a selectable phase clock signal; (b) a first circuit configuration coupled to the configurable clock signal control circuit and operable as a Dickson converter circuit to convert an applied input voltage to a first output voltage having a first conversion ratio relative to the applied input voltage, the first circuit configuration having: at least one switch responsive to a first clock signal phase; at least one switch responsive to a second clock signal phase; and at least one switch responsive to said selectable phase clock signal; as well as (c) a second circuit configuration coupled to the configurable clock signal control circuit and operable as a Dickson converter circuit to convert the applied input voltage to a second output voltage having a second conversion ratio relative to the applied input voltage, the second circuit configuration having: at least one switch responsive to a phase of the first clock signal; at least one switch responsive to a phase of the second clock signal; and at least one switch responsive to the selectable phase clock signal.

2. A DC to DC conversion circuit, comprising: (a) a configurable clock signal control circuit, the configurable clock signal control circuit selectively outputting a first phase clock signal, a second phase clock signal and a selectable phase clock signal; (b) a first circuit configuration coupled to the configurable clock signal control circuit and operable as a Dickson converter circuit to convert an applied input voltage to a first output voltage having a first conversion ratio relative to the applied input voltage, the first circuit configuration having: at least one switch responsive to a first clock signal phase; at least one switch responsive to a second clock signal phase; and at least one switch responsive to said selectable phase clock signal; (c) a second circuit configuration coupled to the configurable clock signal control circuit and operable as a Dickson converter circuit to convert the applied input voltage to a second output voltage having a second conversion ratio relative to the applied input voltage, the second circuit configuration having: at least one switch responsive to a phase of the first clock signal; at least one switch responsive to a phase of the second clock signal; and at least one switch responsive to said selectable phase clock signal; as well as (d) a configuration element for selectively configuring the DC-to-DC conversion circuit into one of the first circuit configuration or the second circuit configuration.

3. A DC to DC conversion circuit, comprising: (a) a first circuit configuration comprising at least two non-parallel capacitors and associated controlled multi-phase switches, the first circuit configuration being operable to convert an applied input voltage to a first output voltage having a first conversion ratio relative to the applied input voltage; (b) a second circuit configuration including a smaller number of equivalent capacitors and associated controlled multiphase switches than the first circuit configuration, the second circuit configuration being operative to convert the applied input voltage to a second output voltage having a second conversion ratio relative to the applied input voltage; as well as (c) a configuration element for selectively configuring the DC-to-DC conversion circuit into one of the first circuit configuration or the second circuit configuration.

4. A DC to DC conversion circuit with a selectable conversion ratio, comprising: (a) an input voltage terminal configured to be coupled to a voltage source; (b) output voltage terminal; (c) a selectable clock signal control circuit that selectively outputs a first clock signal phase or a second clock signal phase; (d) a switch array comprising a plurality of switches coupled directly or indirectly to the input voltage terminal, each switch of the switch array being controlled by one of the first clock signal phase or the second clock signal phase, and at least one switch of the switch array being coupled to an output of the selectable clock signal control circuit; (e) a configuration element configured to selectively couple a first capacitor to one of at least two nodes of the switch array; as well as (f) a connection line for coupling the second capacitor to the switch array; wherein, in a first configuration, wherein (1) the first capacitor and the second capacitor are coupled to the switch array, and (2) an input voltage from the voltage source is coupled to the input voltage terminal, the first capacitor is not connected in parallel with the second capacitor, and the switch array is operated to charge and discharge the first capacitor and the second capacitor to provide a first output voltage having a first conversion ratio relative to the input voltage at the output voltage terminal; and Wherein, in a second configuration, wherein (1) the first capacitor and the second capacitor are coupled to the switch array, and (2) an input voltage from the voltage source is coupled to the input voltage terminal, the first capacitor is connected in parallel with the second capacitor, and the switch array is operated to charge and discharge the first capacitor and the second capacitor to provide a second output voltage having a second conversion ratio relative to the input voltage at the output voltage terminal, the second conversion ratio being different from the first conversion ratio.

5. A DC to DC conversion circuit with a selectable conversion ratio, comprising: (a) an input voltage terminal configured to be coupled to a voltage source; (b) output voltage terminal; (c) at least one first clock signal control circuit that selectively outputs an applied clock signal phase or a first logic state; (d) at least one second clock signal control circuit that selectively outputs an applied clock signal phase or a second logic state; (e) a switch array comprising a plurality of switches directly or indirectly coupled to the input voltage terminal, each switch of the switch array being controlled by one of a first clock signal phase and a second clock signal phase, and at least one switch of the switch array being coupled to an output of the first clock signal control circuit, and at least one switch of the switch array being coupled to an output of the second clock signal control circuit; (f) a connection line for optionally coupling the first capacitor to the switch array; as well as (g) a connection line for optionally coupling a second capacitor to the switch array; wherein, in a first configuration, wherein (1) the first capacitor and the second capacitor are coupled to the switch array, and (2) an input voltage from the voltage source is coupled to the input voltage terminal, the first capacitor is not connected in parallel with the second capacitor, and the switch array is operated to charge and discharge the first capacitor and the second capacitor to provide a first output voltage having a first conversion ratio relative to the input voltage at the output voltage terminal; and Wherein, in a second configuration, wherein (1) only one of the first capacitor and the second capacitor has been coupled to the switch array, and (2) an input voltage from the voltage source has been coupled to the input voltage terminal, the switch array is operated to charge and discharge one of the first capacitor or the second capacitor coupled to the switch array to provide a second output voltage having a second conversion ratio relative to the input voltage at the output voltage terminal, the second conversion ratio being different from the first conversion ratio.

6. A method for DC to DC conversion, comprising: (a) providing a configurable clock signal control circuit, wherein the configurable clock signal control circuit selectively outputs a first phase clock signal, a second phase clock signal, and a selectable phase clock signal; (b) configuring a first circuit of the DC to DC conversion circuit to operate as a Dickson converter circuit to convert an applied input voltage to a first output voltage having a first conversion ratio relative to the applied input voltage, the first circuit configuration having: at least one switch responsive to a first clock signal phase; at least one switch responsive to a second clock signal phase; and at least one switch responsive to said selectable phase clock signal; (c) configuring a second circuit of the DC-to-DC conversion circuit to operate as a Dickson converter circuit to convert the applied input voltage to a second output voltage having a second conversion ratio relative to the applied input voltage, the second circuit configuration having: at least one switch responsive to a phase of the first clock signal; at least one switch responsive to a phase of the second clock signal; and at least one switch responsive to said selectable phase clock signal; as well as (d) selectively enabling the first circuit or selectively enabling the second circuit.

7. A method for DC to DC conversion, comprising: (a) providing a configurable clock signal control circuit, wherein the configurable clock signal control circuit selectively outputs a first phase clock signal, a second phase clock signal, and a selectable phase clock signal; (b) configuring a first circuit of the DC to DC conversion circuit to operate as a Dickson converter circuit to convert an applied input voltage to a first output voltage having a first conversion ratio relative to the applied input voltage, the first circuit configuration having: at least one switch responsive to a first clock signal phase; at least one switch responsive to a second clock signal phase; and at least one switch responsive to said selectable phase clock signal; (c) configuring a second circuit of the DC-to-DC conversion circuit to operate as a Dickson converter circuit to convert the applied input voltage to a second output voltage having a second conversion ratio relative to the applied input voltage, the second circuit configuration having: at least one switch responsive to a phase of the first clock signal; at least one switch responsive to a phase of the second clock signal; and at least one switch responsive to said selectable phase clock signal; (d) selectively configuring the DC-to-DC conversion circuit to enable one of the first circuit or the second circuit; as well as (e) selectively enabling the first circuit or selectively enabling the second circuit.

8. A method for DC to DC conversion, the method comprising: (a) providing a first circuit configuration, the first circuit configuration comprising at least two non-parallel capacitors and associated controlled multi-phase switches, the first circuit configuration being operable to convert an applied input voltage to a first output voltage having a first conversion ratio relative to the applied input voltage; (b) providing a second circuit configuration including a smaller number of equivalent capacitors and associated controlled multiphase switches than the first circuit configuration, the second circuit configuration being operative to convert the applied input voltage to a second output voltage having a second conversion ratio relative to the applied input voltage; as well as (c) selectively configuring a DC-to-DC conversion circuit into one of the first circuit configuration or the second circuit configuration.

9. A method for DC / DC conversion, the method comprising: (a) providing an input voltage terminal, wherein the input voltage terminal is configured to be coupled to a voltage source; (b) providing an output voltage terminal; (c) providing a selectable clock signal control circuit, the selectable clock signal control circuit selectively outputting a first clock signal phase or a second clock signal phase; (d) providing a switch array, the switch array comprising a plurality of switches coupled directly or indirectly to the input voltage terminal, each switch of the switch array being controlled by one of the first clock signal phase or the second clock signal phase, and at least one switch of the switch array being coupled to an output of the selectable clock signal control circuit; (e) providing a configuration element configured to selectively couple a first capacitor to one of at least two nodes of the switch array; as well as (f) providing a connection line for coupling a second capacitor to the switch array; wherein, in a first configuration, wherein (1) the first capacitor and the second capacitor are coupled to the switch array, and (2) an input voltage from the voltage source is coupled to the input voltage terminal, the first capacitor is not connected in parallel with the second capacitor, and the switch array is operated to charge and discharge the first capacitor and the second capacitor to provide a first output voltage having a first conversion ratio relative to the input voltage at the output voltage terminal; and Wherein, in a second configuration, wherein (1) the first capacitor and the second capacitor are coupled to the switch array, and (2) an input voltage from the voltage source is coupled to the input voltage terminal, the first capacitor is connected in parallel with the second capacitor, and the switch array is operated to charge and discharge the first capacitor and the second capacitor to provide a second output voltage having a second conversion ratio relative to the input voltage at the output voltage terminal, the second conversion ratio being different from the first conversion ratio.

10. A DC to DC conversion circuit operable as a selectable conversion ratio Dickson converter circuit, comprising: (a) a configurable clock signal control circuit, the configurable clock signal control circuit outputting a first phase clock signal, a second phase clock signal and a selectable phase clock signal; (b) at least one switch responsive to a phase of a first clock signal; (c) at least one switch responsive to a phase of a second clock signal; as well as (d) at least one switch responsive to the selectable phase clock signal; wherein, in a first circuit configuration for converting an applied input voltage to a first output voltage having a first conversion ratio relative to the applied input voltage, the selectable phase clock signal matches the phase of the first phase clock signal, and Wherein, in a second circuit configuration for converting the applied input voltage into a second output voltage having a second conversion ratio relative to the applied input voltage, the selectable phase clock signal matches the phase of the second phase clock signal.

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