Subnanosecond square wave pulse generator

Abstract

The invention discloses a subnanosecond square wave pulse generator, which comprises a clock source unit, a control logic unit, a high-speed switch, a pre-driving and amplifying unit and an output unit, and is characterized in that the output end of the clock source unit is connected with the input end of the control logic unit, and the clock source unit is used for receiving the high-speed switch; the output end of the control logic unit is connected with the control end of the high-speed switching circuit; the output end of the high-speed switch is connected with the input end of the pre-driving and amplifying unit, and the pre-driving and amplifying unit is used for driving the high-speed switch; the output end of the pre-driving and amplifying unit is connected with the input end of the output unit, and the output unit is used for further processing the amplified and conditioned pulse signal so as to output a subnanosecond square wave pulse. According to the invention, high-precision subnanosecond square wave pulses can be obtained.

Description

Technical Field

[0001] The present application relates to a pulse generator, and in particular to a sub-nanosecond square wave pulse generator. Background Art

[0002] Existing square wave pulse generators usually have difficulty achieving sub-nanosecond pulse width accuracy while maintaining good signal integrity. In addition, at high frequencies, the rise time and fall time of the signal have a significant impact on the pulse shape, so for sub-nanosecond applications, it is necessary to ensure that these two parameters are as small as possible. Summary of the invention

[0003] In view of the deficiencies in the prior art, the purpose of the present application is to provide a sub-nanosecond square wave pulse generator, which can obtain high-quality, steep-edge sub-nanosecond square wave pulses.

[0004] To achieve the above objectives, this application provides the following technical solutions: A sub-nanosecond square wave pulse generator, the generator comprising: a clock source unit, a control logic unit, a high-speed switch, a pre-drive and amplification unit and an output unit, wherein the clock source unit is used to provide a clock signal for the generation of sub-nanosecond square wave pulses; the control logic unit is used to set the parameters of the sub-nanosecond square wave pulses and generate control signals based on these parameters; the high-speed switch is used to perform fast switching based on the control signal to generate a pulse signal with a steep edge; the pre-drive and amplification unit is used to amplify and condition the pulse signal with a steep edge; the output unit is used to further process the amplified and conditioned pulse signal to output a sub-nanosecond square wave pulse; the protection unit is used to provide protection for the output unit.

[0005] Optionally, the clock source unit includes: an atomic clock, a constant temperature crystal oscillator, a first phase-locked loop, a second phase-locked loop, an adder, a first operational amplifier, and an output driver, wherein the input of the first phase-locked loop is connected to the output of the atomic clock, the input of the second phase-locked loop is connected to the output of the constant temperature crystal oscillator, the output of the first phase-locked loop is connected to the first input of the adder, the output of the second phase-locked loop is connected to the second input of the adder, the output of the adder is connected to the in-phase input of the first operational amplifier, the output of the first operational amplifier is connected to the input of the output driver, and the output of the output driver is connected to the input of the control logic unit; the clock source unit also includes a temperature compensation circuit, and the temperature compensation circuit is connected to the inverting input of the first operational amplifier.

[0006] Optionally, the temperature compensation circuit includes a temperature sensor and a heating or cooling element.

[0007] Optionally, the pre-drive and amplification unit includes: a first capacitor, a second operational amplifier, a voltage divider network, a matching network, a gate driver, and a power MOSFET tube, wherein the first end of the first capacitor is connected to the output end of the high-speed switch, the second end of the first capacitor is connected to the non-inverting input end of the second operational amplifier, the voltage divider network is arranged between the inverting input end and the output end of the second operational amplifier, the output end of the second operational amplifier is connected to the input end of the gate driver through the matching network, the output end of the gate driver is connected to the gate of the power MOSFET tube, the source of the power MOSFET tube is connected to the third ground terminal, and the drain of the power MOSFET tube is connected to the protection unit.

[0008] Optionally, the output unit includes: a first filtering and voltage stabilization module, a second filtering and voltage stabilization module, a signal conditioning module, a signal processing module and an output module, wherein the first filtering and voltage stabilization module is used to provide a stable power supply signal and filter out noise in the power signal; the second filtering and voltage stabilization module is used to further purify the power signal; the signal conditioning module is used to regulate the amplified and conditioned pulse signal; the signal processing module is used to convert the regulated pulse signal into a sub-nanosecond square wave pulse with steep edges and accurate pulse width; and the signal output module is used to output a sub-nanosecond square wave pulse with steep edges and accurate pulse width.

[0009] Optionally, the first filtering and voltage stabilization module includes: a first low voltage dropout regulator, a fifth resistor, a first transistor, a second inductor and a fourth capacitor, wherein the first end of the fifth resistor is connected to the base of the first transistor to form a first node, and the second end of the fifth resistor is connected to the input of the first low voltage dropout regulator; the output of the first low voltage dropout regulator is connected to the first end of the second inductor; the second end of the second inductor is connected to a -5V power supply; the first end of the fourth capacitor is connected to the output of the first low voltage dropout regulator, and the second end of the fourth capacitor is connected to the seventh ground terminal; the collector of the first transistor is connected to the sixth ground terminal, and the emitter of the first transistor is connected to the first input of the signal conditioning module to form a second node.

[0010] Optionally, the second filtering and voltage stabilization module includes: a second low voltage dropout regulator, a ninth capacitor and a third inductor, wherein the input end of the second low voltage dropout regulator is connected to a +5V power supply through the third inductor, and the output end of the second low voltage dropout regulator is connected to the first input end of the signal processing module to form an eighth node; the first end of the ninth capacitor is connected to the input end of the second low voltage dropout regulator, and the second end of the ninth capacitor is connected to the eighth ground end.

[0011] Optionally, the signal adjustment module includes: a second transistor, a sixth resistor, an eighth resistor, a ninth resistor, a tenth resistor, a fifth capacitor, a sixth capacitor and a switch, wherein the first end of the sixth resistor is connected to the second node as the first input end of the signal adjustment module, and the second end of the sixth resistor is connected to the first input end of the signal processing module to form a fourth node; the emitter of the second transistor is connected to the second node, the base of the second transistor is connected to the first end of the ninth resistor to form a fifth node, and the collector of the second transistor is connected to the second input end of the signal processing module to form a third node; the second end of the ninth resistor is connected to the third node through the eighth resistor; the first end of the fifth capacitor is connected to the fifth node, and the second end of the fifth capacitor is connected to the sixth ground terminal through the switch; the first end of the tenth resistor is connected to the first node, and the second end of the tenth resistor is connected to the first end of the sixth capacitor; the second end of the sixth capacitor is connected to the sixth ground terminal through the switch.

[0012] Optionally, the signal processing module includes: a third transistor, a fourth transistor, a seventh resistor, a seventh capacitor, an eighth capacitor, an eleventh resistor, a tenth capacitor and an eleventh capacitor, wherein the base of the third transistor is connected to the third node as the second input terminal of the signal processing module, the collector of the third transistor is connected to the sixth ground terminal, and the emitter of the third transistor is connected to the base of the fourth transistor; the emitter of the fourth transistor is connected to the first end of the eleventh resistor to form a sixth node; the second end of the eleventh resistor is connected to the fourth node as the first input terminal of the signal processing module; the collector of the fourth transistor is connected to the first end of the seventh capacitor to form a seventh node; the second end of the seventh capacitor is connected to the first input terminal of the signal output module to form an eighth node; the eighth capacitor is connected in parallel to both ends of the seventh capacitor; the first end of the tenth capacitor is connected to the fourth node, and the second end of the tenth capacitor is connected to the sixth ground terminal; the first end of the eleventh capacitor is connected to the fourth node, and the second end of the eleventh capacitor is connected to the sixth ground terminal.

[0013] Optionally, the signal output module includes: a fifth transistor, a twelfth resistor, a thirteenth resistor and a fourteenth resistor, wherein the emitter of the fifth transistor is connected to the sixth node, and the collector of the fifth transistor is connected to the first end of the twelfth resistor; the second end of the twelfth resistor is connected to the eighth node as the first input end of the signal output module; the base of the fifth transistor is connected to the first end of the thirteenth resistor to form a ninth node; the second end of the thirteenth resistor is connected to the output end of the output unit; the first end of the fourteenth resistor is connected to the ninth node, and the second end of the fourteenth resistor is connected to the fourth node.

[0014] Compared with the prior art, the present invention has the following beneficial effects: This application can achieve efficient generation and precise control of sub-nanosecond square wave pulses by integrating high-precision clock source units, flexible control logic units, high-speed switches, sophisticated pre-drive and amplification units, optimized output units, and comprehensive protection units. This application can not only ensure that the pulses have extremely high time resolution and stability, but also effectively filter out noise and interference to ensure the purity and integrity of the signal. In addition, the multi-level protection mechanism significantly improves the reliability and anti-interference ability of the system, allowing the entire pulse generator to operate stably in a complex and changeable electrical environment, and ultimately output high-quality, steep-edge sub-nanosecond square wave pulses. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a schematic diagram of the circuit structure of a sub-nanosecond square wave pulse generator provided by an embodiment of the present application; Figure 2 yes Figure 1 A schematic diagram of the circuit structure of a clock source unit in a sub-nanosecond square wave pulse generator is shown; Figure 3 yes Figure 1 A schematic diagram of the circuit structure of a pre-driving and amplifying unit in a sub-nanosecond square wave pulse generator is shown; Figure 4 yes Figure 1 A schematic diagram of the circuit structure of a protection unit in a sub-nanosecond square wave pulse generator is shown; Figure 5 yes Figure 1 A schematic diagram of the circuit structure of an output unit in a sub-nanosecond square wave pulse generator is shown.

[0016] The following are the descriptions of the reference numerals: 1. Clock source unit; 11. Atomic clock; 12. Constant temperature crystal oscillator; 13. First phase-locked loop; 14. Second phase-locked loop; 15. Adder; 16. Amplifier; 17. Output driver; 18. Temperature compensation circuit; 2. Control logic unit; 3. High-speed switch; 4. Pre-drive and amplification unit; 41. Voltage divider network; 42. Matching network; 43. Gate driver; 44. Power MOSFET tube; 5. Protection unit; 6. Output unit; 61. First filtering and voltage stabilization module; 62. Second filtering and voltage stabilization module; 63. Signal conditioning module; 64. Signal processing module; 65. Signal output module. DETAILED DESCRIPTION

[0017] The specific embodiments of the present application will be described in detail below with reference to the accompanying drawings. Although the specific embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0018] It should be noted that certain words are used in the specification and claims to refer to specific components. Those skilled in the art should understand that technicians may use different nouns to refer to the same component. This specification and claims do not use the difference in nouns as a way to distinguish components, but use the difference in the functions of the components as the criterion for distinction. As mentioned throughout the specification and claims, "including" or "comprising" is an open term, so it should be interpreted as "including but not limited to". The subsequent description of the specification is a preferred embodiment of the implementation of the present application, but the description is based on the general principles of the specification and is not used to limit the scope of the present application. The scope of protection of this application shall be based on the definition of the attached claims.

[0019] To facilitate understanding of the embodiments of the present application, further explanation will be given below using specific embodiments as examples in conjunction with the accompanying drawings, and the various drawings do not constitute a limitation on the embodiments of the present application.

[0020] Figure 1 FIG. 1 is a schematic diagram of a sub-nanosecond square wave pulse generator proposed in an exemplary embodiment of the present application. Figure 1 As shown, the sub-nanosecond square wave pulse generator includes: a clock source unit 1, a control logic unit 2, a high-speed switch 3, a pre-drive and amplification unit 4 and an output unit 6, wherein the clock source unit 1 is used to provide a clock signal for the generation of sub-nanosecond square wave pulses; the control logic unit 2 is used to set the parameters of the sub-nanosecond square wave pulses and generate control signals based on these parameters; the high-speed switch 3 is used to perform fast switching based on the control signal to generate a pulse signal with a steep edge; the pre-drive and amplification unit 4 is used to amplify and condition the pulse signal with a steep edge; the output unit 6 is used to further process the amplified and conditioned pulse signal to output a sub-nanosecond square wave pulse.

[0021] The present application can obtain high-quality, steep-edge sub-nanosecond square wave pulses by integrating a high-precision clock source unit, a flexible control logic unit, a high-speed switch, a sophisticated pre-drive and amplification unit, an optimized output unit, and a comprehensive protection unit.

[0022] This application has important practical significance by obtaining high-quality sub-nanosecond square wave pulses. For example, high-quality sub-nanosecond square wave pulses can significantly improve the resolution and accuracy of radar systems, where short pulse width means higher time resolution, thereby providing finer target details in radar images. The steep edge of the pulse helps to accurately measure the distance of the target, especially in high dynamic range applications. Another example: in material science and non-destructive testing, high-quality short pulses can more accurately detect tiny defects or cracks inside the material, and by analyzing the pulse reflection or transmission characteristics, the physical properties of the material can be deeply understood.

[0023] In another exemplary embodiment, Figure 2 As shown, the clock source unit 1 includes: an atomic clock 11, a constant temperature crystal oscillator 12, a first phase-locked loop 13, a second phase-locked loop 14, an adder 15, a first operational amplifier 16 and an output driver 17, wherein the input end of the first phase-locked loop 13 is connected to the output end of the atomic clock 11, the input end of the second phase-locked loop 14 is connected to the output end of the constant temperature crystal oscillator 12, the output end of the first phase-locked loop 13 is connected to the first input end of the adder 15, the output end of the second phase-locked loop 14 is connected to the second input end of the adder 15, and the output end of the adder 15 is connected to the output end of the adder 16. The clock source unit 1 further comprises a temperature compensation circuit 18 (including a temperature sensor and a heating or cooling element, the heating element includes any one of a resistance heater, a thermistor and an electric heating film, and the cooling element includes any one of a Peltier effect cooler, a fan and a heat sink), and the temperature compensation circuit 18 is connected to the inverting input terminal of the first operational amplifier 16.

[0024] In this embodiment, the atomic clock 11 works based on the resonant frequency of specific atoms (such as cesium, rubidium, etc.), and can maintain its timing accuracy for a long time without obvious drift, so that the clock source unit 1 can maintain extremely high time accuracy for a long time. The constant temperature crystal oscillator 12 can provide a very stable frequency output in a short period of time. The constant temperature crystal oscillator 12 is placed in a temperature-controlled environment. The constant temperature crystal oscillator 12 can minimize the impact of temperature on frequency stability, thereby providing better short-term frequency stability than ordinary crystal oscillators. The function of the first phase-locked loop 13 is to lock the extremely stable and accurate frequency signal provided by the atomic clock 11 to a specific frequency. The first phase-locked loop 13 adjusts the output frequency of its internal oscillator to match the frequency and phase of the frequency signal of the atomic clock 11. The first phase-locked loop 13 continuously adjusts the frequency of its internal oscillator through a feedback mechanism until its output signal is completely synchronized with the frequency and phase of the atomic clock 11. In addition, the first phase-locked loop 13 can also filter out the noise and interference of the frequency signal output by the atomic clock 11, thereby improving the signal quality.

[0025] Similarly, the second phase-locked loop 14 is used to ensure that the output frequency of its internal oscillator is synchronized with the frequency and phase of the signal generated by the oven-controlled crystal oscillator 12 .

[0026] The signals output by the atomic clock 11 and the oven-controlled crystal oscillator 12 are respectively adjusted by the first phase-locked loop 13 and the second phase-locked loop 14 and sent to the adder 15 for merging processing, so as to generate a precise and stable clock signal based on the long-term stability of the atomic clock 11 and the short-term stability of the oven-controlled crystal oscillator 12, thereby providing a solid foundation for generating square wave pulses with sub-nanosecond accuracy.

[0027] It should be noted that the adder 15 combines the two signals from the first phase-locked loop 13 and the second phase-locked loop 14 and outputs the combined signal. This output signal is often weak. By setting a first operational amplifier 16 after the adder 15, the strength of the output signal can be enhanced to ensure that it has sufficient amplitude to drive the output driver 17.

[0028] It should also be noted that although the first operational amplifier 16 can enhance the strength of the output signal, its current driving capability is limited, and the output driver 17 can provide a stronger current driving capability to ensure that the signal can be transmitted to the subsequent circuit without losing strength. In addition, for high-speed signals (such as sub-nanosecond pulses), fast rise and fall times are required, and the output driver 17 is usually designed with fast response characteristics, which can accelerate the edge conversion of high-speed signals, thereby helping to produce clear and accurate pulse shapes.

[0029] It should be further explained that the clock source unit 1 is configured with a temperature compensation circuit 18 because temperature changes will affect the operating frequency of the constant temperature crystal oscillator and the phase-locked loop, thereby generating frequency drift, which will cause signal distortion or increase delay, especially in high-speed signal processing. The present application introduces a temperature compensation circuit 18 to help the first operational amplifier 16 reduce gain changes or bias point drift caused by temperature, and ensure that the signal maintains good linearity and signal-to-noise ratio throughout the entire operating temperature range, thereby ensuring that the clock source unit 1 can provide a highly accurate and stable clock signal even in different temperature environments, thereby supporting the generation of high-quality sub-nanosecond square wave pulses.

[0030] In another exemplary embodiment, the high-speed switching circuit uses GaN (Gallium Nitride) or SiC (Silicon Carbide) transistors.

[0031] In this embodiment, since the transistors of these two materials have higher carrier mobility and lower on-resistance, the high carrier mobility of GaN and SiC transistors means that electrons or holes can move faster through semiconductor materials under the action of an electric field, so when a control signal is applied, it can support extremely fast switching speeds, which can theoretically reach sub-nanosecond levels. In addition, lower on-resistance means less energy loss when the transistor is on, and the state transition can be completed in a shorter time, which helps to reduce the switching time, making the rise time and fall time of the pulse signal shorter, that is, the edge is steeper.

[0032] In another exemplary embodiment, the control logic unit adopts FPGA.

[0033] In this embodiment, the FPGA is used to program and set various parameters of the output pulse, such as pulse width, repetition rate, etc., and control the work of the subsequent stages according to these parameters. The FPGA is also responsible for synchronizing all internal operations with the clock source. First, the FPGA is synchronized with the clock source unit to ensure that all internal operations can be performed based on a very precise time reference. Based on the above-set pulse parameters, the FPGA will generate a series of control signals according to a preset algorithm or logic. These control signals are used to accurately control the working state of the high-speed switch, that is, to determine when to turn on and off the switch, thereby forming a pulse sequence with a specific width and interval.

[0034] It should be noted that, since the control logic unit adopts FPGA, the output end of the output driver in the clock source unit can be specifically connected to the global clock input pin (such as GCLK0) of the control logic unit, and the control end of the high-speed switch can be connected to the I / O pin (such as GPIO_0) of the control logic unit.

[0035] In another exemplary embodiment, Figure 3 As shown, the pre-driving and amplifying unit 4 includes: a first capacitor C1, a second operational amplifier U2, a gate driver 43 and a power MOSFET tube 44, wherein the first end of the first capacitor C1 is connected to the output end of the high-speed switch, the second end of the first capacitor C1 is connected to the in-phase input end of the second operational amplifier U2, a voltage divider network 41 is arranged between the inverting input end and the output end of the second operational amplifier U2, the output end of the second operational amplifier U2 is connected to the input end of the gate driver 43 through a matching network 42, the output end of the gate driver 43 is connected to the gate of the power MOSFET tube 44, the source of the power MOSFET tube 44 is connected to the third ground terminal GND3, and the drain of the power MOSFET tube 44 is connected to the protection unit 5.

[0036] In this embodiment, the first capacitor C1 is used as a coupling capacitor in the pre-driving and amplifying unit 4, and its main function is to block the DC component and only allow AC signals to pass through to ensure that the signal transmitted to the second operational amplifier U2 does not contain any unnecessary DC bias.

[0037] The second operational amplifier U2 and the voltage divider network 41 form a negative feedback amplifier. The voltage divider network 41 is connected between the inverting input terminal and the output terminal of the second operational amplifier U2 to form a voltage feedback loop, which helps to stabilize the gain of the second operational amplifier and improve the linearity. The second operational amplifier U2 amplifies the signal received from the first capacitor C1 and adjusts the output voltage level according to the ratio set by the voltage divider network 41.

[0038] The output of the second operational amplifier U2 is connected to the input of the gate driver 43 after passing through the matching network 42. The matching network 42 is used to ensure impedance matching between the signal source and the load, thereby reducing reflections and improving signal integrity. The gate driver 43 is responsible for converting the control signal provided by the second operational amplifier U2 into a drive signal sufficient to quickly turn on or off the power MOSFET tube 44. The power MOSFET tube 44 serves as the final switching element, and its gate receives a signal from the gate driver 43. When the gate of the power MOSFET tube 44 receives sufficient voltage, the MOSFET tube is turned on, so that current can flow from the power supply to the load. Since the power MOSFET tube 44 has a low on-resistance, it can effectively amplify the signal provided by the previous stage to generate the required output pulse.

[0039] like Figure 3As shown, the voltage divider network 41 includes a first resistor R1 and a second resistor R2, wherein the first end of the first resistor R1 is connected to the output end of the second operational amplifier U2, the second end of the first resistor R1 is connected to the inverting input end of the second operational amplifier U2, the first end of the second resistor R2 is connected to the second end of the first resistor R1, and the second end of the second resistor R2 is connected to the first ground terminal GND1.

[0040] The matching network 42 includes a third resistor R3, a first inductor L1 and a second capacitor C2, wherein a first end of the third resistor R3 is connected to an output end of the second operational amplifier U2, a second end of the third resistor R3 is connected to an input end of the gate driver 43 via the first inductor L1, a first end of the second capacitor C2 is connected to a second end of the third resistor R3, and a second end of the second capacitor C2 is connected to a second ground end GND2.

[0041] The pre-drive and amplification unit 4 achieves highly accurate amplification and conditioning of the input signal (i.e., a pulse signal with steep edges) by precisely configuring the voltage divider network 41 and the programmable second operational amplifier U2, and can ensure that the output pulse strictly meets the expected requirements in terms of shape and amplitude. The module uses the second operational amplifier U2 in combination with the matching network 42 and the gate driver 43, which can not only adjust the gain and frequency response according to specific application requirements, but also effectively convert the amplified control signal into a driving level required for fast switching of the power MOSFET tube 44. This design ensures an extremely short delay from receiving the input signal to generating the output pulse, which is essential for achieving sub-nanosecond rise time and fall time. Specifically, the high gain and wide bandwidth characteristics of the second operational amplifier U2 support fast signal processing, while the matching network 42 optimizes signal transmission efficiency and reduces reflection loss. The gate driver 43 further accelerates the switching speed of the power MOSFET tube 44, enabling it to complete state switching in nanoseconds or even sub-nanoseconds, thereby generating high-quality square wave pulses with steep edges.

[0042] In another exemplary embodiment, Figure 5As shown, the output unit includes: a first filtering and voltage stabilizing module, a second filtering and voltage stabilizing module, a signal regulating module, a signal processing module and a signal output module, wherein the first filtering and voltage stabilizing module is used to provide a stable power supply signal and filter out noise in the power signal; the second filtering and voltage stabilizing module is used to further purify the power signal; the signal regulating module is used to regulate the amplified and conditioned pulse signal; the signal processing module is used to convert the regulated pulse signal into a sub-nanosecond square wave pulse with a steep edge and an accurate pulse width; the signal output module is used to output a sub-nanosecond square wave pulse with a steep edge and an accurate pulse width.

[0043] In another exemplary embodiment, the first filtering and voltage stabilization module 61 includes: a first low voltage dropout regulator LDO1, a fifth resistor R5, a first transistor T1, a second inductor L2 and a fourth capacitor C4, wherein the first end of the fifth resistor R5 is connected to the base of the first transistor T1 to form a first node N1, the second end of the fifth resistor R5 is connected to the input end of the first low voltage dropout regulator LDO1, the output end of the first low voltage dropout regulator LDO1 is connected to the first end of the second inductor L2, the second end of the second inductor L2 is connected to a -5V power supply, the first end of the fourth capacitor C4 is connected to the output end of the first low voltage dropout regulator LDO1, the second end of the fourth capacitor C4 is connected to the seventh ground terminal GND7, the collector of the first transistor T1 is connected to the sixth ground terminal GND6, and the emitter of the first transistor T1 is connected to the first input end of the signal conditioning module to form a second node N2.

[0044] In this embodiment, the first low dropout regulator LDO1 is used to provide a stable voltage output, and can maintain the stability of the output voltage even if the input voltage fluctuates within a certain range.

[0045] The fifth resistor R5 serves as a current limiting resistor, which is used to limit the current flowing into the base of the first transistor T1 and help set the operating point of the first transistor T1. In addition, the fifth resistor R5 also participates in forming a part of the feedback path to ensure the output stability of the first low voltage dropout regulator.

[0046] The second inductor L2 and the fourth capacitor C4 together form an LC filter, which is used to filter out high-frequency noise or interference in the power signal provided by the -5V power supply to ensure the purity of the power signal. In addition, the fourth capacitor C4 also acts as a bypass capacitor, which can quickly respond to transient current requirements and absorb voltage fluctuations, thereby maintaining a smoother DC voltage output.

[0047] In another exemplary embodiment, the second filtering and voltage stabilization module 62 includes: a second low voltage dropout regulator LDO2, a ninth capacitor C9 and a third inductor L3, wherein the input end of the second low voltage dropout regulator LDO2 is connected to a +5V power supply through the third inductor L3, the output end of the second low voltage dropout regulator LDO2 is connected to the first input end of the signal processing module to form an eighth node N8, the first end of the ninth capacitor C9 is connected to the input end of the second low voltage dropout regulator LDO2, and the second end of the ninth capacitor C9 is connected to the eighth ground terminal GND8.

[0048] In this embodiment, the working principle of the second filtering and voltage stabilizing module is similar to that of the first filtering and voltage stabilizing module, which will not be repeated here. The difference is that the second filtering and voltage stabilizing module is used to filter and stabilize the +5V power supply.

[0049] In another exemplary embodiment, the signal conditioning module 63 includes: a second transistor T2, a sixth resistor R6, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a fifth capacitor C5, a sixth capacitor C6 and a switch S, wherein the first end of the sixth resistor R6 is connected to the second node N2 as the first input end of the signal conditioning module, the second end of the sixth resistor R6 is connected to the first input end of the signal processing module to form a fourth node N4, the emitter of the second transistor T2 is connected to the second node N2, and the base of the second transistor T2 is connected to the first end of the ninth resistor R9 to form a fifth node Point N5, the collector of the second transistor T2 is connected to the second input end of the signal processing module to form a third node N3, the second end of the ninth resistor R9 is connected to the third node N3 through the eighth resistor R8, the first end of the fifth capacitor C5 is connected to the fifth node N5, the second end of the fifth capacitor C5 is connected to the sixth ground terminal GND6 through the switch S, the first end of the tenth resistor R10 is connected to the first node N1, the second end of the tenth resistor R10 is connected to the first end of the sixth capacitor C6, and the second end of the sixth capacitor C6 is connected to the sixth ground terminal GND6 through the switch S.

[0050] In this embodiment, the input pulse signal enters the signal conditioning module from the second node N2 through the sixth resistor R6 and is transmitted to the emitter of the second transistor T2. The base of the second transistor T2 is grounded through the ninth resistor R9 and the fifth capacitor C5, and the base is also indirectly connected to the third node N3 through the ninth resistor R9 and the eighth resistor R8, thereby forming a local feedback loop. This feedback mechanism can help stabilize the operating point of the second transistor T2 and set the gain, thereby reducing the gain fluctuation of the second transistor T2 caused by temperature changes or other factors. The ninth resistor R9 and the eighth resistor R8 together form a voltage divider network, which is used to adjust the voltage of the base of the second transistor T2 relative to its emitter, optimize the conduction state of the second transistor T2, and thus affect the conduction degree of the second transistor T2, so that the input signal can be amplified under optimal conditions (the voltage divider network composed of the ninth resistor R9 and the eighth resistor R8 can provide a stable DC voltage for the base of the second transistor T2 without relying on the input signal. This DC voltage determines the static operating point (Q point) of the second transistor T2. The appropriate static operating point setting helps to ensure that the second transistor T2 maintains a stable working state within the entire operating temperature range. In addition, the voltage divider network not only determines the static operating point of the second transistor T2, but also affects the AC gain of the second transistor T2. When the second transistor T2 is in the linear amplification region, its The gain is mainly determined by the base current and the emitter resistance. By adjusting the ratio of the ninth resistor R9 and the eighth resistor R8, the voltage applied to the base can be accurately controlled, thereby indirectly controlling the base current and affecting the gain. By adjusting the ratio of R9 and R8, the voltage applied to the base of T2 can be accurately controlled. Furthermore, a higher base voltage causes more current to flow into the second transistor T2, increasing its conduction degree; and vice versa. Therefore, by appropriately selecting the values ​​of the two resistors, the conduction degree of the second transistor T2 can be flexibly adjusted as needed to adapt to different application requirements. If the base voltage is too high or too low, the second transistor T2 may enter the saturation region or the cut-off region, resulting in serious signal distortion or even failure to amplify the signal normally. Through a reasonable voltage divider network design, it can be ensured that the second transistor T2 is always in the best conduction state, neither oversaturated nor cut-off, thereby ensuring accurate signal amplification). When the second transistor T2 is turned on, the current flows from the collector to the emitter, and the input signal is amplified in the process. The amplified signal is output to the second input end of the signal processing module through the third node N3. The fifth capacitor C5 plays a coupling role here, ensuring that only AC signals can reach the base of the second transistor T2 to avoid any unnecessary DC offset. The sixth capacitor C6 can further filter out unnecessary high-frequency noise to ensure signal quality.The switch S can be used to control whether to ground the fifth capacitor C5 and the sixth capacitor C6, depending on the requirements of a specific application scenario. For example, in some cases, it may be necessary to turn off these capacitors to change the behavior of the circuit or perform debugging.

[0051] The signal conditioning module utilizes local feedback (a voltage divider network formed by the ninth resistor R9 and the eighth resistor R8) to effectively reduce gain fluctuations of the second transistor T2 caused by temperature changes or other factors, thereby improving the stability of the output signal of the second transistor T2.

[0052] In summary, the signal conditioning module realizes effective amplification, filtering and necessary conditioning of the received pulse signal through the coordinated work of the above components, and can ensure that the purity and strength of the pulse signal meet the requirements of subsequent processing.

[0053] In another exemplary embodiment, the signal processing module 64 includes: a third transistor T3, a fourth transistor T4, a seventh resistor R7, a seventh capacitor C7, an eighth capacitor C8, an eleventh resistor R11, a tenth capacitor C10 and an eleventh capacitor C11, wherein the base of the third transistor T3 is connected to the third node N3 as the second input terminal of the signal processing module, the collector of the third transistor T3 is connected to the sixth ground terminal GND6, the emitter of the third transistor T3 is connected to the base of the fourth transistor T4, the emitter of the fourth transistor T4 is connected to the first end of the eleventh resistor R11 to form a sixth node N6, and the eleventh resistor R11 The second end of the transistor T4 is connected to the fourth node N4 as the first input end of the signal processing module, the collector of the fourth transistor T4 is connected to the first end of the seventh capacitor C7 to form a seventh node N7, the second end of the seventh capacitor C7 is connected to the first input end of the signal output module to form an eighth node, the eighth capacitor C8 is connected in parallel to both ends of the seventh capacitor C7, the first end of the tenth capacitor C10 is connected to the fourth node N4, the second end of the tenth capacitor C10 is connected to the sixth ground terminal GND6, the first end of the eleventh capacitor C11 is connected to the fourth node N4, and the second end of the eleventh capacitor C11 is connected to the sixth ground terminal GND6.

[0054] In this embodiment, the third transistor T3 and the fourth transistor T4 form a cascade amplifier. The input signal enters the base of the third transistor T3 through the third node N3. The third transistor T3 acts as a first-stage amplifier, and its collector is connected to the sixth ground terminal GND6, while the emitter is connected to the base of the fourth transistor (T4). The fourth transistor T4 acts as a second-stage amplifier, and its emitter is connected to the fourth node N4 through the eleventh resistor R11 to form the sixth node N6. This dual-stage amplifier structure can significantly improve the gain and contribute to the shaping of the signal, so that the generated square wave pulse is clearer and steeper.

[0055] The seventh capacitor C7 and the eighth capacitor C8 are connected in parallel between the collector of the fourth transistor T4 and the first input terminal of the signal output module, and their main function is to filter out high-frequency noise and smooth the signal edge, thereby generating a purer square wave pulse. In addition, the seventh capacitor C7 and the eighth capacitor C8 can also be used to help stabilize the output signal to prevent instability or distortion caused by transient response. The tenth capacitor C10 and the eleventh capacitor C11 are connected to the sixth ground terminal from the fourth node N4 respectively. The tenth capacitor C10 and the eleventh capacitor C11 are used as bypass capacitors to help remove noise in the power supply, ensure that the signal processing module can work in a clean power supply environment, and avoid the influence of power supply fluctuations on signal quality.

[0056] In summary, the signal processing module can significantly improve the strength and clarity of the input signal by adopting a two-stage amplification structure composed of the third transistor T3 and the fourth transistor T4, ensuring that the generated square wave pulse has a steep rising edge and falling edge. After the input signal enters the base of the third transistor T3 via the third node N3 for preliminary amplification, it is further enhanced and shaped by the fourth transistor T4, and finally output to the signal output module. The seventh capacitor C7 and the eighth capacitor C8 connected in parallel between the collector of the fourth transistor T4 and the signal output module effectively filter out high-frequency noise and smooth the signal edge, ensuring the purity and stability of the pulse. In addition, the tenth capacitor C10 and the eleventh capacitor C11 act as bypass capacitors to remove noise in the power supply, ensuring that the signal processing process is carried out in a clean power supply environment, and avoiding the influence of power supply fluctuations on signal quality. This tightly coupled design enables the signal processing module to accurately convert the amplified signal into a high-quality square wave pulse that meets the sub-nanosecond level accuracy requirements.

[0057] In another exemplary embodiment, the signal output module 65 includes: a fifth transistor T5, a twelfth resistor R12, a thirteenth resistor R13 and a fourteenth resistor R14, wherein the emitter of the fifth transistor T5 is connected to the sixth node N6, the collector of the fifth transistor T5 is connected to the first end of the twelfth resistor R12, the second end of the twelfth resistor R12 is connected to the eighth node N8 as the first input end of the signal output module, the base of the fifth transistor T5 is connected to the first end of the thirteenth resistor R13 to form a ninth node N9, the second end of the thirteenth resistor R13 is connected to the output end OUT of the output module, the first end of the fourteenth resistor R14 is connected to the ninth node N9, and the second end of the fourteenth resistor R14 is connected to the fourth node N4.

[0058] In this embodiment, the input signal enters the emitter of the fifth transistor T5 from the sixth node N6. The fifth transistor T5 acts as a switch or buffer, and its collector is connected to the eighth node N8 through the twelfth resistor R12, and the base of the fifth transistor T5 is connected to the ninth node N9 through the thirteenth resistor R13, and the other end of the thirteenth resistor R13 is directly connected to the output terminal OUT of the output module. This configuration allows the fifth transistor T5 to respond quickly and adjust its conduction state according to the change of the base voltage, thereby accurately controlling the transmission of the signal. The fourteenth resistor R14 is connected between the ninth node N9 and the fourth node N4), which can help stabilize the base voltage of the fifth transistor T5 and provide an additional feedback path to ensure the stability of signal transmission.

[0059] The signal output module uses the fifth transistor T5 as a high-speed switch and combines appropriate resistor and capacitor configurations, so that the signal output module can ensure that the generated square wave pulse has very steep rising and falling edges.

[0060] In summary, the signal output module works closely with the pre-stage signal processing module to ensure that each link from signal amplification and shaping to final output can complete the task efficiently and accurately, thereby achieving the generation of high-quality sub-nanosecond square wave pulses.

[0061] In another exemplary embodiment, the pulse generator further comprises a protection unit 5, such as Figure 4As shown, the protection unit 5 includes a transient voltage suppression diode D, a fourth resistor R4, a solid-state switch, a common mode choke CMC, an iron oxide bead FB, a first bidirectional diode TVS1, a second bidirectional diode TVS2 and a third capacitor C3, wherein the first end of the fourth resistor R4 is connected to the drain of the power MOSFET tube, the second end of the fourth resistor R4 is connected to the first end of the first bidirectional diode TVS1 through the solid-state switch, the second end of the first bidirectional diode TVS1 is connected to the first end of the iron oxide bead FB through the common mode choke CMC, the second end of the iron oxide bead FB is connected to the first end of the third capacitor C3, and the first end of the first bidirectional diode TVS1 is connected to the fourth ground terminal GND4, the second end of the third capacitor C3 is connected to the signal input terminal IN of the output module 6, and the second end of the third capacitor C3 is connected to the fifth ground terminal GND5, the second bidirectional diode TVS2 is connected in parallel to the two ends of the first bidirectional diode TVS1, and the transient voltage suppression diode D is connected in parallel to the two ends of the iron oxide bead FB.

[0062] In this embodiment, the transient voltage suppression diode D and the first bidirectional diode TVS1 and the second bidirectional diode TVS2 work together to quickly turn on when a transient overvoltage is detected to clamp the voltage within a safe range. This fast response mechanism can effectively protect the subsequent circuit from the impact of instantaneous high voltage. The first bidirectional diode TVS1 and the second bidirectional diode TVS2 are connected in parallel to share the current in the overvoltage event, which means that the entire protection circuit can handle a larger peak pulse current (IPP), thereby improving the protection against high-energy transient events. If one of the TVS diodes fails or ages, the other can continue to provide protection. This redundant design increases the overall reliability of the protection unit. In some cases, two TVS diodes in parallel can achieve a lower effective clamping voltage. This is because when the two TVS diodes are turned on at the same time, the total dynamic resistance will be reduced, thereby making the clamping voltage lower, which can further protect the subsequent circuit from high voltage impact.

[0063] The fourth resistor R4 can limit the maximum current passing through the solid-state switch to prevent damage caused by excessive current. The solid-state switch quickly cuts off or restores the circuit connection as needed, providing an additional safety barrier for the circuit.

[0064] The common mode choke CMC and the ferrite bead FB work together to suppress electromagnetic interference from the external environment. Among them, the common mode choke CMC mainly filters the common mode noise in the low frequency to medium frequency range, and can generate a reverse magnetic field through its internal coil to offset the common mode current. The ferrite bead FB exhibits high impedance in the high frequency band, can absorb and consume high frequency noise energy, and ensure the purity of the signal path. Since the two work in different frequency bands, they can effectively filter out noise of various frequencies in a complex electrical environment (including common mode noise, differential mode noise, and high frequency noise, etc.), ensure the purity of the transmitted signal, and reduce signal distortion, so as to ensure that the generated sub-nanosecond square wave pulse has a steep rising edge and falling edge, which meets the high precision requirements. Therefore, compared with a single magnetic bead, the present application can provide a wider noise suppression range by connecting the common mode choke CMC and the ferrite bead FB in parallel to work together, thereby maximizing the accuracy of the square wave pulse.

[0065] The third capacitor C3 is used as a bypass capacitor and is placed at the signal input terminal IN of the output module to help filter out high-frequency noise in the power supply, ensuring that the signal entering the output module is as pure as possible, reducing the possibility of distortion and interference.

[0066] The above components together constitute a multi-level protection network. From transient voltage suppression, current limiting, electromagnetic interference suppression to high-frequency noise filtering, each link works closely together to provide comprehensive protection measures for the transmission unit.

[0067] It should be noted that the solid-state switch can be, for example, a MOSFET, the gate of the MOSFET is connected to the timer TM, the source of the MOSFET is connected to the second end of the fourth resistor R4, and the drain of the MOSFET is connected to the first end of the first bidirectional diode TVS1. In addition, the fourth resistor R4 is a thermistor, and the third capacitor C3 is a ceramic capacitor. By using MOSFET as a solid-state switch, fast and precise control of the current path is achieved through its excellent high-speed switching capability and extremely low on-resistance (Rds(on)). This design enables the MOSFET to quickly cut off the circuit connection when an abnormal situation is detected, preventing overcurrent or overvoltage from damaging subsequent sensitive circuits, and ensuring that the system can operate efficiently and stably under various working conditions.

[0068] Thermistors have the property of changing their resistance value as temperature changes, which not only enables them to effectively limit the maximum current during the startup phase or overload conditions to avoid damage caused by excessive current, but also self-adjust according to temperature changes to provide additional temperature compensation functions. This dual role significantly improves the robustness and safety of the system, especially in high-power or high-temperature environments.

[0069] At the same time, the third capacitor C3 is a ceramic capacitor. With its excellent high-frequency filtering performance and low equivalent series resistance (ESR) and equivalent series inductance (ESL), it can effectively remove high-frequency noise in the power supply and ensure the purity of the signal path. Ceramic capacitors can also quickly provide additional charge during transient events (such as power supply voltage mutations) to maintain voltage stability, thereby preventing transient voltage fluctuations from affecting the system. This feature is particularly critical for applications that require high precision and high reliability, ensuring that the sub-nanosecond square wave pulses output by the pulse generator have steep rising and falling edges, reducing the possibility of distortion and interference.

[0070] In summary, this combination not only greatly improves the overall reliability of the pulse generator, but also ensures its stable operation in complex electrical environments. Through the precise control of MOSFET, the current limiting and temperature compensation of thermistors, and the efficient filtering of ceramic capacitors, the entire generator can generate high-quality, high-precision sub-nanosecond square wave pulses, thus meeting the strict requirements of modern high-tech fields for high-precision time bases and signal integrity.

[0071] The above embodiments are only for illustrating the technical concept and features of the present application, and their purpose is to enable people familiar with the technology to understand the content of the present application and implement it accordingly, and they cannot be used to limit the protection scope of the present application. Any equivalent changes or modifications made according to the spirit of the present application should be included in the protection scope of the present application.

Claims

1. A sub-nanosecond square wave pulse generator, characterized in that: The generator comprises: Clock source unit, control logic unit, high-speed switch, pre-drive and amplification unit, protection unit and output unit, among which, The clock source unit is used to provide a clock signal for generating sub-nanosecond square wave pulses; The control logic unit is used to set parameters of the sub-nanosecond square wave pulse and generate a control signal based on the parameters; The high-speed switch is used to perform fast switching based on the control signal to generate a pulse signal with a steep edge; The pre-driving and amplifying unit is used to amplify and condition the pulse signal with a steep edge; The output unit is used to further process the amplified and conditioned pulse signal to output a sub-nanosecond square wave pulse; The protection unit is used to provide protection for the output unit.

2. A sub-nanosecond square wave pulse generator according to claim 1, characterized in that: The clock source unit comprises: Atomic clock, constant temperature crystal oscillator, first phase-locked loop, second phase-locked loop, adder, first operational amplifier, output driver, wherein, The input end of the first phase-locked loop is connected to the output end of the atomic clock, The input end of the second phase-locked loop is connected to the output end of the oven-controlled crystal oscillator. The output terminal of the first phase-locked loop is connected to the first input terminal of the adder, The output terminal of the second phase-locked loop is connected to the second input terminal of the adder, The output end of the adder is connected to the non-inverting input end of the first operational amplifier, The output terminal of the first operational amplifier is connected to the input terminal of the output driver, The output end of the output driver is connected to the input end of the control logic unit; The clock source unit further includes a temperature compensation circuit, and the temperature compensation circuit is connected to the inverting input terminal of the first operational amplifier.

3. A sub-nanosecond square wave pulse generator according to claim 2, characterized in that: The temperature compensation circuit includes a temperature sensor and a heating or cooling element.

4. A sub-nanosecond square wave pulse generator according to claim 1, characterized in that: The pre-driving and amplifying unit comprises: A first capacitor, a second operational amplifier, a voltage divider network, a matching network, a gate driver, and a power MOSFET tube, wherein: The first end of the first capacitor is connected to the output end of the high-speed switch, The second end of the first capacitor is connected to the non-inverting input end of the second operational amplifier. The voltage divider network is arranged between the inverting input terminal and the output terminal of the second operational amplifier. The output terminal of the second operational amplifier is connected to the input terminal of the gate driver through the matching network. The output end of the gate driver is connected to the gate of the power MOSFET tube. The source of the power MOSFET is connected to the third ground terminal. The drain of the power MOSFET is connected to the protection unit.

5. A sub-nanosecond square wave pulse generator according to claim 1, characterized in that: The output unit comprises: A first filtering and voltage stabilizing module, a second filtering and voltage stabilizing module, a signal regulating module, a signal processing module and a signal output module, wherein: The first filtering and voltage stabilizing module is used to provide a stable power supply signal and filter out noise in the power supply signal; The second filtering and voltage stabilizing module is used to further purify the power supply signal; The signal conditioning module is used to condition the amplified and conditioned pulse signal; The signal processing module is used to convert the adjusted pulse signal into a sub-nanosecond square wave pulse with a steep edge and an accurate pulse width; The signal output module is used to output sub-nanosecond square wave pulses with steep edges and accurate pulse width.

6. A sub-nanosecond square wave pulse generator according to claim 5, characterized in that: The first filtering and voltage stabilizing module comprises: a first low voltage dropout regulator, a fifth resistor, a first transistor, a second inductor and a fourth capacitor, wherein: A first end of the fifth resistor is connected to the base of the first transistor to form a first node, and a second end of the fifth resistor is connected to the input end of the first low voltage dropout regulator; The output end of the first low voltage dropout regulator is connected to the first end of the second inductor; The second end of the second inductor is connected to a -5V power supply; A first end of the fourth capacitor is connected to the output end of the first low voltage dropout regulator, and a second end of the fourth capacitor is connected to the seventh ground end; The collector of the first transistor is connected to the sixth ground terminal, and the emitter of the first transistor is connected to the first input terminal of the signal adjustment module to form a second node.

7. A sub-nanosecond square wave pulse generator according to claim 5, characterized in that: The second filtering and voltage stabilizing module comprises: a second low voltage dropout regulator, a ninth capacitor and a third inductor, wherein: The input end of the second low voltage dropout regulator is connected to a +5V power supply through the third inductor, and the output end of the second low voltage dropout regulator is connected to the first input end of the signal processing module to form an eighth node; A first end of the ninth capacitor is connected to the input end of the second low voltage dropout regulator, and a second end of the ninth capacitor is connected to the eighth ground end.

8. A sub-nanosecond square wave pulse generator according to claim 6, characterized in that: The signal conditioning module comprises: A second transistor, a sixth resistor, an eighth resistor, a ninth resistor, a tenth resistor, a fifth capacitor, a sixth capacitor and a switch, wherein: The first end of the sixth resistor is connected to the second node as the first input end of the signal adjustment module, and the second end of the sixth resistor is connected to the first input end of the signal processing module to form a fourth node; The emitter of the second transistor is connected to the second node, the base of the second transistor is connected to the first end of the ninth resistor to form a fifth node, and the collector of the second transistor is connected to the second input end of the signal processing module to form a third node; The second end of the ninth resistor is connected to the third node via the eighth resistor; A first end of the fifth capacitor is connected to the fifth node, and a second end of the fifth capacitor is connected to a sixth ground terminal via the switch; A first end of the tenth resistor is connected to the first node, and a second end of the tenth resistor is connected to a first end of the sixth capacitor; The second end of the sixth capacitor is connected to the sixth ground end through the switch.

9. A sub-nanosecond square wave pulse generator according to claim 8, characterized in that: The signal processing module comprises: a third transistor, a fourth transistor, a seventh resistor, a seventh capacitor, an eighth capacitor, an eleventh resistor, a tenth capacitor and an eleventh capacitor, wherein: The base of the third transistor is connected to the third node as the second input terminal of the signal processing module, the collector of the third transistor is connected to the sixth ground terminal, and the emitter of the third transistor is connected to the base of the fourth transistor; The emitter of the fourth transistor is connected to the first end of the eleventh resistor to form a sixth node; The second end of the eleventh resistor is connected to the fourth node as the first input end of the signal processing module; The collector of the fourth transistor is connected to the first end of the seventh capacitor to form a seventh node; The second end of the seventh capacitor is connected to the first input end of the signal output module to form an eighth node; The eighth capacitor is connected in parallel to both ends of the seventh capacitor; A first end of the tenth capacitor is connected to the fourth node, and a second end of the tenth capacitor is connected to the sixth ground terminal; A first end of the eleventh capacitor is connected to the fourth node, and a second end of the eleventh capacitor is connected to the sixth ground terminal.

10. A sub-nanosecond square wave pulse generator according to claim 9, characterized in that: The signal output module comprises: a fifth transistor, a twelfth resistor, a thirteenth resistor and a fourteenth resistor, wherein: The emitter of the fifth transistor is connected to the sixth node, and the collector of the fifth transistor is connected to the first end of the twelfth resistor; The second end of the twelfth resistor is connected to the eighth node as the first input end of the signal output module; The base of the fifth transistor is connected to the first end of the thirteenth resistor to form a ninth node; The second end of the thirteenth resistor is connected to the output end of the output unit; A first end of the fourteenth resistor is connected to the ninth node, and a second end of the fourteenth resistor is connected to the fourth node.

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