Level conversion circuit, power supply chip and electronic equipment

Abstract

The invention provides a level conversion circuit, a power supply chip and electronic equipment, a power-on reset signal is accessed to the setting end of a first RS trigger, and the first RS trigger is correspondingly connected with a second RS trigger; the first end of the first pull-down unit and the first end of the second pull-down unit are used for accessing a low-voltage domain control signal; the second end of the first pull-down unit is connected between the positive output end of the first RS trigger and the setting end of the second RS trigger, and the third end of the first pull-down unit is grounded; the second end of the second pull-down unit is connected between the reverse output end of the first RS trigger and the reset end of the second RS trigger, and the third end of the second pull-down unit is grounded. Through state switching of the first pull-down unit and the second pull-down unit, the states of the first RS trigger and the second RS trigger are adjusted, the purpose of rapidly changing the high-voltage domain control signal is achieved, and the output switch signal voltage controlled by the high-voltage domain control signal is enabled to rise or fall more rapidly.

Description

Technical Field

[0001] The present invention relates to the field of power supplies, and in particular to a level conversion circuit, a power supply chip and an electronic device. Background Art

[0002] In the field of switching power supply design, such as the design of high-voltage and high-power non-isolated power chips (also known as BUCK chips), the power level uses high-voltage devices, such as upper and lower power tubes and the drive circuit of the upper power tube, which belongs to the high-voltage domain; the logic control module uses low-voltage devices, which belongs to the low-voltage domain. The control signal transmission between the high-voltage domain and the low-voltage domain requires the use of a level conversion circuit.

[0003] With the development of technology, the switching frequency is getting higher and higher, and the efficiency requirements are getting higher and higher, which requires a faster power tube switching rate to ensure a faster rise and fall rate of the output switch signal voltage (also known as SW). How to design a level conversion circuit that meets this requirement has become one of the difficult problems that technicians in this field are concerned about. Summary of the invention

[0004] The object of the present invention is to provide a level conversion circuit, a power chip and an electronic device to improve the above-mentioned problem.

[0005] In order to achieve the above purpose, the technical solution adopted by the embodiment of the present invention is as follows: In a first aspect, an embodiment of the present invention provides a level conversion circuit, the level conversion circuit comprising: a first RS trigger, a second RS trigger, a first pull-down unit, and a second pull-down unit; The set end of the first RS flip-flop is used to receive a power-on reset signal, the positive output end of the first RS flip-flop is connected to the set end of the second RS flip-flop, the negative output end of the first RS flip-flop is connected to the reset end of the second RS flip-flop, and the positive output end of the second RS flip-flop serves as the output end of the level conversion circuit; The first end of the first pull-down unit and the first end of the second pull-down unit are used to access the low-voltage domain control signal; The second end of the first pull-down unit is connected between the positive output end of the first RS flip-flop and the set end of the second RS flip-flop, and the third end of the first pull-down unit is grounded; The second end of the second pull-down unit is connected between the inverting output end of the first RS flip-flop and the reset end of the second RS flip-flop, and the third end of the second pull-down unit is grounded.

[0006] In the level conversion circuit provided in the embodiment of the present invention, the states of the first RS trigger and the second RS trigger are adjusted by switching the states of the first pull-down unit and the second pull-down unit, thereby achieving the purpose of quickly changing the high-voltage domain control signal (PWM_HV), so that the output switch signal voltage (SW) controlled by the high-voltage domain control signal (PWM_HV) can rise or fall faster.

[0007] Optionally, the first pull-down unit is used to switch to a conducting state when sampling a rising edge of the low-voltage domain control signal, and the duration of the conducting state is a first preset duration, so that the positive output end of the second RS trigger outputs a high-level high-voltage domain control signal; The second pull-down unit is used to switch to an on state when sampling the falling edge of the low-voltage domain control signal, and the duration of the on state is a second preset duration, so that the positive output end of the second RS trigger outputs a low-level high-voltage domain control signal.

[0008] Optionally, the first pull-down unit includes a rising edge sampling circuit, a first driving circuit and a first pull-down tube; The input end of the rising edge sampling circuit serves as the first end of the first pull-down unit, the output end of the rising edge sampling circuit is connected to the input end of the first driving circuit, the output end of the first driving circuit is connected to the first end of the first pull-down tube, the second end of the first pull-down tube serves as the second end of the first pull-down unit, and the third end of the first pull-down tube serves as the third end of the first pull-down unit; The rising edge sampling circuit is used to sample the rising edge of the low-voltage domain control signal, and when sampling the rising edge of the low-voltage domain control signal, output a first high pulse signal to the first driving circuit, wherein the pulse width of the first high pulse signal is the first preset duration; The first driving circuit is used for outputting a driving signal to the first pull-down tube when receiving the first high pulse signal, so as to switch the first pull-down tube to a conducting state.

[0009] Because the first preset duration is less than the duration of the high level of the low-voltage domain control signal, the first pull-down tube will not be in the on state during the duration of the high level of the low-voltage domain control signal, which can reduce power consumption. The first preset duration is greater than the duration of the rising edge of the output switch signal voltage, thereby ensuring that the output switch signal voltage can smoothly complete the jump.

[0010] Optionally, the second pull-down unit includes a falling edge sampling circuit, a second driving circuit and a second pull-down tube; The input end of the falling edge sampling circuit serves as the first end of the second pull-down unit, the output end of the falling edge sampling circuit is connected to the input end of the second driving circuit, the output end of the second driving circuit is connected to the first end of the second pull-down tube, the second end of the second pull-down tube serves as the second end of the second pull-down unit, and the third end of the second pull-down tube serves as the third end of the second pull-down unit; The falling edge sampling circuit is used to sample the falling edge of the low-voltage domain control signal, and when sampling the falling edge of the low-voltage domain control signal, output a second high pulse signal to the second driving circuit, wherein the pulse width of the second high pulse signal is the second preset duration; The second driving circuit is used for outputting a driving signal to the second pull-down tube when receiving the second high pulse signal, so as to switch the second pull-down tube to a conducting state.

[0011] Because the second preset duration is less than the low level duration of the low voltage domain control signal, the second pull-down tube will not be in the on state during the low level duration of the low voltage domain control signal, which can reduce power consumption. The second preset duration is greater than the duration of the falling edge of the output switch signal voltage, thereby ensuring that the output switch signal voltage can smoothly complete the jump.

[0012] Optionally, the level conversion circuit further includes a first diode and a second diode; The anode of the first diode and the anode of the second diode are used to access the output switch signal voltage; The cathode of the first diode is connected between the forward output terminal of the first RS flip-flop and the set terminal of the second RS flip-flop; A cathode of the second diode is connected between an inverting output terminal of the first RS flip-flop and a reset terminal of the second RS flip-flop.

[0013] The first diode and the second diode play a protective role, clamping the minimum voltage of the V21 / V22 node at (SW-VD), where VD is the forward conduction voltage of the first diode and the second diode, thereby preventing the first pull-down unit or the second pull-down unit from pulling the V21 / V22 node down to 0, causing the low-voltage device in the high-voltage domain to withstand the high voltage of 0--BST, resulting in device breakdown.

[0014] In a second aspect, an embodiment of the present invention provides a power chip, the power chip comprising a third switch tube, a third drive circuit, a first capacitor and the above-mentioned level conversion circuit; The output end of the level conversion circuit is connected to the input end of the third driving circuit, the output end of the third driving circuit is connected to the first end of the third switch tube, the second end of the third switch tube is used to access the high-voltage domain electrical signal, and the third end of the third switch tube is used to connect to the subsequent circuit; The low level end of the third driving circuit and one end of the first capacitor are connected to the third end of the third switch tube, and the other end of the first capacitor is connected to the high level end of the third driving circuit; The signal connected to the low level end of the third driving circuit is the output switch signal voltage, and the signal connected to the high level end of the third driving circuit is the bootstrap voltage, wherein the bootstrap voltage=the output switch signal voltage+the preset voltage; The high level end of the first RS trigger and the high level end of the second RS trigger are connected to the bootstrap voltage, and the low level end of the first RS trigger and the low level end of the second RS trigger are connected to the output switch signal voltage.

[0015] In a third aspect, an embodiment of the present invention provides an electronic device, including: the above-mentioned power chip.

[0016] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 A schematic diagram of the structure of a level conversion circuit provided by an embodiment of the present invention.

[0019] Figure 2 A schematic diagram of the structure of a power chip provided in an embodiment of the present invention.

[0020] Figure 3 A schematic diagram of working signals of a level conversion circuit provided by an embodiment of the present invention.

[0021] In the figure: 10 - first RS trigger; 20 - second RS trigger; 30 - first pull-down unit; 31 - rising edge sampling circuit; 40 - second pull-down unit; 41 - falling edge sampling circuit. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0023] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0024] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. At the same time, in the description of the present invention, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0025] Moreover, the terms "comprises," "comprising," or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0026] Some embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0027] Please refer to Figure 1 , Figure 1 The schematic diagram of the structure of the level conversion circuit provided by the embodiment of the present invention is as follows: The level conversion circuit comprises: a first RS trigger 10 , a second RS trigger 20 , a first pull-down unit 30 and a second pull-down unit 40 .

[0028] like Figure 1 As shown, the level conversion circuit is divided into a high voltage domain (SW-BST) and a low voltage threshold (0-VCC).

[0029] The set end of the first RS trigger 10 is used to access the power-on reset signal (POR), the positive output end of the first RS trigger 10 is connected to the set end of the second RS trigger 20, the reverse output end of the first RS trigger 10 is connected to the reset end of the second RS trigger 20, the reset end of the first RS trigger 10 is connected to the positive output end of the first RS trigger 10, and the positive output end of the second RS trigger 20 serves as the output end of the level conversion circuit.

[0030] The first end of the first pull-down unit 30 and the first end of the second pull-down unit 40 are used to access the low-voltage domain control signal (PWM_LV).

[0031] A second terminal of the first pull-down unit 30 is connected between the positive output terminal of the first RS flip-flop 10 and the set terminal of the second RS flip-flop 20 , and a third terminal of the first pull-down unit 30 is grounded.

[0032] A second terminal of the second pull-down unit 40 is connected between the inverting output terminal of the first RS flip-flop 10 and the reset terminal of the second RS flip-flop 20 , and a third terminal of the second pull-down unit 40 is grounded.

[0033] In an optional embodiment, the high level end of the first RS trigger 10 and the high level end of the second RS trigger 20 are connected to the bootstrap voltage (BST), and the low level end of the first RS trigger 10 and the low level end of the second RS trigger 20 are connected to the output switch signal voltage (SW), and the bootstrap voltage (BST) = the output switch signal voltage (SW) + the preset voltage.

[0034] In an optional embodiment, the first pull-down unit 30 is used to switch to an on state when a rising edge of the low-voltage domain control signal is sampled, and the duration of the on state is a first preset duration, so that the positive output end of the second RS trigger 20 outputs a high-level high-voltage domain control signal (PWM_HV).

[0035] The second pull-down unit 40 is used to switch to the on state when sampling the falling edge of the low-voltage domain control signal, and the duration of the on state is a second preset duration, so that the positive output end of the second RS trigger 20 outputs a low-level high-voltage domain control signal (PWM_HV).

[0036] Among them, the first preset time length is greater than the circuit transmission delay + the output switch signal voltage rising edge change time length, and less than or equal to the high level duration of the low voltage domain control signal; the second preset time length is greater than the circuit transmission delay + the output switch signal voltage falling edge change time length, and less than or equal to the low level duration of the low voltage domain control signal.

[0037] In the level conversion circuit provided in the embodiment of the present invention, the states of the first RS trigger and the second RS trigger are adjusted by switching the states of the first pull-down unit and the second pull-down unit, thereby achieving the purpose of quickly changing the high-voltage domain control signal (PWM_HV), so that the output switch signal voltage (SW) controlled by the high-voltage domain control signal (PWM_HV) can rise or fall faster.

[0038] It should be noted that after the high-voltage domain control signal (PWM_HV) becomes a high level, the output switch signal voltage (SW) rises rapidly, and after the high-voltage domain control signal (PWM_HV) becomes a low level, the output switch signal voltage (SW) drops rapidly.

[0039] like Figure 1 As shown in the figure, at the beginning of power-on, the loop has not started working yet, and the low-voltage domain control signal (PWM_LV) remains at a low level. The initial state of the high-voltage domain is as follows: The initial state of the power-on reset signal (POR) is a low level, that is, the set end of the first RS flip-flop 10 is a low level L, the forward output end of the first RS flip-flop 10 is a high level H, that is, V21 is a high level H, the reset end of the first RS flip-flop 10 is a high level H, and the reverse output end of the first RS flip-flop 10 is a low level L, that is, V22 is a low level L; The set end of the second RS flip-flop 20 is a high level H (the same as V21), the reset end of the second RS flip-flop 20 is a low level L, the reverse output end of the second RS flip-flop 20 is a high level H, and the forward output end of the second RS flip-flop 20 is a low level L, that is, the high-voltage domain control signal (PWM_HV) is a low level L at this time.

[0040] Optionally, the transition time of the power-on reset signal (POR) is earlier than the arrival time of the first rising edge of the low-voltage domain control signal (PWM_LV). After the power-on reset signal (POR) jumps to a high level, the power-on reset signal (POR) remains at a high level thereafter, the set end of the first RS trigger 10 is a high level H, the forward output end of the first RS trigger 10 is a high level H, that is, V21 is a high level H, the reset end of the first RS trigger 10 is a high level H, and the reverse output end of the first RS trigger 10 is a low level L, that is, V22 is a low level L; The set end of the second RS flip-flop 20 is a high level H (the same as V21), the reset end of the second RS flip-flop 20 is a low level L, the reverse output end of the second RS flip-flop 20 is a high level H, and the forward output end of the second RS flip-flop 20 is a low level L, that is, the high-voltage domain control signal (PWM_HV) is a low level L at this time.

[0041] When the first pull-down unit 30 is turned on and the second pull-down unit 40 is turned off, that is, V21 is pulled to a low level L, the set end of the second RS flip-flop 20 is a low level L (the same as V21), and the positive output end of the second RS flip-flop 20 is a high level H, that is, the high-voltage domain control signal (PWM_HV) is a high level H; the positive output end of the first RS flip-flop 10 is pulled to a low level L, the reset end of the first RS flip-flop 10 also becomes a low level L, and the reverse output end of the first RS flip-flop 10 is a high level H, that is, V22 is a high level H, the reset end of the second RS flip-flop 20 is a high level H, and the reverse output end of the second RS flip-flop 20 is a low level L. In this case, even if the first pull-down unit 30 is restored to be disconnected and the second pull-down unit 40 remains disconnected, the states of V21, V22 and the high-voltage domain control signal (PWM_HV) will be latched through the two RS flip-flops.

[0042] When the first pull-down unit 30 is disconnected and the second pull-down unit 40 is turned on, that is, V22 is pulled to the low level L, the reset terminal of the second RS flip-flop 20 is at the low level L (the same as V22), and the inverting output terminal of the second RS flip-flop 20 is at the high level H.

[0043] The reverse output terminal of the first RS flip-flop 10 is at a low level L, and the forward output terminal of the first RS flip-flop 10 is at a high level H, that is, V21 is at a high level H, and the set terminal of the second RS flip-flop 20 is at a high level H, so the forward output terminal of the second RS flip-flop 20 is at a low level L. In this case, even if the first pull-down unit 30 remains disconnected and the second pull-down unit 40 is disconnected again, the states of V21, V22 and the high-voltage domain control signal (PWM_HV) are latched by the two RS flip-flops.

[0044] Please continue to refer to Figure 1 The first pull-down unit 30 includes a rising edge sampling circuit 31, a first driving circuit U1 and a first pull-down tube Q1. The rising edge sampling circuit 31 and the first driving circuit U1 are low voltage devices, and the first pull-down tube Q1 is a high voltage device.

[0045] It should be noted that the first pull-down tube Q1 needs to have a small on-resistance, so the channel width W of the first pull-down tube Q1 needs to be large enough, which will cause the gate (G) parasitic capacitance to become larger. In this case, in order to achieve the purpose of fast switching, a first drive circuit U1 needs to be provided.

[0046] The input end of the rising edge sampling circuit 31 serves as the first end of the first pull-down unit 30 (connected to the low-voltage domain control signal PWM_LV), the output end of the rising edge sampling circuit 31 is connected to the input end of the first driving circuit U1, the output end of the first driving circuit U1 is connected to the first end of the first pull-down tube Q1, the second end of the first pull-down tube Q1 serves as the second end of the first pull-down unit 30 (connected between the positive output end of the first RS trigger 10 and the set end of the second RS trigger 20), and the third end of the first pull-down tube Q1 serves as the third end of the first pull-down unit 30 (grounded).

[0047] The rising edge sampling circuit 31 is used to sample the rising edge of the low-voltage domain control signal. When the rising edge of the low-voltage domain control signal is sampled, a first high pulse signal is output to the first drive circuit U1. The pulse width of the first high pulse signal is a first preset duration, wherein the first preset duration is less than the high level duration of the low-voltage domain control signal and greater than the rising edge change duration of the output switch signal voltage.

[0048] The first driving circuit U1 is used for outputting a driving signal to the first pull-down tube Q1 when receiving the first high pulse signal, so that the first pull-down tube Q1 is switched to a conducting state.

[0049] Because the first preset duration is less than the high level duration of the low voltage domain control signal, the first pull-down tube Q1 will not be in the on state during the high level duration of the low voltage domain control signal, which can reduce power consumption. The first preset duration is greater than the rising edge change duration of the output switch signal voltage, thereby ensuring that the output switch signal voltage can smoothly complete the jump.

[0050] Please continue to refer to Figure 1 The second pull-down unit 40 includes a falling edge sampling circuit 41, a second driving circuit U2 and a second pull-down tube Q2; wherein the falling edge sampling circuit 41 and the second driving circuit U2 are low-voltage devices, and the second pull-down tube Q2 is a high-voltage device.

[0051] The input end of the falling edge sampling circuit 41 serves as the first end of the second pull-down unit 40 (connected to the low-voltage domain control signal), the output end of the falling edge sampling circuit 41 is connected to the input end of the second driving circuit U2, the output end of the second driving circuit U2 is connected to the first end of the second pull-down tube Q2, the second end of the second pull-down tube Q2 serves as the second end of the second pull-down unit 40 (connected between the reverse output end of the first RS trigger 10 and the reset end of the second RS trigger 20), and the third end of the second pull-down tube Q2 serves as the third end of the second pull-down unit 40 (grounded).

[0052] The falling edge sampling circuit 41 is used to sample the falling edge of the low-voltage domain control signal. When the falling edge of the low-voltage domain control signal is sampled, a second high pulse signal is output to the second drive circuit U2. The pulse width of the second high pulse signal is a second preset duration, wherein the second preset duration is greater than the duration of the falling edge change of the output switch signal voltage, and is less than the duration of the low level of the low-voltage domain control signal.

[0053] The second driving circuit U2 is used for outputting a driving signal to the second pull-down tube Q2 when receiving the second high pulse signal, so that the second pull-down tube Q2 is switched to a conducting state.

[0054] Because the second preset duration is less than the low level duration of the low voltage domain control signal, the second pull-down tube Q2 will not be in the on state during the low level duration of the low voltage domain control signal, which can reduce power consumption. The second preset duration is greater than the duration of the falling edge of the output switch signal voltage, thereby ensuring that the output switch signal voltage can smoothly complete the jump.

[0055] In an optional embodiment, the input end of the first driving circuit U1 and the input end of the second driving circuit U2 can be directly connected to the low-voltage domain control signal PWM_LV, the first preset duration is equal to the high level duration of the low-voltage domain control signal, and the second preset duration is equal to the low level duration of the low-voltage domain control signal.

[0056] In an optional implementation, the on-resistance of the first pull-down tube Q1 and the on-resistance of the second pull-down tube Q2 are less than or equal to 1 / N of the on-resistance of the first RS trigger 10 (the first NAND gate M1 or the second NAND gate M2 therein), where N is a preset value (which may be but is not limited to a number of 10 or more). Thus, the driving capabilities of the first pull-down tube Q1 and the second pull-down tube Q2 are much greater than those of the first RS trigger 10 (the first NAND gate M1 or the second NAND gate M2 therein).

[0057] It can be seen from the analysis that after the rising edge of the low-voltage domain control signal (PWM_LV) arrives, the high-voltage domain control signal (PWM_HV) will become a high level, and the output switch signal voltage (SW) will rise rapidly. During the rapid rise of the output switch signal voltage (SW), due to the effect of the equivalent pull-up resistor of the first RS trigger 10 (the second NAND gate M2 therein) and the parasitic capacitance to ground of the second pull-down tube Q2, the voltage of the V22 node rises slower than the output switch signal voltage (SW), and may present a low level relative to the (SW--BST) voltage domain. Since the driving capability of the first pull-down tube Q1 is much greater than the driving capability of the first RS trigger 10, the low level state of V21 will not change, and the output state of the second RS trigger 20 will not change, thereby ensuring that the state of the high-voltage domain control signal (PWM_HV) is stable and will not be mis-flipped.

[0058] Regarding the structure of the RS trigger, the embodiment of the present invention also provides an optional implementation method, please continue to refer to Figure 1 , the first RS flip-flop 10 includes a first NAND gate M1 and a second NAND gate M2.

[0059] The first input terminal of the first NAND gate M1 serves as the set terminal of the first RS flip-flop 10 (for receiving the power-on reset signal POR), the second input terminal of the first NAND gate M1 is connected to the output terminal of the second NAND gate M2, and the output terminal of the first NAND gate M1 serves as the positive output terminal of the first RS flip-flop 10 (connected to the set terminal of the second RS flip-flop 20).

[0060] The first input terminal of the second NAND gate M2 and the second input terminal of the second NAND gate M2 (the reset terminal of the first RS flip-flop 10) are connected to the output terminal of the first NAND gate M1, and the output terminal of the second NAND gate M2 serves as the inverting output terminal of the first RS flip-flop 10 (connected to the reset terminal of the second RS flip-flop 20).

[0061] Please continue to refer to Figure 1 , the second RS flip-flop 20 includes a third NAND gate M3 and a fourth NAND gate M4.

[0062] The first input terminal of the third NAND gate M3 serves as the set terminal of the second RS flip-flop 20 (connected to the positive output terminal of the first RS flip-flop 10 ), the second input terminal of the third NAND gate M3 is connected to the output terminal of the fourth NAND gate M4, and the output terminal of the third NAND gate M3 serves as the positive output terminal of the second RS flip-flop 20 .

[0063] A first input terminal of the fourth NAND gate M4 is connected to the output terminal of the third NAND gate M3 , and a second input terminal of the fourth NAND gate M4 serves as a reset terminal of the second RS flip-flop 20 (connected to the inverting output terminal of the first RS flip-flop 10 ).

[0064] In an optional implementation, the high level end of the first RS trigger 10 and the high level end of the second RS trigger 20 are connected to the bootstrap voltage, the low level end of the first RS trigger 10 and the low level end of the second RS trigger 20 are connected to the output switch signal voltage, and the bootstrap voltage=output switch signal voltage+preset voltage. Specifically, the high level end of the first NAND gate M1, the high level end of the second NAND gate M2, the high level end of the third NAND gate M3, and the high level end of the fourth NAND gate M4 are connected to the bootstrap voltage, and the low level end of the first NAND gate M1, the low level end of the second NAND gate M2, the low level end of the third NAND gate M3, and the low level end of the fourth NAND gate M4 are connected to the output switch signal voltage.

[0065] Please continue to refer to Figure 1In an optional implementation, the level conversion circuit further includes a first diode D1 and a second diode D2.

[0066] The anode of the first diode D1 and the anode of the second diode D2 are used to access the output switch signal voltage (SW).

[0067] A cathode of the first diode D1 is connected between the forward output terminal of the first RS flip-flop 10 and the set terminal of the second RS flip-flop 20 .

[0068] A cathode of the second diode D2 is connected between the inverting output terminal of the first RS flip-flop 10 and the reset terminal of the second RS flip-flop 20 .

[0069] The first diode D1 and the second diode D2 play a protective role, clamping the minimum voltage of the V21 / V22 node at (SW-VD), where VD is the forward conduction voltage of the first diode D1 and the second diode D2, thereby preventing the first pull-down unit 30 or the second pull-down unit 40 from pulling the V21 / V22 node down to 0, causing the low-voltage device in the high-voltage domain to withstand the high voltage of 0--BST, resulting in device breakdown.

[0070] In an optional implementation, the first NAND gate M1 , the second NAND gate M2 , the third NAND gate M3 , the fourth NAND gate M4 , the first diode D1 , and the second diode D2 are all low-voltage devices in the high-voltage isolation region.

[0071] The present invention also provides a power chip. Figure 2 , Figure 2 A schematic diagram of the structure of a power chip provided by an embodiment of the present invention. The power chip includes a third switch tube Q3, a third drive circuit U3, a first capacitor C1 and the above-mentioned level conversion circuit.

[0072] The output end of the level conversion circuit is connected to the input end of the third driving circuit U3, the output end of the third driving circuit U3 is connected to the first end of the third switch tube Q3, the second end of the third switch tube Q3 is used to access the high-voltage domain electrical signal (VIN), and the third end of the third switch tube Q3 is used to connect to the subsequent circuit.

[0073] The low level end of the third driving circuit U3 and one end of the first capacitor C1 are connected to the third end of the third switch tube Q3 , and the other end of the first capacitor C1 is connected to the high level end of the third driving circuit U3 .

[0074] The signal connected to the low level end of the third driving circuit U3 is the output switch signal voltage, and the signal connected to the high level end of the third driving circuit U3 is the bootstrap voltage, which is the output switch signal voltage + the preset voltage.

[0075] The high level end of the first RS trigger 10 and the high level end of the second RS trigger 20 are connected to the bootstrap voltage (BST), and the low level end of the first RS trigger 10 and the low level end of the second RS trigger 20 are connected to the output switch signal voltage (SW).

[0076] It should be understood that when the high-voltage domain control signal (PWM_HV) output by the level conversion circuit is at a high level, the third drive circuit U3 outputs a control signal to control the third switch tube Q3 to be in an on state, and the output switch signal voltage (SW) starts to rise until it is equal to the high-voltage domain electrical signal (VIN). When the high-voltage domain control signal (PWM_HV) output by the level conversion circuit is at a low level, the third drive circuit U3 outputs a control signal to control the third switch tube Q3 to be in an off state, and the output switch signal voltage (SW) starts to rise until it drops to 0V.

[0077] Please refer to Figure 3 , Figure 3 A schematic diagram of the working signal of the level conversion circuit provided by an embodiment of the present invention. Wherein, T1 represents the first preset duration, T2 represents the second preset duration, PWM_LV represents the low voltage domain control signal, R_PWM_LV represents the first high pulse signal, F_PWM_LV represents the second high pulse signal, PWM_HV represents the high voltage domain control signal, BST represents the bootstrap voltage, and SW represents the output switch signal voltage.

[0078] An embodiment of the present invention further provides an electronic device, including: the above-mentioned power chip.

[0079] The electronic device may be, but is not limited to, a mobile phone, a computer, a server, or other intelligent terminals.

[0080] In summary, the embodiment of the present invention provides a level conversion circuit, a power chip and an electronic device, wherein the set end of the first RS trigger is connected to the power-on reset signal, the positive output end of the first RS trigger is connected to the set end of the second RS trigger, the reverse output end of the first RS trigger is connected to the reset end of the second RS trigger, and the positive output end of the second RS trigger is used as the output end of the level conversion circuit; the first end of the first pull-down unit and the first end of the second pull-down unit are used to access the low-voltage domain control signal; the second end of the first pull-down unit is connected between the positive output end of the first RS trigger and the set end of the second RS trigger, and the third end of the first pull-down unit is grounded; the second end of the second pull-down unit is connected between the reverse output end of the first RS trigger and the reset end of the second RS trigger, and the third end of the second pull-down unit is grounded. By switching the states of the first pull-down unit and the second pull-down unit, the states of the first RS trigger and the second RS trigger are adjusted, thereby achieving the purpose of quickly changing the high-voltage domain control signal, so that the output switch signal voltage controlled by the high-voltage domain control signal can be more quickly increased or decreased.

[0081] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

[0082] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A level conversion circuit, characterized in that: The level conversion circuit comprises: a first RS trigger, a second RS trigger, a first pull-down unit and a second pull-down unit; The set end of the first RS flip-flop is used to receive a power-on reset signal, the positive output end of the first RS flip-flop is connected to the set end of the second RS flip-flop, the negative output end of the first RS flip-flop is connected to the reset end of the second RS flip-flop, and the positive output end of the second RS flip-flop serves as the output end of the level conversion circuit; The first end of the first pull-down unit and the first end of the second pull-down unit are used to access the low-voltage domain control signal; The second end of the first pull-down unit is connected between the positive output end of the first RS flip-flop and the set end of the second RS flip-flop, and the third end of the first pull-down unit is grounded; The second end of the second pull-down unit is connected between the inverting output end of the first RS flip-flop and the reset end of the second RS flip-flop, and the third end of the second pull-down unit is grounded.

2. The level conversion circuit according to claim 1, characterized in that: The first pull-down unit is used to switch to a conducting state when sampling a rising edge of the low-voltage domain control signal, and the duration of the conducting state is a first preset duration, so that the positive output end of the second RS trigger outputs a high-level high-voltage domain control signal; The second pull-down unit is used to switch to an on state when sampling the falling edge of the low-voltage domain control signal, and the duration of the on state is a second preset duration, so that the positive output end of the second RS trigger outputs a low-level high-voltage domain control signal.

3. The level conversion circuit according to claim 1 or 2, characterized in that: The first pull-down unit includes a rising edge sampling circuit, a first driving circuit and a first pull-down tube; The input end of the rising edge sampling circuit serves as the first end of the first pull-down unit, the output end of the rising edge sampling circuit is connected to the input end of the first driving circuit, the output end of the first driving circuit is connected to the first end of the first pull-down tube, the second end of the first pull-down tube serves as the second end of the first pull-down unit, and the third end of the first pull-down tube serves as the third end of the first pull-down unit; The rising edge sampling circuit is used to sample the rising edge of the low-voltage domain control signal, and when sampling the rising edge of the low-voltage domain control signal, output a first high pulse signal to the first driving circuit, wherein the pulse width of the first high pulse signal is a first preset duration; The first driving circuit is used for outputting a driving signal to the first pull-down tube when receiving the first high pulse signal, so as to switch the first pull-down tube to a conducting state.

4. The level conversion circuit according to claim 1 or 2, characterized in that: The second pull-down unit includes a falling edge sampling circuit, a second driving circuit and a second pull-down tube; The input end of the falling edge sampling circuit serves as the first end of the second pull-down unit, the output end of the falling edge sampling circuit is connected to the input end of the second driving circuit, the output end of the second driving circuit is connected to the first end of the second pull-down tube, the second end of the second pull-down tube serves as the second end of the second pull-down unit, and the third end of the second pull-down tube serves as the third end of the second pull-down unit; The falling edge sampling circuit is used to sample the falling edge of the low-voltage domain control signal, and when sampling the falling edge of the low-voltage domain control signal, output a second high pulse signal to the second driving circuit, wherein the pulse width of the second high pulse signal is a second preset duration; The second driving circuit is used for outputting a driving signal to the second pull-down tube when receiving the second high pulse signal, so as to switch the second pull-down tube to a conducting state.

5. The level conversion circuit according to claim 1 or 2, characterized in that: The first RS trigger includes a first NAND gate and a second NAND gate; The first input end of the first NAND gate serves as the set end of the first RS flip-flop, the second input end of the first NAND gate is connected to the output end of the second NAND gate, and the output end of the first NAND gate serves as the positive output end of the first RS flip-flop; The first input terminal of the second NAND gate and the second input terminal of the second NAND gate are connected to the output terminal of the first NAND gate, and the output terminal of the second NAND gate serves as the inverting output terminal of the first RS trigger.

6. The level conversion circuit according to claim 1 or 2, characterized in that: The second RS trigger includes a third NAND gate and a fourth NAND gate; The first input terminal of the third NAND gate serves as the set terminal of the second RS flip-flop, the second input terminal of the third NAND gate is connected to the output terminal of the fourth NAND gate, and the output terminal of the third NAND gate serves as the positive output terminal of the second RS flip-flop; The first input terminal of the fourth NAND gate is connected to the output terminal of the third NAND gate, and the second input terminal of the fourth NAND gate serves as a reset terminal of the second RS flip-flop.

7. The level conversion circuit according to claim 1 or 2, characterized in that: The high level end of the first RS trigger and the high level end of the second RS trigger are connected to the bootstrap voltage, and the low level end of the first RS trigger and the low level end of the second RS trigger are connected to the output switch signal voltage, and the bootstrap voltage = the output switch signal voltage + the preset voltage.

8. The level conversion circuit according to claim 1 or 2, characterized in that: The level conversion circuit also includes a first diode and a second diode; The anode of the first diode and the anode of the second diode are used to access the output switch signal voltage; The cathode of the first diode is connected between the forward output terminal of the first RS flip-flop and the set terminal of the second RS flip-flop; A cathode of the second diode is connected between an inverting output terminal of the first RS flip-flop and a reset terminal of the second RS flip-flop.

9. A power chip, characterized in that: The power chip comprises a third switch tube, a third drive circuit, a first capacitor and a level conversion circuit as described in any one of claims 1 to 8; The output end of the level conversion circuit is connected to the input end of the third driving circuit, the output end of the third driving circuit is connected to the first end of the third switch tube, the second end of the third switch tube is used to access the high-voltage domain electrical signal, and the third end of the third switch tube is used to connect to the subsequent circuit; The low level end of the third driving circuit and one end of the first capacitor are connected to the third end of the third switch tube, and the other end of the first capacitor is connected to the high level end of the third driving circuit; The signal connected to the low level end of the third driving circuit is the output switch signal voltage, and the signal connected to the high level end of the third driving circuit is the bootstrap voltage, wherein the bootstrap voltage=the output switch signal voltage+the preset voltage; The high level end of the first RS trigger and the high level end of the second RS trigger are connected to the bootstrap voltage, and the low level end of the first RS trigger and the low level end of the second RS trigger are connected to the output switch signal voltage.

10. An electronic device, characterized in that: include: The power chip as claimed in claim 9.

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