All-digital phase discrimination method, phase discriminator and decimal all-digital phase-locked loop circuit

Abstract

The invention discloses an all-digital phase discriminating method, a phase discriminator and a decimal all-digital phase-locked loop circuit, and in the all-digital phase discriminating method and the phase discriminator, a coarse and fine combined measurement mode is adopted, so that the requirement on the measuring range of a time measurement circuit is effectively reduced; moreover, the first count value part is counted by using the oscillation period of the ring oscillator and the period stability, so that the large dynamic range and linearity of phase measurement are ensured; the second count value part is used for measuring and averaging a plurality of edges of an oscillation signal by utilizing irrelevance between an oscillation signal period and a reference clock period, so that a dead zone in time measurement is avoided, interpolation of a delay chain is realized, unit delay limitation is broken through, and the measurement precision is effectively improved; besides, the decimal type all-digital phase-locked loop circuit provided with the phase discriminator can realize large-dynamic-range phase discrimination without a traditional digital time converter, the nonlinearity of phase measurement is reduced, the overall architecture is more concise, all-digital integration is easy, and the performance is effectively improved.

Description

Technical Field

[0001] The invention relates to the technical field of phase-locked loops, and in particular to a full-digital phase identification method, a phase detector and a fractional full-digital phase-locked loop circuit. Background Art

[0002] A phase-locked loop (PLL) is a circuit used to generate a stable and accurate clock signal and maintain phase synchronization. It is widely used in wireless communications, clock synthesis, data recovery and other fields.

[0003] Traditional PLLs are mainly composed of a phase detector (PD), a charge pump (CP), a loop filter (LF), and a voltage-controlled oscillator (VCO). Although analog PLLs have lower phase noise, they are sensitive to process deviations and temperature changes, are complex to design, and are difficult to achieve high integration in modern complementary metal oxide semiconductor (CMOS) processes. In addition, analog PLLs have limitations in programmability and are difficult to adapt to the needs of modern digital systems for flexible frequency adjustment.

[0004] To overcome the limitations of analog PLL, digital PLL (DPLL) has gradually developed. DPLL uses digital circuits to replace traditional analog filters and charge pumps, enhancing programmability, improving process compatibility, and reducing sensitivity to environmental factors. However, DPLL still relies on analog VCO and fails to achieve full digitalization.

[0005] The all-digital phase-locked loop (ADPLL) is a further development of the DPLL. All analog modules in the PLL structure, including the VCO and phase detector, are replaced with digital circuits to achieve higher programmability, lower power consumption and higher process migration capabilities. The ADPLL is mainly composed of a divider, a digital phase detector (DPD), a digital loop filter (DLF) and a digitally controlled oscillator (DCO). Among them, the DCO is directly controlled by a digital signal, replacing the analog VCO, making the ADPLL easier to integrate into modern digital systems.

[0006] The fractional all-digital phase-locked loop (Fractional-N ADPLL) is an important branch of ADPLL. Fractional-N ADPLL realizes fractional frequency division through digital control, which improves the flexibility of frequency adjustment and makes it widely used in 5G communication (fifth-generation mobile communication technology), high-precision clock generation and other fields. Traditionally, Fractional-NADPLL uses a multi-mode divider (MMDIV) and a time-to-digital converter (TDC) to achieve fractional frequency division. Among them, MMDIV periodically switches the integer division coefficient to make the average frequency of the feedback signal reach the required fractional multiple, while TDC is responsible for measuring the phase error and providing feedback adjustment. However, this solution has the following problems: (1) TDC needs to have a large dynamic range: Since the periodic phase error generated by MMDIV is large, TDC must be able to measure a wider range of phase deviations, which increases power consumption and places higher requirements on linearity.

[0007] (2) TDC quantization noise affects system performance: TDC resolution is limited, and quantization error will cause the overall phase noise of the phase-locked loop to deteriorate and increase the output clock jitter.

[0008] In order to reduce the dynamic range requirement of TDC and improve system performance, the mainstream design in recent years has adopted the solution of MMDIV, digital time converter (DTC) and TDC. As a programmable delay unit, DTC makes fine phase adjustments to the feedback signal, thereby reducing the phase error range that TDC needs to measure. However, although the MMDIV, DTC and TDC solutions effectively reduce the dynamic range requirement of TDC, the nonlinearity of DTC and the dead zone problem of TDC still restrict the performance of Fractional-NADPLL. The key technical challenges it faces are mainly reflected in the following two aspects: (1) DTC linearity problem: DTC is composed of a cascade of delay units. Its delay accuracy is affected by process deviation, temperature drift and power supply fluctuation, resulting in the accumulation of nonlinear errors. The traditional all-digital delay chain architecture is difficult to maintain high-precision time control, and nonlinear errors are difficult to optimize. Therefore, mainstream DTC designs usually use analog circuits to improve linearity, but this increases design complexity and power consumption.

[0009] (2) TDC dead zone problem: TDC is limited by its limited time resolution. When the phase error is less than the minimum resolution of TDC, the TDC output remains unchanged, causing the PLL to be unable to adjust the phase correctly, affecting the phase locking effect. This dead zone problem directly affects the phase noise performance of the Fractional-N ADPLL, which is particularly prominent in high-precision clock synthesis applications. It is necessary to further optimize the TDC design to improve measurement accuracy.

[0010] In view of this, the present invention is proposed. Summary of the invention

[0011] The purpose of the present invention is to provide a fully digital phase identification method, a phase detector and a fractional fully digital phase-locked loop circuit, which can ensure a large dynamic range and linearity of phase measurement, avoid the dead zone problem in time measurement, realize the interpolation of the delay chain, break through the unit delay limitation, and effectively improve the measurement accuracy. In addition, the fractional fully digital phase-locked loop circuit does not require a traditional digital time converter, can achieve phase identification with a large dynamic range, reduces the nonlinearity of phase measurement, and has a simpler overall architecture, which is easy to fully digitally integrate and effectively improves performance.

[0012] The objective of the present invention is achieved through the following technical solutions: A fully digital phase identification method, comprising: When the edge of the input fractional frequency division signal is detected, the oscillation starts to generate an oscillation signal, and stops when the edge of the reference clock signal is detected, and the edges of the oscillation ring signal are counted to obtain a first count value of the phase measurement; The oscillation signal is delayed by a delay chain, and when the edge of the reference clock signal is detected, the state code value on the delay chain is recorded, and after encoding and nonlinear correction of the state code value, a second count value of the phase measurement is obtained; The first count value and the second count value of the phase measurement are combined with the input frequency divider quantization compensation signal to generate a phase error amount.

[0013] A phase detector, used to implement the above-mentioned all-digital phase identification method, comprising: a ring oscillator, a time measurement circuit based on a delay chain, and an output encoder; the ring oscillator is connected to the time measurement circuit based on the delay chain, and the ring oscillator and the time measurement circuit based on the delay chain are both connected to the output encoder; wherein: The ring oscillator is used to start oscillating to generate an oscillation signal when an edge of an input fractional frequency division signal is detected, and stop when an edge of a reference clock signal is detected, and count the edges of the oscillation ring signal to obtain a first count value for phase measurement; The time measurement circuit based on the delay chain is used to delay the oscillation signal through the delay chain, record the state code value on the delay chain when the edge of the reference clock signal is detected, and obtain the second count value of the phase measurement after encoding and nonlinear correction of the state code value; The output encoder is used to combine the first count value and the second count value of the phase measurement with the input frequency divider quantization compensation signal to generate a phase error amount.

[0014] A fractional all-digital phase-locked loop circuit comprises: a digitally controlled oscillator, a multi-mode frequency divider, the aforementioned phase detector, and a digital loop filter, which are sequentially connected to form a loop; wherein: The digitally controlled oscillator is used to generate a clock frequency signal according to an input digital control signal; The frequency divider is used to perform fractional frequency division on the clock frequency signal generated by the digitally controlled oscillator, and output the fractional frequency division signal and the corresponding frequency divider quantization compensation signal to the phase detector; The phase detector is used to output a phase error amount according to an input fractional frequency division signal and a frequency divider quantization compensation signal; The digital loop filter is used to perform digital filtering on the phase error signal to generate a digital control signal output to the digital control oscillator.

[0015] It can be seen from the technical solution provided by the present invention that in the process of all-digital phase identification, the method of obtaining the first count value of phase measurement is a coarse measurement method, and the method of obtaining the second count value is a fine measurement method. The combination of the two can effectively reduce the requirements for the range of the time measurement circuit; and the first count value part uses the oscillation cycle counting and cycle stability to ensure the large dynamic range and linearity of the phase measurement; the second count value part uses the irrelevance of the oscillation signal period and the reference clock period, and measures and averages multiple edges of the oscillation signal to avoid the dead zone problem in time measurement, realize the interpolation of the delay chain, break through the unit delay limit, and effectively improve the measurement accuracy; in addition, the corresponding fractional all-digital phase-locked loop circuit does not require a traditional digital time conversion unit and is suitable for full digital implementation. Compared with the traditional solution based on time-to-digital converter, the present invention uses the oscillation period to improve linearity while ensuring large dynamic range phase identification. Overall, the present invention adopts a simpler digital structure to improve the accuracy of the phase detector while optimizing the overall performance of the phase-locked loop. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0017] Figure 1 A flow chart of a fully digital phase identification method provided by an embodiment of the present invention; Figure 2 A schematic diagram of a phase detector provided by an embodiment of the present invention; Figure 3A schematic diagram of a fractional all-digital phase-locked loop circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0018] The following is a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the protection scope of the present invention.

[0019] First, the terms that may be used in this article are explained as follows: The terms "include", "comprises", "contains", "has" or other descriptions with similar semantics should be interpreted as non-exclusive inclusion. For example, including certain technical feature elements (such as raw materials, components, ingredients, carriers, dosage forms, materials, dimensions, parts, components, mechanisms, devices, steps, procedures, methods, reaction conditions, processing conditions, parameters, algorithms, signals, data, products or products, etc.) should be interpreted as including not only certain technical feature elements explicitly listed, but also other technical feature elements known in the art that are not explicitly listed.

[0020] The term "consisting of..." means excluding any technical feature elements not explicitly listed. If this term is used in a claim, it will make the claim closed, so that it does not contain technical feature elements other than the technical feature elements explicitly listed, except for the conventional impurities related to them. If this term only appears in a clause of a claim, it only limits the elements explicitly listed in the clause, and the elements recorded in other clauses are not excluded from the overall claim.

[0021] Unless otherwise specified or limited, the terms "connected" and "connection" should be understood in a broad sense, for example: it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this article can be understood according to specific circumstances.

[0022] The following is a detailed description of a fully digital phase identification method, phase detector and fractional fully digital phase-locked loop circuit provided by the present invention. The contents not described in detail in the embodiments of the present invention belong to the prior art known to professionals in the field. If no specific conditions are specified in the embodiments of the present invention, the conventional conditions in the field or the conditions recommended by the manufacturer are followed. If the manufacturer of the reagents or instruments used in the embodiments of the present invention is not specified, they are all conventional products that can be purchased commercially.

[0023] Embodiment 1 The embodiment of the present invention provides a fully digital phase identification method, which converts the phase difference measurement into the measurement of the state of the ring oscillation circuit, such as Figure 1 As shown, it mainly includes the following steps: Step 1: When an edge of the input fractional frequency division signal is detected, oscillation starts to generate an oscillation signal, and stops when an edge of the reference clock signal is detected. The edges of the oscillation ring signal are counted to obtain a first count value of phase measurement.

[0024] In the embodiment of the present invention, the oscillation period of a ring oscillator (RO) is used as a unit to quantize the phase error and implement coarse measurement. The first count value may also be referred to as a coarse count. The stability of the oscillation period of the ring oscillator ensures the linearity and stability of phase quantization over a large dynamic range.

[0025] Exemplarily, when a rising edge of the fractional frequency division signal is detected, oscillation starts from phase 0 and stops when a rising edge of the reference clock signal is detected.

[0026] Exemplarily, counting the edges of the oscillation ring signal includes: counting the rising edge and the falling edge of the oscillation signal respectively to avoid metastable state. Of course, in practical applications, other counting methods can also be used, which will not be described in detail in the present invention.

[0027] Step 2: Delay the oscillation signal through a delay chain. When the reference clock signal edge is detected, record the state code value on the delay chain. After encoding and nonlinear correction of the state code value, obtain the second count value of the phase measurement.

[0028] Preferably, the encoding and non-linear correction of the state code value includes: first pre-processing the state code value (for example, bubble elimination); then, performing multiple edge position detections, including 1 / 0 or 0 / 1 state jumps, and encoding the state code value of the detected edge position to obtain the encoded edge code value; and then performing non-linear correction on the encoded edge code value.

[0029] In the embodiment of the present invention, the average value of each edge code value after nonlinear correction may be used as the second count value of phase measurement.

[0030] In the embodiment of the present invention, after the rough counting measurement of this part of the measurement, the remaining phase amount of less than one oscillation signal period can be called fine measurement, and the phase quantization accuracy can be improved by the high-precision delay unit in the delay chain. In addition, by utilizing the irrelevance between the oscillation period of the ring oscillator and the TDC reference clock period, combining multiple oscillation signal edges (such as measuring the rising and falling edges at the same time) for time measurement and averaging, the dead zone problem in time measurement is effectively avoided, the interpolation of the delay chain is realized, the unit delay limitation is broken, and the measurement accuracy is effectively improved.

[0031] Step 3: Combine the first count value and the second count value of the phase measurement with the input frequency divider quantization compensation signal to generate a phase error amount.

[0032] Preferably, the calculation process here is: perform phase normalization operations on the first count value and the second count value respectively, and then sum them with the input divider quantization compensation signal to generate a phase error amount.

[0033] Exemplarily, a suitable first count value (a rising edge or falling edge count value of an oscillation pulse) may be selected according to a specific range of the second count value to effectively avoid the influence of a metastable state.

[0034] In the embodiment of the present invention, the combination of fine measurement and the aforementioned coarse measurement reduces the requirement on the range of the time measurement circuit (only one oscillation period of the ring oscillator needs to be covered).

[0035] Embodiment 2 The embodiment of the present invention further provides a phase detector, which is mainly used to implement the all-digital phase identification method provided in the above embodiment, such as Figure 2 As shown, it mainly includes: a ring oscillator (Ring Oscillator, RO), a time measurement circuit based on delay chains (Tapped-Delay Lines, TDL) and an output encoder; the ring oscillator is connected to the time measurement circuit based on the delay chain, and the ring oscillator and the time measurement circuit based on the delay chain are both connected to the output encoder, and the phase detector is called RO-TDL-DPD.

[0036] The ring oscillator is used to start oscillating to generate an oscillation signal when an edge of an input fractional frequency division signal is detected, and stop when an edge of a reference clock signal is detected, and count the edges of the oscillation ring signal to obtain a first count value (which can be called a coarse count) for phase measurement.

[0037] The time measurement circuit based on the delay chain is used to delay the oscillation signal through the delay chain, and when the edge of the reference clock signal is detected, the state code value on the delay chain is recorded, and after encoding and nonlinear correction of the state code value, a second count value (which can be called a fine count) of the phase measurement is obtained.

[0038] The output encoder is used to combine the first count value and the second count value of the phase measurement with the input frequency divider quantization compensation signal to generate a phase error amount.

[0039] like Figure 2 As shown, the ring oscillator includes: an oscillation ring and an oscillation ring edge counter connected in sequence; wherein: the oscillation ring is used to start oscillating to generate an oscillation signal when an edge of an input fractional frequency division signal is detected, and stop when an edge of a reference clock signal is detected; the oscillation ring edge counter is used to count the edges of the oscillation ring signal to obtain a first count value for phase measurement.

[0040] The ring oscillator in this part is mainly used to implement step 1 in the aforementioned embodiment. Considering that the aforementioned embodiment has already introduced the relevant measurement process, it will not be repeated here.

[0041] like Figure 2 As shown, the time measurement circuit based on the delay chain includes: a delay chain, a delay chain sampling module and a data processing module connected in sequence; wherein: the delay chain is used to delay the oscillation signal; the delay chain sampling module is used to record the state code value on the delay chain when the edge of the reference clock signal is detected; the data processing module is used to encode and nonlinearly correct the state code value to obtain a second count value of the phase measurement.

[0042] The delay chain-based time measurement circuit in this part is mainly used to implement step 2 in the aforementioned embodiment. The residual phase error that is less than one ring oscillator oscillation period is measured by the delay chain-based time measurement circuit. Considering that the aforementioned embodiment has already introduced the relevant measurement process, it will not be repeated here.

[0043] Similarly, the specific calculation process involved in the output encoder can be found in the introduction of the aforementioned embodiment, which will not be described in detail here.

[0044] Embodiment 3 The embodiment of the present invention provides a fractional-type all-digital phase-locked loop (Fractional-N ADPLL) circuit, such as Figure 3 As shown, it mainly includes: a digitally controlled oscillator (DCO), a multi-mode frequency divider (MMDIV), a phase detector, and a digital loop filter, which are connected in sequence to form a loop.

[0045] The digital controlled oscillator is used to generate a clock frequency signal according to an input digital control signal.

[0046] The frequency divider is used to perform fractional frequency division on the clock frequency signal generated by the digitally controlled oscillator, and output the fractional frequency division signal and the corresponding frequency divider quantization compensation signal to the phase detector.

[0047] The phase detector is used to output a phase error according to the input fractional frequency division signal and the frequency divider quantization compensation signal. The phase detector here is the phase detector provided by the above embodiment, and the phase error is generated by the method provided by the above embodiment and output to the digital loop filter.

[0048] The digital loop filter is used to digitally filter the phase error signal, and generate a digital control signal output to the digital control oscillator in combination with a control algorithm (eg, a proportional-integral-differential control algorithm), thereby ultimately achieving frequency locking.

[0049] The above-mentioned fractional all-digital phase-locked loop circuit provided by the embodiment of the present invention is provided with a phase detector for realizing all-digital phase identification, and the phase error is quantified by counting the period of the ring oscillator to realize high dynamic range phase identification. At the same time, based on the high-precision time measurement of the delay chain, combined with multi-edge measurement averaging and nonlinear correction, the resolution limitation of the delay unit of the delay chain is broken through. In addition, the irrelevance of the oscillation period of the ring oscillator and the reference clock signal can effectively reduce the influence of the dead zone effect in time measurement.

[0050] The above-mentioned fractional all-digital phase-locked loop circuit provided by the present invention does not require a digital time converter and is suitable for full digital implementation. In comparison, the present invention uses the oscillation period of the ring oscillator to improve linearity while ensuring a large dynamic range of phase discrimination. Overall, the present invention adopts a simpler digital structure, while improving the accuracy of the phase detector, optimizing the overall performance of the phase-locked loop.

[0051] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with the technical field within the technical scope disclosed in the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims. The information disclosed in the background technology section of this article is only intended to deepen the understanding of the overall background technology of the present invention, and should not be regarded as an admission or in any form that the information constitutes prior art known to those skilled in the art.

Claims

1. A fully digital phase identification method, characterized in that: include: When the edge of the input fractional frequency division signal is detected, the oscillation starts to generate an oscillation signal, and stops when the edge of the reference clock signal is detected, and the edges of the oscillation ring signal are counted to obtain a first count value of the phase measurement; The oscillation signal is delayed by a delay chain, and when the edge of the reference clock signal is detected, the state code value on the delay chain is recorded, and after encoding and nonlinear correction of the state code value, a second count value of the phase measurement is obtained; The first count value and the second count value of the phase measurement are combined with the input frequency divider quantization compensation signal to generate a phase error amount.

2. A fully digital phase identification method according to claim 1, characterized in that: The counting of the edges of the oscillation ring signal includes: counting the rising edge and the falling edge of the oscillation signal respectively.

3. The all-digital phase identification method according to claim 1, characterized in that: The encoding and non-linear correction of the state code value includes: First, the state code value is preprocessed; then, multiple edge position detections are performed, and the state code values ​​of the detected edge positions are encoded to obtain the encoded edge code values; and then the encoded edge code values ​​are nonlinearly corrected.

4. The all-digital phase identification method according to claim 1, characterized in that: The step of combining the first count value and the second count value of the phase measurement with the input frequency divider quantization compensation signal to generate the phase error comprises: Phase normalization operations are performed on the first count value and the second count value respectively, and then summed with the input frequency divider quantization compensation signal to generate a phase error amount.

5. A phase detector, characterized in that: The method for realizing the all-digital phase discrimination method according to any one of claims 1 to 4 comprises: a ring oscillator, a time measurement circuit based on a delay chain, and an output encoder; the ring oscillator is connected to the time measurement circuit based on the delay chain, and the ring oscillator and the time measurement circuit based on the delay chain are both connected to the output encoder; wherein: The ring oscillator is used to start oscillating to generate an oscillation signal when an edge of an input fractional frequency division signal is detected, and stop when an edge of a reference clock signal is detected, and count the edges of the oscillation ring signal to obtain a first count value for phase measurement; The time measurement circuit based on the delay chain is used to delay the oscillation signal through the delay chain, record the state code value on the delay chain when the edge of the reference clock signal is detected, and obtain the second count value of the phase measurement after encoding and nonlinear correction of the state code value; The output encoder is used to combine the first count value and the second count value of the phase measurement with the input frequency divider quantization compensation signal to generate a phase error amount.

6. A phase detector according to claim 5, characterized in that: The ring oscillator comprises: an oscillation ring and an oscillation ring edge counter connected in sequence; wherein: The oscillation ring is used to start oscillating to generate an oscillation signal when an edge of an input fractional frequency division signal is detected, and stop when an edge of a reference clock signal is detected; The oscillation ring edge counter is used to count the edges of the oscillation ring signal to obtain a first count value for phase measurement.

7. A phase detector according to claim 5, characterized in that: The time measurement circuit based on the delay chain comprises: a delay chain, a delay chain sampling module and a data processing module connected in sequence; wherein: The delay chain is used to delay the oscillation signal; The delay chain sampling module is used to record the state code value on the delay chain when the reference clock signal edge is detected; The data processing module is used to obtain a second count value of phase measurement after encoding and nonlinearly correcting the state code value.

8. A fractional all-digital phase-locked loop circuit, characterized in that: include: A digital controlled oscillator, a multi-mode frequency divider, a phase detector as claimed in any one of claims 5 to 7, and a digital loop filter, which are connected in sequence to form a loop; wherein: The digitally controlled oscillator is used to generate a clock frequency signal according to an input digital control signal; The frequency divider is used to perform fractional frequency division on the clock frequency signal generated by the digitally controlled oscillator, and output the fractional frequency division signal and the corresponding frequency divider quantization compensation signal to the phase detector; The phase detector is used to output a phase error amount according to an input fractional frequency division signal and a frequency divider quantization compensation signal; The digital loop filter is used to perform digital filtering on the phase error signal to generate a digital control signal output to the digital control oscillator.

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