Phase-locked loop (PLL) with direct feed-forward circuit

Abstract

The invention relates to a phase-locked loop (PLL) with a direct feed-forward circuit. A phase locked loop (PLL) apparatus (102A) includes: 1) a detector (104A) configured to output an error signal indicative of a phase offset between a feedback clock signal and a reference clock signal; 2) a charge pump (106A) coupled to the detector (104A) and configured to output a charge pump signal based on the error signal; 3) an integrator (108A) having a feedback path (202), an input node (109A), a reference node (111A), and an output node, where the input node (109A) is coupled to the charge pump (106A) and receives the charge pump signal; 4) a voltage controlled oscillator (112A) coupled to the output node of the integrator (108A) via a resistor; and 5) a feed-forward circuit (110A) directly coupled to the detector (104) A and configured to apply an average version of the error signal to correct a voltage level received by the VCO (112A).

Description

[0001] Information about divisional applications

[0002] This application is a divisional application of an invention patent application with an application date of December 11, 2019, application number 201980067472.X, and invention name “Phase-locked loop (PLL) with direct feedforward circuit”. Technical Field

[0003] The present application relates generally to a phase locked loop (PLL), and more particularly to a PLL with a direct feed forward circuit. Background Art

[0004] A phase-locked loop (PLL) is a control circuit for providing an output signal based on the phase difference between two input signals. Example PLL topologies include a phase detector, a charge pump, a loop filter, and a voltage-controlled oscillator (VCO). Example uses of PLLs include signal demodulation, signal recovery from noisy communication channels, frequency synthesis based on an input frequency, and distribution of precisely timed clock pulses. Example systems using PLLs include radio systems, telecommunication systems, and / or computer systems.

[0005] PLLs are imperfect control circuits where inaccuracies in the form of phase noise are a persistent problem. Phase noise occurs due to imperfections in PLL components such as the voltage controlled oscillator, charge pump, and / or loop filter. The push for PLL miniaturization has been found to increase phase noise. Work is ongoing to improve PLL design and performance. Summary of the invention

[0006] According to at least one example of the present invention, a phase-locked loop (PLL) device includes a detector configured to output an error signal indicating a phase offset between a feedback clock signal and a reference clock signal. The PLL device also includes a charge pump coupled to the detector and configured to output a charge pump signal based on the error signal. The PLL device also includes an integrator having a feedback path, an input node, a reference node, and an output node, wherein the input node is coupled to the charge pump and receives the charge pump signal. The PLL device also includes a voltage-controlled oscillator (VCO) coupled to the output node of the integrator via a resistor. The PLL device also includes a feed-forward circuit directly coupled to the detector and configured to apply an average version of the error signal to correct a voltage level received by the VCO.

[0007] According to at least one example of the present invention, a device includes a circuit system configured to operate based on a clock signal. The device also includes a PLL configured to adjust the clock signal based on a reference clock signal. The PLL includes a detector configured to output an error signal indicating a phase offset between a feedback clock signal and a reference clock signal. The PLL also includes a charge pump coupled to the detector and configured to output a charge pump signal based on the error signal. The PLL also includes an integrator having a feedback path, an input node, a reference node, and an output node, wherein the input node is coupled to the charge pump and receives the charge pump signal. The PLL also includes a VCO coupled to the output node of the integrator via a resistor, wherein the VCO is configured to adjust the phase of the clock signal based on the output of the integrator. The PLL also includes a feedforward circuit directly coupled to the detector and configured to apply an average version of the error signal to correct a voltage level received by the VCO.

[0008] According to at least one example of the present invention, a PLL method includes detecting, by a detector, an error signal indicating a phase offset between a feedback clock signal and a reference clock signal. The method also includes adjusting a charge pump output based on the error signal. The method also includes integrating, by an integrator, the charge pump output over time. The method also includes converting the integrated charge pump output into a voltage signal. The method also includes applying a correction to the voltage signal using a feedforward circuit directly coupled to the detector. The method also includes using, by a voltage controlled oscillator, the corrected voltage signal to provide an output signal having a phase based on the corrected voltage signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] To describe various examples in detail, reference will now be made to the accompanying drawings, in which:

[0010] Figure 1 is a block diagram illustrating an electronic device according to various examples;

[0011] Figure 2 is a schematic diagram illustrating a phase locked loop (PLL) circuit according to various examples;

[0012] Figure 3 is a schematic diagram illustrating another PLL circuit according to various examples;

[0013] Figure 4 is a block diagram illustrating a PLL circuit with modeled components according to various examples;

[0014] Figure 5 is a graph illustrating phase noise as a function of frequency for various PLL circuits according to various examples; and

[0015] Figure 6 is a flow chart illustrating a PLL method according to various examples. DETAILED DESCRIPTION

[0016] Disclosed herein are phase-locked loop (PLL) circuits, devices, and methods for direct feedforward circuits that reduce phase noise. As used herein, a "direct feedforward circuit" refers to a feedforward circuit connected to a phase detector of a PLL circuit. In an example PLL circuit, a phase detector compares an input signal phase with a reference signal phase and provides an error signal (e.g., an up or down signal). An example up signal indicates that the input signal phase needs to increase toward the reference signal phase. An example down signal indicates that the input signal phase needs to decrease toward the reference signal phase. The feedforward circuit receives the error signal from the phase detector and adjusts the voltage fed into a voltage-controlled oscillator (VCO) that provides an output signal of the PLL circuit. In some examples, the feedforward circuit provides the feedforward signal to a loop filter of the PLL circuit. More specifically, the feedforward signal is used to adjust the reference signal of the loop filter so that the output of the loop filter is adjusted, resulting in a voltage adjustment fed into the VCO. In other examples, the feedforward circuit provides the feedforward signal to an input node of the VCO to adjust the voltage fed into the VCO. In either case, the feedforward signal provides correction to the PLL circuit output to reduce phase noise.

[0017] In some examples, the feed-forward circuit includes two branches, including a first and a second branch. The first branch is coupled to a first output node (e.g., an up signal node) of a phase detector, and the second branch is coupled to a second output node (e.g., a down signal node). As an example, the first branch includes an inverter and a first resistor, and the second branch includes a buffer and a second resistor. The first and second branches are joined at the output node of the feed-forward circuit, resulting in the feed-forward circuit providing an average value of the input at its output node.

[0018] With correction provided by the feedforward circuit, the phase error at the output of the PLL circuit is reduced compared to other PLL circuit topologies. In addition, the disclosed PLL circuit topology supports miniaturization because at least some components are relatively smaller than other PLL circuit topologies. In some instances, the disclosed PLL circuit topology is used with WiFi radios and / or other cases where low noise performance of the PLL is required. To provide a better understanding, various PLL circuit options, feedforward circuit options, and related PLL method options are described using the following figure.

[0019] Figure 1 is a block diagram illustrating an electronic device 100 according to various examples. Figure 1In the embodiment, the electronic device 100 represents an integrated circuit (IC), a multi-die module, a printed circuit board (PCB), a consumer product (such as a radio device, a telecommunication device, or a computer device), and / or other devices. As shown, the electronic device 100 includes a PLL circuit 102 coupled to other components 116. In different examples, the other components 116 are different. In one example, the other components 116 include a signal demodulation component. In another example, the other components 116 include a signal recovery component. In another example, the other components 116 include a frequency synthesis component. In another example, the other components 116 include a clock distribution component. In different examples, the electronic device 100 is sold as a unit for use in a radio system, a telecommunication system, and / or a computer system.

[0020] like Figure 1 , the PLL circuit 102 includes a phase or frequency detector (PFD) 104 that receives a feedback signal (CLK) from other components 116. The PFD 104 also receives a reference clock signal (REF_CLK). The output of the PFD 104 is an error signal between the phase of the CLK signal and the phase of the REF_CLK signal. As previously discussed, an example output from the PFD 104 includes an up or down signal indicating how the CLK signal should be adjusted to align with the CLK_REF signal (up means increasing the phase of the CLK signal, and down means decreasing the phase of the CLK signal). The output from the PFD 104 is provided to a charge pump 106 and a feed-forward circuit 110. The output of the charge pump 106 is provided to a first input node 109 of the loop filter 108.

[0021] In one example (labeled as Option 1), the feedforward circuit 110 provides a feedforward signal to a second input node 111 of the loop filter 108. Under Option 1, the feedforward signal is combined with a reference signal (V_REF*) at a feedforward node 115, where V_REF* is obtained by applying the reference signal (V_REF) to a resistor (R_O1). More specifically, the output of the loop filter 108 is a function of the combination of the V_REF* signal and the feedforward signal applied to the second input node 111, where the output of the loop filter 108 is used to provide a voltage to an input node 114 of the VCO 112. The output of the VCO 112 is a signal having a phase based on the voltage at the input node 114 of the VCO 112.

[0022] In another example (labeled as Option 2), the feedforward circuit 110 provides a feedforward signal to a feedforward node 117 coupled to an input node 114 of the VCO 112. Under Option 2, the output of the loop filter 108 is combined with the feedforward signal at the feedforward node 117, and the combined signal is provided to the input node 114 of the VCO 112, causing the voltage at the input node 114 to be adjusted based on the feedforward signal from the feedforward circuit 110. Under either of Options 1 and 2, the feedforward circuit 110 is directly coupled to the PFD 104, and the feedforward signal is used to adjust the voltage provided to the VCO 112 such that the phase error of the output signal 118 of the PLL circuit 102 is reduced.

[0023] In operation, the PFD 104 of the PLL circuit 102 is a detector configured to output an error signal indicating a phase offset between the CLK signal and the REF_CLK signal. The charge pump 106 is coupled to the PFD 104 and is configured to output a charge pump signal based on the error signal. In some examples, the loop filter 108 includes an integrator having a feedback path, an input node (e.g., a first input node 109), a reference node (e.g., a second input node 111), and an output node, wherein the input node is coupled to the charge pump 106 and receives the charge pump signal. In some examples, the VCO 112 is coupled to the output node of the integrator via a resistor. At the same time, the feed-forward circuit 110 is directly coupled to the PFD 104 and is configured to apply an average version of the error signal to correct the voltage level received by the VCO 112.

[0024] In some examples (like option 1), the feedforward circuit 110 is coupled to a reference node of the integrator (e.g., the feedforward node 115 is connected to the second input node 111) and applies an average version of the error signal to the reference node to correct the voltage level received by the VCO 112. In such examples, a reference signal resistor (e.g., R_O1) is between the reference signal node (e.g., the second input node 111) and the feedforward node 115, where the feedforward circuit 110 applies the feedforward signal to the reference node of the integrator.

[0025] In other examples (like Option 2), the feed-forward circuit 110 is coupled to a resistor at the output of the loop filter 108 (see, e.g. Figure 2 and 3 ) and a feed-forward node 117 between the VCO 112 and the loop filter 108, wherein the feed-forward circuit 110 applies an averaged version of the error signal to the feed-forward node 117 to correct the voltage level received by the VCO 112. For either of options 1 and 2, in some examples, the feedback path of the integrator of the loop filter 108 includes only a capacitor. In other examples, the feedback path of the integrator of the loop filter 108 includes a capacitor and a feedback resistor.

[0026] In some examples, PFD 104 includes a first output node and a second output node (see, e.g., Figures 2 to 4 ). In such examples, the feedforward circuit 110 includes a first path coupled to the first output node and a second path coupled to the second output node. The first and second paths operate to average pulses (corresponding to the error signal) output from the first and second output nodes of the PFD 104. In one example, the first output node of the PFD 104 is configured to output an up signal to the first path, and the second output node of the detector is configured to output a down signal to the second path. In some examples, the first path of the feedforward circuit 110 includes an inverter and a first resistor, and the second path of the feedforward circuit 110 includes a buffer and a second resistor. Also, in some examples, the feedforward circuit 110 has a gain of Vdd / (2*π), where Vdd is a power supply voltage provided to the integrator.

[0027] Figure 2 1 is a schematic diagram illustrating a PLL circuit 102A according to various examples. Figure 2 In the example of Figure 1 More specifically, the PLL circuit 102A includes a PFD 104A coupled to a charge pump 106A, wherein Figure 2 The PFD 104A and charge pump 106A are Figure 1 104A receives a reference clock signal (REF_CLK) and a feedback signal (CLK) as inputs. In some examples, when the phase of the CLK signal needs to be increased to align with the phase of the REF_CLK signal, the output of the PFD 104A is an up signal. On the other hand, in some examples, when the phase of the CLK signal needs to be decreased to align with the phase of the REF_CLK signal, the output of the PFD 104A is a down signal.

[0028] exist Figure 2 In the example of , charge pump 106A receives the up and down signals from PFD 104A and adjusts the charge pump signal to loop filter 108A accordingly. More specifically, the output of charge pump 106A is input to negative input node 109A ( Figure 1 109 in the example of the first input node 109). Figure 2 In FIG. 1 , the loop filter 108A corresponds to an integrator formed by using the operational amplifier 201 and the capacitor 204 in the feedback loop 202. Meanwhile, the feedforward circuit 110A ( Figure 1 ) the feedforward signal ( Figure 2) is provided to the positive input node 111A ( Figure 1 111 in the example of the second input node 111). Figure 2 , the feedforward signal is combined with V_REF* as an input to the positive input of loop filter 108A, where the V_REF* signal is a function of the V_REF signal and R_O1 (the V_REF* signal is a version of the V_REF signal derived due to R_O1).

[0029] The output of loop filter 108A is a function of the difference between the signals at negative input node 109A and positive input node 111A. Figure 2 In the example of , the output of loop filter 108A is provided to an RC circuit having a resistor (R_OUT) and a capacitor (C_OUT). Between R_OUT and C_OUT is a node 208 coupled to an input node 114A of VCO 112A. Thus, for PLL circuit 102A, the voltage at input node 114A of VCO 112A is a function of the operation of PFD 104A, charge pump 106A, feed-forward circuit 110A (which applies a feed-forward signal to input node 111A of loop filter 108A), loop filter 108A, and the RC circuit, wherein the use of feed-forward circuit 110A reduces the phase noise of the output signal of PLL circuit 102A.

[0030] Figure 3 1 is a schematic diagram illustrating another PLL circuit 102B according to various examples. Figure 3 In the example of Figure 1 More specifically, the PLL circuit 102B includes a PFD 104B coupled to a charge pump 106B, wherein Figure 3 The PFD 104B and charge pump 106B are Figure 1 104B receives a reference clock signal (REF_CLK) and a feedback signal (CLK) as inputs. In some examples, when the phase of the CLK signal needs to be increased to align with the phase of the REF_CLK signal, the output of the PFD 104B is an up signal. On the other hand, in some examples, when the phase of the CLK signal needs to be decreased to align with the phase of the REF_CLK signal, the output of the PFD 104B is a down signal.

[0031] exist Figure 3In the example of , charge pump 106B receives the up and down signals from PFD 104B and adjusts the current to loop filter 108B up or down. More specifically, the output of charge pump 106B is input to negative input node 109B ( Figure 1 At the same time, the reference voltage is input to the positive input node 111B of the loop filter 108B ( Figure 1 ) in an instance of the second input node 111 in Figure 3 In FIG. 1 , the loop filter 108B corresponds to an integrator formed using the operational amplifier 301 and the capacitor 304 in the feedback loop 302 .

[0032] exist Figure 3 , the output of loop filter 108B is a function of the difference between the signals at negative input node 109B and positive input node 111B. As shown, the output of loop filter 108B is provided to an RC circuit having a resistor (R_OUT) and a capacitor (C_OUT). Between R_OUT and C_OUT is node 308 which is coupled to input node 114B of VCO 112B. Figure 3 In the example of FIG. 1 , node 308 receives a feedforward signal ( Figure 3 108B). Thus, for PLL circuit 102B, the voltage at input node 114B of VCO 112B is a function of the operation of PFD 104B, charge pump 106B, loop filter 108B, RC circuit, and feed-forward circuit 110B (which applies a feed-forward signal to node 308), wherein use of feed-forward circuit 110B reduces the phase noise of PLL circuit 102B.

[0033] Figure 4 is a block diagram illustrating a PLL circuit 102C having modeled components according to various examples. Figure 4 In the example of Figure 2 The PLL circuit 102A, Figure 3 PLL circuit 102B or feed-forward option 1 or 2 under Figure 1 As shown, the PLL circuit 102C includes a PFD 104C, which is Figure 3 PFD 104B or Figure 1 104C. The inputs to PFD 104C include a feedback signal (CLK) and a reference signal (REF_CLK). More specifically, in Figure 4 In the example of FIG. 4 , the REF_CLK signal is shown as being provided to the PFD 104C via the limiter 402. Meanwhile, the CLK signal is shown as being provided to the PFD 104C via the VCO 112C ( Figure 3VCO 112B or Figure 1 The output of the VCO 112 (instance of VCO 112 in FIG. 1 ) is passed to the divider buffer 406 and the feedback divider 408 provided to the PFD 104C, wherein the output of the feedback divider 408 is the CLK signal. Figure 4 In the example of Figure 3 PLL circuit 102B or feed-forward option 2 under Figure 1 PLL 102.

[0034] exist Figure 4 In the embodiment, the charge pump 106C receives the output of the PFD 104C, wherein the charge pump 106C is Figure 3 The charge pump 106B or Figure 1 An example of a charge pump 106 is shown in FIG. Figure 4 As shown in FIG. 1 , charge pump 106C applies a gain (Kd) to the signal from PFD 104C. Thereafter, as Figure 3 The loop filter 108B in or Figure 1 The loop filter 108C of the example loop filter 108 in FIG. 1 applies a frequency dependent gain to the output of the charge pump 106C by integrating (1 / sC). The output of the loop filter 108C is combined with the output of the feed-forward circuit 110C, which is Figure 3 The feedforward circuit 110B or Figure 1 An example of a feed-forward circuit 110 is shown in FIG. Figure 4 As shown in FIG. 4 , the feedforward circuit 110C applies a gain (Kf) to the output of the PFD 104C. The output of the feedforward circuit 110C and the output of the loop filter 108C are combined at node 404, which is Figure 3 Node 308 or Figure 1 . The output from node 404 is provided to VCO 112C, causing VCO 112C to output a signal having a phase that varies with the signal at node 404. Figure 4 , the output from VCO 112C is provided to divider buffer 406 as previously discussed and is local oscillator signal 410.

[0035] The control loop behavior of the PLL circuit 102C can be represented using various parameters. More specifically, in some examples, the phase of the output of the VCO 112C as a function of the phase error between the feedback signal (e.g., CLK) and the reference signal (e.g., REF_CLK) is given by:

[0036]

[0037] Where R = K f / K d, where Φ OUT is the phase of the output of VCO 112C, Φ e is the phase error between the CLK signal and the CLK_REF signal, Kd is the gain applied by the charge pump 106C, s is the frequency of the control loop, C is the capacitance of the control loop, R is the resistance of the control loop, and Kv is the gain expressed as the change in the VCO output frequency caused by a change in the control voltage at its input. Additionally, in some examples, as Φ e The output voltage (V c ) is given as follows:

[0038]

[0039] where Kd is the gain applied by the charge pump 106C, s is the frequency of the control loop, C is the capacitance of the control loop, R is the resistance of the control loop, and K f is the gain applied by the feedforward circuit 110C. Moreover, in some instances, the zero point of the control loop is determined based on other values. For example, in some instances, the zero point control loop is determined as:

[0040]

[0041] Moreover, in some examples, the bandwidth of the control loop is estimated based on other values. For example, in some examples, the bandwidth (BW) of the control loop is estimated as:

[0042] BW∝K d .RK v ∝K f .K v Equation (4)

[0043] Figure 5 5 is a graph 500 illustrating phase noise (in dB) as a function of frequency for various PLL circuits according to various examples. In graph 500, various phase noise curves 502, 504, 506, 508, and 510 are shown. More specifically, noise curve 502 corresponds to a prior art PLL circuit and phase noise curve 504 corresponds to Figure 2 For PLL circuit 102A, phase noise curve 506 corresponds to Figure 3 102B, phase noise curve 508 corresponds to a prior art PLL circuit with a noise-free VCO, and phase noise curve 510 corresponds to a prior art PLL circuit with a noise-free VCO. Figure 2 The phase noise curve 512 corresponds to the PLL circuit 102A with a noise-free VCO. Figure 3As shown in graph 500, using a feed-forward circuit as described herein reduces phase noise compared to a prior art PLL circuit that uses an actual resistor R in series with a capacitor C in its feedback path.

[0044] Figure 6 6 is a flow chart illustrating a PLL method 600 according to various examples. As shown, the method 600 includes detecting, by a detector, at box 602, an error signal indicating a phase offset between a feedback clock signal (CLK) and a reference clock signal (REF_CLK). At box 604, adjusting a charge pump output based on the error signal. At box 606, integrating the charge pump output over time by an integrator. At box 608, converting the integrated charge pump output into a voltage signal. At box 610, applying a correction to the voltage signal using a feedforward circuit directly coupled to the detector. In some examples, the operation of box 610 involves applying the correction to a reference node of the integrator using the feedforward circuit. In other examples, the operation of box 610 involves applying the correction to an input node of a VCO using the feedforward circuit. At box 612, applying a correction to a reference node of the integrator using the VCO (e.g., Figure 4 VCO 112C, Figure 3 VCO 112B, Figure 2 VCO 112A, Figure 1 The VCO 112 in FIG. 1 uses the corrected voltage signal to provide an output signal having a phase based on the corrected voltage signal.

[0045] Specific terms have been used in the detailed description and claims to refer to specific system components. It should be understood by those skilled in the art that different parties may refer to components by different names. The present invention is not intended to distinguish between components that have different names but not different functions. In the present invention and the claims, the terms "include" and "comprise" are used in an open manner and should therefore be interpreted as meaning "including (but not limited to)...". Moreover, the term "couple (couples) is intended to mean an indirect or direct wired or wireless connection. Therefore, if a first device is coupled to a second device, the connection may be by a direct connection or by an indirect connection via other devices and connections. The statement "based on..." is intended to mean "based at least in part on...". Therefore, if X is based on Y, X can be a function of Y and any number of other factors.

[0046] The above discussion is intended to illustrate the principles and various embodiments of the present invention. Those skilled in the art will appreciate numerous changes and modifications after fully understanding the above disclosure. The appended claims are intended to be interpreted to include all such changes and modifications.

Claims

1. A device comprising: a phase offset detector having a first clock input, a second clock input, and an output; a charge pump having an input and an output, wherein the input of the charge pump is coupled to the output of the phase offset detector; a feedforward circuit having an input and an output, wherein the input of the feedforward circuit is coupled to the output of the phase offset detector; an amplifier having a first input, a second input, and an output, wherein the first input of the amplifier is coupled to the output of the charge pump and the second input of the amplifier is coupled to a reference voltage terminal; and An oscillator has an input coupled to the output of the amplifier.

2. The device of claim 1, further comprising a voltage generator having an output coupled to the second input of the amplifier.

3. The device of claim 1, further comprising a capacitor having a first terminal coupled to the output of the amplifier.

4. The apparatus of claim 1 , wherein the output of the phase offset detector is a first output of the phase offset detector, wherein the phase offset detector has a second output, and wherein the feed-forward circuit has a second input coupled to the second output of the phase offset detector.

5. The device of claim 4, wherein the phase offset detector is configured to output a first signal at the first output of the phase offset detector based on the first clock input and the second clock input, and to output a second signal at the second output of the phase offset detector based on the first clock input and the second clock input.

6. The apparatus of claim 1, wherein the feed-forward circuit comprises an inverter having an input and an output, wherein the input of the inverter is coupled to the output of the phase offset detector.

7. The apparatus of claim 6, wherein the output of the inverter is coupled to the second input of the amplifier.

8. The apparatus of claim 6, wherein the output of the inverter is coupled to the output of the amplifier.

9. The apparatus of claim 6, wherein the feedforward circuit further comprises a buffer having an input coupled to the second output of the phase offset detector and an output coupled to the output of the inverter.

10. The device of claim 9, wherein the buffer is coupled to the output of the inverter via a resistor.

11. The apparatus of claim 1, wherein the oscillator is a voltage controlled oscillator.

12. The apparatus of claim 1, wherein the output of the feedforward circuit is coupled to the second input of the amplifier.

13. The apparatus of claim 1, wherein the output of the feedforward circuit is coupled to the output of the amplifier.

14. The apparatus of claim 1, wherein the reference voltage terminal is coupled to the second input of the amplifier via a resistor.

15. The apparatus of claim 14, wherein an intermediate node between the resistor and the second input of the amplifier is directly connected to the output of the feedforward circuit.

16. The device of claim 1, further comprising a feedback divider coupled between an output of the oscillator and the second clock input.

17. The device of claim 1, further comprising a limiter having an output coupled to the first clock input.

18. The apparatus of claim 1, further comprising a phase locked loop (PLL), the PLL comprising: Output terminals; the oscillator, wherein an output of the oscillator is coupled to the output terminal of the PLL; the amplifier; the charge pump; the feedforward circuit; and The phase shift detector.

19. An apparatus comprising: a phase offset detector having a first clock input, a second clock input, and an output; a charge pump having an input and an output, wherein the input of the charge pump is coupled to the output of the phase offset detector; a feedforward circuit having an input and an output, wherein the input of the feedforward circuit is coupled to the output of the phase offset detector; a filter having a first input and an output, wherein the first input of the filter is coupled to the output of the charge pump; and An oscillator has an input coupled to the output of the filter.

20. The apparatus of claim 19, wherein the filter comprises an RC filter.

21. The device of claim 19, wherein the filter comprises a second input and an amplifier having a first input, a second input, and an output, wherein the first input of the amplifier is coupled to the first input of the filter, wherein the second input of the amplifier is coupled to the second input of the filter, wherein the output of the amplifier is coupled to the output of the filter, and wherein the second input of the filter is coupled to a reference voltage terminal.

22. The device of claim 21, further comprising a capacitor coupled between the first input of the amplifier and the output of the amplifier.

23. The apparatus of claim 19, wherein the output of the feedforward circuit is coupled to the output of the filter.

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