Ethernet physical interface expansion device and data uplink and downlink transmission method
By adding interface expansion modules and multiple PHY chips to the CPU module, and using programmable logic devices and header mechanisms, the problem of insufficient number of built-in Ethernet interfaces in traditional CPUs is solved, and flexible interface expansion and efficient data transmission are achieved.
Patent Information
- Application Number
- CN202411983341.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2025-04-18
AI Technical Summary
Traditional CPUs usually only have one Ethernet interface built-in, which limits the scalability and flexibility of the system, especially in application scenarios where multiple Ethernet interfaces are required that are physically isolated from each other.
It provides an Ethernet physical interface expansion device, including a CPU module, an interface expansion module and multiple PHY chips, connects the CPU module and the PHY chip through the MII interface, and uses CPLD or FPGA programmable logic devices to realize uplink and downlink transmission of data, and uses a header mechanism to mark the data source and destination port.
It realizes flexible expansion of any number of Ethernet physical interfaces, reduces hardware requirements and costs, supports multiple Ethernet rates and interface types, and improves the adaptability and reliability of the system.
Smart Images
Figure CN119854054A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of Ethernet, and in particular to an Ethernet physical interface expansion device and a data transmission method. Background Art
[0002] In modern network communication systems, Ethernet, as a mainstream LAN technology, is widely used in various occasions due to its high speed, high reliability and cost-effectiveness. With the development of network technology and the increase in application needs, the demand for the number and rate of Ethernet interfaces is also growing. Especially in the field of embedded systems and industrial control, multiple physically isolated Ethernet interfaces are often required to meet different network communication needs, such as data acquisition, video monitoring, remote control, etc.
[0003] However, traditional solutions have some limitations and shortcomings: not all CPUs have built-in Ethernet interfaces, and even if they do, their types and quantities are limited by the CPU manufacturer's market strategy and technical positioning. Most CPUs for embedded systems usually only have one built-in Ethernet interface, which limits the scalability and flexibility of the system. In many application scenarios, for safety and reliability reasons, the system needs to provide multiple physically isolated Ethernet interfaces. For example, in critical infrastructure, two independent Ethernet interfaces may be required for data backup and failover. Summary of the invention
[0004] The object of the present invention is to provide an Ethernet physical interface expansion device and a data transmission method to improve the above technical problems.
[0005] In order to achieve the above-mentioned object of the invention, the embodiment of the present invention provides the following technical solutions:
[0006] An Ethernet physical interface expansion device comprises a CPU module, an interface expansion module and N PHY chips; the interface expansion module is connected to the CPU module and each of the PHY chips through an MII interface; wherein:
[0007] A CPU module, used for receiving or sending data from the interface expansion module;
[0008] An interface expansion module, used to realize uplink transmission and downlink transmission of data between the CPU module and each of the PHY chips;
[0009] The PHY chip is used to receive or send data from the interface expansion module and perform conversion to achieve physical layer communication with an external network.
[0010] Furthermore, the interface expansion module adopts a CPLD programmable logic device or an FPGA programmable logic device;
[0011] The interface expansion module includes an internal logic circuit and a header mechanism; the internal logic circuit includes an uplink channel processing unit and a downlink channel processing unit; wherein:
[0012] An uplink channel processing unit, used for processing the data sent by the PHY chip according to the header mechanism, aggregating the data, and transmitting the data to the CPU module;
[0013] A downlink channel processing unit, used for processing the data sent by the CPU module according to the header mechanism, dispersing the data, and transmitting the data to the corresponding PHY chips;
[0014] The header mechanism is used to mark the data source port of the data sent by the PHY chip in the uplink channel processing unit; and to specify the data output port of the data sent by the CPU module in the downlink channel processing unit.
[0015] Furthermore, the structures of the uplink channel processing unit and the downlink channel processing unit are the same, and both include M Ethernet physical interfaces; wherein the uplink / downlink channel processing unit is connected to the CPU module via an Ethernet physical interface, and the Ethernet physical interface is used as the upper Ethernet physical interface; the uplink / downlink channel processing unit is respectively connected to each of the PHY chips via M-1 Ethernet physical interfaces, and the M-1 Ethernet physical interfaces are used as the lower Ethernet physical interfaces.
[0016] Furthermore, the interface types of the Ethernet physical interface include MII interface, GMII interface, RGMII interface and SGM interface; the rates of the Ethernet physical interface include 10M, 100M, 1G, 10G and 40G.
[0017] Furthermore, the header mechanism includes a 1-byte header for marking the Ethernet physical interface.
[0018] A data uplink transmission method includes:
[0019] S1. Receiving data transmitted by the corresponding PHY chip through each of the lower Ethernet physical interfaces;
[0020] S2, using the header mechanism, allocating headers corresponding to the lower Ethernet physical interfaces through the internal logic circuit;
[0021] S3, based on each of the headers, updating the data of each of the lower Ethernet physical interfaces;
[0022] S4, transmitting each updated data to the CPU module through the upper Ethernet physical interface;
[0023] S5. Process the headers corresponding to each updated data through the CPU module and upload them to the upper layer protocol.
[0024] Furthermore, when each of the lower Ethernet physical interfaces receives data simultaneously, a polling mechanism is used to perform fair scheduling on the received data.
[0025] A data downlink transmission method includes:
[0026] A1. Based on the header mechanism, mark the data to obtain the corresponding header;
[0027] A2, adding 1 to the length of the data through the CPU module, and transmitting it to the upper Ethernet physical interface;
[0028] A3, identifying the header corresponding to the data through the internal logic circuit, and determining the corresponding lower Ethernet physical interface;
[0029] A4, using the internal logic circuit to remove the header corresponding to the data to obtain updated data;
[0030] A5. According to the Ethernet layer 2 header data specification, the updated data is transmitted to the corresponding lower Ethernet physical interface.
[0031] The beneficial effects of the present invention are:
[0032] The device has a flexible interface device, which can expand any number of Ethernet physical interfaces as needed, providing extremely high flexibility to meet the demand for the number of interfaces in different application scenarios; by using programmable logic devices such as FPGA or CPLD, the demand for additional hardware is reduced, reducing the overall cost; it supports multiple Ethernet rates and interface types, including 10M / 100M / 1G / 10G / 40G, as well as MII / GMII / RGMII / SGMII, etc., improving the adaptability of the device.
[0033] The uplink transmission method of the present invention efficiently processes data from each PHY chip through a header mechanism, simplifies the data aggregation process, and can perform efficient uplink data transmission. The CPU only needs to process the header to distinguish the data source, and does not need to perform complex routing or table lookup operations, thereby simplifying the CPU processing flow; the downlink transmission method accurately marks the data through the header mechanism, ensuring that the data can be correctly sent to the specified PHY chip, improving the efficiency of data forwarding, ensuring the integrity of the data and the correctness of the verification, and maintaining the reliability of data transmission. BRIEF DESCRIPTION OF THE DRAWINGS
[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.
[0035] Figure 1 It is a structural schematic diagram of an Ethernet physical interface expansion device according to an embodiment of the present invention;
[0036] Figure 2 This is a flow chart of a method for uplink data transmission in an embodiment of the present invention;
[0037] Figure 3 A schematic diagram of the data format of the Ethernet layer 2 frame format in an embodiment of the present invention;
[0038] Figure 4 Schematic diagram of uplink data processing of the interface expansion module in an embodiment of the present invention;
[0039] Figure 5 Schematic diagram of uplink data processing of the CPU module in an embodiment of the present invention;
[0040] Figure 6 This is a flow chart of a method for downlink data transmission in an embodiment of the present invention;
[0041] Figure 7 Schematic diagram of downlink data processing of the CPU module in an embodiment of the present invention;
[0042] Figure 8 The figure is a schematic diagram of downlink data processing of the interface expansion module in an embodiment of the present invention. DETAILED DESCRIPTION
[0043] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. The components of the embodiments of the present invention generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents the selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present invention.
[0044] See also Figure 1The present embodiment provides an Ethernet physical interface expansion device comprising a CPU module, an interface expansion module and N PHY chips; the interface expansion module is connected to the CPU module and each of the PHY chips through an MII interface; wherein:
[0045] A CPU module, used for receiving or sending data from the interface expansion module;
[0046] An interface expansion module, used to realize uplink transmission and downlink transmission of data between the CPU module and each of the PHY chips;
[0047] The PHY chip is used to receive or send data from the interface expansion module and perform conversion to achieve physical layer communication with an external network.
[0048] This device reduces the use of additional hardware components, reduces the system's failure points, and improves the system's stability and reliability; it does not require additional switching chips or complex wiring, simplifies the device, and is easy to implement and maintain.
[0049] The interface expansion module adopts a CPLD programmable logic device or an FPGA programmable logic device;
[0050] The interface expansion module includes an internal logic circuit and a header mechanism; the internal logic circuit includes an uplink channel processing unit and a downlink channel processing unit; wherein:
[0051] An uplink channel processing unit, used for processing the data sent by the PHY chip according to the header mechanism, aggregating the data, and transmitting the data to the CPU module;
[0052] A downlink channel processing unit, used for processing the data sent by the CPU module according to the header mechanism, dispersing the data, and transmitting the data to the corresponding PHY chips;
[0053] The header mechanism is used to mark the data source port of the data sent by the PHY chip in the uplink channel processing unit; and to specify the data output port of the data sent by the CPU module in the downlink channel processing unit.
[0054] The structures of the uplink channel processing unit and the downlink channel processing unit are the same, and both include M Ethernet physical interfaces; wherein the uplink / downlink channel processing unit is connected to the CPU module via an Ethernet physical interface, and the Ethernet physical interface is used as the upper Ethernet physical interface; the uplink / downlink channel processing unit is respectively connected to each of the PHY chips via M-1 Ethernet physical interfaces, and the M-1 Ethernet physical interfaces are used as the lower Ethernet physical interfaces.
[0055] The number of Ethernet physical interfaces is limited by the number of available pins of the CPLD programmable logic device or the FPGA programmable logic device. For example, the total number of resources inside the FPGA programmable logic device is limited, and the bandwidth of the Ethernet port and the extended Ethernet port of the CPU module is limited. If two Ethernet physical interfaces are used to connect to the CPU module, it is necessary to define the selection strategy of the two interfaces, which greatly increases the complexity of the Ethernet physical interface extension device. Therefore, in this device, an Ethernet physical interface is selected as the Ethernet physical interface seat and connected to the CPU module, which can simplify the structure of the device to the greatest extent and further maintain the robustness of the device.
[0056] When data is transmitted, the upper Ethernet physical interface and the lower Ethernet physical interface can adopt different rates. For example, when the rate of the upper Ethernet physical interface is 1000M, and the rate of the lower Ethernet physical interface to be expanded is 100M, it can be easily expanded to 10 interfaces. As long as the number of expansion ports is within 10, there will be no problem of insufficient bandwidth; if the number of expansion ports exceeds 10, the bandwidth of the CPU Ethernet port is insufficient, congestion will occur, and the "complete message" needs to be discarded.
[0057] When data is transmitted downstream, the speed of each Ethernet physical interface may be different. For example, five Ethernet physical interfaces with a speed of 100M and one Ethernet physical interface with a speed of 1000M are extended at the same time.
[0058] The upper Ethernet physical interface and the lower Ethernet physical interface set in this device can use different rates at the same time, which can be suitable for different application environments, greatly enhancing the applicability of this device; through effective data aggregation and dispersion mechanism, the utilization rate of bandwidth is improved, especially in a multi-interface environment; no additional switching chips or complex wiring are required, making the device design more concise, easy to implement and maintain.
[0059] The device does not include the routing capability between the downlink interfaces, that is, the data forwarding between the externally extended Ethernet interfaces (downlink Ethernet physical interfaces) must pass through the CPU. The device can achieve transparent access and is transparent and invisible to external Ethernet users. The device does not modify the upper layer protocol and has no effect on the TCP / IP protocol stack.
[0060] The interface types of the Ethernet physical interface include MII interface, GMII interface, RGMII interface, SGM interface, RMII interface, SMII interface, SSMII interface, SSSMII interface, XGMII interface, TBI interface, RTBI interface, XAUI interface, XIAUI interface; the speed of the Ethernet physical interface includes 10M, 100M, 1G, 10G, 40G. Among them, the MII interface is a 10M / 100M basic interface, and the GMII interface is a 1000M basic interface.
[0061] The header mechanism includes a 1-byte header, which is used to mark the Ethernet physical interfaces whose number is less than 256. The header works at the link layer and does not affect the upper layer protocol, thus ensuring transparency to network protocols such as TCP / IP. The device adopts a header mechanism, which can flexibly mark and identify data of different Ethernet physical interfaces, thereby improving the flexibility of network configuration; compared with traditional physical interface expansion solutions, it can further reduce the hardware requirements of the device, thereby reducing costs; it avoids complex routing and switching logic, simplifies the data transmission process, and reduces the complexity of the device. The header only acts inside the interface expansion module and is transparent and invisible to external Ethernet users.
[0062] For external Ethernet devices, this device provides transparent access and the external Ethernet protocol does not require any modification.
[0063] The channel from the external expansion network port to the CPU module is called the uplink channel. The purpose of the uplink channel is single, which is to aggregate the data received by multiple Ethernet physical interfaces into one data channel and record the corresponding source port information (the Ethernet physical interface). Figure 2 As shown, a method for uplink data transmission includes:
[0064] S1. Receiving data transmitted by the corresponding PHY chip through each of the lower Ethernet physical interfaces;
[0065] S2, using the header mechanism, allocating headers corresponding to the lower Ethernet physical interfaces through the internal logic circuit;
[0066] S3, based on each of the headers, updating the data of each of the lower Ethernet physical interfaces;
[0067] S4, transmitting each updated data to the CPU module through the upper Ethernet physical interface;
[0068] S5. Process the headers corresponding to each updated data through the CPU module and upload them to the upper layer protocol.
[0069] When the lower Ethernet physical interfaces receive data at the same time, a polling mechanism is used to fairly schedule the received data.
[0070] like Figure 3 As shown, the Ethernet layer 2 frame format is used as an example for uplink data transmission, and the corresponding data includes the preamble (7 bytes), SFD (1 byte), layer 2 header data, and FCS (4 bytes). The corresponding data is obtained through multiple PHY chips, and directly uploaded to the interface expansion module of this device through the corresponding lower Ethernet physical interface, without any table lookup or routing operation. The preamble and SFD are discarded or penetrated as is through the interface expansion module; Figure 4 As shown, based on the header mechanism, a 1-byte header is added to the data to be uploaded, that is, through the lower Ethernet physical interface, the ID number corresponding to the lower Ethernet physical interface is used as the header; the second-layer header data is transmitted through the interface extension module, and the data format and quantity corresponding to the second-layer header data are not limited; the FCS (4 bytes) is removed, and the 4-byte FCS check code is updated according to the header to generate the corresponding upload data.
[0071] The Ethernet physical interface is used to transmit the uploaded data to the CPU module. Figure 5 As shown, the CPU module receives the complete uploaded data, namely "HD (header) + layer 2 header data (layer 2 + data) + FCS". The data reception is determined to be complete based on the FCS check code, and the HD and FCS check codes are removed by the CPU module, and then the layer 2 header data is uploaded to the upper layer protocol. The upper layer protocol processes the layer 2 header data in the same way as in the prior art, and no changes are required, which further proves that the present invention is applicable to multiple application scenarios.
[0072] That is, the channel from the CPU module to the external expansion network port is called the downlink channel. During the downlink process, the data transmitted by the CPU module needs to be dispersed into multiple data paths according to the destination network port, and then routed and transmitted to the corresponding Ethernet physical interface, so that Figure 6 As shown, a data downlink transmission method includes:
[0073] A1. Based on the header mechanism, mark the data to obtain the corresponding header;
[0074] A2, adding 1 to the length of the data through the CPU module, and transmitting it to the upper Ethernet physical interface;
[0075] A3, identifying the header corresponding to the data through the internal logic circuit, and determining the corresponding lower Ethernet physical interface;
[0076] A4, using the internal logic circuit to remove the header corresponding to the data to obtain updated data;
[0077] A5. According to the Ethernet layer 2 header data specification, the updated data is transmitted to the corresponding lower Ethernet physical interface respectively;
[0078] A6. Transmitting the updated data to an external network through each of the lower Ethernet physical interfaces.
[0079] like Figure 7 As shown, the CPU module obtains the downstream data, and based on the header mechanism, updates the format of the downstream data, connects the 1-byte header HD to the header of the downstream data, and updates the length of the downstream data, that is, adds 1. The updated downstream data is received through the upper Ethernet physical interface; based on the header, the required lower Ethernet physical interface is determined; as shown Figure 8 As shown, the updated downlink data is updated twice through the interface extension module, the header is removed, and the SFD and the leading code are generated at the head of the secondary header data of the updated downlink data in sequence, and the FCS check code is generated at the tail of the secondary header data of the updated downlink data to obtain the final data to be transmitted. The final data to be transmitted is transmitted to the external network through the corresponding determined downlink Ethernet physical interface.
[0080] In summary, the device has a simple structure and a flexible interface device. It can expand any number of Ethernet physical interfaces as needed, providing extremely high flexibility to meet the requirements for the number of interfaces in different application scenarios. By using programmable logic devices such as FPGA or CPLD, the demand for additional hardware is reduced, no additional resources are required, the resource occupation is small, no Ethernet performance is lost, and the overall cost is reduced. It supports multiple Ethernet rates and interface types, including 10M / 100M / 1G / 10G / 40G, etc., as well as MII / GMII / RGMII / SGMII, etc., which improves the adaptability of the device.
[0081] The uplink transmission method of the present invention efficiently processes data from each PHY chip through a header mechanism, simplifies the data aggregation process, and can perform efficient uplink data transmission. The CPU only needs to process the header to distinguish the data source, and does not need to perform complex routing or table lookup operations, thereby simplifying the CPU processing flow; the downlink transmission method accurately marks the data through the header mechanism, ensuring that the data can be correctly sent to the specified PHY chip, improving the efficiency of data forwarding, ensuring the integrity of the data and the correctness of the verification, and maintaining the reliability of data transmission.
[0082] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.
Claims
1. An Ethernet physical interface expansion device, characterized in that: It includes a CPU module, an interface expansion module and N PHY chips; the interface expansion module is connected to the CPU module and each of the PHY chips through the MII interface; wherein: A CPU module, used for receiving or sending data from the interface expansion module; An interface expansion module, used to realize uplink transmission and downlink transmission of data between the CPU module and each of the PHY chips; The PHY chip is used to receive or send data from the interface expansion module and perform conversion to achieve physical layer communication with an external network.
2. The Ethernet physical interface expansion device according to claim 1, characterized in that: The interface expansion module adopts a CPLD programmable logic device or an FPGA programmable logic device; The interface expansion module includes an internal logic circuit and a header mechanism; the internal logic circuit includes an uplink channel processing unit and a downlink channel processing unit; wherein: An uplink channel processing unit, used for processing the data sent by the PHY chip according to the header mechanism, aggregating the data, and transmitting the data to the CPU module; A downlink channel processing unit, used for processing the data sent by the CPU module according to the header mechanism, dispersing the data, and transmitting the data to the corresponding PHY chips; The header mechanism is used to mark the data source port of the data sent by the PHY chip in the uplink channel processing unit; and to specify the data output port of the data sent by the CPU module in the downlink channel processing unit.
3. The Ethernet physical interface expansion device according to claim 2, characterized in that: The structures of the uplink channel processing unit and the downlink channel processing unit are the same, and both include M Ethernet physical interfaces; wherein the uplink / downlink channel processing unit is connected to the CPU module via an Ethernet physical interface, and the Ethernet physical interface is used as the upper Ethernet physical interface; the uplink / downlink channel processing unit is respectively connected to each of the PHY chips via M-1 Ethernet physical interfaces, and the M-1 Ethernet physical interfaces are used as the lower Ethernet physical interfaces.
4. The Ethernet physical interface expansion device according to claim 3, characterized in that: The interface types of the Ethernet physical interface include MII interface, GMII interface, RGMII interface and SGM interface; the rates of the Ethernet physical interface include 10M, 100M, 1G, 10G and 40G.
5. The Ethernet physical interface expansion device according to claim 3, characterized in that: The header mechanism includes a 1-byte header for marking the Ethernet physical interface.
6. A method for uplink data transmission, used to implement the Ethernet physical interface expansion device described in any one of claims 1 to 5, characterized in that: include: S1. Receiving data transmitted by the corresponding PHY chip through each of the lower Ethernet physical interfaces; S2, using the header mechanism, allocating headers corresponding to the lower Ethernet physical interfaces through the internal logic circuit; S3, based on each of the headers, updating the data of each of the lower Ethernet physical interfaces; S4, transmitting each updated data to the CPU module through the upper Ethernet physical interface; S5. Process the headers corresponding to each updated data through the CPU module and upload them to the upper layer protocol.
7. The method for uplink data transmission according to claim 6, characterized in that: When the lower Ethernet physical interfaces receive data at the same time, a polling mechanism is used to fairly schedule the received data.
8. A method for downlink data transmission, used to implement the Ethernet physical interface expansion device according to any one of claims 1 to 5, characterized in that: include: A1. Based on the header mechanism, mark the data to obtain the corresponding header; A2, adding 1 to the length of the data through the CPU module, and transmitting it to the upper Ethernet physical interface; A3, identifying the header corresponding to the data through the internal logic circuit, and determining the corresponding lower Ethernet physical interface; A4, using the internal logic circuit to remove the header corresponding to the data to obtain updated data; A5. According to the Ethernet layer 2 header data specification, the updated data is transmitted to the corresponding lower Ethernet physical interface respectively; A6. Transmitting the updated data to an external network through each of the lower Ethernet physical interfaces.