Slave address determination device and method, storage medium and electronic equipment

Abstract

The invention discloses a slave address determination device and method, a storage medium and electronic equipment, and relates to the technical field of automobile integrated circuit design and application, and the slave address determination device comprises a voltage input module, an analog-to-digital converter ADC sampling module, a first number of sampling result decoding modules, and a slave address decoding circuit. The voltage input module inputs a first number of voltage values to the ADC sampling module; the ADC sampling module receives the voltage value; converting each received voltage value into a corresponding voltage sampling value to obtain a first number of voltage sampling values; respectively inputting the first number of voltage sampling values into a first number of sampling result decoding modules; the slave address decoding circuit obtains an interval value which is output by each sampling decoding module and corresponds to a first numerical value interval in which the voltage sampling numerical value input into the sampling decoding module is located; and determining the slave address according to the obtained interval value so as to improve the convenience of setting the slave address.

Description

Technical Field

[0001] The present invention relates to the field of automotive integrated circuit design and application technology, and in particular to a slave address determination device, method, storage medium and electronic equipment. Background Art

[0002] In automotive electronic systems, it is very common for a host to control multiple slaves, for example, in modern smart cars, ECUs (Electronic Control Units) interact with multiple sensors. As a host, ECUs can control slaves, such as collecting various sensor data from sensors.

[0003] The architecture of the host controlling the slave is usually used to achieve centralized control and distributed execution to ensure the efficiency and reliability of the system. For example, communication protocols such as CAN, LIN, I2C, SPI, etc. are used to complete the system application of the host controlling multiple slaves. In these applications, multiple identical chips as slaves need to match the correct address to ensure normal communication with the host in the application and complete the entire function.

[0004] In the related art, a method of burning the slave address into NVM (Non-Volatile Memory) can be used to record the slave address, so that the host can determine the slave address from the NVM and communicate with the corresponding slave.

[0005] However, this implementation must be burned at the board level in most scenarios, because different slaves often perform different functions in the application, so the matching address must be burned in the correct position. The burning process is complicated and requires special fixtures. In addition, for chips with OTP (One Time Programmable) media, the address can only be set once. Once the slave address is written incorrectly, the burned chip will be wasted, which is not convenient enough. Summary of the invention

[0006] The present invention aims to solve one of the technical problems in the related art at least to a certain extent. To this end, one object of the present invention is to provide a slave address determination device, method, storage medium and electronic device to improve the convenience of setting the slave address.

[0007] According to a first aspect of an embodiment of the present invention, there is provided a slave address determination device, the device comprising: a voltage input module, an analog-to-digital converter ADC sampling module, a first number of sampling result decoding modules, and a slave address decoding circuit; The voltage input module is used to input a first number of voltage values ​​to the ADC sampling module; The ADC sampling module is used to receive the voltage value; convert each received voltage value into a corresponding voltage sampling value to obtain a first number of voltage sampling values; and input the first number of voltage sampling values ​​into a first number of sampling result decoding modules respectively; The slave address decoding circuit is used to obtain the interval value output by each sampling decoding module and corresponding to the first value interval where the voltage sampling value input to the sampling decoding module is located; and determine the slave address according to the obtained interval value.

[0008] Optionally, the first numerical range is obtained in the following manner: Obtaining a preset reference voltage; Dividing the reference voltage into a valid voltage interval and an invalid voltage interval; The effective voltage interval is divided into no less than 2 first numerical intervals, and different first numerical intervals correspond to different interval values.

[0009] Optionally, the device further comprises a fault signal generating module; The fault signal generating module is used to generate a fault signal based on a fault indication pin and / or a preset register flag bit if there is at least one interval value output by the sampling decoding module located in a second numerical interval representing the invalid voltage interval.

[0010] Optionally, when the first number is greater than or equal to 2, the slave address decoding circuit determines the slave address according to the obtained interval value, including: Determine the coefficients corresponding to each sampling decoding module; The weighted sum of each interval value is performed based on the determined coefficient to obtain a slave address corresponding to the summed result.

[0011] Optionally, the voltage input module includes a first number of resistor networks formed by series-connected resistors with different resistance values, and inputs a voltage value to the ADC sampling module based on each resistor network.

[0012] Optionally, the device further comprises an address register; The address register is used to store the determined slave address after the slave address decoding circuit determines the slave address according to the obtained interval value, so that the host obtains the slave address in the address register through a preset communication interface and compares it with the target slave address to be communicated set in the host.

[0013] According to a second aspect of an embodiment of the present invention, a method for determining a slave address is provided, the method comprising: inputting a first number of voltage values; Convert each voltage value into a corresponding voltage sampling value to obtain a first number of voltage sampling values; Obtaining an interval value corresponding to a first numerical interval in which the obtained voltage sampling value is located; The slave address is determined based on the obtained interval value.

[0014] According to a third aspect of an embodiment of the present invention, there is provided a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the above-mentioned slave address determination method is implemented.

[0015] According to a fourth aspect of an embodiment of the present invention, there is provided an electronic device, comprising: a memory and a processor; a computer program is stored in the memory, and when the computer program is executed by the processor, the above-mentioned slave address determination method is implemented.

[0016] In the solution provided by the embodiment of the present invention, by inputting different combinations of the first number of voltage values, different combinations of voltage sampling values ​​can be sampled, and then different interval values ​​can be obtained accordingly to determine different slave addresses. In the case of multiple slaves, different slaves can be set to different slave addresses. By adjusting the voltage value of the voltage input module, flexible address setting can be achieved. If the slave address is written incorrectly, it can also be repaired by adjusting the voltage setting module, thereby providing convenience in address setting.

[0017] Furthermore, the above solution does not need to identify the slave address through NVM, which can save materials and reduce the complexity of determining the slave address.

[0018] In addition, the voltage sampling value is obtained by inputting the voltage value, and then the slave address is obtained by combining and decoding the corresponding interval value. This allows more slave address settings to be supported when the input voltage value is small, and the number of pins required for the input voltage value can be reduced. Fewer pin overheads are suitable for application scenarios with a small number of chip pins, further improving convenience.

[0019] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a structural schematic diagram of a first slave address determination device provided by an embodiment of the present invention; Figure 2 is a structural schematic diagram of a second slave address determination device provided by an embodiment of the present invention; Figure 3 It is a flowchart of a method for determining a slave address provided by an embodiment of the present invention; Figure 4 It is a structural schematic diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0021] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0022] The following describes a slave address determination device, method, storage medium, and electronic device according to embodiments of the present invention with reference to the accompanying drawings.

[0023] In one embodiment of the present invention, see Figure 1 , provides a slave address determination device, comprising: a voltage input module, an analog-to-digital converter ADC sampling module, a first number of sampling result decoding modules, and a slave address decoding circuit; the voltage input module is used to input a first number of voltage values ​​to the ADC sampling module; The ADC sampling module is used to receive voltage values; convert each received voltage value into a corresponding voltage sampling value to obtain a first number of voltage sampling values; and input the first number of voltage sampling values ​​into a first number of sampling result decoding modules respectively; The slave address decoding circuit is used to obtain the interval value output by each sampling decoding module and corresponding to the first value interval where the voltage sampling value input to the sampling decoding module is located; and determine the slave address according to the obtained interval value.

[0024] In an embodiment of the present invention, when electronic device A is able to control electronic device B, for example, to obtain data of electronic device B, electronic device A is called a host and electronic device B is called a slave. The above-mentioned device can be applied to the slave address determination device and can be applied to any one of the multiple slaves controlled by the host.

[0025] Figure 1 FIG. 4 shows a case where there are two sampling result decoding modules. In other cases, there may be more than two sampling result decoding modules, or only one sampling result decoding module.

[0026] The above-mentioned voltage input module can preset the overall range of voltage value adjustment, which can be given by the internal power supply voltage or the reference voltage specially used by the ADC (Analog-to-Digital Converter) sampling module, so that each voltage value input by the voltage input module is within this overall range.

[0027] See also Figure 2The voltage input module is the peripheral voltage divider circuit in the figure. The ADDR1 and ADDR2 pins will be divided externally to input the voltage value required by the corresponding address. Figure 2 In the illustrated embodiment, the first number is two.

[0028] The ADC sampling module converts each voltage value into a voltage sampling value, specifically, including the following steps: 1. Sampling: The ADC first samples the analog signal, that is, it captures the voltage value of the signal at a specific time point. According to the Nyquist sampling theorem, the sampling frequency must be at least twice the highest frequency of the signal to avoid aliasing.

[0029] 2. Hold: After sampling, the ADC will temporarily hold the voltage value for subsequent quantization processing. This stage is called "sample and hold".

[0030] 3. Quantization: In the quantization stage, the ADC converts the sampled and held voltage value into discrete digital values. This process involves mapping the continuous analog voltage to a finite number of discrete levels. The accuracy of quantization depends on the resolution of the ADC, which is usually expressed in the number of bits, such as 8 bits, 10 bits, 12 bits, etc. An n-bit ADC can quantize the analog signal into 2n different levels.

[0031] 4. Encoding: The discrete levels after quantization are converted into binary code, which is a format that digital systems can understand and process. For example, a 3-bit ADC can quantize the analog signal into 8 levels and represent it with a 3-bit binary number (from 000 to 111).

[0032] 5. Output: Finally, the ADC outputs this binary value, which is the voltage sampling value.

[0033] For example, suppose there is a 10-bit ADC with a reference voltage of 5V. This means that the ADC can quantize the voltage range of 0V to 5V into 1024 different levels (2^10). Each level represents a voltage increment of 5V / 1024 ≈ 4.88mV. If the ADC samples a voltage of 2.5V, it will output a value close to 512 (because 2.5V / 4.88mV ≈ 512).

[0034] From the above, the voltage sampling values ​​of VADDR1 and VADDR2 are obtained after ADC sampling.

[0035] Figure 2In the figure, VREFH represents the reference voltage, and [1 / 8 VREFH, 1 / 4 VREFH), [1 / 4 VREFH, 3 / 8VREFH), [3 / 8 VREFH, 1 / 2 VREFH), [1 / 2 VREFH, 5 / 8 VREFH), [5 / 8 VREFH, 3 / 4VREFH), [3 / 4VREFH, 7 / 8VREFH] is the first numerical interval generated by segmenting the valid area of ​​the reference voltage.

[0036] Specifically, the first numerical interval can be obtained in the following manner: Obtain a preset reference voltage; divide the reference voltage into a valid voltage interval and an invalid voltage interval; divide the valid voltage interval into no less than 2 first numerical intervals, and different first numerical intervals correspond to different interval values.

[0037] Figure 2 The figure also shows the invalid voltage interval, that is, the segment indicating "invalid" in the ADDR1 decoding module and the ADDR2 decoding module, which is the lowest voltage segment [0, 1 / 8 VREFH] and the highest voltage segment [7 / 8 VREFH, VREFH], which are respectively used as the fault areas of short circuit to power supply and short circuit to ground, so as to perform fault diagnosis and error reporting when the short circuit scenario occurs. When the voltage sampling falls into the invalid area, an error flag is generated, and the host can identify the fault by obtaining the error flag.

[0038] The figure divides the effective voltage area into the above 6 first value intervals, namely the effective areas 0 to 5 in the ADDR1 decoding module and the ADDR2 decoding module. Combined with the voltage values ​​input from the two pins to the ADC sampling module, the slave address decoding circuit can support up to 36 different slave addresses through combination decoding. From a mathematical logic point of view, the multiplication combination of the 6 first value intervals of the two pins can obtain 36 different results.

[0039] by Figure 2 In the specific embodiment, the ADDR1 decoding module and the ADDR2 decoding module are a first number of sampling result decoding modules, the first number is 2, and receive inputs from the pins VADDR1 and VADDR2 respectively. Figure 2 The 6 first numerical intervals of ADDR1 are valid areas 0 to 5, which correspond to different interval values, namely the slave address segments [0,5], [6,11], [12,17], [18,23], [24,29], [30,35], where the address is an integer. Then, the corresponding specific slave address is obtained according to the 6 valid intervals 0 to 5 of ADDR2.

[0040] For example, in the ADDR1 decoding module, the voltage sampling value falls in the valid area 1, and the corresponding slave address segment is [6,11]; in the ADDR2 decoding module, the voltage sampling value falls in the valid area 5, then the address with the subscript 5 in the [6,11] array is selected, and the slave address corresponding to the slave is identified as 11. Abstractly speaking, it can be understood that the valid areas 0 to 5 of ADDR1 represent the base address A_base of the slave address as 0, 6, 12, 18, 24, and 30 respectively. The valid areas 0 to 5 of ADDR2 can represent the offset of the slave address based on the base address A_base, ranging from 0 to 5. For example, in the scenario above, the slave address is 11, which is obtained by adding the base address 6 to the offset address 5. Different addresses of the slave can be preset with different numbers, so that the specified slave address can be found by the number 11.

[0041] Further mathematical logic abstraction is performed. If the code of the valid area 0~5 is set to 0~5, and the address codes of ADDR1 and ADDR2 are defined as Code_A1 and Code_A0 respectively, then the slave address can be expressed as 6* Code_A1+Code_A0, that is, different sampling decoding modules correspond to different coefficients, that is, the interval value Code_A1 corresponds to the coefficient 6, and Code_A0 corresponds to the coefficient 1. That is, when the first number is greater than or equal to 2, the coefficient corresponding to each sampling decoding module can be determined; based on the determined coefficient, the weighted sum of each interval value is performed to obtain the slave address corresponding to the sum result.

[0042] Specifically, Figure 2 In the embodiment shown, assuming that the reference voltage VREFH of the ADC is 5V, the first number of voltage values ​​input to the slave address recognition circuit after the peripheral voltage divider circuit divides the voltage needs to be within 5V. The slave address recognition circuit is a circuit composed of the above-mentioned ADC sampling module, sampling result decoding module, and slave address decoding circuit. If it is higher than 5V, it will be considered as a short circuit to the power supply. Assuming that the two voltage values ​​of ADDR1 and ADDR2 are 2.8V and 1.56V respectively when the peripheral circuit is working in the entire system, according to the above Figure 2 In the embodiment shown, ADDR1 falls in valid area 3, and the corresponding sampling decoding module output interval value is 3, and ADDR2 falls in valid area 1, and the corresponding sampling decoding module output interval value is 1. Therefore, the slave address decoding circuit outputs the slave address as 6*3+1=19. Address 19 will be automatically stored in the current register for communication with the host.

[0043] Figure 2 In the embodiment, the reference voltage is not a limited value, but can be set according to the design of the entire system, such as 3.3V, 1.8V, etc., and there can be multiple setting references.

[0044] Furthermore, the division of the effective voltage interval and the invalid voltage interval is not limited to Figure 2 The voltage range may be divided into 8 equal parts, wherein more interval segments may be set for the valid voltage range or the invalid voltage range, or the voltage range may be divided in an unequal manner, which is not limited in the embodiment of the present invention.

[0045] When there are more than two sampling decoding modules, there may be more coefficients, for example, the coefficient of ADDR1 is 6 and the coefficient of ADDR2 is 1. If there is an interval value corresponding to ADDR3, it is only necessary to set the coefficient to be not less than 36 to ensure a one-to-one mapping between the calculated value and the address.

[0046] When there is only one sampling decoding module, for example, only ADDR1, which falls in the valid area 3, the corresponding sampling decoding module output interval value is 3, then the address pre-marked as the value 3 is used as the slave address.

[0047] In the solution provided by the embodiment of the present invention, by inputting different combinations of the first number of voltage values, different combinations of voltage sampling values ​​can be sampled, and then different interval values ​​can be obtained accordingly to determine different slave addresses. In the case of multiple slaves, different slaves can be set to different slave addresses. By adjusting the voltage value of the voltage input module, flexible address setting can be achieved. If the slave address is written incorrectly, it can also be repaired by adjusting the voltage setting module, thereby providing convenience in address setting.

[0048] Furthermore, the above solution does not need to identify the slave address through NVM, which can save materials and reduce the complexity of determining the slave address.

[0049] In addition, the voltage sampling value is obtained by inputting the voltage value, and then the slave address is obtained by combining and decoding the corresponding interval value. This allows more slave address settings to be supported when the input voltage value is small, and the number of pins required for the input voltage value can be reduced. Fewer pin overheads are suitable for application scenarios with a small number of chip pins, further improving convenience.

[0050] In one embodiment of the present invention, the device also includes a fault signal generating module; the fault signal generating module is used to generate a fault signal based on a fault indication pin and / or a preset register flag bit if there is an interval value output by at least one sampling decoding module that is located in a second numerical interval representing an invalid voltage interval.

[0051] like Figure 2As shown, ADDR1 / 2 are the first pin and the second pin of the input address respectively. When any sample value of ADDR1 or ADDR2 is determined to be in the invalid area, the fault indication pin DIAG will display the fault status for the host to obtain, and the corresponding register flag bit can also be set to 1 for the host to read and find out the cause of the fault.

[0052] In this way, in a short-circuit scenario, the above device can support the diagnosis and identification of short-circuit faults, meeting application scenarios with high functional safety requirements.

[0053] In one embodiment of the present invention, the voltage input module includes a first number of resistor networks formed by series-connected resistors with different resistance values, and inputs a voltage value to the ADC sampling module based on each resistor network.

[0054] like Figure 2 As shown, there is a voltage divider circuit in the voltage input module. The voltage divider circuit is a basic circuit structure used to distribute the input voltage to different components or reduce the voltage size. Its working principle is based on Ohm's law and the law of resistor voltage division. In the voltage divider circuit, two resistors are connected in series to form a resistor network. For example, resistors R1 and R2 form one resistor network, and R3 and R4 form another resistor network. In any resistor network, one resistor is connected to the input voltage, that is, the voltage divider source in the figure, and the other is the ground wire, that is, the GND wire in the figure.

[0055] In this way, the voltage output to ADDR1 and ADDR2 is a part of the input voltage, and the output voltage can be controlled by adjusting the resistance ratio of the two resistors in any resistor network, so that the pins of the ADC sampling module can obtain different voltages.

[0056] In one embodiment of the present invention, the device also includes an address register; the address register is used to store the determined slave address after the slave address decoding circuit determines the slave address according to the obtained interval value, so that the host obtains the slave address in the address register through a preset communication interface and compares it with the target slave address to be communicated set in the host.

[0057] In this way, the host can also read the address through the communication interface to confirm whether it is consistent with the target slave address that the peripheral circuit hopes to identify.

[0058] In addition, by storing the slave address through the address register, it is also possible to avoid using NVM burning and reduce the complexity of address storage.

[0059] The communication interface may be a communication interface based on a communication protocol such as CAN, LIN, I2C, SPI, etc. The host sets the target slave address, and when it is determined that the slave address in the address register of the slave is consistent with the target slave address, communication can be performed with the slave, thereby enabling slave address identification through the address register.

[0060] In one embodiment of the present invention, Figure 3 As shown, a method for determining a slave address is provided, and the method includes the following steps S301-S304.

[0061] S301: input a first number of voltage values; S302: Convert each voltage value into a corresponding voltage sampling value to obtain a first number of voltage sampling values; S303: Obtaining an interval value corresponding to a first numerical interval in which the obtained voltage sampling value is located; S304: Determine the slave address according to the obtained interval value.

[0062] In the solution provided by the embodiment of the present invention, by inputting different combinations of the first number of voltage values, different combinations of voltage sampling values ​​can be sampled, and then different interval values ​​can be obtained accordingly to determine different slave addresses. In the case of multiple slaves, different slaves can be set to different slave addresses. By adjusting the voltage value of the voltage input module, flexible address setting can be achieved. If the slave address is written incorrectly, it can also be repaired by adjusting the voltage setting module, thereby providing convenience in address setting.

[0063] Furthermore, the above solution does not need to identify the slave address through NVM, which can save materials and reduce the complexity of determining the slave address.

[0064] In addition, the voltage sampling value is obtained by inputting the voltage value, and then the slave address is obtained by combining and decoding the corresponding interval value. This allows more slave address settings to be supported when the input voltage value is small, and the number of pins required for the input voltage value can be reduced. Fewer pin overheads are suitable for application scenarios with a small number of chip pins, further improving convenience.

[0065] In one embodiment of the present invention, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the above-mentioned slave address determination method is implemented.

[0066] In one embodiment of the present invention, an electronic device is provided, including: a memory and a processor; a computer program is stored in the memory, and when the computer program is executed by the processor, the above-mentioned slave address determination method is implemented.

[0067] Figure 4 It is a structural block diagram of an electronic device according to an embodiment of the present invention.

[0068] like Figure 4 As shown, the electronic device 400 includes: a processor 401 and a memory 403. The processor 401 and the memory 403 are connected, such as through a bus 402. Optionally, the electronic device 400 may further include a transceiver 404. It should be noted that in actual applications, the transceiver 404 is not limited to one, and the structure of the electronic device 400 does not constitute a limitation on the embodiments of the present invention.

[0069] Processor 401 may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. It may implement or execute various exemplary logic blocks, modules and circuits described in conjunction with the disclosure of the present invention. Processor 401 may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0070] The bus 402 may include a path to transmit information between the above components. The bus 402 may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus. The bus 402 may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 4 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0071] The memory 403 is used to store a computer program corresponding to the slave address determination method of the above embodiment of the present invention, and the computer program is controlled and executed by the processor 401. The processor 401 is used to execute the computer program stored in the memory 403 to implement the content shown in the above method embodiment.

[0072] Among them, the electronic device 400 includes but is not limited to: mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 4 The electronic device 400 shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present invention.

[0073] It should be noted that the logic and / or steps represented in the flowchart or described in other ways herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purpose of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples (non-exhaustive list) of computer-readable media include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0074] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0075] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0076] In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0077] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0078] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0079] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0080] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A device for determining a slave address, characterized in that: The device comprises: a voltage input module, an analog-to-digital converter ADC sampling module, a first number of sampling result decoding modules, and a slave address decoding circuit; the voltage input module is used to input a first number of voltage values ​​to the ADC sampling module; The ADC sampling module is used to receive the voltage value; convert each received voltage value into a corresponding voltage sampling value to obtain a first number of voltage sampling values; and input the first number of voltage sampling values ​​into a first number of sampling result decoding modules respectively; The slave address decoding circuit is used to obtain the interval value output by each sampling decoding module and corresponding to the first value interval where the voltage sampling value input to the sampling decoding module is located; and determine the slave address according to the obtained interval value.

2. The device according to claim 1, characterized in that The first numerical interval is obtained in the following manner: Obtaining a preset reference voltage; Dividing the reference voltage into a valid voltage interval and an invalid voltage interval; The effective voltage interval is divided into no less than 2 first numerical intervals, and different first numerical intervals correspond to different interval values.

3. The device according to claim 2, characterized in that The device also includes a fault signal generating module; The fault signal generating module is used to generate a fault signal based on a fault indication pin and / or a preset register flag bit if there is at least one interval value output by the sampling decoding module located in a second numerical interval representing the invalid voltage interval.

4. The device according to claim 1, characterized in that When the first number is greater than or equal to 2, the slave address decoding circuit determines the slave address according to the obtained interval value, including: Determine the coefficients corresponding to each sampling decoding module; The weighted sum of each interval value is performed based on the determined coefficient to obtain a slave address corresponding to the summed result.

5. The device according to claim 1, characterized in that The voltage input module includes a first number of resistor networks formed by serially connected resistors with different resistance values, and inputs a voltage value to the ADC sampling module based on each resistor network.

6. The device according to claim 1, characterized in that The device also includes an address register; The address register is used to store the determined slave address after the slave address decoding circuit determines the slave address according to the obtained interval value, so that the host obtains the slave address in the address register through a preset communication interface and compares it with the target slave address to be communicated set in the host.

7. A method for determining a slave address, characterized in that: The method comprises: inputting a first number of voltage values; Convert each voltage value into a corresponding voltage sampling value to obtain a first number of voltage sampling values; Obtaining an interval value corresponding to a first numerical interval in which the obtained voltage sampling value is located; The slave address is determined based on the obtained interval value.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the slave address determination method as claimed in claim 7 is implemented.

9. An electronic device, characterized in that: include: Memory, processor; The memory stores a computer program, and when the computer program is executed by the processor, the slave address determination method as claimed in claim 7 is implemented.

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