Method of forming semiconductor structure

Abstract

A method of forming a semiconductor structure includes the following operations. A trench is formed in the substrate. A dielectric layer is formed to cover an inner surface of the trench. A bottom conductive layer is deposited on the dielectric layer and in the trench at a first temperature of 350 DEG C to 450 DEG C. An annealing process is performed on the bottom conductive layer at a second temperature greater than or equal to 470 DEG C. A portion of the bottom conductive layer is removed to form a recess on the bottom conductive layer and in the trench. A top conductive layer is formed in the recess. The annealing process can reduce the resistivity of the bottom conductive layer. If the semiconductor structure is used as a word line structure, the deposition temperature can avoid word line swing or word line collapse.

Description

Technical Field

[0001] The present disclosure relates to methods of forming semiconductor structures. Background Art

[0002] Semiconductor devices have applications in many electronic devices, including communication devices, automotive electronics, and other technology platforms. With the increasing demand for improved functionality and miniaturization in portable devices such as mobile phones, digital cameras, and laptop computers, there is a need to provide package-on-package semiconductor devices with flexible interconnect geometries compatible with pick-and-place and molding processes while also having minimal package size. Package-on-package stacking technology is being widely used in semiconductor device manufacturing and will play an increasingly important role in the future. Since the interconnection wiring between circuits is shorter, signal propagation speed can be accelerated and noise and cross-talk can be reduced, so package-on-package stacking technology can improve the electrical performance of the device. However, various problems may arise in the package-on-package stacking process and affect the final electrical properties, quality, and yield. Therefore, there are still challenges in improving performance, quality, output, and reliability. Summary of the Invention

[0003] The present disclosure provides a method for forming a semiconductor structure. The method includes the following operations: forming a trench in a substrate; forming a dielectric layer to cover an inner surface of the trench; depositing a bottom conductive layer on the dielectric layer and in the trench at a first temperature of 350°C to 450°C; performing an annealing process on the bottom conductive layer at a second temperature greater than or equal to 470°C; removing a portion of the bottom conductive layer to form a recess on the bottom conductive layer and in the trench; and forming a top conductive layer in the recess.

[0004] In some embodiments, the bottom conductive layer includes titanium nitride (TiN).

[0005] In some embodiments, the top conductive layer includes polysilicon.

[0006] In some embodiments, the second temperature is from 470°C to 650°C.

[0007] In some embodiments, the annealing process is performed by rapid thermal annealing (RTA).

[0008] In some embodiments, during the annealing process, the annealing time is between 5 minutes and 100 minutes.

[0009] In some embodiments, the annealing process is performed under an inert gas atmosphere or a nitrogen atmosphere.

[0010] In some embodiments, the trench has a width of 12 nm to 30 nm.

[0011] In some embodiments, depositing the bottom conductive layer is performed by chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0012] In some embodiments, the method further includes forming a doped region in the substrate before forming the trench in the substrate, wherein after forming the trench in the substrate, the trench penetrates the doped region.

[0013] The present disclosure provides a method for forming a semiconductor structure. The method includes the following operations: forming a first trench and a second trench in a substrate; forming a dielectric layer to cover a first inner surface of the first trench and a second inner surface of the second trench; depositing a titanium nitride layer on the dielectric layer and in the first trench and the second trench at a first temperature of 350°C to 450°C; and performing an annealing process on the titanium nitride layer at a second temperature greater than or equal to 470°C.

[0014] In some embodiments, the first trench has a first top edge, the second trench has a second top edge adjacent to the first top edge, and a distance between the first top edge and the second top edge is 12 nm to 30 nm.

[0015] In some embodiments, the second temperature is from 470°C to 650°C.

[0016] In some embodiments, during the annealing process, the annealing time is between 5 minutes and 100 minutes.

[0017] In some embodiments, the annealing process is performed by rapid thermal annealing.

[0018] In some embodiments, the method further includes the following operations: After performing an annealing process on the titanium nitride layer, removing a portion of the titanium nitride layer to expose the sidewalls and top surface of the dielectric layer; forming a polysilicon layer on the titanium nitride layer and in the first trench and the second trench; and removing a portion of the polysilicon layer to expose the sidewalls and top surface of the dielectric layer.

[0019] In some embodiments, the method further includes: after removing the portion of the polysilicon layer, forming an insulating capping layer to fill the first trench and the second trench.

[0020] In some embodiments, the method further includes forming a doped region in the substrate before forming the first trench and the second trench in the substrate, wherein after forming the first trench and the second trench in the substrate, the first trench and the second trench penetrate the doped region.

[0021] In some embodiments, the first trench has a first depth greater than a second depth of the second trench.

[0022] In some embodiments, the method further includes forming an isolation structure in the substrate before forming the first trench and the second trench in the substrate, wherein after forming the first trench and the second trench in the substrate, the first trench penetrates into the isolation structure.

[0023] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] A more complete understanding of the present disclosure can be obtained by reading the following detailed description of the embodiments and referring to the accompanying drawings.

[0025] Figures 1 to 9 is a schematic cross-sectional view of an intermediate stage in forming a semiconductor structure according to various embodiments of the present disclosure.

[0026] Figure 10 is a top view of a semiconductor structure according to some embodiments of the present disclosure.

[0027] Figure 11 The resistivity of the titanium nitride layer in Examples 1 to 6 and Comparative Example 1 of the present disclosure is shown.

[0028] Figure 12 The resistivity of the titanium nitride layer in Examples 6 to 8 and Comparative Example 1 of the present disclosure is shown.

[0029] Figure 13 The spatial imbalance of the titanium nitride layers of Examples 6 to 8 and Comparative Examples 1 to 2 in the present disclosure is shown. DETAILED DESCRIPTION

[0030] Reference will now be made in detail to the embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the description to refer to the same or like elements.

[0031] The following embodiments are described and disclosed in detail with reference to the accompanying drawings. For clarity, many practical details will be included in the following description. However, it should be understood that these practical details are not intended to limit the present disclosure. In other words, these practical details are not essential to some embodiments of the present disclosure. Furthermore, to simplify the drawings, some existing structures and components are shown schematically in the drawings.

[0032] It should be understood that although the terms first, second, and third, etc., may be used herein to describe various elements, components, regions, layers, and / or blocks, these elements, components, regions, layers, and / or blocks should not be limited by these terms. These terms are only used to distinguish a single element, component, region, layer, or block from another element, component, region, layer, or block. Therefore, a first element, component, region, layer, or block hereinafter may also be referred to as a second element, component, region, layer, or block without departing from the teachings of this disclosure.

[0033] With the rapid growth of the electronics industry, the development of semiconductor devices has achieved high performance and miniaturization. As the size of semiconductor devices, such as dynamic random access memory (DRAM) devices, decreases, the gate channel length decreases accordingly. As a result, short channel effects may occur. To address such issues, buried-channel array transistor (BCAT) elements have been proposed. The present disclosure provides a method for forming a semiconductor structure. The semiconductor structure includes a bottom conductive layer and a top conductive layer that can serve as a wordline structure for the BCAT. During the manufacturing process, the bottom conductive layer is deposited in the trench at a low temperature of 350°C to 450°C, and then the bottom conductive layer is treated with an annealing process above the deposition temperature to reduce its resistivity. Even if the protrusion between the trenches has a small width and / or the trenches are narrow, wordline wiggling or wordline collapse can be avoided due to the low deposition temperature.

[0034] The present disclosure provides a method of forming a semiconductor structure. Figures 1 to 9 is a schematic cross-sectional view of an intermediate stage in the formation of a semiconductor structure according to various embodiments of the present disclosure. Although the methods disclosed herein are described below using a series of operations or steps, the order in which these operations or steps are presented should not be construed as limiting the present disclosure. For example, certain operations or steps may be performed in a different order and / or concurrently with other steps. Furthermore, not all illustrated operations, steps, and / or features must be performed to implement an embodiment of the present disclosure. Furthermore, each operation or step described herein may include multiple sub-steps or actions.

[0035] refer to Figure 1. Receive the substrate 110. In some embodiments, an isolation structure 120 is formed in the substrate 110, and the isolation structure 120 surrounds at least one active area AA of the substrate 110. An active area AA is a protruding portion of the substrate 110. The number of active areas AA is not limited to 1. The number of active areas AA can be adjusted according to design requirements. In some other embodiments, multiple active areas AA protrude from the substrate 110, and each active area AA is surrounded by the isolation structure 120. In some embodiments, the substrate 110 is a silicon substrate. Alternatively, the substrate 110 may include other elemental semiconductors, such as germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof. In some embodiments, the isolation structure 120 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials. In some embodiments, the isolation structure 120 is a shallow trench isolation (STI) structure. The isolation structure 120 can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), or the like.

[0036] like Figure 2 As shown, a hard mask layer 210 is formed on the substrate 110. In some embodiments, the hard mask layer 210 has a single-layer structure or a multi-layer structure. In some embodiments, the hard mask layer 210 is an insulating oxide layer, such as a silicon oxide layer. In some embodiments, the hard mask layer 210 includes a pad oxide layer on the substrate 110 and a nitride layer on the pad oxide layer. The thickness of the nitride layer can be greater than the thickness of the pad oxide layer.

[0037] Now please note Figure 3 A doped region 310 is formed in the active region AA of the substrate 110. In some embodiments, the active region AA is doped with an N-type dopant, such as phosphorus (P), arsenic (As), or antimony (Sb). In some other embodiments, the active region AA is doped with a P-type dopant, such as boron (B) or indium (In). In some embodiments, the doping concentration of the active region AA is higher than the doping concentration of the substrate 110.

[0038] Please refer to Figure 4, multiple trenches are formed in the substrate 110. The trenches include a first trench T1, a second trench T2, a third trench T3, and a fourth trench T4. The number of trenches is not limited to four and can be adjusted as required by the design. The first trench T1 and the second trench T2 penetrate the doped region 310. The third trench T3 and the fourth trench T4 penetrate the isolation structure 120. In some other embodiments, after the trenches are formed in the substrate 110, the doped region 310 is formed in the substrate 110 having the trenches.

[0039] In some embodiments, the formation of the groove includes the following operations. A hard mask layer 210 is formed on the substrate 110. A photoresist layer (not shown) is then formed on the hard mask layer 210. The photoresist layer is patterned to have openings that expose multiple portions of the hard mask layer 210. An etching process is further performed to remove the hard mask layer 210 and multiple portions of the active area AA that are not protected by the patterned photoresist layer through the openings of the patterned photoresist layer, thereby forming a groove in the active area AA of the substrate 110. The patterned photoresist layer can be removed after the groove is formed. In some embodiments, such as Figure 4 As shown, the hard mask layer 210 still remains on the substrate 110 after the trenches are formed.

[0040] The first trench T1, the second trench T2, the third trench T3, and the fourth trench T4 can be formed by performing an etching process. The etching process may include a selective wet etching process or a selective dry etching process. In some embodiments, the wet etching solution includes tetramethylammonium hydroxide (TMAH), HF / HNO3 / CH3COOH solution, or other suitable solutions. In some other embodiments, the wet etching solution includes NH4OH, KOH, HF, TMAH, other suitable wet etching solutions, or combinations thereof. In some other embodiments, the dry etching process includes a biased plasma etching process using a chlorine-based compound. Other dry etchant gases include CF4, NF3, SF6, or combinations thereof.

[0041] In some embodiments, the trenches each have a width of 12 nm to 30 nm, such as 12 nm, 14 nm, 16 nm, 18 nm, 20 nm, 22 nm, 24 nm, 26 nm, 28 nm, or 30 nm. For example, the first trench T1 has a first width W1 of 12 nm to 30 nm. For example, the second trench T2 has a second width W2 of 12 nm to 30 nm. In some embodiments, the first trench T1 has a first top edge, the second trench T2 has a second top edge adjacent to the first top edge, and a distance D1 between the first top edge and the second top edge is 12 nm to 30 nm, such as 12 nm, 14 nm, 16 nm, 18 nm, 20 nm, 22 nm, 24 nm, 26 nm, 28 nm, or 30 nm. In some embodiments, the first trench T1 has a first top edge, the third trench T3 has a third top edge adjacent to the first top edge, and a distance D2 between the first and third top edges is 12 nm to 30 nm, e.g., 12 nm, 14 nm, 16 nm, 18 nm, 20 nm, 22 nm, 24 nm, 26 nm, 28 nm, or 30 nm. Similarly, in some embodiments, the second trench T2 has a second top edge, the fourth trench T4 has a fourth top edge adjacent to the second top edge, and a distance D3 between the second and fourth top edges is 12 nm to 30 nm, e.g., 12 nm, 14 nm, 16 nm, 18 nm, 20 nm, 22 nm, 24 nm, 26 nm, 28 nm, or 30 nm.

[0042] In some embodiments, as Figure 4 As shown, the third depth d3 of the third trench T3 and / or the fourth depth d4 of the fourth trench T4 are greater than the first depth d1 of the first trench T1 and / or the second depth d2 of the second trench T2, but the present invention is not limited thereto. In some other embodiments, the third depth d3 of the third trench T3 and / or the fourth depth d4 of the fourth trench T4 are similar to the first depth d1 of the first trench T1 and / or the second depth d2 of the second trench T2.

[0043] refer to Figure 5A dielectric layer 510 is formed to cover the first inner surface S1 of the first trench T1, the second inner surface S2 of the second trench T2, the third inner surface S3 of the third trench T3, and the fourth inner surface S4 of the fourth trench T4. In some embodiments, the dielectric layer 510 conformally covers the first inner surface S1, the second inner surface S2, the third inner surface S3, and the fourth inner surface S4. In some embodiments, the dielectric layer 510 includes one or more layers of dielectric material, such as silicon oxide, titanium nitride, silicon nitride, or a high-k dielectric material, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include hafnium oxide (HfO2), hafnium silicate (HfSiO4), HfSiON, HfTaO, HfTiO, HfZrO, lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium oxide (ZrO2), zirconium silicate (ZrSiO4), aluminum oxide (Al2O3), titanium oxide, a hafnium oxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, and / or combinations thereof. In some embodiments, dielectric layer 510 is formed by atomic layer deposition (ALD) or atomic layer chemical vapor deposition (ALCVD).

[0044] like Figure 6 As shown, a bottom conductive layer 610 is deposited on the dielectric layer 510 and in the first trench T1, the second trench T2, the third trench T3, and the fourth trench T4. In some embodiments, the bottom conductive layer 610 is deposited at a first temperature between 350°C and 450°C, such as 350°C, 360°C, 370°C, 380°C, 390°C, 400°C, 410°C, 420°C, 430°C, 440°C, or 450°C. When the deposition temperature falls within this temperature range, wordline swing or wordline collapse can be avoided. If the deposition temperature is below 350°C, the gas used for deposition may not fully react. If the deposition temperature is above 450°C, wordline swing or wordline collapse may occur. In some embodiments, the bottom conductive layer 610 is deposited by chemical vapor deposition (CVD) or physical vapor deposition (PVD). In some embodiments, the bottom conductive layer 610 includes titanium nitride. In some embodiments, the bottom conductive layer 610 is a titanium nitride layer. It is noteworthy that even if the portion between the trenches has a small width (e.g., 12 nm to 30 nm) and / or the trenches have a small width (e.g., 12 nm to 30 nm), wordline swing or wordline collapse can be avoided by using a low deposition temperature. The low deposition temperature improves structural stability.

[0045] Please still refer to Figure 6, an annealing process AP is performed on the bottom conductive layer 610 at a second temperature greater than or equal to 470°C. The annealing process AP can reduce the resistivity of the bottom conductive layer 610, thereby improving its electrical performance. In some embodiments, the second temperature is 470°C to 650°C, for example, 470°C, 480°C, 490°C, 500°C, 510°C, 520°C, 530°C, 540°C, 550°C, 560°C, 570°C, 580°C, 590°C, 600°C, 610°C, 620°C, 630°C, 640°C or 650°C. If the annealing temperature is lower than 470°C, the resistivity of the bottom conductive layer 610 may not be effectively reduced. If the annealing temperature is too high, the performance of the overall structure may be affected by overheating. In some embodiments, during the annealing process AP, the annealing time is 5 minutes to 100 minutes, for example, 5 minutes, 10 minutes, 15 minutes, 20 minutes, 25 minutes, 30 minutes, 35 minutes, 40 minutes, 45 minutes, 50 minutes, 55 minutes, 60 minutes, 65 minutes, 70 minutes, 75 minutes, 80 minutes, 85 minutes, 90 minutes, 95 minutes, or 100 minutes. In some embodiments, the annealing process AP is performed by rapid thermal annealing at a temperature exceeding 1,000° C. for no more than a few seconds. In some embodiments, the annealing process AP is performed in an inert gas atmosphere or a nitrogen atmosphere to prevent oxidation of the bottom conductive layer 610.

[0046] Now please note Figure 7 Portions of the bottom conductive layer 610 are removed to form recesses R on the bottom conductive layer 610 and in the first, second, third, and fourth trenches T1, T2, T3, and T4, respectively. In some embodiments, portions of the bottom conductive layer 610 are removed to expose the sidewalls SW and top surface TS of the dielectric layer 510.

[0047] Please refer to Figure 8 A top conductive layer 810 is formed in the groove R and on the bottom conductive layer 610. In some embodiments, the top conductive layer 810 includes polysilicon. In some embodiments, the top conductive layer 810 is a polysilicon layer. Figure 8 As shown, the top conductive layer 810 is in direct contact with the bottom conductive layer 610. In some embodiments, the top conductive layer 810 is formed by the following operations. A conductive layer is formed on the bottom conductive layer 610, in the first trench T1, the second trench T2, the third trench T3, and the fourth trench T4, and on the dielectric layer 510. In some embodiments, the conductive layer includes polysilicon. In some embodiments, the conductive layer is a polysilicon layer. Portions of the conductive layer are removed to expose the sidewalls SW and the top surface TS of the dielectric layer 510. Thus, the remaining portions of the conductive layer are the top conductive layer 810.

[0048] refer to Figure 9An insulating capping layer 910 is formed to fill the first trench T1, the second trench T2, the third trench T3, and the fourth trench T4. Thus, a semiconductor structure 900 is formed. In some embodiments, as Figure 9 As shown, the insulating cap layer 910 covers the top surface TS of the dielectric layer 510. In some other embodiments, a portion of the insulating cap layer 910 is removed by, for example, chemical mechanical polishing (CMP) and / or etch-back methods to expose the top surface TS of the dielectric layer 510. In some embodiments, the insulating cap layer 910 includes an insulating nitride, such as silicon nitride.

[0049] The semiconductor structure 900 includes a first word line structure WL1 and a second word line structure WL2, wherein the first word line structure WL1 and the second word line structure WL2 respectively include a portion of the bottom conductive layer 610 and a portion of the top conductive layer 810. Figure 9 , the doped region 310 includes a plurality of first source / drain regions and a second source / drain region. In some examples, the second source / drain region between the first bit line structure WL1 and the second bit line structure WL2 may be a source region of a transistor, and the first source / drain region disposed on opposite sides of each of the first word line structure WL1 and the second word line structure WL2 may be a drain region of the transistor. In some embodiments, the semiconductor structure 900 further includes a capacitor (not shown) electrically connected to the first source / drain region and a bit line contact (not shown) electrically connected to the second source / drain region. In addition, the word line structures in the third trench T3 and the fourth trench T4 may serve as passing word lines (PWLs).

[0050] Please refer to Figure 10 , Figure 10 is a top view of a semiconductor structure according to some embodiments of the present disclosure. In some embodiments, Figure 8 yes Figure 10 The semiconductor structure is a cross-sectional view along the section line AA. In order to clearly show the relative positions between the various components, Figure 10 Some elements are omitted. In some embodiments, Figure 10 The semiconductor structure shown is an array transistor, such as a BCAT. Figure 8 and Figure 10 As shown, the active area AA is surrounded by the isolation structure 120 and isolated from each other by the isolation structure 120. A portion of the active area AA is disposed between the first word line structure WL1 and the second word line structure WL2. In addition, the first word line structure WL1 and the second word line structure WL2 are embedded in the active area AA and the isolation structure 120, respectively.

[0051] The features of the present disclosure will be described in more detail below with reference to experiments. Although the following experiments are described, the materials, their amounts and ratios, process details, process steps, etc. can be appropriately changed without exceeding the scope of the present disclosure. Therefore, the present disclosure should not be interpreted restrictively by the following experiments.

[0052] Experiment 1: Measurement of the resistivity of titanium nitride layer

[0053] The methods for forming the titanium nitride layer in Examples 1-4 and Examples 6-8 each include depositing a titanium nitride layer in a trench and then annealing the titanium nitride layer. The methods for forming the titanium nitride layer in Example 5 and Comparative Example 1 each include depositing a titanium nitride layer in a trench. The experimental conditions for Examples 1-8 and Comparative Example 1 are shown in Table 1 below.

[0054] Table 1

[0055] Deposition temperature (℃) Annealing temperature (℃) Annealing time (minutes) Example 1 380 475 20 Example 2 380 475 60 Example 3 380 525 20 Example 4 380 525 60 Example 5 420 N / A N / A Example 6 420 525 20 Example 7 420 525 60 Example 8 420 525 90 Comparative Example 1 475 N / A N / A

[0056] Figure 11 The resistivity of the titanium nitride layer in Examples 1 to 6 and Comparative Example 1 of the present disclosure is shown. As can be seen from Examples 1 to 4, the resistivity of the titanium nitride layer can be reduced by increasing the annealing temperature and / or increasing the annealing time. As can be seen from Examples 1 to 6, the resistivity of the titanium nitride layer can be reduced by increasing the deposition temperature. As can be seen from Example 6 and Comparative Example 1, although the deposition temperature of Example 6 is lower than that of Comparative Example 1, due to the annealing process, the titanium nitride layer of Example 6 can have a resistivity similar to that of the titanium nitride layer of Comparative Example 1.

[0057] Figure 12 The resistivity of the titanium nitride layer in Examples 6 to 8 and Comparative Example 1 of the present disclosure is shown. It can be seen from Examples 6 to 8 that the resistivity of the titanium nitride layer can be reduced by increasing the annealing time. It can be seen from Example 8 and Comparative Example 1 that although the deposition temperature of Example 8 is lower than that of Comparative Example 1, the resistivity of the titanium nitride layer in Example 8 can be lower than that of the titanium nitride layer in Comparative Example 1 due to the sufficient annealing time.

[0058] Experiment 2: Measurement of spatial imbalance of titanium nitride layer

[0059] Figure 13The spatial imbalance of the titanium nitride layer of Examples 6 to 8 and Comparative Examples 1 to 2 in the present disclosure is shown. In Comparative Example 2, the spatial imbalance of the structure having the groove before the titanium nitride layer was deposited in the groove was observed by scanning electron microscope (SEM). In Comparative Example 1 and Examples 6 to 8, the spatial imbalance of the structure having the groove filled with the titanium nitride layer was observed by SEM. It can be seen from Comparative Example 1 and Examples 6 to 8 that the titanium nitride layer of Examples 6 to 8 has a lower spatial imbalance, which is similar to the spatial imbalance of Comparative Example 2. This experimental result indicates that depositing the titanium nitride layer at a low temperature and performing an annealing process on the titanium nitride layer can effectively improve the word line swing.

[0060] In summary, the present disclosure provides a method for forming a semiconductor structure comprising a bottom conductive layer and a top conductive layer that can serve as a wordline structure. The method comprises a simple process flow. The method includes depositing the bottom conductive layer in a trench at a relatively low deposition temperature and then annealing the bottom conductive layer at an annealing temperature higher than the deposition temperature. The bottom conductive layer can have a low resistivity and can avoid wordline swing or wordline collapse issues.

[0061] Although the present disclosure has been described in considerable detail with reference to certain embodiments, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

[0062] It will be apparent to those skilled in the art that various modifications and variations may be made to the structure of the present disclosure without departing from the scope or spirit of the present disclosure. In view of the foregoing, the present disclosure is intended to cover modifications and variations of the present disclosure that fall within the appended claims.

[0063]

Explanation of symbols

[0064] 110:Substrate

[0065] 120: Isolation Structure

[0066] 210: Hard mask layer

[0067] 310: doped region

[0068] 510: dielectric layer

[0069] 610: bottom conductive layer

[0070] 810: top conductive layer

[0071] 900:Semiconductor Structure

[0072] 910: Insulation covering

[0073] A:Hatch line

[0074] AA: Active Area

[0075] AP: Annealing process

[0076] D1, D2, D3: distance

[0077] d1: first depth

[0078] d2: second depth

[0079] d3: third depth

[0080] d4: fourth depth

[0081] R: Groove

[0082] S1: first inner surface

[0083] S2: Second inner surface

[0084] S3: third inner surface

[0085] S4: fourth inner surface

[0086] SW: Sidewall

[0087] T1: First groove

[0088] T2: Second groove

[0089] T3: The third groove

[0090] T4: The fourth groove

[0091] TS: Top surface

[0092] W1: first width

[0093] W2: Second width

[0094] WL1: first word line structure

[0095] WL2: second word line structure.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: forming a groove in a substrate; forming a dielectric layer to cover the inner surface of the trench; Depositing a bottom conductive layer on the dielectric layer and in the trench at a first temperature of 350° C. to 450° C.; performing an annealing process on the bottom conductive layer at a second temperature greater than or equal to 470° C.; removing a portion of the bottom conductive layer to form a recess on the bottom conductive layer and in the trench; as well as A top conductive layer is formed in the groove. The method of claim 1 , wherein the bottom conductive layer comprises titanium nitride. The method of claim 1 , wherein the top conductive layer comprises polysilicon. The method according to claim 1 , wherein the second temperature is 470° C. to 650° C. The method according to claim 1 , wherein the annealing process is performed by rapid thermal annealing. The method according to claim 1 , wherein during the annealing process, an annealing time ranges from 5 minutes to 100 minutes. The method according to claim 1 , wherein the annealing process is performed under an inert gas atmosphere or a nitrogen atmosphere. The method according to claim 1 , wherein the trench has a width of 12 nm to 30 nm.

9. The method of claim 1, wherein depositing the bottom conductive layer is performed by chemical vapor deposition or physical vapor deposition.

10. The method according to claim 1, wherein: Also includes: Before forming the trench in the substrate, a doped region is formed in the substrate, wherein after forming the trench in the substrate, the trench penetrates the doped region.

11. A method for forming a semiconductor structure, characterized in that: include: forming a first trench and a second trench in a substrate; forming a dielectric layer to cover a first inner surface of the first trench and a second inner surface of the second trench; Depositing a titanium nitride layer on the dielectric layer and in the first trench and the second trench at a first temperature of 350° C. to 450° C.; as well as An annealing process is performed on the titanium nitride layer at a second temperature greater than or equal to 470° C. 12 . The method of claim 11 , wherein the first trench has a first top edge, the second trench has a second top edge adjacent to the first top edge, and a distance between the first top edge and the second top edge is 12 nm to 30 nm.

13. The method according to claim 11, wherein the second temperature is 470°C to 650°C. 14 . The method according to claim 11 , wherein during the annealing process, an annealing time ranges from 5 minutes to 100 minutes. The method according to claim 11 , wherein the annealing process is performed by rapid thermal annealing.

16. The method according to claim 11, wherein: Also includes: After performing the annealing process on the titanium nitride layer, removing a portion of the titanium nitride layer to expose the sidewall and top surface of the dielectric layer; forming a polysilicon layer on the titanium nitride layer and in the first trench and the second trench; as well as A portion of the polysilicon layer is removed to expose the sidewall and the top surface of the dielectric layer.

17. The method according to claim 16, wherein: Also includes: After removing the portion of the polysilicon layer, an insulating capping layer is formed to fill the first trench and the second trench.

18. The method according to claim 11, wherein: Also includes: Before forming the first trench and the second trench in the substrate, a doped region is formed in the substrate, wherein after forming the first trench and the second trench in the substrate, the first trench and the second trench penetrate the doped region. The method according to claim 11 , wherein a first depth of the first trench is greater than a second depth of the second trench.

20. The method according to claim 19, wherein: Also includes: An isolation structure is formed in the substrate before forming the first trench and the second trench in the substrate, wherein after forming the first trench and the second trench in the substrate, the first trench penetrates into the isolation structure.

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