Efuse unit structure and memory

Abstract

The invention relates to an efuse unit structure and a memory, the efuse unit structure comprises a JFET tube, the drain electrode and the grid electrode of the JFET tube are connected with power supply voltage; and the fuse wire is provided with a first end and a second end opposite to the first end, the second end is grounded, and the source electrode of the JFET tube is electrically connected with the first end of the fuse wire. The width of the depletion layer in the JFET tube is controlled by controlling the voltage between the grid electrode and the drain electrode of the JFET tube, correspondingly, the value of the current passing through the JFET tube can be controlled by controlling the width of the depletion layer in the JFET tube, so that the value of the current passing through the fuse wire can meet the performance requirement of fusing of the fuse wire, and the reliability of the fuse wire is improved. According to the efuse unit structure, the read performance of the efuse unit structure is further improved, meanwhile, by arranging the JFET in the efuse unit structure, compared with the scheme that an MOS transistor is arranged in an existing efuse unit structure, the effect of saving the area is achieved, and the miniaturization of the efuse unit structure is further improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to an efuse unit structure and a memory. Background Art

[0002] The efuse (Electrically Programmable Fuse) technology is a one-time programmable storage technology widely used inside chips. It can be used to record chip configuration information or to repair unavoidable bad components in integrated circuits due to semiconductor processes. When a chip fails, the efuse circuit in the chip can repair the chip defects. When the chip runs incorrectly, the efuse circuit can automatically correct the chip, thereby improving the chip yield.

[0003] The characteristic of the efuse circuit is that the default stored bit is logic "0", and the required bit can be written from logic "0" to logic "1" through programming. Once written to logic "1", it can no longer be written to logic "0", but the bit that has not been written to logic "0" can still be written to logic "1" through programming.

[0004] The existing efuse technology controls the current in the circuit to control whether the fuse is blown to complete the programming operation of writing from logic "0" to logic "1".

[0005] Currently, the performance of efuse devices still needs to be improved. Summary of the invention

[0006] The problem solved by the embodiments of the present invention is to provide an efuse unit structure and a memory to improve the performance of the efuse unit structure.

[0007] To solve the above problems, an embodiment of the present invention provides an efuse unit structure, including: a JFET tube, wherein the drain and the gate of the JFET tube are connected to the power supply voltage; a fuse, wherein the fuse has a first end and a second end opposite to the first end, the second end is grounded, and the source of the JFET tube is electrically connected to the first end of the fuse.

[0008] Optionally, the JFET tube includes: a first doping region, the first doping region having a first surface and a second surface opposite to the first surface; a second doping region, respectively located in the first surface of the first doping region and in the second surface of the first doping region, the doping type of the second doping region is different from the doping type of the first doping region; a first contact electrode, electrically connected to the third end of the first doping region, and the first contact electrode is used as a source; a second contact electrode, electrically connected to the fourth end of the first doping region, the fourth end is opposite to the third end, and the second contact electrode is used as a drain; a third contact electrode, electrically connected to the second doping region, and the third contact electrode is used as a gate.

[0009] Optionally, the doping type of the first doping region is N-type doping, and the doping type of the second doping region is P-type doping; or, the doping type of the first doping region is P-type doping, and the doping type of the second doping region is N-type doping.

[0010] Optionally, when the doping type of the first doping region is N-type doping, the doping type of the second doping region is P-type doping, and the doping concentration of the P-type doping is greater than the doping concentration of the N-type doping.

[0011] Optionally, materials of the first contact electrode, the second contact electrode and the third contact electrode include one or both of aluminum and copper.

[0012] Optionally, when the voltage difference between the drain and the gate of the JFET tube is equal to 0V, the fuse is in a blown state.

[0013] Optionally, when the fuse is in a blown state, a resistance of the fuse is greater than 3000Ω.

[0014] Optionally, when the voltage difference between the drain and the gate of the JFET tube is not equal to 0V, the fuse is in an on state.

[0015] Optionally, when the fuse is in an on state, a resistance range of the fuse is 10 kΩ to 1 MΩ.

[0016] Optionally, the material of the fuse includes polysilicon.

[0017] Correspondingly, an embodiment of the present invention also provides a memory, including: providing the efuse unit structure provided in an embodiment of the present invention; a control circuit, the control circuit electrically connects the drain and gate of the JFET tube and provides a power supply voltage to the drain and gate of the JFET tube.

[0018] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0019] The efuse unit structure provided by the embodiment of the present invention is provided with a JFET tube. The width of the depletion layer in the JFET tube is controlled by controlling the voltage between the gate and the drain of the JFET tube. Accordingly, the current value passing through the JFET tube can be controlled by controlling the width of the depletion layer in the JFET tube, so that the current value flowing through the fuse can meet the performance requirements of fuse blowing, thereby improving the reading performance of the efuse unit structure. At the same time, by arranging the JFET tube in the efuse unit structure, compared with the solution of arranging the MOS tube in the existing efuse unit structure, it has the effect of saving area, and further improves the miniaturization of the efuse unit structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a circuit diagram corresponding to an efuse unit structure;

[0021] Figure 2 1 is a schematic diagram of an efuse unit structure circuit according to an embodiment of the efuse unit structure of the present invention;

[0022] Figure 3 The JFET tube in the efuse unit structure of the present invention is at V GS The structural diagram when it is 0V;

[0023] Figure 4 The JFET tube in the efuse unit structure of the present invention is at V GS Structural diagram when it is not 0V. DETAILED DESCRIPTION

[0024] At present, the performance of the efuse unit structure still needs to be improved. This paper analyzes the reasons why its performance needs to be improved by combining an efuse unit structure.

[0025] Figure 1 It is a circuit schematic diagram corresponding to an efuse unit structure.

[0026] refer to Figure 1 The efuse unit structure includes a MOS tube T and a fuse 1, a drain D of the MOS tube T is connected to one end of the fuse 1, a source S of the MOS tube T is connected to the ground terminal GND, and the other end of the fuse 1 is connected to the power supply VDD.

[0027] After research, it was found that the efuse unit structure belongs to a one-time programmable memory. Before executing the programming operation, the fuse 1 in the efuse unit structure has not been blown, that is, the fuse is in the on state. At this time, the input voltage of the gate G of the MOS tube T is less than or equal to 0V, the MOS tube T is not turned on, and the resistance value of the fuse 1 is small. When performing a programming operation, under normal circumstances, the input voltage of the gate G of the MOS tube T is stable and provides a large voltage, which can make the fuse 1 flow through a large fusing current, so that the fuse 1 is fully blown by the large fusing current, and the fusing effect of the fuse 1 is good. At this time, the resistance of the fuse 1 is very large, for example, compared with the fuse that is turned on, the resistance of the fuse 1 is infinite; however, when performing a programming operation, due to factors such as the unstable input voltage of the gate G of the MOS tube T or the short pulse time of the input voltage of the gate G of the MOS tube T, it is easy to cause the fusing current flowing through the fuse 1 to be small, and the fuse 1 is not completely blown, so that the fuse 1 is not fully blown, resulting in a phenomenon that the fuse 1 is not fully blown, resulting in a small resistance value of the fuse 1, for example: only 100 to 1000 times the resistance value of the fuse 1 when it is turned on. Compared with the case where the resistance value is infinite, the resistance value of the fuse 1 at this time is small, and when reading data, there is a leakage current passing through the fuse 1, which leads to the risk of reading failure of the efuse unit structure.

[0028] In order to solve the above technical problems, an embodiment of the present invention provides an efuse unit structure, including: a JFET tube, the drain and the gate of the JFET tube are connected to the power supply voltage; a fuse, the fuse having a first end and a second end opposite to the first end, the second end is grounded, and the source of the JFET tube is electrically connected to the first end of the fuse.

[0029] The efuse unit structure provided by the embodiment of the present invention is provided with a JFET (Junction Field-Effect Transistor) tube. The width of the depletion layer in the JFET tube is controlled by controlling the voltage between the gate and the drain of the JFET tube. Accordingly, the current value passing through the JFET tube can be controlled by controlling the width of the depletion layer in the JFET tube, so that the current value flowing through the fuse can meet the performance requirements of the fuse blowing, thereby reducing the probability of the fuse not blowing or not completely blowing, thereby improving the stability of the programming operation of the efuse unit structure, and improving the success probability of reading the efuse unit structure. At the same time, by setting the JFET tube in the efuse unit structure, compared with the solution of setting the MOS tube in the existing efuse unit structure, it has the effect of saving area, and further improves the miniaturization of the efuse unit structure.

[0030] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0031] Figure 2 It is a schematic diagram of the circuit structure of an efuse unit structure according to an embodiment of the present invention; Figure 3 The JFET tube in the efuse unit structure of the present invention is at V GS The structural diagram when it is 0V; Figure 4 The JFET tube in the efuse unit structure of the present invention is at V GS Structural diagram when it is not 0V.

[0032] The efuse unit structure includes: a JFET (Junction Field-Effect Transistor) tube 130, wherein the drain and the gate of the JFET tube 130 are connected to a power supply voltage; a fuse 120, wherein the fuse 120 has a first end and a second end opposite to the first end, the second end is grounded, and the source of the JFET tube 130 is electrically connected to the first end of the fuse 120.

[0033] It should be noted that a JFET tube 130 is set in the efuse unit structure, and the width of the depletion layer 112 in the JFET tube 130 is controlled by controlling the voltage between the gate and the drain of the JFET tube 130. Accordingly, the width of the channel in the JFET tube 130 can be controlled by controlling the width of the depletion layer 112 in the JFET tube 130, thereby controlling the current value passing through the JFET tube 130, so that the current value flowing through the fuse 120 can meet the performance requirements of the fuse 120 being blown, thereby improving the reading performance of the efuse unit structure. At the same time, by setting the JFET tube 130 in the efuse unit structure, compared with the solution of setting a MOS tube in the existing efuse unit structure, it has the effect of saving area, and further improves the miniaturization of the efuse unit structure.

[0034] Specifically, the drain and gate of the JFET tube 130 are connected to the power supply voltage, and the power supply voltage can control the voltage value between the drain and gate of the JFET tube 130, which means that the JFET tube 130 can control the current value flowing through the fuse 120 in the efuse unit structure. When the current value reaches the current value at which the fuse 120 blows, the fuse 120 blows, and the resistance in the efuse unit structure is regarded as infinite. At this time, the efuse unit structure completes a programming operation from logic "0" to logic "1". When the current value does not reach the current value at which the fuse 120 blows, the fuse 120 is not completely blown, but the resistance value of the fuse 120 itself will change with the change of the current value, thereby enabling the JFET tube 130 to achieve the effect of regulating the resistance value range of the fuse 120 in the efuse unit structure.

[0035] In this embodiment, the JFET tube 130 includes: a first doping region 111, the first doping region 111 has a first surface 170 and a second surface 171 opposite to the first surface 170, a second doping region 110, respectively located in the first surface 170 of the first doping region 111 and in the second surface 171 of the first doping region 111, and the doping type of the second doping region 110 is different from the doping type of the first doping region 111.

[0036] Specifically, the first doped region 111 is used as a conductive channel of the JFET tube 130 .

[0037] The doping type of the first doping region 111 determines the channel type of the JFET tube 130 .

[0038] As an example, the doping type of the first doping region 111 is N-type doping, and the doping type of the second doping region 110 is P-type doping.

[0039] That is to say, the channel type of the JFET tube 130 is an N-type channel.

[0040] In other embodiments, the doping type of the first doping region 111 is P-type doping, and the doping type of the second doping region 110 is N-type doping, that is, the channel type of the JFET tube 130 is a P-type channel.

[0041] It should be noted that, by forming the second doping region 110 in the first surface 170 of the first doping region 111 and in the second surface 171 of the first doping region 111, and the doping type of the second doping region 110 is different from the doping type of the first doping region 111, two PN junctions can be formed in the JFET tube 130, that is, a depletion layer 112 (i.e., a space charge region) will be generated between the interface between the first doping region 111 and the second doping region 110. Since two PN junctions can be formed in the JFET tube 130, that is, two depletion layers 112 are provided in the JFET tube 130.

[0042] It should also be noted that by controlling the voltage between the gate and drain of the JFET tube 130, the width of the depletion layer 112 in the JFET tube 130 is controlled, thereby controlling the width of the channel between the depletion layer 112, and further controlling the current value in the JFET tube 130.

[0043] Specifically, by setting the second doping region 110 in the first surface 170 and the second surface 171 of the first doping region 111, the subsequently formed third contact electrode can directly contact the second doping region 110, so that the third contact electrode can act as a gate to control the movement of negative charges in the second doping region 110 toward the first doping region 111.

[0044] In this embodiment, when the doping type of the first doping region 111 is N-type doping, the doping type of the second doping region 110 is P-type doping, and the doping concentration of the P-type doping is greater than the doping concentration of the N-type doping.

[0045] In this embodiment, the JFET tube 130 also includes: a first contact electrode (not shown), which is electrically connected to the third end 117 of the first doping region 111, and the first contact electrode is used as a source; a second contact electrode (not shown), which is electrically connected to the fourth end 116 of the first doping region 111, the fourth end 116 is opposite to the third end 117, and the second contact electrode is used as a drain; a third contact electrode (not shown), which is electrically connected to the second doping region 110, and the third contact electrode is used as a gate.

[0046] It should be noted that the drain and the gate of the JFET tube 130 are connected to the power supply voltage, which means that the third contact electrode and the second contact electrode are electrically connected to the power supply voltage.

[0047] It should also be noted that when the efuse unit structure is in a working state, the drain and source of the JFET tube 130 are also connected to the power supply voltage, which means that the first contact electrode and the second contact electrode are electrically connected to the power supply voltage, so that the conductive channel between the drain and the source of the JFET tube 130 generates current. Correspondingly, the magnitude of the current passing through the conductive channel can be controlled by controlling the voltage value between the drain and the gate.

[0048] It should be particularly noted that the power supply voltage electrically connected to the third contact electrode and the second contact electrode, and the power supply voltage electrically connected to the first contact electrode and the second contact electrode are two separate power supply voltages and are not shared.

[0049] In this embodiment, the materials of the first contact electrode, the second contact electrode and the third contact electrode include one or both of aluminum and copper.

[0050] Specifically, aluminum and copper are commonly used conductive materials in contact electrodes, and have low material costs and good conductive properties.

[0051] like Figure 3 As shown, in this embodiment, the voltage difference (V GS ) is equal to 0V, the fuse 120 is in a blown state.

[0052] Specifically, when the voltage difference between the drain and the gate of the JFET tube 130 is equal to 0V, no depletion layer 112 is generated in the JFET tube 130, and the thickness of the depletion layer 112 in the JFET tube 130 is the smallest. Correspondingly, the width of the conductive channel between the depletion layers 112 is maximized. At this time, the current value passing through the JFET tube 130 is the largest, causing the fuse 120 electrically connected to the JFET tube 130 to be blown, and the resistance in the fuse unit structure is regarded as infinite. At this time, the efuse unit structure completes a programming operation from logic "0" to logic "1".

[0053] As an example, when the fuse 120 is in a blown state, the resistance of the fuse 120 is greater than 3000Ω.

[0054] like Figure 4 As shown, in this embodiment, the voltage difference (V GS ) is not equal to 0V, the fuse 120 is in the on state.

[0055] It should be noted that when the voltage difference between the drain and the gate of the JFET tube 130 is not equal to 0V, the thickness of the depletion layer 112 in the JFET tube 130 will increase, and accordingly, the width of the conductive channel between the two depletion layers 112 will become smaller. When the width of the conductive channel becomes smaller, the number of electrons passing through the conductive channel is limited, thereby reducing the current value passing through the JFET tube 130, and accordingly, the fuse 120 is not blown or is not completely blown. Since the resistance value of the fuse 120 itself will change with the change of the current value, the JFET tube 130 can achieve the effect of regulating the resistance value range of the fuse 120 in the efuse unit structure.

[0056] It should also be noted that in different efuse unit structures, the V in the JFET tube 130 can be set according to the maximum current value that different fuses 120 need to blow. GS of size, so that the JFET tube 130 can ensure that all fuses 120 in the efuse unit structure can be blown, thereby improving the stability of the efuse unit structure in the programming operation.

[0057] As an example, when the fuse 120 is in the on state, the resistance range of the fuse 120 should not be too large or too small. If the resistance of the fuse 120 is too large, it is easy to cause the fuse 120 to splash and burn other circuits; if the resistance of the fuse 120 is too small, it is easy to cause the fuse 120 to not be completely blown, resulting in the failure of the efuse unit structure programming. For this reason, when the fuse 120 is in the on state, the resistance range of the fuse 120 is 10kΩ to 1MΩ.

[0058] The efuse unit structure belongs to a one-time programmable memory, and information is stored in the efuse unit structure by whether the fuse 120 is blown by current.

[0059] As an example, the fuse 120 has a first end and a second end opposite to the first end, the second end is grounded, and the source of the JFET 130 is electrically connected to the first end of the fuse 120 .

[0060] The source of the JFET tube 130 is electrically connected to the first end of the fuse 120, so that the free electrons in the conductive channel of the JFET tube 130 can enter the fuse 120, so that the current value flowing through the fuse 120 can meet the performance requirements of the fuse 120 being blown and meet the programming operation of the efuse unit structure.

[0061] In this embodiment, the material of the fuse 120 includes polysilicon.

[0062] It should be noted that polysilicon material is a conductive material. Before the fuse 120 is not blown or is not completely blown, free electrons pass through the fuse 120. In the process of free electrons passing through the fuse 120, the polysilicon material can generate different resistance values ​​according to different current values, so that the JFET tube 130 has the function of adjusting the resistance range of the efuse unit structure. At the same time, polysilicon material is a material that is easy to blow, which reduces the difficulty of the fuse 120 blowing.

[0063] Correspondingly, an embodiment of the present invention also provides a memory, which is used to implement the programming operation of the efuse unit structure, and the memory includes: the efuse unit structure provided by the aforementioned embodiment; a control circuit, which is electrically connected to the drain and gate of the JFET tube and provides a power supply voltage to the drain and gate of the JFET tube.

[0064] It should be noted that, by providing a power supply voltage to the drain and gate of the JFET tube through the control circuit and controlling the voltage between the gate and the drain of the JFET tube, the width of the depletion layer in the JFET tube can be controlled. Accordingly, the width of the depletion layer in the JFET tube can be controlled to control the current value passing through the JFET tube, so that the current value flowing through the fuse can meet the performance requirements of the fuse blowing, reducing the probability of the fuse not blowing or not completely blowing, thereby improving the stability of the programming operation of the efuse unit structure. At the same time, by setting the JFET tube in the efuse unit structure, compared with the solution of setting the MOS tube in the existing efuse unit structure, it has the effect of saving area, and further improves the miniaturization of the efuse unit structure.

[0065] Specifically, the detailed description of the efuse unit structure will not be repeated here, please refer to the above.

[0066] The control circuit is used to provide power supply voltage to the drain and gate of the JFET tube.

[0067] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. An efuse unit structure, characterized in that: include: A JFET tube, wherein the drain and the gate of the JFET tube are connected to a power supply voltage; The fuse has a first end and a second end opposite to the first end, the second end is grounded, and the source of the JFET tube is electrically connected to the first end of the fuse.

2. The efuse unit structure according to claim 1, characterized in that: The JFET tube comprises: a first doping region, wherein the first doping region has a first surface and a second surface opposite to the first surface; second doping regions, respectively located in the first surface of the first doping region and in the second surface of the first doping region, wherein the doping type of the second doping region is different from the doping type of the first doping region; a first contact electrode electrically connected to the third end of the first doped region, and the first contact electrode is used as a source electrode; a second contact electrode electrically connected to a fourth end of the first doped region, the fourth end being opposite to the third end, and the second contact electrode being used as a drain; The third contact electrode is electrically connected to the second doping region, and the third contact electrode is used as a gate.

3. The efuse unit structure according to claim 2, characterized in that: The doping type of the first doping region is N-type doping, and the doping type of the second doping region is P-type doping; Alternatively, the doping type of the first doping region is P-type doping, and the doping type of the second doping region is N-type doping.

4. The efuse unit structure according to claim 3, characterized in that: When the doping type of the first doping region is N-type doping, the doping type of the second doping region is P-type doping, and the doping concentration of the P-type doping is greater than the doping concentration of the N-type doping.

5. The efuse unit structure according to claim 2, characterized in that: The materials of the first contact electrode, the second contact electrode and the third contact electrode all include one or both of aluminum and copper.

6. The efuse unit structure according to claim 1, characterized in that: When the voltage difference between the drain and the gate of the JFET tube is equal to 0V, the fuse is in a blown state.

7. The efuse unit structure according to claim 6, characterized in that: When the fuse is in a blown state, the resistance of the fuse is greater than 3000Ω.

8. The efuse unit structure according to claim 1, characterized in that: When the voltage difference between the drain and the gate of the JFET tube is not equal to 0V, the fuse is in the on state.

9. The efuse unit structure according to claim 8, characterized in that: When the fuse is in an on state, a resistance range of the fuse is 10 kΩ to 1 MΩ.

10. The efuse unit structure according to claim 1, characterized in that: The material of the fuse includes polysilicon.

11. A memory, characterized in that: include: The efuse unit structure according to any one of claims 1 to 10; A control circuit is electrically connected to the drain and gate of the JFET tube and provides a power supply voltage to the drain and gate of the JFET tube.

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