Semiconductor device and manufacturing method thereof, storage system and electronic equipment

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, a storage system and electronic equipment. Wherein the stacked structure comprises a plurality of insulating layers and a plurality of gate function layers which are stacked and alternately arranged, the stacked structure further comprises an array region and a step region located on at least one side of the array region, and the stacked structure is provided with a plurality of steps corresponding to the gate function layers in the step region; the gate isolation structure penetrates through the stacking structure and comprises a first sub-part extending to the step region; the plurality of conductive columns are arranged in the step region and penetrate through the stacked structure; wherein each gate functional layer comprises a gate part at least arranged in the array region, a first connecting part arranged at the step and a second connecting part connected to the side wall of the first sub-part, the second connecting part is connected between the first connecting part and the gate part, and the first connecting part is connected with the corresponding conductive column; according to the semiconductor device, the process difficulty can be simplified, the connection difficulty between the conductive column and the gate part is reduced, and the yield of the semiconductor device is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, a storage system, and an electronic device. Background Art

[0002] With the development of planar flash memory, the production process of semiconductors has made great progress. However, in recent years, the development of planar flash memory has encountered various challenges: physical limits, existing development technology limits, and storage electron density limits. In this context, in order to solve the difficulties encountered by planar flash memory and pursue lower production costs per unit storage unit, various three-dimensional (3D) flash memory structures have emerged, such as 3D NOR (3D non-or) flash memory and 3D NAND (3D non-and) flash memory.

[0003] Among them, 3D NAND memory takes its small size and large capacity as its starting point, and uses a highly integrated design concept of stacking storage units in a three-dimensional mode to produce memory with high storage density per unit area and efficient storage unit performance. It has become the mainstream process for the design and production of emerging memories.

[0004] However, in current memories, there are still major defects in the connection process of the gate layer, which need to be improved. Summary of the invention

[0005] The embodiments of the present application provide a semiconductor device and a manufacturing method thereof, a storage system, and an electronic device, which can reduce the difficulty of connecting a conductive column and a gate portion, simplify the process, and improve the yield rate.

[0006] An embodiment of the present application provides a semiconductor device, comprising:

[0007] A stacked structure, the stacked structure comprising a plurality of insulating layers and a plurality of gate functional layers stacked and alternately arranged, the stacked structure further comprising an array region and a step region located at at least one side of the array region, the stacked structure having a plurality of steps in the step region respectively arranged corresponding to the plurality of gate functional layers;

[0008] a gate isolation structure, which penetrates the stacked structure and includes a first sub-portion extending to the step region;

[0009] A plurality of conductive pillars are disposed in the step area and penetrate the stack structure;

[0010] Among them, each gate functional layer includes at least a gate portion arranged in the array area, a first connecting portion arranged at the step, and a second connecting portion connected to the side wall of the first sub-portion, the second connecting portion is connected between the first connecting portion and the gate portion, and the first connecting portion is connected to the corresponding conductive column.

[0011] In some embodiments of the present application, the gate functional layer further includes an interlayer dielectric portion disposed in the step region, and the interlayer dielectric portion is adjacent to the first connecting portion and the gate portion.

[0012] In some embodiments of the present application, the second connecting portion is adjacent to the first sub-portion and the interlayer dielectric portion.

[0013] In some embodiments of the present application, the first connection portion in one of the gate functional layers and the interlayer dielectric portion in another of the gate functional layers are at least partially overlapped along the stacking direction of the stacking structure.

[0014] In some embodiments of the present application, the thickness of the first connecting portion is greater than the thickness of the interlayer dielectric portion.

[0015] In some embodiments of the present application, the first sub-portion extends along a first direction, the first direction is a direction from the array area to the step area, the plurality of steps include a plurality of step groups arranged along a second direction, the second direction intersects with the first direction, and each of the step groups includes a plurality of steps arranged along the first direction;

[0016] The first sub-portion is disposed on at least one side of the step group, and each of the first connecting portions in the step group is connected to the second connecting portion on the side wall of the first sub-portion.

[0017] In some embodiments of the present application, the semiconductor device further includes a channel structure disposed in the array region and penetrating the stacked structure, and the gate portion is connected between the channel structure and the second connecting portion.

[0018] In some embodiments of the present application, the gate isolation structure further includes a second sub-portion disposed in the array region, and the gate portion is adjacent to the channel structure and the second sub-portion.

[0019] In some embodiments of the present application, the gate isolation structure also includes a third sub-portion arranged between the array area and the step area, the width of the third sub-portion along a first direction perpendicular to the first direction is greater than the width of the first sub-portion along the first direction perpendicular to the first direction, the first direction is the direction from the array area to the step area, and the width of the third sub-portion along the first direction perpendicular to the first direction is greater than the width of the second sub-portion along the first direction perpendicular to the first direction.

[0020] In some embodiments of the present application, a plurality of the first sub-sections are arranged in the step area, a plurality of the second sub-sections are arranged in the array area, a plurality of the third sub-sections are arranged between the array area and the step area, the array area includes a plurality of storage blocks, and one of the third sub-sections is connected between one of the first sub-sections and one of the second sub-sections along the first direction, and is located between two adjacent storage blocks.

[0021] In some embodiments of the present application, the gate isolation structure is in a bead chain shape along an extension direction of the gate isolation structure in a transverse cross section perpendicular to the stacking direction of the stacking structure.

[0022] In some embodiments of the present application, at least one of the conductive pillars passes through a corresponding one of the steps and is connected to the first connecting portion at the corresponding one of the steps.

[0023] According to the above-mentioned purpose of the present application, an embodiment of the present application further provides a method for manufacturing a semiconductor device, which comprises the following steps:

[0024] Forming a plurality of insulating layers and a plurality of interlayer dielectric layers stacked and alternating to form a stacked structure, wherein the stacked structure includes an array region and a step region located at at least one side of the array region, wherein the stacked structure has a plurality of steps formed in the step region corresponding to the plurality of interlayer dielectric layers respectively;

[0025] Replacing the plurality of interlayer dielectric layers with gate functional layers, each of the gate functional layers being formed with at least a gate portion located in the array region, a first connecting portion located at the step, and a second connecting portion connected between the gate portion and the first connecting portion;

[0026] forming a gate isolation structure penetrating the stacked structure, wherein the gate isolation structure is formed with a first sub-portion extending to the step region, and the second connecting portion is connected to a side wall of the first sub-portion;

[0027] A plurality of conductive pillars are formed in the step region and penetrate the stack structure, and the conductive pillars are connected to the corresponding first connecting portions.

[0028] In some embodiments of the present application, the step of forming a plurality of stacked and alternating insulating layers and a plurality of interlayer dielectric layers to form a stacked structure includes:

[0029] A first sacrificial portion located on the interlayer dielectric layer is formed at the step;

[0030] A plurality of gate isolation holes, channel holes and step connection holes are formed through the stack structure, wherein the gate isolation holes are at least located in the array region and the step region, the channel holes are located in the array region, the step connection holes are located in the step region, and at least one of the step connection holes passes through a corresponding step;

[0031] A second sacrificial portion is formed in the gate isolation hole, the channel hole, and the step connection hole.

[0032] In some embodiments of the present application, the step of replacing the plurality of interlayer dielectric layers with gate functional layers further includes:

[0033] The second sacrificial portion in the gate isolation hole is removed, and the plurality of gate isolation holes include a plurality of gate isolation hole groups, wherein the plurality of gate isolation holes arranged along a first direction are formed in the gate isolation hole groups, and the first direction is a direction from the array area to the step area;

[0034] Removing the insulating layer and the interlayer dielectric layer at the inner wall of the gate isolation hole, so that the plurality of gate isolation holes in the gate isolation hole group are connected to form a first gate isolation trench located in the step area and a second gate isolation trench located in the array area;

[0035] The first gate isolation groove is used to replace the portion of the interlayer dielectric layer connected to the first gate isolation groove with the second connecting portion, and the first sacrificial portion and the interlayer dielectric layer at the step are replaced with the connecting portion, and the second gate isolation groove is used to replace the interlayer dielectric layer in the array area with the gate portion.

[0036] In some embodiments of the present application, the step of removing the insulating layer and the interlayer dielectric layer at the inner wall of the gate isolation hole further includes:

[0037] forming a third gate isolation trench located between the array region and the step region, wherein the third gate isolation trench is connected between one of the first gate isolation trenches and one of the second gate isolation trenches along the first direction;

[0038] A third sub-portion is formed in the third gate isolation trench to separate the first gate isolation trench from the second gate isolation trench.

[0039] In some embodiments of the present application, the step of forming a gate isolation structure penetrating the stack structure includes:

[0040] The first sub-portion is formed in the first gate isolation groove, and the second sub-portion is formed in the second gate isolation groove, respectively, to form the gate isolation structure.

[0041] In some embodiments of the present application, the step of forming a plurality of conductive pillars located in the step region and penetrating the stack structure includes:

[0042] removing the second sacrificial portion in the step connection hole;

[0043] The conductive pillars are formed in the step connection holes, and at least one of the conductive pillars passes through a corresponding step and is connected to the first connection portion at the corresponding step.

[0044] According to the above-mentioned purpose of the present application, an embodiment of the present application further provides a storage system, which includes a controller and the semiconductor device, wherein the controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

[0045] According to the above-mentioned purpose of the present application, an embodiment of the present application further provides an electronic device, which includes the storage system.

[0046] The present application provides a semiconductor device and a manufacturing method thereof, a storage system, and an electronic device. By setting a first connecting portion at each step and setting a second connecting portion connected between the first connecting portion and the gate portion on the side wall of the first sub-portion, a conductive column can directly penetrate the stacking structure and connect with the first connecting portion, thereby connecting the conductive column to the gate portion in the corresponding gate functional layer. In the present application, the conductive column is set to penetrate the stacking structure, and there is no need to make the conductive column terminate at a corresponding layer of steps, which can simplify the process difficulty, reduce the connection difficulty between the conductive column and the gate portion, and improve the yield rate of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0048] Figure 1 A schematic diagram of a planar structure of a semiconductor device provided in some embodiments of the present application;

[0049] Figure 2 The semiconductor device provided in some embodiments of the present application is Figure 1 A schematic diagram of a cross-sectional structure along the A-A' line;

[0050] Figure 3 The semiconductor device provided in some embodiments of the present application is Figure 1 A schematic diagram of a cross-sectional structure along the B-B' line;

[0051] Figure 4 A flow chart of a method for manufacturing a semiconductor device provided for some embodiments of the present application;

[0052] Figures 5 to 15 A schematic diagram of the structure of the semiconductor device manufacturing process provided in some embodiments of the present application;

[0053] Fig.16 A schematic diagram of a structure of a storage system provided for some embodiments of the present application;

[0054] Fig.17 A schematic diagram of the structure of an electronic device provided for some embodiments of the present application. DETAILED DESCRIPTION

[0055] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0056] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the various specific processes and material examples provided by the present application, but those of ordinary skill in the art can appreciate the application of other processes and / or the use of other materials.

[0057] The present application embodiment provides a semiconductor device. Figure 1 , Figure 2 as well as Figure 3 The semiconductor device includes a stacked structure 10 , a gate isolation structure 20 , and a plurality of conductive pillars 30 .

[0058] Among them, the stacking structure 10 includes multiple insulating layers 12 and multiple gate functional layers 11 that are stacked and alternately arranged. The stacking structure 10 also includes an array area 101 and a step area 102 located on at least one side of the array area 101. The stacking structure 10 has multiple steps 110 arranged in the step area 102 corresponding to the multiple gate functional layers 11 respectively; the gate isolation structure 20 runs through the stacking structure 10 and includes a first sub-portion 21 extending to the step area 102; multiple conductive pillars 30 are arranged in the step area 102 and run through the stacking structure 10.

[0059] Furthermore, each gate functional layer 11 includes at least a gate portion 111 arranged in the array area 101, a first connecting portion 112 arranged at the step 110, and a second connecting portion 113 connected to the side wall of the first sub-portion 21, the second connecting portion 113 is connected between the first connecting portion 112 and the gate portion 111, and the first connecting portion 112 is connected to the corresponding conductive column 30.

[0060] Continuing from the above, the embodiment of the present application sets a first connecting portion 112 at each step 110, and sets a second connecting portion 113 connected between the first connecting portion 112 and the gate portion 111 on the side wall of the first sub-portion 21, so that the conductive column 30 can directly penetrate the stacking structure 10 and connect with the first connecting portion 112, so that the conductive column 30 can be connected to the gate portion 111 in the corresponding gate functional layer 11. In the embodiment of the present application, the conductive column 30 is set to penetrate the stacking structure 10, and there is no need to make the conductive column 30 end at the corresponding layer of step 110, which can simplify the process difficulty, reduce the connection difficulty between the conductive column 30 and the gate portion 111, and improve the yield rate of the semiconductor device.

[0061] Specifically, please continue to combine Figure 1 , Figure 2 ,as well as Figure 3 In some embodiments, the semiconductor device includes a substrate 50, a stacked structure 10 disposed on the substrate 50, and the stacked structure 10 includes an array region 101, a step region 102 located on at least one side of the array region 101, and a transition region 103 located between the array region 101 and the step region 102.

[0062] The substrate 50 may be a Si substrate, a Ge substrate, a SiGe substrate, SOI (Silicon On Insulator) or GOI (Germanium On Insulator), etc. In other embodiments, the semiconductor substrate may also be a substrate including other element semiconductors or compound semiconductors, such as SiC, or may be a stacked structure, such as Si / SiGe, etc.

[0063] The stacking structure 10 includes multiple gate functional layers 11 and multiple insulating layers 12 stacked and alternately arranged on a substrate 50. Furthermore, the stacking structure 10 also includes multiple steps 110 arranged in the step area 102, and the multiple steps 110 are arranged one-to-one corresponding to the multiple gate functional layers 11. The material of the insulating layer 12 can be silicon oxide.

[0064] The semiconductor device also includes a plurality of channel structures 40 arranged in the array area 101, and the plurality of channel structures 40 penetrate the stacked structure 10, and the channel structure 40 may include a charge storage layer, a tunneling layer and a channel layer in sequence from the outside to the inside; in some embodiments, the material of the tunneling layer may be silicon oxide, the material of the charge storage layer may be silicon nitride or silicon nitride oxide, and the material of the channel layer may be polysilicon.

[0065] In some embodiments, the semiconductor device further includes a plurality of dummy channel structures 41 disposed in the transition region 103 , and the dummy channel structures 41 can be used to buffer stress and improve the reliability of the semiconductor device. The dummy channel structures 41 are not used for electrical connection functions and storage functions.

[0066] In the step region 102 of the semiconductor device, a plurality of steps 110 are arranged in an array along a first direction X and a second direction Y. The first direction X is a direction from the array region 101 to the step region 102 , and the second direction Y intersects the first direction X.

[0067] In some embodiments, the first direction X is perpendicular to the second direction Y.

[0068] The semiconductor device also includes a gate isolation structure 20 that penetrates the stack structure 10 and extends from the array area 101 to the step area 102 along the first direction X; specifically, the gate isolation structure 20 includes a first sub-portion 21 located in the step area 102, a second sub-portion 22 located in the array area 101, and a third sub-portion 23 located in the transition area 103, and the first sub-portion 21, the second sub-portion 22 and the third sub-portion 23 all extend along the first direction X.

[0069] Among them, the width of the third sub-section 23 along the direction perpendicular to the first direction X is greater than the width of the first sub-section 21 along the direction perpendicular to the first direction X, and the width of the third sub-section 23 along the direction perpendicular to the first direction X is greater than the width of the second sub-section 22 along the direction perpendicular to the first direction X; and the gate isolation structure 20 is in a bead chain shape along the extension direction of the gate isolation structure 20 in a transverse cross-section perpendicular to the stacking direction of the stacking structure 10.

[0070] In some embodiments, the array area 101 includes a plurality of storage blocks arranged along the second direction Y, a third sub-section 23 is connected between a first sub-section 21 and a second sub-section 22 along the first direction X, and is located between two adjacent storage blocks; further, the second sub-section 22 not connected to the third sub-section 23 is located in each storage block, and each storage block can be divided into at least two sub-blocks, and the first sub-section 21 not connected to the third sub-section 23 is located between two adjacent rows of steps 110 arranged along the second direction Y.

[0071] In some embodiments, the gate functional layer 11 includes a gate portion 111 located in the array area 101 and the transition area 103, a first connection portion 112 located in the step area 102, and a second connection portion 113 located in the step area 102 and the transition area 103; wherein the gate portion 111 is connected to the channel structure 40 and the side walls of the second sub-portion 22, the first connection portion 112 is located at the step 110, and the second connection portion 113 is connected to the side walls of the first sub-portion 21. In addition, the second connection portion 113 is also connected to the first connection portion 112, and the second connection portion 113 is connected to the gate portion 111 on the side of the step area 102 close to the transition area 103, and then the second connection portion 113 is connected between the gate portion 111 and the first connection portion 112.

[0072] It should be noted that a first connecting portion 112 is provided at each step 110, and the first sub-portion 21 passes through multiple steps 110, and then a second connecting portion 113 corresponding to each step 110 is connected to the side wall of the first sub-portion 21, so that in each gate functional layer 11, the first connecting portion 112 located at the step 110 can be connected to the gate portion 111 in the gate functional layer 11 through the second connecting portion 113, so that the gate portion 111 in each gate functional layer 11 can be conductively connected to the corresponding step 110 through the second connecting portion 113.

[0073] In some embodiments, the multiple steps 110 include multiple step groups arranged along the second direction Y, and each step group includes multiple steps 110 arranged along the first direction X; wherein a first sub-portion 21 is provided on at least one side of the step group, and each first connecting portion 112 in the step group is connected to the second connecting portion 113 at the side wall of the first sub-portion 21.

[0074] Furthermore, the semiconductor device also includes a plurality of conductive pillars 30 arranged in the step area 102, and at least one conductive pillar 30 is correspondingly arranged at each step 110. The conductive pillars 30 at each step 110 penetrate the stacking structure 10 along the stacking direction of the stacking structure 10, and are connected to the first connecting portion 112 at the corresponding step 110, so that each conductive pillar 30 is connected to the gate portion 111 in the corresponding gate functional layer 11 through the first connecting portion 112 and the second connecting portion 113, and then the signal can be selectively transmitted to the gate portion 111 of each gate functional layer 11 through the plurality of conductive pillars 30, and then the signal is transmitted to the corresponding channel structure 40 through the gate portion 111.

[0075] In some embodiments, the gate portion 111, the first connection portion 112, and the second connection portion 113 may all be a stacked structure of a high-K dielectric layer, an adhesive layer, and a metal material layer, and the material of the high-K dielectric layer may include aluminum oxide or zirconium oxide, and the material of the adhesive layer may include titanium nitride. ，The material of the metal material layer may be tungsten, and the material of the conductive pillar 30 may also include tungsten; it should be noted that the high-K dielectric layer may also be omitted. Figure 2 As shown, the first connection portion 112 and the second connection portion 113 are a stacked structure of an adhesive layer and a metal material layer.

[0076] In some embodiments, the gate functional layer 11 also includes an interlayer dielectric portion 114 at least disposed within the step region 102 , the interlayer dielectric portion 114 is adjacent to the first connecting portion 112 and the gate portion 111 , and the second connecting portion 113 is adjacent to the first sub-portion 21 and the interlayer dielectric portion 114 ; wherein the thickness of the first connecting portion 112 is greater than the thickness of the interlayer dielectric portion 114 .

[0077] Among the multiple gate functional layers 11 arranged along the stacking direction of the stacking structure 10, the first connection portion 112 of one gate functional layer 11 at least partially overlaps with the interlayer dielectric portion 114 of another gate functional layer 11 along the stacking direction of the stacking structure 10, that is, the orthographic projection of the first connection portion 112 of one gate functional layer 11 on the substrate 50 is located within the orthographic projection of the interlayer dielectric portion 114 of another gate functional layer 11 on the substrate 50, so that the conductive column 30 at each step 110, in addition to passing through and being connected to the first connection portion 112 at the corresponding step 110, also passes through the interlayer dielectric portion 114 of other gate functional layers 11 in the stacking direction of the stacking structure 10, so that the conductive column 30 at each step 110 is only electrically connected to the gate portion 111 in the gate functional layer 11 corresponding to the step 110.

[0078] It should be noted that in some embodiments, the substrate 50 in the semiconductor device can be removed as needed in subsequent processes, and since the conductive pillars 30 penetrate the stack structure 10, signal input can be achieved from either or both of the opposite sides of the stack structure 10.

[0079] It can be understood that, in the embodiment of the present application, the second connection portion 113 is provided at the side wall of the first sub-portion 21 of the gate isolation structure 20 corresponding to each gate functional layer 11, and the first connection portion 112 connected to the second connection portion 113 is provided at each step 110, and the second connection portion 113 can be extended to the side of the step area 102 close to the array area 101 and connected to the gate portion 111, so that the conductive column 30 can directly penetrate the stacked structure 10 to realize the electrical connection between the conductive column 30 and the gate portion 111 of the corresponding gate functional layer 11, which is relatively better than the related art. In the process, it is necessary to make each conductive column 30 terminate at the corresponding step 110, and the SCT process of the related technology requires the gate and the conductive column to extend towards each other to achieve contact. This reduces the difficulty of opening the conductive column 30, reduces the difficulty of connecting the conductive column 30 with the corresponding gate portion 111, simplifies the process, and improves the yield and stability of the semiconductor device. At the same time, compared with the SCT process that requires a larger area of ​​openings to be set at each step to form a conductive column, the embodiment of the present application can also reduce the area of ​​the conductive column 30 opening to improve the area utilization of the semiconductor device.

[0080] To sum up, in the embodiment of the present application, a first connecting portion 112 is set at each step 110, and a second connecting portion 113 connected between the first connecting portion 112 and the gate portion 111 is set on the side wall of the first sub-portion 21, so that the conductive column 30 can directly penetrate the stacking structure 10 and connect with the first connecting portion 112, so that the conductive column 30 can be connected to the gate portion 111 in the corresponding gate functional layer 11. In the embodiment of the present application, the conductive column 30 is set to penetrate the stacking structure 10, and there is no need to make the conductive column 30 end at the corresponding layer of step 110, which can simplify the process difficulty, reduce the connection difficulty between the conductive column 30 and the gate portion 111, and improve the yield rate of the semiconductor device.

[0081] In addition, an embodiment of the present application further provides a method for manufacturing a semiconductor device, which comprises the following steps:

[0082] Forming a plurality of insulating layers and a plurality of interlayer dielectric layers stacked and alternating to form a stacked structure, the stacked structure comprising an array region and a step region located at at least one side of the array region, the stacked structure having a plurality of steps formed in the step region corresponding to the plurality of interlayer dielectric layers respectively;

[0083] Replacing the plurality of interlayer dielectric layers with gate functional layers, each gate functional layer being formed with at least a gate portion located in the array region, a first connecting portion located at the step, and a second connecting portion connected between the gate portion and the first connecting portion;

[0084] A gate isolation structure is formed that penetrates the stack structure, wherein a first sub-portion extending to the step region is formed in the gate isolation structure, and a second connecting portion is connected to a side wall of the first sub-portion;

[0085] A plurality of conductive pillars are formed in the step area and penetrate the stacked structure, and the conductive pillars are connected to corresponding first connecting portions.

[0086] Specifically, please combine Figure 1 , Figure 2 , Figure 3 , Figure 4 as well as Figures 5 to 14 The method for manufacturing a semiconductor device provided in an embodiment of the present application comprises the following steps:

[0087] Step S10, forming a plurality of insulating layers 12 and a plurality of interlayer dielectric layers 13 stacked and alternating to form a stacked structure 10, the stacked structure 10 comprising an array region 101 and a step region 102 located on at least one side of the array region 101, the stacked structure 10 having a plurality of steps 110 formed in the step region 102 corresponding to the plurality of interlayer dielectric layers 13 respectively.

[0088] In step S10, a substrate 50 is provided, and the substrate 50 may be a Si substrate, a Ge substrate, a SiGe substrate, SOI (Silicon On Insulator) or GOI (Germanium On Insulator), etc. In other embodiments, the semiconductor substrate may also be a substrate including other element semiconductors or compound semiconductors, such as SiC, or may be a stacked structure, such as Si / SiGe, etc.

[0089] A plurality of insulating layers 12 and interlayer dielectric layers 13 are stacked and alternately formed on a substrate 50 to form a stacked structure 10, and the stacked structure 10 is provided with an array region 101, a step region 102 located at least on one side of the array region 101, and a transition region 103 located between the array region 101 and the step region 102. The plurality of insulating layers 12 and the plurality of interlayer dielectric layers 13 are etched to form a plurality of steps 110 corresponding to the plurality of interlayer dielectric layers 13 in the step region 102.

[0090] In some embodiments, the material of the insulating layer 12 may include silicon oxide, and the material of the interlayer dielectric layer 13 may include silicon nitride.

[0091] Next, a first sacrificial portion 14 is formed on the interlayer dielectric layer 13 at each step 110 . In some embodiments, the first sacrificial portion 14 may be made of polysilicon.

[0092] Then, an insulating dielectric layer 15 covering the plurality of steps 110 is formed. Figure 5 As shown, and in some embodiments, the material of the insulating dielectric layer 15 may include silicon oxide.

[0093] Next, a plurality of gate isolation holes 201, channel holes 401, dummy channel holes 410, and step connection holes 301 are formed through the stacked structure 10, wherein the gate isolation holes 201 are at least located in the array region 101 and the step region 102, the channel holes 401 are located in the array region 101, the dummy channel holes 410 are located in the transition region 103, the step connection holes 301 are located in the step region 102, and at least one step connection hole 301 passes through a corresponding step 110, as shown in FIG. Figure 6 shown.

[0094] Then, a second sacrificial portion 31 is formed in the gate isolation hole 201 , the channel hole 401 , the dummy channel hole 410 , and the step connection hole 301 .

[0095] A cap layer 16 is formed on the side of the stacked structure 10 and the insulating dielectric layer 15 away from the substrate 50. Figure 7 As shown; in some embodiments, the material of the cap layer 16 may include polysilicon material.

[0096] Step S20, replacing the plurality of interlayer dielectric layers 13 with gate functional layers 11, each gate functional layer 11 having at least a gate portion 111 located in the array region 101, a first connecting portion 112 located at the step 110, and a second connecting portion 113 connected between the gate portion 111 and the first connecting portion 112.

[0097] In step S20, the second sacrificial portion 31 in the channel hole 401 can be removed first, and then a channel structure 40 can be formed in the channel hole 401. Specifically, a charge storage layer, a tunneling layer and a channel layer can be formed in the channel hole 401 in sequence; in some embodiments, the material of the tunneling layer can be silicon oxide, the material of the charge storage layer can be silicon nitride or silicon nitride oxide, and the material of the channel layer can be polysilicon.

[0098] Next, the second sacrificial portion 31 in the gate isolation hole 201 is removed. Figure 8 and the plurality of gate isolation holes 201 include a plurality of gate isolation hole groups, the gate isolation hole group is formed with a plurality of gate isolation holes 201 arranged along a first direction X, the first direction X is the direction from the array area 101 to the step area 102.

[0099] The insulating layer 12 and the interlayer dielectric layer 13 at the inner wall of the gate isolation hole 201 are removed, so that the aperture of the gate isolation hole 201 is enlarged. Fig. 9As shown, the plurality of gate isolation holes 201 in the gate isolation hole group are connected to form a first gate isolation trench 2021 located in the step area 102, a second gate isolation trench 2022 located in the array area 101, and a third gate isolation trench 2023 located in the transition area 103, wherein the third gate isolation trench 2023 is connected between a first gate isolation trench 2021 and a second gate isolation trench 2022 along the first direction X, as shown in FIG. Fig.10 As shown; it should be noted that, one of the first gate isolation grooves 2021 can correspond to a gate isolation hole group, one of the second gate isolation grooves 2022 can correspond to a gate isolation hole group, and one of the third gate isolation grooves 2023 can correspond to a gate isolation hole group.

[0100] It can be understood that the array area 101 includes a plurality of storage blocks arranged along the second direction Y, a third sub-section 23 is connected between a first sub-section 21 and a second sub-section 22 along the first direction X, and is located between two adjacent storage blocks; further, the second sub-section 22 not connected to the third sub-section 23 is located in each storage block, and each storage block can be divided into at least two sub-blocks, and the first sub-section 21 not connected to the third sub-section 23 is located between two adjacent rows of steps 110 arranged along the second direction Y.

[0101] Between two adjacent storage blocks, a third sub-portion 23 is formed in the third gate isolation groove 2023 to separate the first gate isolation groove 2021 from the second gate isolation groove 2022. Fig.11 shown.

[0102] Then, the part of the interlayer dielectric layer 13 connected to the first gate isolation groove 2021 is replaced by the second connecting portion 113 through the first gate isolation groove 2021, and the first sacrificial portion 14 and the interlayer dielectric layer 13 at the step 110 are replaced by the first connecting portion 112, and the interlayer dielectric layer 13 of the array area 101 is replaced by the gate portion 111 through the second gate isolation groove 2022. Fig.12 and Fig.13 shown.

[0103] It should be noted that since the formation of the gate portion 111 requires at least the removal of all the interlayer dielectric layers 13 in the array area 101, while the formation of the first connecting portion 112 and the second connecting portion 113 only requires the removal of part of the interlayer dielectric layer 13 adjacent to the first gate isolation groove 2021, the amounts of etching solution required for the two are different, and the components may also be different. Therefore, two etching replacement processes are required to be performed separately. Among them, the embodiment of the present application fills the third gate isolation groove 2023 with the third sub-portion 23 in advance to separate the first gate isolation groove 2021 and the second gate isolation groove 2022, so as to provide a prerequisite for two separate etchings to avoid one etching replacement process affecting the other etching replacement process.

[0104] For example, a portion of the interlayer dielectric layer 13 connected to the first gate isolation trench 2021 may be replaced with the second connection portion 113 through the first gate isolation trench 2021, and the first sacrificial portion 14 and the interlayer dielectric layer 13 at the step 110 may be replaced with the first connection portion 112, and then the interlayer dielectric layer 13 of the array region 101 may be replaced with the gate portion 111 through the second gate isolation trench 2022. Alternatively, the interlayer dielectric layer 13 of the array region 101 may be replaced with the gate portion 111 through the second gate isolation trench 2022, and then a portion of the interlayer dielectric layer 13 connected to the first gate isolation trench 2021 may be replaced with the second connection portion 113 through the first gate isolation trench 2021, and the first sacrificial portion 14 and the interlayer dielectric layer 13 at the step 110 may be replaced with the first connection portion 112.

[0105] It should be noted that, in the process of replacing part of the interlayer dielectric layer 13 connected to the first gate isolation groove 2021 with the second connecting portion 113 through the first gate isolation groove 2021, and replacing the first sacrificial portion 14 and the interlayer dielectric layer 13 at the step 110 with the first connecting portion 112, the first sacrificial portion 14 and the cap layer 16 at the step 110 are selectively removed by an etching liquid. Since the first sacrificial portion 14 is removed, the etching liquid etches the entire upper surface of the interlayer dielectric layer 13 at the step 110, so that the interlayer dielectric layer 13 at the step 110 can be etched away. However, the contact area between the interlayer dielectric layer 13 at the side wall of the first gate isolation groove 2021 and the etching liquid is small, so only part of the interlayer dielectric layer 13 is etched away.

[0106] Step S30 , forming a gate isolation structure 20 penetrating the stacked structure 10 , wherein a first sub-portion 21 extending to the step region 102 is formed in the gate isolation structure 20 , and the second connecting portion 113 is connected to a sidewall of the first sub-portion 21 .

[0107] In step S30, a first sub-portion 21 is formed in the first gate isolation trench 2021, and a second sub-portion 22 is formed in the second gate isolation trench 2022. The first sub-portion 21, the second sub-portion 22 and the third sub-portion 23 together form a gate isolation structure 20. Fig.14 shown.

[0108] In some embodiments, the first sub-portion 21 includes a silicon nitride layer covering the inner wall of the first gate isolation groove 2021, and a silicon material layer filling the first gate isolation groove 2021, the second sub-portion 22 includes a silicon nitride layer covering the inner wall of the second gate isolation groove 2022, and a silicon material layer filling the second gate isolation groove 2022, and the third sub-portion 23 includes a silicon nitride layer covering the inner wall of the third gate isolation groove 2023, and a silicon material layer filling the third gate isolation groove 2023.

[0109] The gate portion 111 is connected between the channel structure 40 and the second sub-portion 22 , and the second connecting portion 113 is connected between the first sub-portion 21 and the first connecting portion 112 .

[0110] It should be noted that the portion of the interlayer dielectric layer 13 that is not etched and replaced forms an interlayer dielectric portion 114, and the interlayer dielectric portion 114 can be distributed in the step area 102 and the transition area 103, the interlayer dielectric portion 114 is adjacent to the first connecting portion 112 and the gate portion 111, and the second connecting portion 113 is adjacent to the first sub-portion 21 and the interlayer dielectric portion 114; wherein, since the first connecting portion 112 is obtained by removing the first sacrificial portion 14 and the interlayer dielectric layer 13 at the step 110, the thickness of the first connecting portion 112 is greater than the thickness of the interlayer dielectric portion 114.

[0111] Since the entire interlayer dielectric layer 13 in the step area 102 does not need to be removed in the embodiment of the present application, it is possible to avoid the interlayer dielectric layer 13 in the step area 102 being completely removed, which would cause a drastic stress change and cause a large bend in the semiconductor device, thereby improving the yield and stability of the semiconductor device.

[0112] Step S40 , forming a plurality of conductive pillars 30 located in the step region 102 and penetrating the stacked structure 10 , and the conductive pillars 30 are connected to corresponding first connection portions 112 .

[0113] In step S40, the second sacrificial portion 31 in the step connection hole 301 is removed. Fig.15 shown.

[0114] A conductive column 30 is formed in the step connection hole 301, and at least one conductive column 30 passes through a corresponding step 110 and is connected to the first connection portion 112 at the corresponding step 110. Figure 2 shown.

[0115] Among the multiple gate functional layers 11 arranged along the stacking direction of the stacking structure 10, the first connection portion 112 of one gate functional layer 11 at least partially overlaps with the interlayer dielectric portion 114 of another gate functional layer 11 along the stacking direction of the stacking structure 10, that is, the orthographic projection of the first connection portion 112 of one gate functional layer 11 on the substrate 50 is located within the orthographic projection of the interlayer dielectric portion 114 of another gate functional layer 11 on the substrate 50, so that the conductive column 30 at each step 110, in addition to passing through and being connected to the first connection portion 112 at the corresponding step 110, also passes through the interlayer dielectric portion 114 of other gate functional layers 11 in the stacking direction of the stacking structure 10, so that the conductive column 30 at each step 110 is only electrically connected to the gate portion 111 in the gate functional layer 11 corresponding to the step 110.

[0116] As mentioned above, in the embodiment of the present application, a first connecting portion 112 is provided at each step 110, and a second connecting portion 113 connected between the first connecting portion 112 and the gate portion 111 is provided on the side wall of the first sub-portion 21, so that the conductive column 30 can directly penetrate the stacked structure 10 and connect with the first connecting portion 112, so that the conductive column 30 can be connected to the gate portion 111 in the corresponding gate functional layer 11. Compared with the related art that requires each conductive column 30 to terminate at the corresponding step 110 and the SCT process of the related art that requires the gate and the conductive column to extend toward each other to achieve contact, the process difficulty can be simplified, and the connection difficulty between the conductive column 30 and the gate portion 111 is reduced, thereby improving the yield rate of the semiconductor device; in addition, in the embodiment of the present application, a high aspect ratio channel hole 401, a gate isolation hole 201, a step connection hole 301 and a virtual channel hole 410 can be formed in the same process, thereby reducing the high aspect ratio hole process in the semiconductor process, effectively simplifying the process difficulty of the semiconductor device process, and reducing the process cost.

[0117] According to the above-mentioned purpose of the present application, the embodiment of the present application also provides a storage system, please refer to Fig.16 The storage system 60 includes a controller 61 and the semiconductor device 62 described in the above embodiments. The controller 61 is coupled to the semiconductor device 62 and is used to control the semiconductor device 62 to store data. The semiconductor device 62 is a semiconductor device manufactured by the semiconductor device manufacturing method described in the above embodiments or the semiconductor device described in the above embodiments.

[0118] Specifically, the controller 61 may control the semiconductor device 62 through the channel CH, and the semiconductor device 62 may perform an operation based on the control of the controller 61 in response to a request from the host 70. The semiconductor device 62 may receive a command CMD and an address ADDR from the controller 61 through the channel CH and access an area selected from the memory array in response to the address. In other words, the semiconductor device 62 may perform an internal operation corresponding to the command on the area selected by the address.

[0119] In some embodiments, the storage system 60 may be implemented as a storage device including but not limited to a universal flash storage (UFS) device, a solid state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC and micro MMC, a secure digital card in the form of SD, mini SD and micro SD, a Personal Computer Memory Card International Association (PCMCIA) card type storage device, a peripheral component interconnect (PCI) type storage device, a high-speed PCI (PCI-E) type storage device, a compact flash (CF) card, a smart media card or a memory stick, etc.

[0120] Specifically, the storage system 60 can be used in terminal products such as computers, televisions, set-top boxes, and vehicles.

[0121] For further information, please refer to Fig.17 Some embodiments of the present application also provide an electronic device 80, which includes a storage system 81, and the storage system 81 is the storage system described in the above embodiments of the present application. Specifically, the electronic device 80 may include but is not limited to mobile phones, desktop computers, tablet computers, laptops, servers, vehicle-mounted devices, wearable devices, mobile power supplies, and any other device that can store data.

[0122] Some embodiments of the present application provide an electronic device, which has the same beneficial effects as the above-mentioned storage system due to the provision of the storage system provided by some embodiments of the present application.

[0123] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0124] The semiconductor device and its manufacturing method, storage system, and electronic device provided in the embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor device, characterized in that: include: A stacked structure, the stacked structure comprising a plurality of insulating layers and a plurality of gate functional layers stacked and alternately arranged, the stacked structure further comprising an array region and a step region located at at least one side of the array region, the stacked structure having a plurality of steps in the step region respectively arranged corresponding to the plurality of gate functional layers; a gate isolation structure, which penetrates the stacked structure and includes a first sub-portion extending to the step region; A plurality of conductive pillars are disposed in the step area and penetrate the stack structure; Among them, each gate functional layer includes at least a gate portion arranged in the array area, a first connecting portion arranged at the step, and a second connecting portion connected to the side wall of the first sub-portion, the second connecting portion is connected between the first connecting portion and the gate portion, and the first connecting portion is connected to the corresponding conductive column.

2. The semiconductor device according to claim 1, wherein: The gate function layer further includes an interlayer dielectric portion disposed in the step region, and the interlayer dielectric portion is adjacent to the first connecting portion and the gate portion.

3. The semiconductor device according to claim 2, characterized in that The second connecting portion is adjacent to the first sub-portion and the interlayer dielectric portion.

4. The semiconductor device according to claim 2, characterized in that The first connection portion in one of the gate functional layers and the interlayer dielectric portion in another of the gate functional layers are at least partially overlapped along the stacking direction of the stacking structure.

5. The semiconductor device according to claim 2, wherein: The thickness of the first connection portion is greater than the thickness of the interlayer dielectric portion.

6. The semiconductor device according to claim 1, wherein: The first sub-portion extends along a first direction, the first direction is a direction from the array area to the step area, the plurality of steps include a plurality of step groups arranged along a second direction, the second direction intersects with the first direction, and each of the step groups includes a plurality of steps arranged along the first direction; The first sub-portion is disposed on at least one side of the step group, and each of the first connecting portions in the step group is connected to the second connecting portion on the side wall of the first sub-portion.

7. The semiconductor device according to claim 1, wherein: The semiconductor device further includes a channel structure disposed in the array region and penetrating the stacked structure, and the gate portion is connected between the channel structure and the second connection portion.

8. The semiconductor device according to claim 7, characterized in that The gate isolation structure further includes a second sub-portion disposed in the array region, and the gate portion is adjacent to the channel structure and the second sub-portion.

9. The semiconductor device according to claim 8, characterized in that The gate isolation structure also includes a third sub-portion arranged between the array area and the step area, the width of the third sub-portion along a first direction perpendicular to the first direction is greater than the width of the first sub-portion along the first direction perpendicular to the first direction, the first direction is the direction from the array area to the step area, and the width of the third sub-portion along the first direction perpendicular to the first direction is greater than the width of the second sub-portion along the first direction perpendicular to the first direction.

10. The semiconductor device according to claim 9, characterized in that A plurality of the first sub-sections are arranged in the step area, a plurality of the second sub-sections are arranged in the array area, a plurality of the third sub-sections are arranged between the array area and the step area, the array area includes a plurality of storage blocks, and a third sub-section is connected between a first sub-section and a second sub-section along the first direction, and is located between two adjacent storage blocks.

11. The semiconductor device according to claim 1, wherein: The gate isolation structure is in a bead chain shape along an extension direction of the gate isolation structure in a transverse cross section perpendicular to the stacking direction of the stacking structure.

12. The semiconductor device according to claim 1, wherein: At least one of the conductive pillars passes through a corresponding one of the steps and is connected to the first connecting portion at the corresponding one of the steps.

13. A method for manufacturing a semiconductor device, characterized in that: The following steps are involved: Forming a plurality of insulating layers and a plurality of interlayer dielectric layers stacked and alternating to form a stacked structure, wherein the stacked structure includes an array region and a step region located at at least one side of the array region, wherein the stacked structure has a plurality of steps formed in the step region corresponding to the plurality of interlayer dielectric layers respectively; Replacing the plurality of interlayer dielectric layers with gate functional layers, each of the gate functional layers being formed with at least a gate portion located in the array region, a first connecting portion located at the step, and a second connecting portion connected between the gate portion and the first connecting portion; forming a gate isolation structure penetrating the stacked structure, wherein the gate isolation structure is formed with a first sub-portion extending to the step region, and the second connecting portion is connected to a side wall of the first sub-portion; A plurality of conductive pillars are formed in the step region and penetrate the stack structure, and the conductive pillars are connected to the corresponding first connecting portions.

14. The method for manufacturing a semiconductor device according to claim 13, characterized in that: The step of forming a plurality of stacked and alternating insulating layers and a plurality of interlayer dielectric layers to form a stacked structure comprises: A first sacrificial portion located on the interlayer dielectric layer is formed at the step; A plurality of gate isolation holes, channel holes and step connection holes are formed through the stack structure, wherein the gate isolation holes are at least located in the array region and the step region, the channel holes are located in the array region, the step connection holes are located in the step region, and at least one of the step connection holes passes through a corresponding step; A second sacrificial portion is formed in the gate isolation hole, the channel hole, and the step connection hole.

15. The method for manufacturing a semiconductor device according to claim 14, characterized in that: The step of replacing the plurality of interlayer dielectric layers with gate functional layers also includes: The second sacrificial portion in the gate isolation hole is removed, and the plurality of gate isolation holes include a plurality of gate isolation hole groups, wherein the plurality of gate isolation holes arranged along a first direction are formed in the gate isolation hole groups, and the first direction is a direction from the array area to the step area; Removing the insulating layer and the interlayer dielectric layer at the inner wall of the gate isolation hole, so that the plurality of gate isolation holes in the gate isolation hole group are connected to form a first gate isolation trench located in the step area and a second gate isolation trench located in the array area; The first gate isolation groove is used to replace the portion of the interlayer dielectric layer connected to the first gate isolation groove with the second connecting portion, and the first sacrificial portion and the interlayer dielectric layer at the step are replaced with the connecting portion, and the second gate isolation groove is used to replace the interlayer dielectric layer in the array area with the gate portion.

16. The method for manufacturing a semiconductor device according to claim 15, characterized in that: The step of removing the insulating layer and the interlayer dielectric layer at the inner wall of the gate isolation hole further comprises: forming a third gate isolation trench located between the array region and the step region, wherein the third gate isolation trench is connected between one of the first gate isolation trenches and one of the second gate isolation trenches along the first direction; A third sub-portion is formed in the third gate isolation trench to separate the first gate isolation trench from the second gate isolation trench.

17. The method for manufacturing a semiconductor device according to claim 15, characterized in that: The step of forming a gate isolation structure penetrating the stack structure comprises: The first sub-portion is formed in the first gate isolation groove, and the second sub-portion is formed in the second gate isolation groove, respectively, to form the gate isolation structure.

18. The method for manufacturing a semiconductor device according to claim 14, characterized in that: The step of forming a plurality of conductive pillars located in the step area and penetrating the stacked structure comprises: removing the second sacrificial portion in the step connection hole; The conductive pillars are formed in the step connection holes, and at least one of the conductive pillars passes through a corresponding step and is connected to the first connection portion at the corresponding step.

19. A storage system, characterized in that: The storage system comprises a controller and the semiconductor device according to any one of claims 1 to 12, wherein the controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

20. An electronic device, characterized in that: Includes the storage system as claimed in claim 19.

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