Semiconductor memory device and method of manufacturing the same

Abstract

A semiconductor memory device and a method of manufacturing the semiconductor memory device are provided herein. The semiconductor memory device includes a channel layer and a source selection line surrounding at least a portion of the channel layer. A p-type impurity is locally doped in the portion of the channel layer, or the gate insulating layer includes a first member interposed between the channel layer and the source selection line and aligned with the data storage layer.

Description

Technical Field

[0001] Various embodiments of the present disclosure are generally directed to semiconductor memory devices and methods of manufacturing semiconductor memory devices, including but not limited to a three-dimensional (3D) semiconductor memory device and methods of manufacturing the three-dimensional semiconductor memory device. Background Art

[0002] Semiconductor memory devices are included in small electronic devices and electronic devices in various fields such as automobiles, medical fields, or data centers. Therefore, the demand for semiconductor memory devices is growing.

[0003] A semiconductor memory device may include memory cells for storing data. In order to realize a high-capacity semiconductor memory device, technical development of a three-dimensional semiconductor memory device including memory cells arranged three-dimensionally is being actively conducted.

[0004] A drain select transistor, a source select transistor, and a plurality of memory cells connected in series between the drain select transistor and the source select transistor form a memory cell string. The memory cell string of the three-dimensional semiconductor memory device is controlled by a plurality of conductive layers stacked and spaced apart from each other and a channel layer extending through the plurality of conductive layers. The plurality of conductive layers can be used as a drain select line acting as a gate electrode of the drain select transistor, a source select line acting as a gate electrode of the source select transistor, and a word line acting as a gate electrode of each memory cell. Summary of the invention

[0005] Embodiments of the present disclosure may provide a semiconductor memory device. The semiconductor memory device may include: a channel layer including a first region, a second region extending from the first region in a first direction, and a third region extending from the second region in the first direction, wherein the second region contains p-type impurities; a plurality of word lines stacked along the sidewalls of the first region and spaced apart from each other in the first direction; a source selection line spaced apart from the plurality of word lines in the first direction, at least one segment of the source selection line surrounding at least a portion of the second region in the channel layer; a data storage layer interposed between the plurality of word lines and the channel layer; and a tunnel insulation layer interposed between the data storage layer and the channel layer and extending beyond the data storage layer in the first direction, such that the tunnel insulation layer is interposed between the channel layer and the source selection line.

[0006] Embodiments of the present disclosure may provide a semiconductor memory device. The semiconductor memory device may include: a channel layer extending in a first direction; a plurality of word lines stacked along the sidewalls of the channel layer and spaced apart from each other in the first direction; a source selection line spaced apart from the plurality of word lines in the first direction and spaced apart from the sidewalls of the channel layer in a second direction perpendicular to the first direction; a doped semiconductor layer spaced apart from the source selection line in the first direction and contacting an end of the channel layer; a gate insulating layer including a first member interposed between the channel layer and the source selection line; and a data storage layer interposed between the plurality of word lines and the channel layer. The first member of the gate insulating layer is aligned with the data storage layer in the first direction.

[0007] Embodiments of the present disclosure may provide a method for manufacturing a semiconductor memory device. The method may include the following steps: forming a stacked body, the stacked body including a first interlayer insulating layer and a plurality of word lines, the first interlayer insulating layer having a first surface and a second surface facing opposite directions, the plurality of word lines and a plurality of second interlayer insulating layers being alternately stacked above the first surface of the first interlayer insulating layer; forming a cell plug, the cell plug including a channel layer, a tunnel insulating layer, a data storage layer, and a blocking insulating layer, the channel layer extending through the stacked body and having a protrusion extending beyond the second surface of the first interlayer insulating layer, the tunnel insulating layer including a first region interposed between the channel layer and the stacked body and a A second area of ​​the protrusion covering the channel layer, the data storage layer extending along the first area and the second area of ​​the tunnel insulating layer, and the blocking insulating layer extending along the data storage layer, wherein the data storage layer is interposed between the tunnel insulating layer and the blocking insulating layer; sequentially removing a portion of the blocking insulating layer and a portion of the data storage layer to expose the second area of ​​the tunnel insulating layer; forming a preliminary doped area in the channel layer by injecting impurities of a first conductive type into an area of ​​the channel layer surrounded by at least the second surface of the first interlayer insulating layer; and forming a source selection line above the second surface of the first interlayer insulating layer.

[0008] Embodiments of the present disclosure may provide a method for manufacturing a semiconductor memory device. The method may include the following steps: forming a stacked body, the stacked body including a first interlayer insulating layer and a plurality of word lines, the first interlayer insulating layer having a first surface and a second surface facing opposite directions, the plurality of word lines and a plurality of second interlayer insulating layers being alternately stacked above the first surface of the first interlayer insulating layer; forming a cell plug, the cell plug including a channel layer, a tunnel insulating layer, a data storage layer and a blocking insulating layer, the channel layer extending through the stacked body and having a protrusion extending beyond the second surface of the first interlayer insulating layer, the tunnel insulating layer including a first region interposed between the channel layer and the stacked body and a second region covering the protrusion of the channel layer, the data storage layer extending along the first region and the second region of the tunnel insulating layer, and the blocking insulating layer extending along the data storage layer, wherein the data storage layer is interposed between the tunnel insulating layer and the blocking insulating layer; sequentially removing a portion of the blocking insulating layer and a portion of the data storage layer to expose the second region of the tunnel insulating layer; forming a gate insulating layer covering the exposed second region of the tunnel insulating layer; and forming a source selection line above the gate insulating layer.

[0009] Embodiments of the present disclosure may provide a semiconductor memory device. The semiconductor memory device may include: a channel layer extending in a first direction and including a first region having doped impurities; a plurality of word lines stacked along the sidewalls of the channel layer and spaced apart from each other in the first direction; a source selection line spaced apart from the plurality of word lines in the first direction and spaced apart from the sidewalls of the channel layer in a second direction perpendicular to the first direction; a doped semiconductor layer contacting an end of the channel layer; a gate insulating layer including a first member interposed between the channel layer and the source selection line. The first region may be at least partially disposed at the height of the source selection line. The thickness of the gate insulating layer may establish a threshold voltage characteristic of a source selection transistor associated with the source selection line. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0011] Figure 2 is a circuit diagram showing a memory cell array according to an embodiment of the present disclosure.

[0012] Figure 3A and Figure 3B is a cross-sectional view showing a semiconductor memory device according to an embodiment of the present disclosure.

[0013] Figure 4 is a cross-sectional view showing a semiconductor memory device according to an embodiment of the present disclosure.

[0014] Figure 5Ais a cross-sectional view of a semiconductor memory device during formation of a first structure according to an embodiment of the present disclosure.

[0015] Figure 5B is a cross-sectional view of a semiconductor memory device during a bonding process between a first structure and a second structure according to an embodiment of the present disclosure.

[0016] Fig. 6A and Figure 6B is a cross-sectional view of a semiconductor memory device during a process of exposing a portion of a tunnel insulating layer according to an embodiment of the present disclosure.

[0017] Fig. 7A , Figure 7B , Figure 7C , Fig.7D and Fig. 7E It is shown in Figure 6B A cross-sectional view of an embodiment of a semiconductor memory device during a process performed by the semiconductor memory device.

[0018] Fig. 8A , Figure 8B , Figure 8C , Fig.8D and Fig. 8E It is shown that in the application Figure 6B A cross-sectional view of an embodiment of a semiconductor memory device during a process performed after a process of the semiconductor memory device is performed.

[0019] Fig. 9 is a block diagram illustrating an electronic system including a semiconductor memory device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] The specific structural or functional descriptions of the embodiments of the concepts of the present disclosure disclosed in this specification or application are exemplified to illustrate the embodiments of the concepts of the present disclosure. The embodiments of the concepts of the present disclosure should not be interpreted as being limited to the embodiments described in this specification or application, and may be modified and replaced by other equivalent embodiments in various forms.

[0021] Although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element, and the order or quantity of components is not limited by these terms. In addition, unless a specific limitation on the amount of a component is expressed in the singular or plural, these terms should not be interpreted as limiting the number of components.

[0022] Various embodiments of the present disclosure relate to a semiconductor memory device capable of controlling a threshold voltage of a source selection transistor and a method of manufacturing the same.

[0023] Figure 1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0024] Reference Figure 1 , a semiconductor memory device 50 includes a peripheral circuit 40 and a memory cell array 10 .

[0025] For example, the peripheral circuit 40 performs a program operation to store data in the memory cell array 10, a read operation to output the data stored in the memory cell array 10, and an erase operation to erase the data stored in the memory cell array 10. In this embodiment, the peripheral circuit 40 includes an input / output circuit 21, a control circuit 23, a voltage generating circuit 31, a row decoder 33, a column decoder 35, a page buffer 37, and a source line driver 39.

[0026] The peripheral circuit 40 is coupled to the memory cell array 10 through a common source line CSL, a bit line BL, a drain select line DSL, a word line WL, and a source select line SSL.

[0027] The input / output circuit 21 transfers a command CMD and an address ADD received from an external device (eg, a memory controller) of the semiconductor memory device 50 to the control circuit 23. The input / output circuit 21 exchanges data DATA with the external device and the column decoder 35.

[0028] In response to receiving the command CMD and the address ADD, the control circuit 23 outputs an operation signal OP_S, a row address RADD, a source line control signal SL_S, a page buffer control signal PB_S, and a column address CADD.

[0029] In response to receiving the operation signal OP_S, the voltage generation circuit 31 generates various operation voltages Vop for a program operation, a read operation, and an erase operation.

[0030] In response to receiving the row address RADD, the row decoder 33 transfers the operating voltage Vop to the drain select line DSL, the word line WL, and the source select line SSL.

[0031] In response to receiving the column address CADD, the column decoder 35 transmits the data DATA input from the input / output circuit 21 to the page buffer 37 or transmits the data DATA stored in the page buffer 37 to the input / output circuit 21. The column decoder 35 exchanges the data DATA with the input / output circuit 21 through the column line CL. The column decoder 35 exchanges the data DATA with the page buffer 37 through the data line DL.

[0032] In response to receiving the page buffer control signal PB_S, the page buffer 37 stores read data received through the bit line BL. The page buffer 37 senses a voltage or current of the bit line BL during a read operation.

[0033] In response to receiving the source line control signal SL_S, the source line driver 39 controls a voltage applied to the common source line CSL.

[0034] The memory cell array 10 includes a plurality of memory blocks. Each memory block includes a plurality of memory cells arranged in a three-dimensional (3D) form. Each memory cell may be a nonvolatile memory cell. In an embodiment, each memory cell may be a NAND flash memory cell.

[0035] Figure 2 is a circuit diagram showing a memory cell array according to an embodiment of the present disclosure.

[0036] Reference Figure 2 , the memory cell array 10 includes a plurality of memory cell strings CS. The plurality of memory cell strings CS are coupled to a plurality of bit lines BL and a doped semiconductor layer DPS provided as a source layer SL. Figure 1 The common source line CSL is shown coupled to a plurality of memory cell strings CS via the doped semiconductor layer DPS.

[0037] Each memory cell string CS includes a source select transistor SST, a plurality of memory cells MC, and a drain select transistor DST. The memory cells MC are connected in series between the source select transistor SST and the drain select transistor DST. The source select transistor SST controls the electrical connection or relationship between the plurality of memory cells MC and the doped semiconductor layer DPS. The drain select transistor DST controls the electrical connection or relationship between the plurality of memory cells MC and the corresponding bit lines BL.

[0038] A plurality of word lines WL provide a plurality of signals to a plurality of gates of a plurality of memory cells MC. In an embodiment, a section of each word line WL may be used as a gate of each memory cell MC. A source select line SSL provides a signal to a gate electrode of a source select transistor SST. In an embodiment, a section of a source select line SSL may be used as a gate electrode of a source select transistor SST. A drain select line DSL provides a signal to a gate electrode of a drain select transistor DST. In an embodiment, a section of a drain select line DSL may be used as a gate electrode of a source select transistor SST.

[0039] An operating voltage to precharge a channel layer of a corresponding memory cell string CS may be applied to each bit line BL. An operating voltage to discharge a channel potential of the memory cell string CS may be applied to the doped semiconductor layer DPS.

[0040] Figure 3A and Figure 3B 2 is a cross-sectional view showing a semiconductor memory device according to an embodiment of the present disclosure. Cross-hatching throughout the drawings shows corresponding or similar areas between the drawings, rather than indicating the material of the areas.

[0041] Figure 3B yes Figure 3A An enlarged cross-sectional view of the "AR1" region is shown.

[0042] Reference Figure 3A and Figure 3B , the semiconductor memory device includes a cell array structure CAS, a doped semiconductor layer DPS, a bit line BL, a peripheral circuit structure 40, and an interconnection structure for electrical connection between the peripheral circuit structure 40 and the cell array structure CAS.

[0043] The cell array structure CAS includes a plurality of memory cells arranged three-dimensionally. In an embodiment, the plurality of memory cells are included in a reference Figure 2 The memory cell strings CS are connected to the plurality of conductive layers 107 and 185. The plurality of conductive layers 107 and 185 include a plurality of first conductive layers 107 used as drain select lines DSL and a plurality of word lines WL and a second conductive layer 185 used as source select lines SSL.

[0044] The plurality of first conductive layers 107 are stacked over or on the semiconductor substrate 61 while being spaced apart in the first direction DR1. The second conductive layer 185 is spaced apart from the plurality of first conductive layers 107 in the first direction DR1. The plurality of first conductive layers 107 and the second conductive layer 185 each extend along a plane perpendicular to an axis oriented in the first direction DR1. In an embodiment, each of the plurality of first conductive layers 107 and the second conductive layer 185 extends in the second direction DR2 along a plane perpendicular to the axis oriented in the first direction DR1.

[0045] In an embodiment, each of the plurality of first conductive layers 107 and the second conductive layer 185 includes at least one of a doped semiconductor layer and a metal layer. The doped semiconductor layer for each of the plurality of first conductive layers 107 and the second conductive layer 185 may include a doped silicon layer. The metal layer for each of the plurality of first conductive layers 107 and the second conductive layer 185 may include tungsten, copper, molybdenum, etc. Each of the plurality of first conductive layers 107 and the second conductive layer 185 may further include a metal nitride layer. The metal nitride layer may include titanium nitride, tantalum nitride, etc. The metal nitride layer may extend along the surface of the metal layer.

[0046] The second conductive layer 185 may include a conductive material different from that of the plurality of first conductive layers 107. In an embodiment, each of the plurality of first conductive layers 107 includes a metal layer and a metal nitride layer, and the second conductive layer 185 includes a doped silicon layer.

[0047] In this embodiment, the first interlayer insulating layer 105 is interposed or located between the plurality of first conductive layers 107 and the second conductive layer 185. The plurality of first conductive layers 107 and the plurality of second interlayer insulating layers 109 are alternately arranged in the first direction DR1. Therefore, one of the plurality of second interlayer insulating layers 109 is disposed between two first conductive layers that are continuous in the first direction DR1 among the plurality of first conductive layers 107.

[0048] The doped semiconductor layer DPS provided as the source layer SL is spaced apart from the second conductive layer 185 in the first direction DR1. A third interlayer insulating layer 187 is disposed between the second conductive layer 185 and the doped semiconductor layer DPS.

[0049] The first interlayer insulating layer 105 , the plurality of second interlayer insulating layers 109 , and the third interlayer insulating layer 187 may each include a silicon oxide layer or the like.

[0050] Each memory cell string CS includes a cell plug CPL. The cell plug CPL includes a channel layer 123, a tunnel insulating layer 121TI, a data storage layer 121DS, and a blocking insulating layer 121BI.

[0051] The channel layer 123 extends in the first direction DR1. The channel layer 123 forms a channel region of the memory cell string CS. The channel layer 123 may be formed of a semiconductor material. In an implementation, the channel layer 123 includes silicon, germanium, or a mixture thereof.

[0052] A plurality of first conductive layers 107 and second conductive layers 185 are stacked around segments or portions of the sidewalls of the respective channel layers 123 and are spaced apart in the first direction DR1 along the sidewalls of the channel layers 123. For example, the sidewalls of the channel layers 123 include an inclined structure extending mainly in the first direction DR1. A stack including a plurality of first conductive layers 107, a plurality of second interlayer insulating layers 109, a first interlayer insulating layer 105, and a second conductive layer 185 extends to surround the sidewalls of the channel layers 123. In an embodiment, the second conductive layer 185 is spaced apart from the sidewalls of the channel layers 123 in the second direction DR2.

[0053] The data storage layer 121DS extends in the first direction DR1 and is interposed between the stack including the plurality of first conductive layers 107 and the channel layer 123. The blocking insulating layer 121BI extends in the first direction DR1 and is interposed between the stack including the plurality of first conductive layers 107 and the data storage layer 121DS. The tunnel insulating layer 121TI is interposed between the data storage layer 121DS and the channel layer 123. In this example, the tunnel insulating layer 121TI extends beyond the data storage layer 121DS and the blocking insulating layer 121BI in the first direction DR1, so that the tunnel insulating layer 121TI is interposed between the second conductive layer 185 and the channel layer 123. In this example, the tunnel insulating layer 121TI extends beyond the second conductive layer 185 in the first direction DR1 and is interposed between the third interlayer insulating layer 187 and the channel layer 123.

[0054] At a height or plane where the first conductive layer 107 for the word line WL is provided, the data storage layer 121DS may be used as a data storage area. The data storage layer 121DS may be formed as a material layer that stores changed data, for example, using Fowler-Nordheim tunneling. In an embodiment, the data storage layer 121DS may be formed as a charge trapping insulating layer or an insulating layer containing conductive nanodots. The charge trapping insulating layer may include a silicon nitride layer. The tunnel insulating layer 121TI may include an insulating material capable of tunneling charges. In an embodiment, the tunnel insulating layer 121TI may include a silicon oxide layer. The blocking insulating layer 121BI may include an insulating material capable of blocking charges. In an embodiment, the blocking insulating layer 121BI may include an insulating layer having a dielectric constant higher than the dielectric constant of the tunnel insulating layer 121TI.

[0055] The cell plug CPL further includes a core insulating layer 125 and a capping pattern 127. The core insulating layer 125 and the capping pattern 127 are disposed in a central region of the cell plug CPL. The channel layer 123 extends along the sidewalls of the core insulating layer 125 and the sidewalls of the capping pattern 127. The capping pattern 127 may serve as a drain junction of the memory cell string CS. The capping pattern 127 may include at least one of an n-type impurity and a p-type impurity. In an embodiment, the capping pattern 127 includes an n-type impurity as a majority carrier.

[0056] The threshold voltage of the drain select transistor coupled to the drain select line DSL may be designed in various ways by controlling impurities present in the capping pattern 127 and impurities present in the channel layer 123 adjacent to the capping pattern 127 .

[0057] The bit lines BL are coupled to the respective capping patterns 127. The bit lines BL may be disposed at locations spaced apart from the semiconductor substrate 201 in the first direction DR1. In an implementation, the bit lines BL are disposed between the semiconductor substrate 201 and the cell plugs CPL.

[0058] The bit line BL is connected to the capping pattern 127 via the bit line connection structure BCC. In an embodiment, the bit line connection structure BCC includes a conductive bit contact plug 133, a conductive pad pattern 137, and a conductive via structure 141. The conductive bit contact plug 133 is disposed in the first insulating structure 131 and is connected to the capping pattern 127. The first insulating structure 131 is disposed at a height between a stack including a plurality of first conductive layers 107 and a plurality of second interlayer insulating layers 109 and the bit line BL. The first insulating structure 131 surrounds the first end of the cell plug CPL closest to the bit line BL (in this example, the end of the cell plug CPL including the capping pattern 127). The conductive pad pattern 137 is disposed in the second insulating structure 135 and is connected to the conductive bit contact plug 133. The second insulating structure 135 is disposed at a height between the first insulating structure 131 and the bit line BL. The conductive via structure 141 is disposed in the third insulating structure 139 and is connected to the conductive pad pattern 137. The third insulating structure 139 is disposed at a height between the second insulating structure 135 and the bit line BL. The bit line BL is disposed in the bit line level insulating layer 143. The bit line level insulating layer 143 overlaps the second insulating structure 135 in the first direction DR1, wherein the third insulating structure 139 is interposed between the bit line level insulating layer 143 and the second insulating structure 135.

[0059] The connection between the bit line BL and the capping pattern 127 is not limited to the above-described embodiments. Although not shown in the drawings, according to embodiments, the bit line BL may be directly connected to the capping pattern 127 .

[0060] The cell array structure CAS is coupled to the peripheral circuit structure 40 via an interconnect structure that may be designed in various ways. In an implementation, the interconnect structure includes a first conductive connection structure 153 , a first conductive bonding structure 155 , a second conductive bonding structure 235 , and a second conductive connection structure 230 .

[0061] The first conductive connection structure 153 and the first conductive bonding structure 155 are disposed in the fourth insulating structure 151. The fourth insulating structure 151 is disposed at a height between the bit line BL and the peripheral circuit structure 40. The first conductive connection structure 153 is shown to be disposed closer to the cell array structure CAS (rather than the first conductive bonding structure 155). The first conductive bonding structure 155 is shown to be disposed closer to the peripheral circuit structure 40 (rather than the first conductive connection structure 153), and is connected to the cell array structure CAS via the first conductive connection structure 153. In an embodiment, the first conductive connection structure 153 is connected to the bit line BL. According to an embodiment, the first conductive bonding structure 155 is electrically connected to the bit line BL via the first conductive connection structure 153, thereby connecting to the cell array structure CAS.

[0062] The fifth insulating structure 210 is disposed between the peripheral circuit structure 40 and the fourth insulating structure 151. The first insulating structure 131, the second insulating structure 135, the third insulating structure 139, the fourth insulating structure 151, and the fifth insulating structure 210 may each include a single insulating layer or a plurality of insulating layers including two or more layers stacked in the first direction DR1.

[0063] The second conductive connection structure 230 and the second conductive bonding structure 235 are disposed in the fifth insulating structure 210. The second conductive connection structure 230 is disposed between the peripheral circuit structure 40 and the second conductive bonding structure 235. The second conductive bonding structure 235 is coupled to the peripheral circuit structure 40 via the second conductive connection structure 230.

[0064] The first conductive bonding structure 155 and the second conductive bonding structure 235 may each include a metal such as copper. The first conductive bonding structure 155 and the second conductive bonding structure 235 may be bonded to each other.

[0065] The second conductive connection structure 230 includes a multi-layer conductive pattern designed to include various structures for electrical connection between the second conductive bonding structure 235 and the peripheral circuit structure 40. In an embodiment, the peripheral circuit structure 40 includes Figure 1 2. The transistor TR of the page buffer 37 shown. The transistor TR is arranged in an active region of the semiconductor substrate 201 separated by the isolation layer 203. The transistor TR includes a first junction region 201J1 and a second junction region 201J2 formed in the active region of the semiconductor substrate 201, and a gate insulating layer 205 and a gate electrode 207 stacked above the active region of the semiconductor substrate 201 between the first junction region 201J1 and the second junction region 201J2. The first junction region 201J1 and the second junction region 201J2 serve as a source junction and a drain junction of the transistor TR. The first junction region 201J1 and the second junction region 201J2 include at least one of an n-type impurity and a p-type impurity. In an embodiment, when the transistor TR is provided as an N-channel metal oxide semiconductor (NMOS) transistor, the first junction region 201J1 and the second junction region 201J2 include n-type impurities as majority carriers.

[0066] The second conductive connection structure 230 connects the transistor TR to the cell array structure CAS via the first conductive bonding structure 155 and the second conductive bonding structure 235. In an embodiment, the second conductive connection structure 230 is electrically connected to the first junction region 201J1 of the transistor TR, and is electrically connected to the bit line BL via the first conductive bonding structure 155 and the second conductive bonding structure 235. Therefore, the transistor TR is electrically connected to the channel layer 123 of the memory cell array structure CAS via the bit line BL and the capping pattern 127.

[0067] The above-mentioned cell array structure CAS, the bit line BL, and the first conductive connection structure 153, the first conductive bonding structure 155, the second conductive bonding structure 235, and the second conductive connection structure 230 of the interconnect structure are arranged between the doped semiconductor layer DPS and the peripheral circuit structure 40. In addition to the first end closest to the bit line BL, the cell plug CPL of the cell array structure CAS also includes a second end contacting the doped semiconductor layer DPS. The second end of the cell plug CPL corresponds to the end of the channel layer 123 contacting the doped semiconductor layer DPS. The doped semiconductor layer DPS may include one or more grooves or slots into which the end of the channel layer 123 is inserted.

[0068] Reference Figure 3B , the channel layer 123 includes a first region 123U, a second region 123D1, and a third region 123D2. The first region 123U is a section or portion of the channel layer 123 disposed in or surrounded by a plurality of first conductive layers 107 provided as a plurality of word lines WL. The first region 123U may be an undoped region. A plurality of word lines WL are stacked along the sidewalls of the first region 123U and spaced apart from each other. The second region 123D1 is a section or portion of the channel layer 123 extending from the first region 123U in the first direction DR1, and at least a portion of the second region 123D1 is disposed in or surrounded by at least a section of the second conductive layer 185 provided as the source selection line SSL. The second region 123D1 is a first doped region containing impurities of a first conductive type (hereinafter, referred to as "first conductive impurities") and impurities of a second conductive type opposite to the first conductive type (hereinafter, referred to as "second conductive impurities"). The first conductive impurities may be p-type impurities, and the second conductive impurities may be n-type impurities. In an embodiment, the second region 123D1 includes any one of boron (B), phosphorus (P), and arsenic (As). The third region 123D2 is a segment or portion of the channel layer 123 extending from the second region 123D1 in the first direction DR1, and includes an end portion of the channel layer 123 contacting the doped semiconductor layer DPS. The third region 123D2 may be a second doped region. The third region 123D2 may include a conductive impurity having a concentration different from that of the second region 123D1. The second region 123D1 may include a p-type impurity having a higher concentration than the third region 123D2 to have a threshold voltage higher than that of the third region 123D2. The concentration of the n-type impurity and the concentration of the p-type impurity in the second region 123D1 may vary according to a threshold voltage design condition of a source select transistor coupled to the second conductive layer 185. The third region 123D2 and the doped semiconductor layer DPS may include n-type impurities as majority carriers.

[0069] When the threshold voltage of the second region 123D1 is higher than the threshold voltage of the third region 123D2 , the threshold voltage characteristic of the source selection transistor coupled to the second conductive layer 185 may be improved or ensured.

[0070] The second conductive layer 185 has a first surface 185S1 and a second surface 185S2 disposed at opposite sides or facing opposite directions of the second conductive layer 185. The first surface 185S1 faces the plurality of first conductive layers 107, and the second surface 185S2 faces the doped semiconductor layer DPS.

[0071] The plurality of word lines WL include a first word line WL1 adjacent to the first interlayer insulating layer 105 adjacent to the second conductive layer 185, wherein the first word line WL1 is the conductive layer 107 closest to the second conductive layer 185. In this example, a boundary between the first region 123U and the second region 123D1 in the channel layer 123 is located at a height between the first word line WL1 and the first surface 185S1 of the second conductive layer 185. In an embodiment, the boundary between the first region 123U and the second region 123D1 may be located at any height at which the first interlayer insulating layer 105 is disposed. A boundary between the second region 123D1 and the third region 123D2 in the channel layer 123 is located at a height between the first surface 185S1 and the second surface 185S2 of the second conductive layer 185, in other words, at any height at which the second conductive layer 185 is disposed. Therefore, one segment or portion of the second conductive layer 185 surrounds one segment of the second region 123D1 in the channel layer 123 in the second direction DR2, and another segment or portion of the second conductive layer 185 surrounds one segment of the third region 123D2 in the channel layer 123 in the second direction DR2.

[0072] Because a section or portion of the second conductive layer 185 surrounds and overlaps a section or portion of the third region 123D2, Figure 3A A gate induced drain leakage (GIDL) current may be generated during an erase operation of the illustrated memory cell string CS.

[0073] The data storage layer 121DS of the cell plug CPL extends in the first direction DR1 and is interposed between the plurality of first conductive layers 107 and the sidewall of the first region 123U in the channel layer 123. The data storage layer 121DS is cut off by or terminated at the second conductive layer 185, and does not extend between the second conductive layer 185 and the channel layer 123. In an embodiment, the data storage layer 121DS contacts the first surface 185S1 of the second conductive layer 185. Because the data storage layer 121DS of the cell plug CPL does not extend between the second conductive layer 185 and the channel layer 123, there is no need to perform an operation of separately programming or erasing a source select transistor, which is performed to control a threshold voltage of the source select transistor coupled to the second conductive layer 185.

[0074] The blocking insulating layer 121BI of the cell plug CPL extends in the first direction DR1 and is interposed between the stack including the plurality of first conductive layers 107 and the data storage layer 121DS. Similar to the data storage layer 121DS, in an embodiment, the blocking insulating layer 121BI contacts the first surface 185S1 of the second conductive layer 185.

[0075] The tunnel insulating layer 121TI of the cell plug CPL extends in the first direction DR1 and is interposed between the data storage layer 121DS and at least the first region 123U of the channel layer 123. In this example, the tunnel insulating layer 121TI extends beyond the data storage layer 121DS and the blocking insulating layer 121BI in the first direction DR1 and is interposed between the second conductive layer 185 and the channel layer 123. The tunnel insulating layer 121TI extends beyond the second surface 185S2 of the second conductive layer 185 in the first direction DR1 and is interposed between the third interlayer insulating layer 187 and the channel layer 123.

[0076] Figure 4 is a cross-sectional view showing a semiconductor memory device according to an embodiment of the present disclosure.

[0077] Figure 4 is a diagram showing the relationship between a semiconductor memory device and Figure 3A The "AR1" region shown corresponds to an enlarged cross-sectional view of the region. Figure 4 Zhongyu Figure 3A and Figure 3B Description of the same or similar elements in the illustrated embodiments.

[0078] Reference Figure 4, the channel layer 123 includes an undoped region 123U and a doped region 123D. The undoped region 123U is a section or portion of the channel layer 123 that is disposed within or surrounded by a plurality of first conductive layers 107 provided as a plurality of word lines WL. Each of the plurality of word lines WL is stacked along the sidewall of the undoped region 123U and spaced apart from each other. The doped region 123D is a portion of the channel layer 123 that includes an end portion of the channel region that contacts the doped semiconductor layer DPS. The doped region 123D may be distributed from the end portion of the channel layer 123 toward the undoped region 123U. The threshold voltage of the undoped region 123U may be higher than the threshold voltage of the doped region 123D. The doped region 123D and the doped semiconductor layer DPS may include n-type impurities as majority carriers.

[0079] As mentioned above Figure 3B As described above, the second conductive layer 185 provided as the source selection line SSL has a first surface 185S1 and a second surface 185S2 .

[0080] In this example, the boundary between the undoped region 123U and the doped region 123D in the channel layer 123 is located at a height between the first surface 185S1 and the second surface 185S2 of the second conductive layer 185. Therefore, one segment or portion of the second conductive layer 185 surrounds one segment of the undoped region 123U in the channel layer 123, and another segment or portion of the second conductive layer 185 surrounds one segment of the doped region 123D in the channel layer 123. Because at least one segment or portion of the second conductive layer 185 surrounds or overlaps one segment or portion of the doped region 123D, a GIDL current may be generated during an erase operation of a memory cell string.

[0081] like Figure 4As shown in the embodiment of the present invention, the semiconductor memory device includes a gate insulating layer 181. The gate insulating layer 181 includes a first member (referred to as a vertical portion 181VP) and a second member (referred to as a horizontal portion 181HP). The vertical portion 181VP is interposed between the second conductive layer 185 and the channel layer 123, and mainly extends in the first direction DR1. The horizontal portion 181HP extends from the vertical portion 181VP along the first surface 185S1 of the second conductive layer 185, and mainly extends in the second direction DR2. The vertical portion 181VP and the horizontal portion 181HP may be formed as a single continuous structure. The threshold voltage of the source selection transistor connected to the second conductive layer 185 may be designed in various ways by controlling the thickness 181TH of the vertical portion 181VP in a direction extending away from the channel layer 123 (e.g., the second direction DR2). As the thickness 181TH of the vertical portion 181VP increases, the threshold voltage of the source selection transistor increases. According to an embodiment, the vertical portion 181VP may be formed to have a thickness greater than that of each of the tunnel insulating layer 121TI, the data storage layer 121DS, and the blocking insulating layer 121BI in a direction (e.g., the second direction DR2) away from the sidewall of the channel layer 123. The terms "vertical" and "horizontal" indicate a relative positional relationship utilized for convenience of description, and do not limit the embodiments of the present disclosure.

[0082] As described above, the source selection transistor coupled to the second conductive layer 185 may improve or ensure threshold voltage characteristics by controlling or adjusting the thickness of the gate insulating layer 181 differently from the cell plug CPL.

[0083] The data storage layer 121DS of the cell plug CPL extends in the first direction DR1 and is interposed between the sidewalls of the plurality of first conductive layers 107 and the channel layer 123. The data storage layer 121DS is cut off by or terminated at the gate insulating layer 181, and does not extend between the second conductive layer 185 and the channel layer 123. Since the data storage layer 121DS of the cell plug CPL does not extend between the second conductive layer 185 and the channel layer 123, it is not necessary to perform an operation of separately programming or erasing a source selection transistor, which is performed to control a threshold voltage of the source selection transistor coupled to the second conductive layer 185. The data storage layer 121DS extends in the same direction as a vertical portion 181VP of the gate insulating layer 181 that is thicker than the data storage layer 121DS in the second direction D2. The gate insulating layer 181 is provided on a surface or end of the data storage layer 121DS that is closest to the second conductive layer 185. The vertical portion 181VP of the gate insulating layer 181 is aligned with the data storage layer 121DS in the first direction DR1.

[0084] The blocking insulating layer 121BI of the cell plug CPL extends in the first direction DR1 and is interposed between the plurality of first conductive layers 107 and the data storage layer 121DS. Similar to the data storage layer 121DS, the blocking insulating layer 121BI is cut off by or terminated at the gate insulating layer 181. The blocking insulating layer 121BI extends in the same direction as a vertical portion 181VP of the gate insulating layer 181 that is thicker than the blocking insulating layer 121BI in the second direction D2. The gate insulating layer 181 is disposed on a surface or end portion of the blocking insulating layer 121BI that is closest to the second conductive layer 185. The vertical portion 181VP of the gate insulating layer 181 is aligned with the blocking insulating layer 121BI in the first direction DR1.

[0085] The data storage layer 121DS and the blocking insulating layer 121BI of the cell plug CPL are interposed not only between the channel layer 123 and the first interlayer insulating layer 105 but also between the channel layer 123 and the plurality of second interlayer insulating layers 109. Figure 4 In the embodiment, the horizontal portion 181HP of the gate insulating layer 181 is interposed between the second conductive layer 185 and the first interlayer insulating layer 105. The vertical portion 181VP of the gate insulating layer 181 extends in the first direction DR1 and is interposed between the channel layer 123 and the third interlayer insulating layer 187.

[0086] The tunnel insulating layer 121TI of the cell plug CPL is interposed between the sidewall of the channel layer 123 and the data storage layer 121DS. The tunnel insulating layer 121TI extends beyond the data storage layer 121DS and the blocking insulating layer 121BI in the first direction DR1, so that the tunnel insulating layer 121TI is interposed between the vertical portion 181VP of the gate insulating layer 181 and the channel layer 123. The tunnel insulating layer 121TI extends beyond the second surface 185S2 of the second conductive layer 185 in the first direction DR1, and is interposed between the third interlayer insulating layer 187 and the channel layer 123. The tunnel insulating layer 121TI, the data storage layer 121DS, and the blocking insulating layer 121BI are parallel to each other and to the sidewall of the channel layer 123, as shown in the embodiment of the drawings, and generally extend at an angle relative to the first direction DR1, resulting in a tapered shape of the cell plug CPL.

[0087] Reference Figure 3B and Figure 4 , the channel layer 123 of the cell plug CPL extends beyond the third interlayer insulating layer 187 in the first direction DR1 and extends into the doped semiconductor layer DPS surrounding or enclosing an end of the channel layer 123. The channel layer 123 of the cell plug CPL surrounds an end of the core insulating layer 125 and prevents contact between the doped semiconductor layer DPS and the core insulating layer 125, thereby isolating the core insulating layer 125 from the doped semiconductor layer DPS.

[0088] Figure 5A is a cross-sectional view of a semiconductor memory device during formation of a first structure.

[0089] Reference Figure 5A , a cell array structure 310 is formed on a sacrificial substrate 301. The sacrificial substrate 301 may include silicon.

[0090] Forming the cell array structure 310 includes forming a stack 300 over or on a sacrificial substrate 301 and forming cell plugs 320. Each cell plug 320 extends through the stack 300 and includes a protrusion extending beyond the stack 300 and into the sacrificial substrate 301.

[0091] Forming the stacked body 300 includes forming a first interlayer insulating layer 305 above or on the sacrificial substrate 301 and stacking a plurality of first material layers alternately with a plurality of second material layers above or on the first interlayer insulating layer 305. In an embodiment, the plurality of first material layers may be a plurality of first conductive layers 307, and the plurality of second material layers may be a plurality of second interlayer insulating layers 309. The embodiments of the present disclosure are not limited to this example. In an embodiment, each of the plurality of first material layers is a sacrificial layer having a different etching rate relative to the etching rate of the plurality of second material layers, and the plurality of second material layers are Figure 5A As shown in the figure, there are multiple second interlayer insulating layers 309. When the first material layer is Figure 5A As shown in the first conductive layer 307, the first material layer can be made of the same Figure 3A and Figure 3B The first conductive layer 107 is formed of the same conductive material as described above. When the first material layer is used as a sacrificial layer, the first material layer may include a silicon nitride layer. The first interlayer insulating layer 305 and the plurality of second interlayer insulating layers 309 may each include a silicon oxide layer.

[0092] The first interlayer insulating layer 305 has a first surface 305S1 and a second surface 305S2 disposed on opposite sides of the first interlayer insulating layer 305 or facing opposite directions. The second surface 305S2 faces the sacrificial substrate 301. The direction faced by the second surface 305S2 is referred to as a first direction DR1. The above-mentioned plurality of first material layers and the plurality of second material layers are alternately stacked above the first surface 305S1 of the first interlayer insulating layer 305 or on the first surface 305S1 of the first interlayer insulating layer 305. In an embodiment, a plurality of first conductive layers 307 and a plurality of second interlayer insulating layers 309 are alternately stacked above the first surface 305S1 of the first interlayer insulating layer 305. The plurality of first conductive layers 307 may be used as a plurality of word lines WL and a drain select line DSL.

[0093] Forming the cell plug 320 includes: forming a mask pattern (not shown) above the stacked body 300; forming a hole H through the stacked body 300 using the mask pattern as an etching barrier using an etching process; forming a memory layer 321 in each hole H; and forming a channel layer 323 on each memory layer 321 in the hole H. The hole H passes through the stacked body 300 and extends into the sacrificial substrate 301. Each memory layer 321 includes Fig. 6A The blocking insulating layer 321BI, the data storage layer 321DS and the tunnel insulating layer 321TI are shown. Fig. 6A The blocking insulating layer 321BI, the data storing layer 321DS and the tunnel insulating layer 321TI shown in FIG. Figure 3B The blocking insulating layer 121BI, the data storage layer 121DS and the tunnel insulating layer 121TI are formed of the same material.

[0094] Each channel layer 323 may be formed by depositing a liner semiconductor layer on each memory layer 321. In an embodiment, the hole H may not be completely filled with the channel layer 323, and the central region of each hole H may be open when the channel layer 323 is formed. In this example, forming the cell plug 320 further includes: filling the central region of the hole H surrounded by each channel layer 323 with a core insulating layer 325; removing a portion of each core insulating layer 325 to form a recessed region; and filling the recessed region with a capping pattern 327. The capping pattern 327 may be formed of a doped semiconductor layer. In an embodiment, the capping pattern 327 may include n-type impurities as majority carriers.

[0095] After forming the cell plug 320, the mask pattern may be removed. Subsequently, a first insulating structure 331 is formed to cover the cell plug 320 and the end of the stack 300. One or more slits (not shown) may be formed through the first insulating structure 331 and the stack 300. The plurality of first conductive layers 307 of the stack 300 may be separated into memory blocks or sub-blocks by the one or more slits.

[0096] Although not shown in the drawings, when each of the plurality of first material layers of the stacked body 300 is formed as a sacrificial layer, a process of replacing the sacrificial layer with the first conductive layer 307 through one or more slits is performed.

[0097] As described above, the stacked body 300 includes a first interlayer insulating layer 305, a plurality of first conductive layers 307, and a plurality of second interlayer insulating layers 309. The cell plug 320 extends through the stacked body 300 and protrudes into the sacrificial substrate 301, and may be formed using various methods. According to the above process, the channel layer 323 of each cell plug 320 includes a protrusion 323PP extending in the first direction DR1 beyond the second surface 305S2 of the first interlayer insulating layer 305. Each memory layer 321 includes a first region interposed between the channel layer 323 and the stacked body 300 and a second region covering the protrusion 323PP of the channel layer 323.

[0098] Forming the first structure 350 includes: forming the bit line connection structure 330 after forming the first insulation structure 331. In an embodiment, forming the bit line connection structure 330 includes: forming a conductive bit contact plug 333 in the first insulation structure 331; forming a second insulation structure 335 to cover the conductive bit contact plug 333; forming a conductive pad pattern 337 in the second insulation structure 335; forming a third insulation structure 339 to cover the conductive pad pattern 337; and forming a conductive via structure 341 in the third insulation structure 339. The conductive bit contact plug 333 extends through the first insulation structure 331 and is electrically coupled to the capping pattern 327. Each conductive pad pattern 337 extends through the second insulation structure 335 and is electrically coupled to one of the conductive bit contact plugs 333. The conductive via structure 341 extends through the third insulation structure 339 and is electrically coupled to the conductive pad pattern 337.

[0099] Forming the first structure 350 includes: forming the bit line 345 after forming the bit line connection structure 330. In an embodiment, forming the bit line 345 includes: forming a bit line level insulation layer 343 to cover the conductive via structure 341; forming a trench or opening extending through the bit line level insulation layer 343; and filling the trench or opening with a conductive material. The conductive material filling the trench or opening may be referred to as a bit line 345, and each bit line 345 is electrically connected to one of the conductive via structures 341 of the bit line connection structure 330.

[0100] Forming the first structure 350 further includes: after forming the bit line 345, forming a first conductive connection structure 353 and a first conductive bonding structure 355 of the interconnect structure. The first conductive connection structure 353 and the first conductive bonding structure 355 are formed in the fourth insulating structure 351. The fourth insulating structure 351 is above the bit line level insulating layer 343. Each of the first conductive connection structures 353 contacts one of the bit lines 345 and extends into the fourth insulating structure 351. Each of the first conductive bonding structures 355 contacts one of the first conductive connection structures 353 and has a surface exposed to the outside of the fourth insulating structure 351.

[0101] Figure 5B is a cross-sectional view of a semiconductor memory device during a bonding process between a first structure and a second structure.

[0102] Reference Figure 5B , can be used with reference Figure 5A The second structure 450 is formed by performing a process separately from the process described above. The second structure 450 includes: a peripheral circuit structure 400, which includes a plurality of transistors 405; a second conductive connection structure 430, which is connected to the peripheral circuit structure 400; and a second conductive bonding structure 435, which is connected to the second conductive connection structure 430. The description of the transistor 405, the second conductive connection structure 430 and the second conductive bonding structure 435 refers to the above Figure 3A .

[0103] The transistor 405 of the peripheral circuit structure 400 is formed in an active region of the semiconductor substrate 401. The semiconductor substrate 401 and the transistor 405 are covered by a fifth insulating structure 410. The second conductive connection structure 430 and the second conductive bonding structure 435 are disposed in the fifth insulating structure 410. The second conductive bonding structures 435 each have a surface exposed to the outside of the fifth insulating structure 410.

[0104] The first structure 350 and the second structure 450 are aligned such that the first conductive bonding structure 355 of the first structure 350 is aligned with the second conductive bonding structure 435 of the second structure 450. Subsequently, the first conductive bonding structure 355 and the second conductive bonding structure 435 are bonded to each other to electrically connect the first structure 350 and the second structure 450.

[0105] The subsequent process is described with reference to the following figures and focuses on Figure 5B The area AR2 shown corresponds to the enlarged area.

[0106] Fig. 6A and Figure 6B is a cross-sectional view of a semiconductor memory device during a process of exposing a portion of a tunnel insulating layer.

[0107] Reference Fig. 6A , in reference Figure 5B After the described bonding process, remove Figure 5B The sacrificial substrate 301 is shown. Therefore, the second region of the memory layer 321 covering the protrusion 323PP of the channel layer 323 is exposed.

[0108] The tunnel insulating layer 321TI of the memory layer 321 may include a first region 321TI1 and a second region 321TI2. The first region 321TI1 is a portion or section of the memory layer 321 disposed between the stack 300 and the channel layer 323, and the second region 321TI2 is a portion or section of the memory layer 321 covering the protrusion 323PP of the channel layer 323. The data storage layer 321DS of the memory layer 321 extends along the first region 321TI1 and the second region 321TI2 of the tunnel insulating layer 321TI. The blocking insulating layer 321BI of the memory layer 321 extends along the data storage layer 321DS, and the data storage layer 321DS is disposed between the blocking insulating layer 321BI and the tunnel insulating layer 321TI. Because Figure 5B The sacrificial substrate 301 is shown to be removed, so a portion or section of the blocking insulating layer 321BI extending along the data storage layer 321DS disposed on the second region 321TI2 of the tunnel insulating layer 321TI may be exposed.

[0109] Reference Figure 6B After selectively removing the exposed portion of the blocking insulating layer 321BI, a portion of the data storage layer 321DS covering the second region 321TI2 of the tunnel insulating layer 321TI is selectively removed. As a result, the second region 321TI2 of the tunnel insulating layer 321TI is exposed.

[0110] 7A to 7E It is shown in Figure 6B A cross-sectional view of an embodiment of a semiconductor memory device during a process performed by the semiconductor memory device.

[0111] Reference Fig. 7A , using by reference Figure 6B The described process exposes the second region 321TI2 of the tunnel insulating layer 321TI as a buffer layer to implant the first conductive impurities 361 into at least the second surface 305S2 of the channel layer 323 closest to or surrounded by the first interlayer insulating layer 305. The first conductive impurities 361 may be p-type impurities.

[0112] Reference Figure 7B , in the channel layer 323 as shown in reference Fig. 7A A preliminary doped region 323PD1 is formed in the portion or region implanted with the first conductive impurities 361. Another portion or region of the channel layer 323 interposed between the plurality of first conductive layers 307 and the memory layer 321 may remain as an undoped region 323U.

[0113] Subsequently, a second conductive layer 385 is formed over the second surface 305S2 of the first interlayer insulating layer 305. The second conductive layer 385 is formed to cover at least a portion of the second region 321TI2 of the tunnel insulating layer 321TI. Figure 3A and Figure 3B The second conductive layer 185 is formed of the same conductive material.

[0114] Reference Figure 7C A portion of the second conductive layer 385 is removed to expose a portion of the second region 321TI2 of the tunnel insulating layer 321TI, which covers the resulting protrusion. The remaining second conductive layer 385 forms a source selection line SSL over the second surface 305S2 of the first interlayer insulating layer 305.

[0115] As described above, since the data storage layer 321DS does not remain or exist between the second conductive layer 385 and the channel layer 323, the phenomenon that the threshold voltage of the source selection transistor changes due to the charges stored in the data storage layer 321DS can be improved. The second region 321TI2 of the tunnel insulation layer 321TI can be advantageously retained to serve as a gate insulation layer of the source selection transistor.

[0116] Subsequently, a third interlayer insulating layer 387 is formed over the source selection line SSL. The third interlayer insulating layer 387 is formed to cover at least a portion of the exposed second region 321TI2 of the tunnel insulating layer 321TI.

[0117] Reference Fig.7D , a portion of the third interlayer insulating layer 387 is removed to expose a portion of the second region 321TI2 of the tunnel insulating layer 321TI. The third interlayer insulating layer 387 may remain to cover the source selection line SSL. The end of the second region 321TI2 of the tunnel insulating layer 321TI may be removed during the process of removing a portion of the third interlayer insulating layer 387 or using a separate etching process. As a result, the end of the protrusion 323PP of the channel layer 323 extending beyond the third interlayer insulating layer 387 is exposed.

[0118] Reference Fig. 7E , a second conductive impurity opposite to the first conductive impurity is doped into Fig.7D The protrusion 323PP and the preliminary doped region 323PD1 of the channel layer 323 are shown.

[0119] In an embodiment, doping the second conductive impurities includes: forming a doped semiconductor layer 391 over the third interlayer insulating layer 387 and contacting the exposed end of the protrusion 323PP; and diffusing the impurities from the doped semiconductor layer 391 to the exposed end of the protrusion 323PP; Fig.7D The protrusion 323PP and the preliminary doped region 323PD1 of the channel layer 323 are shown.

[0120] The doped semiconductor layer 391 includes a second conductive impurity. The second conductive impurity may be an n-type impurity. As the second conductive impurity diffuses from the doped semiconductor layer 391 to Fig.7D In the preliminary doping region 323PD1 shown, a first doping region 323D1 and a second doping region 323D2 are formed in the channel layer 323 .

[0121] As described above, when the first doping region 323D1 includes p-type impurities at a higher concentration than the second doping region 323D2, the threshold voltage of the first doping region 323D1 is higher than the threshold voltage of the second doping region 323D2. Therefore, the threshold voltage characteristics of the source selection transistor coupled to the source selection line SSL can be improved or ensured.

[0122] FIG. 8A to FIG. 8E It is shown that in the application Figure 6B A cross-sectional view of an embodiment of a semiconductor memory device during a process performed after a process of a semiconductor memory device of FIG. FIG. 8A to FIG. 8E Configuration or reference 7A to 7E Description of configurations similar or identical to those described in the description of the process.

[0123] Reference Fig. 8A A gate insulating layer 381 is formed on the second surface 305S2 of the first interlayer insulating layer 305 to cover the gate insulating layer 381 through the reference Figure 6B The described process exposes the second region 321TI2 of the tunnel insulation layer 321TI.

[0124] Subsequently, a second conductive layer 385 is formed over the gate insulating layer 381. The second conductive layer 385 is formed over a surface of the gate insulating layer 381 or on a surface of the gate insulating layer 381.

[0125] Reference Figure 8B , a portion of the second conductive layer 385 is removed to expose the gate insulating layer 381. The remaining second conductive layer 385 forms a source selection line SSL over the gate insulating layer 381. When the gate insulating layer 381 is interposed between the source selection line SSL and the protrusion 323PP of the channel layer 323, the source selection line SSL may surround a portion of the protrusion 323PP.

[0126] As described above, since the gate insulating layer 381 is additionally deposited after a portion of the data storage layer 321DS is removed, the deposition thickness of the gate insulating layer 381 may be controlled or determined according to the selected threshold voltage or target threshold voltage of the source selection transistor coupled to the source selection line SSL. Therefore, the threshold voltage of the source selection transistor may be improved or ensured to be higher than the initial threshold voltage of the memory cell coupled to the word line WL.

[0127] Reference Figure 8C , a third interlayer insulating layer 387 is formed over the source selection line SSL. The third interlayer insulating layer 387 is formed to cover the exposed surface of the gate insulating layer 381.

[0128] Reference Fig.8D To expose the end of the protrusion 323PP in the channel layer 323, remove Figure 8C A portion of the third interlayer insulating layer 387, a portion of the gate insulating layer 381, and a portion of the second region 321TI2 of the tunnel insulating layer 321TI are shown. The third interlayer insulating layer 387 remains to cover or isolate the source selection line SSL.

[0129] Reference Fig. 8E , a portion of the protrusion 322PP of the channel layer 323 is doped with n-type impurities.

[0130] In an implementation, doping the n-type impurities includes: forming a doped semiconductor layer 391 over the third interlayer insulating layer 387 and contacting the exposed end of the protrusion 323PP; and diffusing the impurities from the doped semiconductor layer 391 into the protrusion 323PP of the channel layer 323 .

[0131] The doped semiconductor layer 391 includes a second conductive impurity, which may be an n-type impurity. As the n-type impurity diffuses from the doped semiconductor layer 391 into the protrusion 323PP, a doped region 323D is formed in the channel layer 323. A portion of the channel layer 323 into which the impurity is not diffused remains as an undoped region 323U.

[0132] Fig. 9 is a block diagram illustrating an electronic system including a semiconductor memory device according to an embodiment of the present disclosure.

[0133] Reference Fig. 9 The electronic system 1000 may be a computing system, a medical device, a communication device, a wearable device, a memory system, etc. The electronic system 1000 includes a host 1100 and a storage device 1200 .

[0134] The host 1100 stores data in the storage device 1200, or reads data stored in the storage device 1200 using an interface. The interface may include at least one of a double data rate (DDR) interface, a universal serial bus (USB) interface, a multimedia card (MMC) interface, an embedded MMC (eMMC) interface, a peripheral component interconnect (PCI) interface, a high-speed PCI (PCI-E) interface, an advanced technology attachment (ATA) interface, a serial ATA (SATA) interface, a parallel ATA (PATA) interface, a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE) interface, a Firewire interface, a universal flash memory (UFS) interface, and a high-speed non-volatile memory (NVMe) interface.

[0135] The memory device 1200 includes a memory controller 1210 and a semiconductor memory device 1220. In an implementation, the memory device 1200 may be configured to form a solid state drive (SSD), a universal serial bus (USB) memory, or the like.

[0136] The memory controller 1210 may store data in the semiconductor memory device 1220 or read data stored in the semiconductor memory device 1220 under the control of the host 1100 .

[0137] The semiconductor memory device 1220 may include one memory chip or a plurality of memory chips. The semiconductor memory device 1220 may store data or output stored data under the control of the memory controller 1210.

[0138] The semiconductor memory device 1220 may be a nonvolatile memory device. Figure 3A , Figure 3B and Figure 4 As described above, the semiconductor memory device 1220 may include a channel layer and a source selection line surrounding a sidewall of a portion of the channel layer. The portion of the channel layer may be as described above with reference to Figure 3B The local doping is p-type impurities, or the gate insulating layer can be as described above. Figure 4 The interposition between the portion of the channel layer and the source select line thus enables a threshold voltage of a source select transistor coupled to the source select line to be controlled.

[0139] According to various embodiments of the present disclosure, since no data storage layer is interposed between the source selection line and the channel layer, there is no need to perform a program operation or an erase operation for controlling a threshold voltage of a source selection transistor.

[0140] CROSS-REFERENCE TO RELATED APPLICATIONS

[0141] This application claims the priority of Korean Patent Application No. 10-2023-0137747 filed in the Korean Intellectual Property Office on October 16, 2023, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor memory device, comprising: a channel layer, the channel layer comprising a first region, a second region extending from the first region in a first direction, and a third region extending from the second region in the first direction, wherein the second region contains p-type impurities; a plurality of word lines stacked along sidewalls of the first region and spaced apart from each other in the first direction; a source selection line spaced apart from the plurality of word lines in the first direction, at least one section of the source selection line surrounding at least a portion of the second region in the channel layer; a data storage layer interposed between the plurality of word lines and the channel layer; and A tunnel insulating layer is interposed between the data storage layer and the channel layer and extends beyond the data storage layer in the first direction such that the tunnel insulating layer is interposed between the channel layer and the source selection line.

2. The semiconductor memory device according to claim 1, in, The second region contains the p-type impurity at a higher concentration than the first region and the third region.

3. The semiconductor memory device according to claim 1, in, A boundary between the first region and the second region in the channel layer is located at a height between the source selection line and the first word line, and The first word line is a word line closest to the source selection line among the plurality of word lines.

4. The semiconductor memory device according to claim 1, in, The source selection line includes a first surface facing the plurality of word lines and a second surface opposite to the first surface; and Wherein, a boundary between the second region and the third region in the channel layer is located at a height between the first surface and the second surface of the source selection line.

5. The semiconductor memory device according to claim 1, wherein: The first region in the channel layer is an undoped region.

6. The semiconductor memory device according to claim 1, wherein: The second region in the channel layer contains n-type impurities and the p-type impurities.

7. The semiconductor memory device according to claim 1, further comprising a doped semiconductor layer spaced apart from the source selection line in the first direction and contacting the third region in the channel layer, wherein: The third region in the channel layer and the doped semiconductor layer each contain n-type impurities as majority carriers.

8. The semiconductor memory device according to claim 1, wherein: A threshold voltage of the second region in the channel layer is higher than a threshold voltage of the third region.

9. The semiconductor memory device according to claim 1, in, The source selection line includes a first surface facing the plurality of word lines and a second surface opposite to the first surface; wherein the data storage layer contacts the first surface of the source selection line; and The tunnel insulation layer protrudes beyond the second surface of the source selection line in the first direction.

10. The semiconductor memory device according to claim 9, further comprising a blocking insulating layer interposed between the plurality of word lines and the data storage layer, wherein The blocking insulating layer contacts the first surface of the source selection line.

11. The semiconductor memory device according to claim 1, further comprising: a doped semiconductor layer, the doped semiconductor layer being spaced apart from the source selection line in the first direction and contacting the third region in the channel layer; a first interlayer insulating layer, the first interlayer insulating layer being disposed between the source selection line and the plurality of word lines; a second interlayer insulating layer disposed between each pair of consecutive word lines in the plurality of word lines; as well as A third interlayer insulating layer is disposed between the source selection line and the doped semiconductor layer.

12. A semiconductor memory device, the semiconductor memory device comprising: a channel layer extending in a first direction; a plurality of word lines stacked along sidewalls of the channel layer and spaced apart from each other in the first direction; a source selection line spaced apart from the plurality of word lines in the first direction and spaced apart from the sidewall of the channel layer in a second direction perpendicular to the first direction; a doped semiconductor layer, the doped semiconductor layer being spaced apart from the source selection line in the first direction and contacting an end portion of the channel layer; a gate insulating layer including a first member interposed between the channel layer and the source selection line; as well as a data storage layer interposed between the plurality of word lines and the channel layer; Wherein, the first component of the gate insulating layer is aligned with the data storage layer in the first direction.

13. The semiconductor memory device according to claim 12, in, The source selection line includes a first surface facing the plurality of word lines and a second surface facing the doped semiconductor layer; and The gate insulating layer further includes a second component extending along the first surface of the source selection line.

14. The semiconductor memory device according to claim 12, wherein: In the second direction, the first member of the gate insulating layer is formed to have a thickness greater than a thickness of the data storage layer.

15. The semiconductor memory device according to claim 12, further comprising a tunnel insulating layer interposed between the sidewall of the channel layer and the data storage layer and extending in the first direction to be interposed between the first member of the gate insulating layer and the channel layer.

16. The semiconductor memory device according to claim 15, wherein: In the second direction, the first member of the gate insulating layer is formed to have a thickness greater than a thickness of the tunnel insulating layer.

17. The semiconductor memory device according to claim 12, further comprising a blocking insulating layer interposed between the plurality of word lines and the data storage layer, wherein The first member of the gate insulating layer is aligned with the blocking insulating layer in the first direction.

18. The semiconductor memory device according to claim 17, wherein: In the second direction, the first member of the gate insulating layer is formed to have a thickness greater than a thickness of the blocking insulating layer.

19. The semiconductor memory device according to claim 12, in, The source selection line includes a first surface facing the plurality of word lines and a second surface facing the doped semiconductor layer; wherein the channel layer comprises an undoped region surrounded by the plurality of word lines and a doped region distributed from the end of the channel layer toward the undoped region; and The boundary between the undoped region and the doped region is located at a height between the first surface of the source selection line and the second surface of the source selection line.

20. The semiconductor memory device according to claim 19, wherein The doped region of the channel layer and the doped semiconductor layer each contain n-type impurities as majority carriers.

21. The semiconductor memory device according to claim 12, further comprising: a first interlayer insulating layer, the first interlayer insulating layer being disposed between the source selection line and the plurality of word lines; a second interlayer insulating layer disposed between each pair of consecutive word lines in the plurality of word lines; as well as A third interlayer insulating layer is disposed between the source selection line and the doped semiconductor layer.

22. A semiconductor memory device, the semiconductor memory device comprising: a channel layer extending in a first direction and including a first region having doped impurities; a plurality of word lines stacked along sidewalls of the channel layer and spaced apart from each other in the first direction; a source selection line spaced apart from the plurality of word lines in the first direction and spaced apart from the sidewall of the channel layer in a second direction perpendicular to the first direction; a doped semiconductor layer, the doped semiconductor layer contacting an end of the channel layer; as well as a gate insulating layer including a first member interposed between the channel layer and the source selection line; wherein the first region is at least partially disposed at the height of the source selection line; and Wherein, the thickness of the gate insulating layer establishes a threshold voltage characteristic of a source select transistor associated with the source select line.

23. A method for manufacturing a semiconductor memory device, the method comprising the steps of: forming a stacked body including a first interlayer insulating layer and a plurality of word lines, the first interlayer insulating layer having a first surface and a second surface facing opposite directions, and the plurality of word lines and a plurality of second interlayer insulating layers are alternately stacked over the first surface of the first interlayer insulating layer; forming a cell plug, the cell plug comprising a channel layer, a tunnel insulating layer, a data storage layer and a blocking insulating layer, the channel layer extending through the stack and having a protrusion extending beyond the second surface of the first interlayer insulating layer, the tunnel insulating layer comprising a first region interposed between the channel layer and the stack and a second region covering the protrusion of the channel layer, the data storage layer extending along the first region and the second region of the tunnel insulating layer, and the blocking insulating layer extending along the data storage layer, wherein the data storage layer is interposed between the tunnel insulating layer and the blocking insulating layer; removing a portion of the blocking insulating layer and a portion of the data storing layer in sequence to expose the second region of the tunnel insulating layer; forming a preliminary doping region in the channel layer by implanting impurities of a first conductivity type into a region of the channel layer surrounded by at least the second surface of the first interlayer insulating layer; and A source selection line is formed over the second surface of the first interlayer insulating layer.

24. The method according to claim 23, further comprising the steps of: forming a third interlayer insulating layer above the source selection line; exposing an end portion of the protrusion of the channel layer by removing an end portion of the second region of the tunnel insulating layer; as well as Impurities of a second conductivity type opposite to the first conductivity type are doped in each of the protrusion and the preliminary doping region of the channel layer.

25. The method according to claim 24, further comprising the steps of: A doped semiconductor layer is formed contacting an end portion of the protrusion of the channel layer.

26. The method according to claim 25, wherein: The doped semiconductor layer includes impurities of the second conductivity type, and The second conductivity type impurities diffuse from the doped semiconductor layer toward the preliminary doping region, so that the protrusion of the channel layer and the preliminary doping region are doped with the second conductivity type impurities.

27. The method according to claim 24, wherein: The first conductivity type impurity is a p-type impurity, and The second conductivity type impurity is an n-type impurity.

28. A method for manufacturing a semiconductor memory device, the method comprising the steps of: forming a stacked body including a first interlayer insulating layer and a plurality of word lines, the first interlayer insulating layer having a first surface and a second surface facing in opposite directions, the plurality of word lines and a plurality of second interlayer insulating layers being alternately stacked over the first surface of the first interlayer insulating layer; forming a cell plug, the cell plug comprising a channel layer, a tunnel insulating layer, a data storage layer and a blocking insulating layer, the channel layer extending through the stack and having a protrusion extending beyond the second surface of the first interlayer insulating layer, the tunnel insulating layer comprising a first region interposed between the channel layer and the stack and a second region covering the protrusion of the channel layer, the data storage layer extending along the first region and the second region of the tunnel insulating layer, and the blocking insulating layer extending along the data storage layer, wherein the data storage layer is interposed between the tunnel insulating layer and the blocking insulating layer; removing a portion of the blocking insulating layer and a portion of the data storing layer in sequence to expose the second region of the tunnel insulating layer; forming a gate insulating layer covering the exposed second region of the tunnel insulating layer; and A source selection line is formed over the gate insulating layer.

29. The method according to claim 28, further comprising the steps of: forming a third interlayer insulating layer above the source selection line; removing a portion of the third interlayer insulating layer, a portion of the gate insulating layer, and a portion of the second region of the tunnel insulating layer to expose an end portion of the protrusion of the channel layer; as well as A portion of the protrusion of the channel layer is doped with an n-type impurity.

30. The method according to claim 29, further comprising the steps of: A doped semiconductor layer is formed contacting an end portion of the protrusion of the channel layer.

31. The method according to claim 30, wherein: The doped semiconductor layer includes the n-type impurities, and The n-type impurities diffuse from the doped semiconductor layer into the protrusions of the channel layer so that the protrusions are doped with the n-type impurities.

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