Power semiconductor device and preparation method thereof

Abstract

The invention relates to the technical field of semiconductor manufacturing, and discloses a power semiconductor device and a preparation method thereof. The preparation method comprises the following steps: forming an epitaxial layer on one side surface of a substrate layer; a first target area on the surface of the epitaxial layer is oxidized to form an oxidation structure, the oxidation structure comprises a first oxidation part located in the first target area and a second oxidation part extending into a second target area, and the surface of one side of the epitaxial layer comprises the first target area and the second target area; forming a groove extending into the epitaxial layer, wherein the first oxidation part is removed in the groove forming process; forming a gate oxide layer on the inner wall of the groove, wherein the gate oxide layer at least covers one end, close to the substrate layer, of the second oxidation part; and forming a gate in the trench with the gate oxide layer. The second oxidation part is located at the corner, close to the groove, of the epitaxial layer and connected with the gate oxide layer, conductive substances on the two sides can be effectively isolated, and reverse electric leakage is prevented from being increased; and the second oxidation part is formed before the groove, so that the pollution to the inner wall surface of the groove is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a power semiconductor device and a preparation method thereof. Background Art

[0002] TMBS (Trench MOS Barrier Schottky) device is a new type of power semiconductor device that combines MOS drain structure and Schottky barrier. It reduces the electric field strength at the Schottky barrier by utilizing the "charge coupling" effect, thereby reducing the forward conduction voltage drop and obtaining a lower reverse leakage current. It is widely used in freewheeling diodes, smartphone chargers, solar cells and other products.

[0003] The process of preparing a TMBS device may include: etching a silicon layer to form a groove, forming a gate oxide layer on the sidewall of the groove, filling polysilicon in the groove, flattening the surface by setting an interlayer electrical insulating material and etching, depositing a metal on the etched silicon layer to form a barrier layer, and depositing a metal electrode layer on the entire surface. However, when etching the interlayer electrical insulating layer material, if the gas supply fluctuates greatly or the ratio of the formulated gas is inappropriate during the etching process, the sidewall gate oxide layer near the device surface in the groove is easily over-etched. If the gate oxide layer is damaged, the silicon layer cannot be effectively isolated from the surface metal layer, resulting in direct contact between the silicon layer and the surface metal layer, causing the reverse leakage of the device to increase, and ultimately leading to device failure. Summary of the invention

[0004] In view of this, the present invention provides a power semiconductor device and a preparation method thereof to solve the problem that the sidewall gate oxide layer in the trench of the existing TMBS device close to the device surface is easily over-etched, resulting in the inability to effectively isolate the conductive materials on both sides.

[0005] In a first aspect, the present invention provides a method for preparing a power semiconductor device, comprising:

[0006] forming an epitaxial layer on a surface of one side of the substrate layer;

[0007] Performing oxidation treatment on a first target area on a side surface of the epitaxial layer facing away from the substrate layer to form an oxidation structure; the oxidation structure includes a first oxidation portion located in the first target area and a second oxidation portion extending into the second target area, and a side surface of the epitaxial layer includes the first target area and the second target area surrounding the first target area;

[0008] forming a trench extending into the epitaxial layer, wherein the first oxide portion is removed during the trench formation;

[0009] forming a gate oxide layer on the inner wall of the trench, wherein the gate oxide layer at least covers one end of the second oxide portion close to the substrate layer;

[0010] A gate is formed in the trench having a gate oxide layer.

[0011] Beneficial effect: The method for preparing a power semiconductor device of the present invention, before the groove is formed, first extends downward from the surface of the epitaxial layer into the interior to form an integral oxide structure; then the first oxide portion located in the first target area of ​​the integral oxide structure and part of the epitaxial layer below the first oxide portion are etched to form a groove of the required depth, and at the same time, the second oxide portion in the integral oxide structure is filled in the corner position of the groove and the surface of the epitaxial layer, and then a gate oxide layer and a gate are formed in the groove. Since the second oxide portion is located at the corner position of the epitaxial layer close to the groove, even if the etching process is performed on one side of the epitaxial layer surface until the epitaxial layer surface and the gate are exposed, the second oxide portion still retains a sufficient thickness, and together with the gate oxide layer, the epitaxial layer at the end edge of the groove is covered, the fault tolerance rate is high, and the process window capability of the single-step etching is significantly broadened, and the conductive materials on both sides can be effectively isolated to avoid the increase of reverse leakage of the device, thereby ensuring the performance of the device. In addition, the second oxide portion at the upper edge of the groove is formed before the groove is formed, which facilitates the compatibility of subsequent processes. The groove is formed after the second oxide portion, which can avoid the contamination of the inner surface of the groove by materials deposited on the surface of the device and the problem of incomplete removal of impurities, thereby ensuring the quality of the device.

[0012] In an optional embodiment, after forming the epitaxial layer on one side surface of the substrate layer and before performing oxidation treatment on the first target area on the side surface of the epitaxial layer away from the substrate layer, the method further includes: forming a protective layer on the side surface of the epitaxial layer away from the substrate layer, wherein the protective layer has a first opening to expose the first target area of ​​the epitaxial layer;

[0013] After the first target area on the surface of the epitaxial layer facing away from the substrate layer is oxidized and before the trench extending into the epitaxial layer is formed, the method further includes: removing the protective layer.

[0014] Beneficial effects: By providing a protective layer of silicon nitride with a first opening, precise oxidation of the target area can be achieved, and it is helpful to form a thick second oxide portion at the edge position above the subsequent trench. It is compatible with other conventional process steps, reduces additional steps, and has simple process preparation steps and low cost.

[0015] In an optional embodiment, after forming the epitaxial layer on one side surface of the substrate layer and before forming the protective layer on the side surface of the epitaxial layer facing away from the substrate layer, the method further includes:

[0016] A pad oxide layer is formed on a surface of the epitaxial layer facing away from the substrate layer, and the pad oxide layer covers a first target region and a second target region on a surface of the epitaxial layer.

[0017] Beneficial effects: The pad oxide layer can reduce the stress of the subsequently deposited silicon nitride protective layer, and avoid the excessive stress generated by the subsequent high-temperature deposited protective layer after the temperature drops to 25°C, which may cause the device to break directly; in addition, the formed thin layer of pad oxide layer can also help guide the lateral diffusion during the subsequent oxidation process of forming the first oxide part and the second oxide part.

[0018] In an optional embodiment, in the step of oxidizing the first target region on the surface of the epitaxial layer facing away from the substrate layer, the thickness of the formed first oxide portion gradually decreases from the middle portion to the outside, and in the direction perpendicular to the surface of the epitaxial layer, the highest point of the first oxide portion is higher than the surface of the second target region of the epitaxial layer, and the lowest point of the second oxide portion is lower than the surface of the second target region of the epitaxial layer; the thickness range of the first oxide portion is

[0019] The thickness of the second oxide portion at one end close to the first oxide portion is equal to the outermost side of the first oxide portion, and the thickness of the second oxide portion gradually decreases from the end close to the first oxide portion to the outside; the highest point of the second oxide portion is higher than the surface of the second target area of ​​the epitaxial layer, and the lowest point of the second oxide portion is lower than the surface of the second target area of ​​the epitaxial layer.

[0020] Beneficial effect: In the present invention, the second oxide portion is formed synchronously with the first oxide portion, and appears to extend laterally from the first oxide portion; in the vertical direction perpendicular to the surface of the epitaxial layer, a portion of the first oxide portion and a portion of the second oxide portion extend into the epitaxial layer, and a portion protrudes from the surface of the epitaxial layer. Such a structure can ensure that in the horizontal direction, in addition to the first oxide portion area etched by the groove, a second oxide portion area with sufficient thickness is still retained after etching, and can also ensure that the second oxide portion has sufficient thickness in the vertical direction.

[0021] In an optional embodiment, after forming a gate in a trench having a gate oxide layer, the method further includes:

[0022] forming an insulating dielectric layer on a surface of the epitaxial layer facing away from the substrate layer, and heating the insulating dielectric layer to flatten the surface of the second target region of the epitaxial layer;

[0023] The insulating dielectric layer on the surface of the epitaxial layer facing away from the substrate layer is removed to expose the surface of the second target area of ​​the epitaxial layer and the gate, and the remaining second oxide portion is connected to the gate oxide layer.

[0024] Beneficial effect: An insulating dielectric layer is deposited on the entire surface of one side of the upper surface of the epitaxial layer, and the insulating dielectric layer covers the surface of the second target area of ​​the epitaxial layer and the exposed gate and the second oxide portion, and then the insulating dielectric layer is heated and annealed, which can eliminate the surface defects of the second target area of ​​the epitaxial layer below the insulating dielectric layer and improve the surface quality of the epitaxial layer between adjacent grooves. It is then removed by etching. In the present invention, the second oxide portion is set at the surface corner position of the groove and the second target area of ​​the epitaxial layer, and the thickness of the second oxide portion is greater than the thickness of the gate oxide layer. Therefore, even if the process formula has a certain error, the second oxide portion still has a sufficient thickness to effectively isolate the conductive materials on both sides.

[0025] In an optional embodiment, forming a gate oxide layer on the inner wall surface of the trench further includes: forming a surface oxide layer on the surface of the second target region of the epitaxial layer, the surface oxide layer is connected to the second oxide portion, and the thickness of the surface oxide layer is equal to the thickness of the gate oxide layer; the thickness of the surface oxide layer and the gate oxide layer is less than the thickness of the second oxide portion;

[0026] Removing the insulating dielectric layer on the surface of the epitaxial layer facing away from the substrate layer also includes: removing the surface oxide layer.

[0027] Beneficial effects: Dry oxidation simultaneously forms a gate oxide layer located on the inner wall of the groove and a surface oxide layer located on the surface of the epitaxial layer, and both the gate oxide layer and the surface oxide layer are connected to the second oxide portion; that is, the second oxide portion is arranged at a corner position of the formed overall oxide film layer, and the overall oxide film layer is separated into a gate oxide layer and a surface oxide layer, and the thickness of the second oxide portion of the separation portion is greater than that of the gate oxide layer and the surface oxide layer, which helps to ensure effective isolation of conductive materials on both sides in subsequent etching.

[0028] In an optional implementation, the distance between the surface of the gate facing away from the substrate layer and the surface of the second target region of the epitaxial layer is in a range of 0.2 μm to 0.25 μm.

[0029] Beneficial effect: The above-mentioned limited distance range can avoid the problem of polysilicon loss caused by the upper surface of the gate in the trench being too close to the surface of the epitaxial layer, thereby preventing the MOS from regulating the electric field on the device surface; and avoid the problem of excessive etching of the epitaxial layer and shallowing of the trench, which affects the drift of the device electrical parameters, due to the surface of the polysilicon gate in the trench being too far from the upper surface of the epitaxial layer.

[0030] In an optional implementation manner, after removing the insulating dielectric layer on the surface of the epitaxial layer facing away from the substrate layer, the method further includes:

[0031] forming a barrier layer on the surface of the second target region of the epitaxial layer, the barrier layer covering at least a portion of the second oxide portion; the barrier layer, the second oxide portion and the gate oxide layer are connected, and are suitable for isolating the epitaxial layer from the external structure;

[0032] A metal layer is formed on a side of the barrier layer facing away from the substrate layer, and the metal layer covers the barrier layer, the second oxide portion and the gate.

[0033] Beneficial effects: The barrier layer and the surface of the epitaxial layer achieve reliable Schottky contact, and the barrier layer, the second oxide portion and the gate oxide layer are connected to form an effective isolation for the epitaxial layer and the metal layer, reducing the reverse leakage of the device, thereby improving the performance of the device.

[0034] In a second aspect, the present invention also provides a power semiconductor device, comprising: a substrate layer, an epitaxial layer, a groove, a gate oxide layer, a gate, and a second oxide portion, wherein the epitaxial layer is formed on one side surface of the substrate layer, and the side surface of the epitaxial layer facing away from the substrate layer includes a first target area and a second target area outside the first target area; the groove is formed in the first target area of ​​the epitaxial layer; the gate oxide layer is formed on the inner wall of the groove; the gate is formed in the trench having the gate oxide layer; the second oxide portion extends into the second target area arranged on one side surface of the epitaxial layer, and is connected to the gate oxide layer in the groove, and the second oxide portion covers the connection between the first target area and the second target area of ​​the epitaxial layer.

[0035] Beneficial effects: In the power semiconductor device of the present invention, the second oxide portion extending into the epitaxial layer is located beside the end of the trench, that is, at the corner between the trench and the surface of the silicon epitaxial layer, and the thickness of the second oxide portion is greater than the thickness of the gate oxide layer, which can effectively ensure that when etching is performed on one side of the epitaxial layer surface, even if an etching error occurs, a sufficiently thick second oxide portion can still be retained to achieve effective isolation of the conductive materials on both sides, reduce the reverse leakage of the device, and thereby ensure device performance.

[0036] In an optional embodiment, it also includes: a barrier layer and a metal layer, the barrier layer is formed on the surface of the second target area of ​​the epitaxial layer, and the barrier layer covers at least a portion of the second oxide portion; the barrier layer, the second oxide portion and the gate oxide layer are connected and are suitable for isolating the epitaxial layer and the external structure; the metal layer is formed on the side of the barrier layer away from the substrate layer to cover the barrier layer, the second oxide portion and the gate.

[0037] Beneficial effects: The barrier layer and the surface of the epitaxial layer achieve reliable Schottky contact, and the barrier layer, the second oxide portion and the gate oxide layer are connected to form an effective isolation for the epitaxial layer and the metal layer, reducing the reverse leakage of the device, thereby improving the performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0039] Figure 1 It is a schematic diagram of the structure after the interlayer electrical insulating material is set in the device preparation process in the related art;

[0040] Figure 2 It is a schematic diagram of the structure after etching the interlayer electrical insulating material in the device preparation process in the related art;

[0041] Figure 3 It is a schematic diagram of the structure of a power device in the related art;

[0042] Figure 4 is a schematic flow chart of a method for preparing a power semiconductor device according to an embodiment of the present invention;

[0043] Figure 5 is a schematic diagram of the structure after forming the first oxidation portion and the second oxidation portion according to an embodiment of the present invention;

[0044] Figure 6 is a schematic diagram of the structure after a hard mask layer is provided in an embodiment of the present invention;

[0045] Figure 7 is a schematic diagram of the structure after the first oxidation portion is removed according to an embodiment of the present invention;

[0046] Figure 8 is a schematic diagram of the structure after the groove is formed in an embodiment of the present invention;

[0047] Fig. 9 is a schematic diagram of the structure after forming a gate oxide layer and a surface oxide layer in an embodiment of the present invention;

[0048] Fig.10 is a schematic diagram of the structure after a gate is filled in a trench according to an embodiment of the present invention;

[0049] Fig.11 is a schematic structural diagram of an embodiment of the present invention after a protective layer is provided on the epitaxial layer;

[0050] Fig.12 is a schematic diagram of the structure of the embodiment of the present invention after the first opening position of the protective layer is oxidized;

[0051] Fig.13 is a schematic diagram of the structure of an embodiment of the present invention after an insulating dielectric layer is provided;

[0052] Fig.14 is a schematic diagram of the structure after the insulating dielectric layer is removed by etching in an embodiment of the present invention;

[0053] Fig.15 It is a schematic structural diagram of a power semiconductor device according to an embodiment of the present invention.

[0054] Description of reference numerals:

[0055] 100, protective layer; 101, first opening; 200, hard mask layer; 201, second opening;

[0056] 1. Substrate layer; 2. Epitaxial layer; 21. First target region; 22. Second target region; 3. Oxidation structure; 31. First oxide portion; 32. Second oxide portion; 4. Trench; 51. Gate oxide layer; 52. Surface oxide layer; 6. Gate; 7. Insulating dielectric layer; 8. Barrier layer; 9. Metal layer. DETAILED DESCRIPTION

[0057] The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only some structures related to the present invention are shown in the accompanying drawings, rather than all structures. In the following description, the description of known structures and technologies is omitted to avoid unnecessary confusion of the concept of the present invention. Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified for the purpose of clear expression, and some details may be omitted. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships between them are only exemplary, and may be deviated due to manufacturing tolerances or technical limitations in practice, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs. In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. In addition, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0058] Among many power semiconductor devices, TMBS devices that combine MOS drain structure and Schottky barrier are used in many products because of their low forward conduction voltage drop and low reverse leakage current. TMBS devices usually include multiple cell regions designed on demand. This application only describes the relevant structure of the cell region and its preparation process. Figures 1 to 3In the related art, after forming an epitaxial layer 2 on a substrate layer 1, forming a trench 4 on the epitaxial layer 2, and forming a gate oxide layer 51 and a gate 6 in the trench 4, the surface of the epitaxial layer 2 facing away from the substrate layer 1 is entirely covered with a Figure 1 The insulating dielectric layer 7 is then etched until the epitaxial layer 2 is exposed, so as to smooth the surface of the epitaxial layer 2 between the trenches 4, thereby reducing the reverse leakage of the device and exposing the gate 6 for subsequent connection with the metal layer 9. However, during the above-mentioned etching of the insulating dielectric layer 7, the gate oxide layer 51 ( Figure 2 As shown in the A part of the figure, the epitaxial layer 2 is etched away together until the surface of the epitaxial layer 2 is exposed. Therefore, the barrier layer 8 and the metal layer 9 are formed in the subsequent step. Figure 3 In the structure shown in FIG. 1 , since the thickness of the gate oxide layer 51 is set to be relatively thin and the epitaxial layer 2 needs to be exposed by etching, Figure 2 If the etching gas formula is not suitable for the area circled in the middle, the gate oxide layer 51 is easily over-etched and cannot form effective isolation, resulting in direct contact between the metal layer 9 and the epitaxial layer 2, causing the reverse leakage of the device to increase or even fail.

[0059] Based on this, see Figures 4 to 15 This embodiment provides a method for preparing a power semiconductor device. Figure 4 The schematic diagram of the preparation method is shown in FIG. 1 , and the preparation method comprises the following steps:

[0060] Step S401 : forming an epitaxial layer 2 on one side surface of the substrate layer 1 .

[0061] In this embodiment, the power semiconductor is a TMBS device as an example for explanation. Exemplarily, the substrate layer 1 is a silicon-based substrate, and the epitaxial layer 2 is a silicon epitaxial layer formed on one side of the silicon-based substrate.

[0062] In step S402, the first target region 21 of the epitaxial layer 2 facing away from the substrate layer 1 is oxidized to form an oxidation structure 3; the oxidation structure 3 includes a first oxidation portion 31 located in the first target region 21 and a second oxidation portion 32 extending into the second target region 22, and one side surface of the epitaxial layer 2 includes the first target region 21 and the second target region 22 surrounding the first target region 21.

[0063] like Figure 5As shown, in this embodiment, an epitaxial layer 2 is formed on the upper surface of the substrate layer 1, and the epitaxial layer 2 is divided into a plurality of first target regions 21 and second target regions 22 based on the horizontal plane. The second target regions 22 are outside the first target regions 21, and the second target regions 22 are between adjacent first target regions 21. The first target region 21 on one side of the upper surface of the epitaxial layer 2 is oxidized to form an oxidation structure 3 integrally on the epitaxial layer 2, including a first oxidation portion 31 located in the first target region 21 and a second oxidation portion 32 located at the edge of the second target region 22 near the first target region 21. The first oxidation portion 31 and the second oxidation portion 32 are both made of silicon dioxide. Specifically, vertical oxidation diffusion is generated in the first target region 21 to form the first oxidation portion 31, and lateral oxidation diffusion is generated at the same time. Due to the influence of the concentration gradient, a silicon dioxide layer with a gradually decreasing volume is generated in the lateral direction, that is, the second oxidation portion 32 is formed.

[0064] Step S403 , forming a trench 4 extending into the epitaxial layer 2 , and the first oxide portion 31 is removed during the formation of the trench 4 .

[0065] Exemplarily, a hard mask layer 200 having a second opening 201 is provided on the upper surface of the epitaxial layer 2, the first oxide portion 31 on the first target region 21 of the epitaxial layer 2 exposed by the second opening 201 is etched away, and the epitaxial layer 2 is etched downward to a certain depth to form a groove 4. Specifically, vaporized tetraethoxysilane (hereinafter referred to as TEOS) and pure oxygen are introduced into a chemical vapor deposition (CVD) device, and the two react at high temperature to generate silicon dioxide, and other gaseous impurities generated after the reaction are extracted out of the device. Silicon dioxide accumulates on the surface of the epitaxial layer 2 as a deposit to form a silicon dioxide film having a thickness of 1000 Å. Then, a patterned photomask is placed on the silicon dioxide film to remove a portion of the silicon dioxide film on the first target region 21 of the epitaxial layer 2, thereby forming a hard mask layer 200 having a second opening 201. Figure 6 shown; see later Figure 7 , the first oxide portion 31 exposed by the second opening 201 is etched away to expose the first target region 21 of the epitaxial layer 2; then, the material of a part of the depth in the first target region 21 of the epitaxial layer 2 is removed by dry etching, and a trench 4 is formed in the first target region 21 of the epitaxial layer 2, such as Figure 8 As shown, the depth of the trench 4 formed in this embodiment ranges from 1.8 μm to 2.3 μm. It can be seen that the thickness of the epitaxial layer 2 is greater than the depth of the trench 4 .

[0066] At this time, the second oxide portion 32 is located at the corner between the upper opening of the groove 4 formed after etching and the surface of the epitaxial layer 2. It can also be understood that the second oxide portion 32 with a certain thickness is filled in the conical area near the original intersection of the side wall of the groove 4 and the surface of the epitaxial layer 2, so that there is no direct sharp turning point between the side wall of the groove 4 and the surface of the epitaxial layer 2.

[0067] Step S404 , forming a gate oxide layer 51 on the inner wall of the trench 4 , wherein the gate oxide layer 51 at least covers one end of the second oxide portion 32 close to the substrate layer 1 .

[0068] Exemplarily, a gate oxide layer 51 is formed on the inner wall of the trench 4 by dry oxidation. The gate oxide layer 51 of this embodiment has a thickness in the range of Silicon dioxide films, such as Fig. 9 As shown, the gate oxide layer 51 contacts the lower end of the second oxide portion 32 to ensure effective isolation of the trench 4 and the epitaxial layer 2 beside the second oxide portion 32 .

[0069] Step S405 , forming a gate 6 in the trench 4 having the gate oxide layer 51 .

[0070] like Fig.10 As shown, polysilicon is filled into the trench 4 located in the first target region 21 of the epitaxial layer 2 until the polysilicon contacts the second oxide portions 32 on both sides of the trench 4 region.

[0071] In addition, in this embodiment, after polysilicon filling, etching back is required to make the gate 6 formed by polysilicon filling lower than the surface of the epitaxial layer 2 outside the trench 4 in the vertical direction, so as to facilitate the subsequent flattening of the surface of the epitaxial layer 2 between the trenches 4.

[0072] In the method for preparing the power semiconductor device of the present embodiment, before the groove 4 is formed, first, an oxidation structure 3 including a first oxidation portion 31 and a second oxidation portion 32 is integrally formed in the epitaxial layer 2, the first oxidation portion 31 is formed in the first target region 21 of the epitaxial layer 2, the second oxidation portion 32 is formed at the edge of the second target region 22 close to the first target region 21, and both the first oxidation portion 31 and the second oxidation portion 32 include a portion extending downward from the surface of the epitaxial layer 2; then, the first oxidation portion 31 and a portion of the epitaxial layer 2 below the first oxidation portion 31 are etched away, and a groove 4 of a required depth is formed in the first target region 21 of the epitaxial layer 2, and the second oxidation portion 32 is filled in the corner position between the groove 4 and the surface of the epitaxial layer 2, and then a gate oxide layer 51 is formed on the inner wall surface of the groove 4 and filled with polysilicon to form a gate 6. Since the second oxide portion 32 is located at the corner of the epitaxial layer 2 near the groove 4, even if the etching process is performed on one side of the surface of the epitaxial layer 2 until the surface of the epitaxial layer 2 and the gate 6 are exposed, the second oxide portion 32 still retains a sufficient thickness, and together with the gate oxide layer 51, it can cover the epitaxial layer 2 at the end edge of the groove 4, thereby effectively isolating the conductive materials on both sides, avoiding the increase of the reverse leakage of the device, thereby ensuring the performance of the device. In addition, the second oxide portion 32 at the upper edge of the groove 4 is formed before the groove 4 is formed, which is convenient for the compatibility of subsequent processes without adding additional processes, and the groove 4 is formed after the second oxide portion 32, which can avoid the contamination of the inner surface of the groove 4 by the materials deposited on the surface of the device and the problem of incomplete removal of impurities, thereby ensuring the quality of the device.

[0073] In one embodiment, after step S401 of forming an epitaxial layer 2 on one side surface of the substrate layer 1 and before step S402 of oxidizing a first target region 21 on the side surface of the epitaxial layer 2 facing away from the substrate layer 1, it also includes: forming a protective layer 100 on the side surface of the epitaxial layer 2 facing away from the substrate layer 1, the protective layer 100 having a first opening 101 to expose the first target region 21 of the epitaxial layer 2.

[0074] Specifically, first, at a temperature of 700° C. to 800° C., a silicon nitride layer is deposited on the entire surface of the epitaxial layer 2 facing away from the substrate layer 1. The thickness of the silicon nitride layer is in the range of Then, by setting a patterned photomask, such as a photoresist layer that has been exposed and developed, the silicon nitride layer on the first target area 21 is etched away, and then the photomask is removed to form a Fig.11 The protective layer 100 having the first opening 101 is made of silicon nitride.

[0075] When the surface side of the epitaxial layer 2 with the silicon nitride protective layer 100 is oxidized, oxygen atoms cannot pass through the silicon nitride protective layer 100, so the protective layer 100 of this embodiment also has the function of isolating water vapor in the environment; oxygen atoms contact the surface of the first target area 21 of the epitaxial layer 2 from the first opening 101 of the protective layer 100. Since the diffusion of oxygen atoms in silicon material is an isotropic process, while the oxygen atoms diffuse longitudinally into the epitaxial layer 2 exposed by the protective layer 100, they also diffuse laterally to the sides. At this time, due to the presence of a concentration gradient of oxygen atoms, and the longitudinal reverse area in the diffusion is much larger than the lateral reverse area, the volume of silicon and oxygen react to generate silicon dioxide will expand, and the expansion will occur in the longitudinal direction to lift the edge of the protective layer 100, forming an overall oxidation structure 3, including a first oxidation portion 31 with a thick middle and a thin edge, and a second oxidation portion 32 with a gradually decreasing volume similar to a bird's beak is generated laterally, such as Fig.12 shown.

[0076] By providing a silicon nitride protection layer 100 with a first opening 101, precise oxidation of the target area is achieved, and it is helpful to form a thicker second oxide portion 32 at the edge position above the subsequent trench 4. It is compatible with other conventional process steps, reduces additional steps, and has simple process preparation steps and low cost.

[0077] Accordingly, after step S402 of oxidizing the first target region 21 on the surface of the epitaxial layer 2 facing away from the substrate layer 1 and before step S403 of forming the trench 4 extending into the epitaxial layer 2 , the method further includes: removing the protective layer 100 .

[0078] Specifically, the protective layer 100 is removed by a wet process, such as a hot phosphoric acid wet chemical process. The wet process is simple, fast, and low-cost.

[0079] On the basis of the above scheme, after step S401 of forming the epitaxial layer 2 on one side surface of the substrate layer 1, and before forming the protective layer 100 on the side surface of the epitaxial layer 2 away from the substrate layer 1, it also includes: forming a cushion oxide layer on the side surface of the epitaxial layer 2 away from the substrate layer 1, and the cushion oxide layer covers the first target area 21 and the second target area 22 of the epitaxial layer 2.

[0080] Specifically, the surface of the silicon epitaxial layer 2 is first dry oxidized to form a pad oxide layer. The temperature range of the dry oxidation is 900-950° C. The thickness range of the formed pad oxide layer is The pad oxide layer can reduce the stress of the subsequently deposited silicon nitride protective layer 100, and avoid the excessive stress generated by the subsequent high-temperature deposited protective layer 100 after the temperature drops to 25°C, which may cause the device to break directly; in addition, the formed thin layer of pad oxide layer helps to guide the lateral diffusion during the subsequent oxidation treatment process of forming the oxidation structure 3.

[0081] In this embodiment, the above-mentioned step S402 performs oxidation treatment on the first target area 21 on the surface of the side of the epitaxial layer 2 facing away from the substrate layer 1, including: forming the first oxidation part 31 and the second oxidation part 32 by wet growth in a furnace tube equipment; the oxidation treatment temperature is 980°C to 1020°C, and the treatment time ranges from 60min to 90min.

[0082] Specifically, wet oxidation usually involves the reaction of silicon material with high-temperature water vapor (or liquid water) to generate an oxide film layer, which grows quickly and can form a thicker structure. Oxidation treatment using wet etching within the above-mentioned temperature range and time range helps to quickly form an oxide structure 3 with a greater thickness, thereby forming a first oxide portion 31 and a second oxide portion 32.

[0083] In one embodiment, in the step S402 of oxidizing the first target region 21 on the surface of the epitaxial layer 2 facing away from the substrate layer 1, the thickness of the formed first oxide portion 31 gradually decreases from the middle portion to the outside, and in the direction perpendicular to the surface of the epitaxial layer 2, the highest point of the first oxide portion 31 is higher than the surface of the second target region 22 of the epitaxial layer 2, and the lowest point of the second oxide portion 32 is lower than the surface of the second target region 22 of the epitaxial layer 2; the thickness range of the first oxide portion 31 is The thickness of the second oxide portion 32 at one end close to the first oxide portion 31 is equal to the outermost portion of the first oxide portion 31, and the thickness gradually decreases from the end close to the first oxide portion 31 to the outside; the highest point of the second oxide portion 32 is higher than the surface of the second target region 22 of the epitaxial layer 2, and the lowest point of the second oxide portion 32 is lower than the surface of the second target region 22 of the epitaxial layer 2.

[0084] It can be understood that the oxidation structure 3 of the present embodiment including the first oxidation portion 31 and the second oxidation portion 32 presents an elliptical structure that is thick in the middle and thin at the edge. The major axis of the elliptical structure is parallel to the surface of the epitaxial layer 2, the middle area is the first oxidation portion 31, and the edge area is the second oxidation portion 32 that gradually decreases in volume and is similar to a bird's beak. In addition, in the vertical direction perpendicular to the surface of the epitaxial layer 2, the first oxidation portion 31 and the second oxidation portion 32 are both structures in which a portion extends into the epitaxial layer 2 and a portion protrudes from the surface of the epitaxial layer 2. This can ensure that in the horizontal direction, except for the first oxidation portion 31 region etched by the groove 4, the second oxidation portion 32 region with sufficient thickness is still retained after etching, and can also ensure that the second oxidation portion 32 has sufficient thickness in the vertical direction.

[0085] Of course, the whole oxide structure 3 can also be presented as half of an elliptical structure that is thick in the middle and thin at the edges, and the half of the elliptical structure is formed by extending downward from the surface of the epitaxial layer 2, and the long axis is flush with the surface of the epitaxial layer 2.

[0086] In one embodiment, after step S405 of forming a gate in a trench having a gate oxide layer, the method further includes:

[0087] Step S406 , forming an insulating dielectric layer 7 on the surface of the epitaxial layer 2 facing away from the substrate layer 1 , and heat-treating the insulating dielectric layer 7 to flatten the surface of the second target region 22 of the epitaxial layer 2 .

[0088] like Fig.13 As shown, an insulating dielectric layer 7 is deposited on the entire surface of one side of the upper surface of the epitaxial layer 2, and the insulating dielectric layer 7 covers the surface of the second target region 22 of the epitaxial layer 2 and the exposed gate 6 and the second oxide portion 32. Then, the insulating dielectric layer 7 is heated and annealed to eliminate the surface defects of the second target region 22 of the epitaxial layer 2 below the insulating dielectric layer 7, and improve the surface quality of the epitaxial layer 2 between adjacent grooves 4. Exemplarily, the above-mentioned insulating dielectric layer 7 is formed by a stacked arrangement of silicate glass (hereinafter referred to as USG) and doped boron phospho-silicate glass (BPSG), and the thickness of the insulating dielectric layer 7 is in the range of The USG is relatively close to the surface of the epitaxial layer 2. In this embodiment, the thickness of the USG is set to The thickness of BPSG is set to

[0089] Step S407 , removing the insulating dielectric layer 7 on the surface of the epitaxial layer 2 facing away from the substrate layer 1 to expose the surface of the second target region 22 of the epitaxial layer 2 and the gate 6 , and the remaining second oxide portion 32 is connected to the gate oxide layer 51 .

[0090] like Fig.14 As shown, illustratively, the insulating dielectric layer 7 and the portion of the second oxide portion 32 that may protrude from the surface of the second target region 22 of the epitaxial layer 2 are etched away until the surface of the second target region 22 of the epitaxial layer 2 is exposed, and the insulating dielectric layer 7 deposited on the gate 6 also needs to be removed; since in this embodiment, the second oxide portion 32 is arranged at the surface corner position of the groove 4 and the second target region 22 of the epitaxial layer 2, and the thickness of the second oxide portion 32 is greater than the thickness of the gate oxide layer 51, even if the process recipe produces a certain error, the second oxide portion 32 still has sufficient thickness to effectively isolate the conductive materials on both sides.

[0091] In one embodiment, step S404 of forming a gate oxide layer 51 on the inner wall surface of the groove 4 also includes: forming a surface oxide layer 52 on the surface of the second target region 22 of the epitaxial layer 2, the surface oxide layer 52 is connected to the second oxide portion 32, and the thickness of the surface oxide layer 52 is equal to the thickness of the gate oxide layer 51; the thickness of the surface oxide layer 52 and the gate oxide layer 51 is less than the thickness of the second oxide portion 32.

[0092] like Fig. 9 As shown, dry oxidation simultaneously forms a gate oxide layer 51 located on the inner wall of the groove 4 and a surface oxide layer 52 located on the surface of the epitaxial layer 2. The gate oxide layer 51 and the surface oxide layer 52 are both connected to the second oxide portion 32. It can be understood that the second oxide portion 32 is arranged at a corner position of the formed overall oxide film layer, and the overall oxide film layer is separated into the gate oxide layer 51 and the surface oxide layer 52. The thickness of the second oxide portion 32 of the separation portion is greater than the thickness of the gate oxide layer 51 and the surface oxide layer 52, which helps to ensure effective isolation of the conductive materials on both sides in subsequent etching.

[0093] Correspondingly, the step S407 of removing the insulating dielectric layer 7 on the surface of the epitaxial layer 2 facing away from the substrate layer 1 further includes: removing the surface oxide layer 52 .

[0094] That is, after removing the insulating dielectric layer 7 on the epitaxial layer 2 located in the second target area 22 in step S407 , it is necessary to continue etching to remove the surface oxide layer 52 until the surface of the epitaxial layer 2 is exposed.

[0095] In one embodiment, in the above step S405 , the distance between the surface of the gate 6 formed away from the substrate layer 1 and the surface of the second target region 22 of the epitaxial layer 2 is in the range of 0.2 μm to 0.25 μm.

[0096] See also Fig.13 , etching and removing the insulating dielectric layer 7 includes: firstly etching the insulating dielectric layer 7 with an etching gas until the second oxide portion 32 is exposed; then the etching gas continues to etch downward the second oxide portion 32, the insulating dielectric layer 7 and the surface oxide layer 52 until the surface of the second target area 22 of the epitaxial layer 2 is exposed, at this time, the insulating dielectric layer 7, the epitaxial layer 2 and the second oxide portion 32 in the groove 4 are etched at the same time, wherein the focus is on etching the insulating dielectric layer 7 in the groove 4 cleanly to expose the gate 6, and at the same time making the surface of the second target area 22 of the epitaxial layer 2 and the second oxide portion 32 on the same horizontal line, thereby improving the flatness of the epitaxial layer 2 between the two grooves 4, and the flatter this part of the epitaxial layer 2 is, the smaller the reverse leakage of the device is.

[0097] Based on this, if the distance between the upper surface of the gate 6 in the groove 4 and the surface of the second target area 22 of the epitaxial layer 2 is too small, the surface of the second target area 22 of the epitaxial layer 2 will not be fully exposed, and the insulating dielectric layer 7 will be completely etched. If etching continues, the polysilicon gate 6 in the groove 4 will be quickly removed due to the large etching selectivity of the gas to polysilicon, resulting in polysilicon loss, which will make it impossible to play the role of MOS regulating the electric field on the device surface; and if the distance between the upper surface of the polysilicon gate 6 in the groove 4 and the surface of the second target area 22 of the epitaxial layer 2 is too large, the surface of the second target area 22 of the epitaxial layer 2 will be excessively etched, because the depth of the groove 4 has been formed first, which is equivalent to the groove 4 becoming shallower, which will affect the drift of the device electrical parameters.

[0098] In one embodiment, reference Fig.15 After the step S407 of removing the insulating dielectric layer 7 on the surface of the epitaxial layer 2 facing away from the substrate layer 1, the method further includes:

[0099] Step S408 , forming a barrier layer 8 on the surface of the second target region 22 of the epitaxial layer 2 , the barrier layer 8 covering at least a portion of the second oxide portion 32 ; the barrier layer 8 , the second oxide portion 32 and the gate oxide layer 51 are connected, suitable for isolating the epitaxial layer 2 from the external structure.

[0100] Specifically, by depositing a thickness of The metal titanium between them is then subjected to high temperature annealing by rapid thermal processing (RTP) equipment to form a Schottky barrier layer 8 of titanium-silicon alloy; then, aqua regia is used to remove excess unreacted metal titanium located on the gate 6 and the second oxide portion 32 to expose the gate 6.

[0101] Step S409 , forming a metal layer 9 on the side of the barrier layer 8 facing away from the substrate layer 1 , wherein the metal layer 9 covers the barrier layer 8 , the second oxide portion 32 and the gate 6 .

[0102] A metal layer 9 is formed by depositing metal aluminum copper on the entire surface of the device on the side where the barrier layer 8 is located, serving as an electrode of the device for conducting connection with the gate 6 .

[0103] The barrier layer 8 and the surface of the epitaxial layer 2 achieve reliable Schottky contact. The barrier layer 8, the second oxide portion 32 and the gate oxide layer 51 are connected to form an effective isolation for the epitaxial layer 2 and the metal layer 9, reduce the reverse leakage of the device, and thus improve the performance of the device.

[0104] refer to Fig.15The present embodiment also provides a power semiconductor device, which is manufactured by the above-mentioned method for manufacturing a power semiconductor device, and includes: a substrate layer 1, an epitaxial layer 2, a groove 4, a gate oxide layer 51, a gate 6, and a second oxide portion 32, wherein the epitaxial layer 2 is formed on one side surface of the substrate layer 1, and the side surface of the epitaxial layer 2 facing away from the substrate layer 1 includes a first target region 21 and a second target region 22 outside the first target region 21; the groove 4 is formed in the first target region 21 of the epitaxial layer 2; the gate oxide layer 51 is formed on the inner wall of the groove 4; the gate 6 is formed in the groove 4 having the gate oxide layer 51; the second oxide portion 32 extends into the second target region 22 arranged on one side surface of the epitaxial layer 2, and is connected to the gate oxide layer 51 in the groove 4, and the second oxide portion 32 covers the connection between the first target region 21 and the second target region 22 of the epitaxial layer 2.

[0105] In the power semiconductor device of this embodiment, the second oxide portion 32 extending into the epitaxial layer 2 is located beside the end of the groove 4, that is, at the corner between the groove 4 and the surface of the silicon epitaxial layer 2, and the thickness of the second oxide portion 32 is greater than the thickness of the gate oxide layer 51, which can effectively ensure that when etching is performed on one side of the surface of the epitaxial layer 2, even if an etching error occurs, a sufficiently thick second oxide portion 32 can still be retained to achieve effective isolation of the conductive materials on both sides, reduce the reverse leakage of the device, and thus ensure the device performance.

[0106] In one embodiment, the above-mentioned power semiconductor device also includes a barrier layer 8 and a metal layer 9, the barrier layer 8 is formed on the surface of the second target area 22 of the epitaxial layer 2, and the barrier layer 8 covers at least part of the second oxide portion 32; the barrier layer 8, the second oxide portion 32 and the gate oxide layer 51 are connected, suitable for isolating the epitaxial layer 2 and the external structure; the metal layer 9 is formed on the side of the barrier layer 8 away from the substrate layer 1 to cover the barrier layer 8, the second oxide portion 32 and the gate 6.

[0107] The barrier layer 8 of this embodiment realizes reliable Schottky contact with the surface of the epitaxial layer 2. The barrier layer 8, the second oxide portion 32 and the gate oxide layer 51 are connected to form an effective isolation for the epitaxial layer 2 and the metal layer 9, reducing the reverse leakage of the device and thus improving the performance of the device.

[0108] The further functional description of each of the above modules is the same as that of the above corresponding embodiments and will not be repeated here.

[0109] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0110] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A method for preparing a power semiconductor device, characterized in that: include: forming an epitaxial layer on a surface of one side of the substrate layer; Performing oxidation treatment on a first target region on a side surface of the epitaxial layer away from the substrate layer to form an oxidation structure; the oxidation structure comprises a first oxidation portion located in the first target region and a second oxidation portion extending into a second target region, and a side surface of the epitaxial layer comprises the first target region and the second target region surrounding the first target region; forming a trench extending into the epitaxial layer, wherein the first oxide portion is removed during the formation of the trench; forming a gate oxide layer on an inner wall of the trench, wherein the gate oxide layer at least covers an end of the second oxide portion close to the substrate layer; A gate is formed in the trench having the gate oxide layer.

2. The method for preparing a power semiconductor device according to claim 1, characterized in that: After forming an epitaxial layer on one side surface of the substrate layer and before performing oxidation treatment on a first target area on a side surface of the epitaxial layer away from the substrate layer, the method further includes: forming a protective layer on a side surface of the epitaxial layer away from the substrate layer, wherein the protective layer has a first opening to expose the first target area of ​​the epitaxial layer; After oxidizing a first target area on a surface of the epitaxial layer facing away from the substrate layer and before forming a trench extending into the epitaxial layer, the method further includes: removing the protective layer.

3. The method for preparing a power semiconductor device according to claim 2, characterized in that: After forming an epitaxial layer on one side surface of the substrate layer and before forming a protective layer on one side surface of the epitaxial layer away from the substrate layer, the method further includes: A pad oxide layer is formed on a surface of the epitaxial layer facing away from the substrate layer, and the pad oxide layer covers the first target region and the second target region on a surface of the epitaxial layer.

4. The method for preparing a power semiconductor device according to claim 3, characterized in that: In the step of oxidizing the first target area on the side of the epitaxial layer away from the substrate layer, the thickness of the first oxide portion formed gradually decreases from the middle part to the outside, and in the direction perpendicular to the surface of the epitaxial layer, the highest point of the first oxide portion is higher than the surface of the second target area of ​​the epitaxial layer, and the lowest point of the second oxide portion is lower than the surface of the second target area of ​​the epitaxial layer; the thickness range of the first oxide portion is The thickness of the second oxide portion at one end close to the first oxide portion is equal to the outermost side of the first oxide portion, and the thickness of the second oxide portion gradually decreases from the end close to the first oxide portion to the outside; the highest point of the second oxide portion is higher than the surface of the second target region of the epitaxial layer, and the lowest point of the second oxide portion is lower than the surface of the second target region of the epitaxial layer.

5. The method for preparing a power semiconductor device according to any one of claims 1 to 4, characterized in that: After forming a gate in the trench having the gate oxide layer, the method further comprises: forming an insulating dielectric layer on a surface of the epitaxial layer facing away from the substrate layer, and heating the insulating dielectric layer to flatten the surface of the second target area of ​​the epitaxial layer; The insulating dielectric layer on the surface of the epitaxial layer facing away from the substrate layer is removed to expose the surface of the second target region of the epitaxial layer and the gate, and the remaining portion of the second oxide portion is connected to the gate oxide layer.

6. The method for preparing a power semiconductor device according to claim 5, characterized in that: The step of forming a gate oxide layer on the inner wall of the trench further includes: forming a surface oxide layer on the surface of the second target region of the epitaxial layer, the surface oxide layer is connected to the second oxide portion, and the thickness of the surface oxide layer is equal to the thickness of the gate oxide layer; the thickness of the surface oxide layer and the gate oxide layer is less than the thickness of the second oxide portion; The step of removing the insulating dielectric layer on a surface of the epitaxial layer facing away from the substrate layer further includes: removing the surface oxide layer.

7. The method for preparing a power semiconductor device according to claim 6, characterized in that: In the step of forming a gate in the trench having the gate oxide layer, a distance between a surface of the formed gate facing away from the substrate layer and a surface of the second target region of the epitaxial layer is in a range of 0.2 μm to 0.25 μm.

8. The method for preparing a power semiconductor device according to claim 7, characterized in that: After removing the insulating dielectric layer on a surface of the epitaxial layer facing away from the substrate layer, the method further comprises: forming a barrier layer on the surface of the second target region of the epitaxial layer, the barrier layer covering at least a portion of the second oxide portion; the barrier layer, the second oxide portion and the gate oxide layer are connected, and are suitable for isolating the epitaxial layer from an external structure; A metal layer is formed on a side of the barrier layer facing away from the substrate layer, and the metal layer covers the barrier layer, the second oxide portion, and the gate.

9. A power semiconductor device, characterized in that: include: substrate layer; An epitaxial layer is formed on one side surface of the substrate layer, and the side surface of the epitaxial layer facing away from the substrate layer includes a first target area and a second target area outside the first target area; a trench formed in a first target region of the epitaxial layer; A gate oxide layer formed on an inner wall of the trench; a gate formed in the trench having the gate oxide layer; The second oxide portion extends into the second target region disposed on one side surface of the epitaxial layer and is connected to the gate oxide layer in the trench. The second oxide portion covers the connection between the first target region and the second target region of the epitaxial layer.

10. The power semiconductor device according to claim 9, characterized in that: Also includes: a barrier layer formed on a surface of the second target region of the epitaxial layer, the barrier layer covering at least a portion of the second oxide portion; The barrier layer, the second oxide portion and the gate oxide layer are connected and are suitable for isolating the epitaxial layer from an external structure; A metal layer is formed on a side of the barrier layer away from the substrate layer to cover the barrier layer, the second oxide portion and the gate.

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