Semiconductor device

Abstract

The invention provides a semiconductor device capable of improving protection performance against overcurrent. In the same semiconductor substrate, a main semiconductor element is provided in an active active region, and a current sensing unit for detecting an overcurrent flowing through the main semiconductor element is provided in a sensing region other than the active active region. The main semiconductor element and the current sensing portion are vertical IGBTs of a trench gate structure. The main semiconductor element has a CS region in all cells. Some of the cells of the current sensing unit have the same structure as the cells of the main semiconductor element, and some of the cells have a structure in which a CS region is excluded from the cells of the main semiconductor element. The average carrier concentration per unit area of the CS region in the sensing region becomes lower than the average carrier concentration per unit area of the CS region in the active active region by not providing the CS region in the cells of the current sensing section.

Description

Technical Field

[0001] The present invention relates to a semiconductor device. Background Art

[0002] Patent document 1 discloses a structure in which a sense IGBT is built in as a current detection element for detecting an overcurrent flowing in a main IGBT (Insulated Gate Bipolar Transistor) section, and holes injected into a drift region in the sense IGBT section are reduced, thereby reducing the conductivity modulation effect in the sense IGBT section relative to that in the main IGBT section. Patent document 2 also discloses a similar technique.

[0003] Prior art literature Patent Literature Patent Document 1: International Publication No. 2020 / 208738 Patent Document 2: Japanese Patent No. 5340961 Summary of the invention

[0004] Technical issues However, in the above-mentioned Patent Document 1, during the Miller period when the IGBT is switched, a phenomenon occurs in which the sense voltage generated in the sense resistor increases sharply due to the sense current flowing in the current detection element. Due to this phenomenon, a semiconductor circuit device having an IGBT with a built-in current detection element and an inductive load such as an inductor may cause malfunction.

[0005] An object of the present invention is to provide a semiconductor device capable of improving protection performance against overcurrent in a simpler manner.

[0006] Technical Solution A semiconductor device according to one embodiment of the present invention is as follows. A first element region and a second element region other than the first element region are provided on a semiconductor substrate. A first element is provided in the first element region. A second element is provided in the second element region. A first semiconductor region of a first conductivity type common to the first element and the second element is provided inside the semiconductor substrate. A second semiconductor region common to the first element and the second element is provided between the back surface of the semiconductor substrate and the first semiconductor region. A back electrode is provided on the back surface of the semiconductor substrate and is electrically connected to the second semiconductor region. The first element comprises a third semiconductor region of a second conductivity type, a fourth semiconductor region of a first conductivity type, a first storage region of a first conductivity type, a first trench, a first gate electrode, and a first electrode.

[0007] The third semiconductor region is arranged between the front surface of the semiconductor substrate and the first semiconductor region in the first element region. The fourth semiconductor region is selectively arranged between the front surface of the semiconductor substrate and the third semiconductor region. The first accumulation region is arranged between the third semiconductor region and the first semiconductor region. The impurity concentration of the first accumulation region is higher than the impurity concentration of the first semiconductor region. The first trench penetrates the fourth semiconductor region and the third semiconductor region from the front surface of the semiconductor substrate and terminates inside the first semiconductor region. The first gate electrode is arranged inside the first trench through a first gate insulating film. The first electrode is arranged on the front surface of the semiconductor substrate and is electrically connected to the third semiconductor region and the fourth semiconductor region. The second element includes a fifth semiconductor region of the second conductivity type, a sixth semiconductor region of the first conductivity type, a second accumulation region of the first conductivity type, a second trench, a second gate electrode, and a second electrode.

[0008] The fifth semiconductor region is arranged between the front surface of the semiconductor substrate and the first semiconductor region in the second element region. The sixth semiconductor region is selectively arranged between the front surface of the semiconductor substrate and the fifth semiconductor region. The second accumulation region is arranged between the fifth semiconductor region and the first semiconductor region. The impurity concentration of the second accumulation region is higher than the impurity concentration of the first semiconductor region. The second trench penetrates the sixth semiconductor region and the fifth semiconductor region from the front surface of the semiconductor substrate and terminates inside the first semiconductor region. The second gate electrode is arranged inside the second trench through a second gate insulating film. The second electrode is arranged on the front surface of the semiconductor substrate and is electrically connected to the fifth semiconductor region and the sixth semiconductor region. The average carrier concentration per unit area of ​​the second accumulation region in the second element region is lower than the average carrier concentration per unit area of ​​the first accumulation region in the first element region.

[0009] According to the above invention, the conduction characteristic of the second element can be reduced to be lower than the conduction characteristic of the first element. Therefore, when the second element is used as a current sensing unit for detecting an overcurrent flowing in the first element, when the first and second elements are turned on, the conductivity modulation in the second element becomes slower than that in the first element and the rise of the sense current flowing in the second element becomes slower. Thus, since the rise of the sense voltage (the potential difference generated between the ends of the sense resistor due to the flow of the sense current) can be suppressed within a certain range, the malfunction of the protection function of the first element when it is normally turned on can be suppressed.

[0010] Technical Effects According to the semiconductor device of the present invention, it is possible to improve the protection performance against overcurrent. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 This is a plan view showing the layout of the semiconductor device according to the first embodiment as viewed from the front side of the semiconductor substrate.

[0012] Figure 2 This is a plan view showing another example of the layout of the semiconductor device according to the first embodiment as viewed from the front side of the semiconductor substrate.

[0013] Figure 3 It is shown Figure 1 A cross-sectional view showing a schematic cross-sectional structure at the cutting line A1 - A2 .

[0014] Figure 4 It is shown Figure 3 Circuit diagram of the equivalent circuit.

[0015] Figure 5 It is shown in detail Figure 1 A cross-sectional view of the cross-sectional structure at the cutting line A1-A2-A3.

[0016] Figure 6 : is a cross-sectional view showing a layout example of a CS region of a current sensing unit.

[0017] Figure 7 This is a cross-sectional view showing the structure of a semiconductor device according to a second embodiment.

[0018] Figure 8 This is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the second embodiment.

[0019] Fig. 9 This is a cross-sectional view showing another example of a state during the manufacture of the semiconductor device according to the second embodiment.

[0020] Fig.10 is a cross-sectional view showing the structure of a semiconductor device according to a reference example.

[0021] Explanation of symbols 1.101n - Drift zone 2, 22, 102, 122 p-type base region 3, 23, 61, 103, 123 CS zone 4, 24, 104, 124 n + Type emission area 5.25 p ++ Type contact area 6, 26, 106, 126 grooves 7, 27, 107, 127 Gate insulating film 8, 28, 108, 128 Gate electrode Units 9, 9a, 9c, 9d, 29, 29a, 29b, 29c, 29d, 109, 129 10, 110 Main semiconductor components 11 Interlayer insulation film 12, 21, 112, 121 Emitting electrode 13, 113 p + Type collector area 14, 114 Collecting electrode 20, 120 Current sensing unit 30, 60, 130 Semiconductor devices 31,131 Active area 32, 132 Active effective area 33, 133 Control pad area 34 Sensing Area 35 Extraction Area 36 Edge terminal area 40, 140 semiconductor substrate 41 Emitter pad 42 Gate pad 43 OC pad 44 Gate channel 45, 46 Gate resistor 47, 141 Sensing resistor 51, 52 p for pn junction isolation + Type Area 53 Field Oxide Film 54 Sensing gate polysilicon layer 61a The first part of the CS region where the carrier concentration is relatively high 61b The second part of the CS region with relatively low carrier concentration 71, 74 Mask for ion implantation 71a Opening of ion implantation mask 72, 75 Ion implantation 73 CS region is formed in the first part where the carrier concentration is relatively high X is a first direction parallel to the front surface of the semiconductor substrate Y is a second direction parallel to the front surface of the semiconductor substrate and perpendicular to the first direction Z Depth d1 Thickness of the first part of the CS region d2 thickness of the second part of the CS region DETAILED DESCRIPTION

[0022] <Overview of Embodiments of the Invention> (1) A semiconductor device according to one embodiment of the present invention is as follows. A first element region and a second element region other than the first element region are provided on a semiconductor substrate. A first element is provided in the first element region. A second element is provided in the second element region. A first semiconductor region of a first conductivity type common to the first element and the second element is provided inside the semiconductor substrate. A second semiconductor region common to the first element and the second element is provided between the back surface of the semiconductor substrate and the first semiconductor region. A back electrode is provided on the back surface of the semiconductor substrate and is electrically connected to the second semiconductor region. The first element includes a third semiconductor region of a second conductivity type, a fourth semiconductor region of a first conductivity type, a first storage region of a first conductivity type, a first trench, a first gate electrode, and a first electrode.

[0023] The third semiconductor region is arranged between the front surface of the semiconductor substrate and the first semiconductor region in the first element region. The fourth semiconductor region is selectively arranged between the front surface of the semiconductor substrate and the third semiconductor region. The first accumulation region is arranged between the third semiconductor region and the first semiconductor region. The impurity concentration of the first accumulation region is higher than the impurity concentration of the first semiconductor region. The first trench penetrates the fourth semiconductor region and the third semiconductor region from the front surface of the semiconductor substrate and terminates inside the first semiconductor region. The first gate electrode is arranged inside the first trench through a first gate insulating film. The first electrode is arranged on the front surface of the semiconductor substrate and is electrically connected to the third semiconductor region and the fourth semiconductor region. The second element includes a fifth semiconductor region of the second conductivity type, a sixth semiconductor region of the first conductivity type, a second accumulation region of the first conductivity type, a second trench, a second gate electrode, and a second electrode.

[0024] The fifth semiconductor region is arranged between the front surface of the semiconductor substrate and the first semiconductor region in the second element region. The sixth semiconductor region is selectively arranged between the front surface of the semiconductor substrate and the fifth semiconductor region. The second accumulation region is arranged between the fifth semiconductor region and the first semiconductor region. The impurity concentration of the second accumulation region is higher than the impurity concentration of the first semiconductor region. The second trench penetrates the sixth semiconductor region and the fifth semiconductor region from the front surface of the semiconductor substrate and terminates inside the first semiconductor region. The second gate electrode is arranged inside the second trench through a second gate insulating film. The second electrode is arranged on the front surface of the semiconductor substrate and is electrically connected to the fifth semiconductor region and the sixth semiconductor region. The average carrier concentration per unit area of ​​the second accumulation region in the second element region is lower than the average carrier concentration per unit area of ​​the first accumulation region in the first element region.

[0025] According to the above invention, when the second element is used as a current sensing unit for detecting an overcurrent flowing through the first element, when the first and second elements are turned on, the rise of the sensing current flowing through the second element can be made slower than the rise of the sensing current flowing through the first element. Therefore, it is possible to suppress the malfunction of the protection function of the first element when it is normally turned on. In addition, since it is possible to eliminate or shorten the dead time during which the protection action of the first element does not react, it is possible to improve the saturation characteristics of the first element.

[0026] (2) In addition, the semiconductor device of the present invention may be such that in the above-mentioned (1), the average carrier concentration per unit area of ​​the second accumulation region in the second element region is greater than or equal to 0.2 times and less than or equal to 0.6 times the average carrier concentration per unit area of ​​the first accumulation region in the first element region.

[0027] According to the above invention, when the first and second elements are turned on, the increase in the sense voltage is suppressed within a certain range, and the breakdown resistance of the second element with respect to dV / dt is improved.

[0028] (3) In the semiconductor device of the present invention, in the above (1) or (2), the second accumulation region may include a first portion and a second portion having a carrier concentration lower than that of the first portion.

[0029] According to the above invention, it is possible to suppress the imbalance in withstand voltage and the imbalance in electric field between the cells of the second element.

[0030] (4) In the semiconductor device of the present invention, in the above-mentioned (3), the thickness of the second portion may be thinner than the thickness of the first portion.

[0031] According to the above invention, since the first and second parts of the second accumulation region can be formed simultaneously by a single ion implantation step, the manufacturing process can be simplified.

[0032] (5) In the semiconductor device of the present invention, in the above (4), the surface of the second accumulation region on the back surface electrode side may be formed into a shape that is recessed toward the second electrode side in the second portion and undulates.

[0033] According to the above invention, since the first and second parts of the second accumulation region can be formed simultaneously by a single ion implantation step, the manufacturing process can be simplified.

[0034] (6) In the semiconductor device of the present invention, in any one of (3) to (5) above, the carrier concentration of the first portion is the same as the carrier concentration of the first accumulation region.

[0035] According to the above invention, since the first and second parts of the first accumulation region and the second accumulation region can be formed simultaneously by a single ion implantation step, the manufacturing process can be simplified.

[0036] (7) In the semiconductor device of the present invention, in the above (1) or (2), the carrier concentration of the second accumulation region may be lower than the carrier concentration of the first accumulation region throughout the entire second accumulation region.

[0037] According to the above invention, it is possible to suppress the unevenness of the withstand voltage within the plane of the second element region.

[0038] (8) In addition, the semiconductor device of the present invention is that in the above (1) or (2), all the first units of the first element have the third semiconductor region, the fourth semiconductor region, the first accumulation region, and the first gate electrode. The second element has a smaller number of second units than the first element. The second unit may include: a third unit having the fifth semiconductor region, the sixth semiconductor region, the second accumulation region, and the second gate electrode; and a fourth unit having the fifth semiconductor region, the sixth semiconductor region, and the second gate electrode, and not having the second accumulation region.

[0039] According to the above invention, the third unit of the second element can be set to the same structure as the first unit of the first element. The second storage region can be configured in a spaced manner in the second element region by the fourth unit of the second element, and the average carrier concentration per unit area of ​​the second storage region in the second element region can be lower than the average carrier concentration per unit area of ​​the first storage region in the first element region.

[0040] (9) In addition, the semiconductor device of the present invention may be configured as described in (8) above, wherein the third unit and the fourth unit are repeatedly arranged in a certain cycle.

[0041] According to the above invention, it is possible to suppress the unevenness of the withstand voltage within the plane of the second element region.

[0042] <Foundation underlying the present invention> First, the structure of a semiconductor device according to a reference example will be described. Fig.10 is a cross-sectional view showing the structure of a semiconductor device according to a reference example. Fig.10 The semiconductor device 130 of the reference example shown in the figure includes a main semiconductor element 110 and a current sensing unit 120 for detecting an overcurrent of the main semiconductor element 110 on the same semiconductor substrate (semiconductor chip) 140. The main semiconductor element 110 is a vertical IGBT with a trench gate structure. The trench gate structure of the main semiconductor element 110 is composed of a p-type base region 102, a CS (carrier storage) region 103, and an n-type base region 104.+ Type emission region 104, p ++ The main semiconductor element 110 comprises an emitter electrode 112, a p-type base region 102 and an n-type contact region (not shown), a trench 106, a gate insulating film 107 and a gate electrode 108. + The type emitter region 104 is connected to the emitter electrode 112 .

[0043] The current sensing unit 120 is a vertical IGBT having a smaller number of units (functional units of the element) 129 having the same structure as the main semiconductor element 110 than the number of units 109 of the main semiconductor element 110. The trench gate structure of the current sensing unit 120 is composed of a p-type base region 122, a CS region 123, and an n-type + Type emission region 124, p ++ The current sensing unit 120 includes an emitter electrode 121, a p-type base region 122, and an n-type contact region (not shown), a trench 126, a gate insulating film 127, and a gate electrode 128. + The emitter region 124 is connected to the emitter electrode 121. The current sensing unit 120 is connected in parallel to the main semiconductor element 110. The emitter electrode 121 of the current sensing unit 120 is connected to the emitter terminal E of the external circuit (not shown) via the sensing resistor 141 and is fixed to the same potential as the emitter electrode 112 of the main semiconductor element 110.

[0044] On the front side of the semiconductor substrate 140, a trench gate structure of the main semiconductor element 110 is provided in an effective region (hereinafter referred to as an active effective region) 132 of the active region 131, and a trench gate structure of the current sensing unit 120 is provided in a portion (hereinafter referred to as a control pad region) 133 of the active region 131 other than the active effective region 132. A p-type common to the main semiconductor element 110 and the current sensing unit 120 is provided on the back side of the semiconductor substrate 140. + The semiconductor substrate 140 is a common n-type collector region 113 and a collector electrode 114. - Type drift region 101.

[0045] When a positive voltage (forward voltage) is applied to the collector electrode 114 relative to the emitter electrode 112 of the main semiconductor element 110, and a voltage greater than the gate threshold voltage is applied to the gate electrode 108 of the main semiconductor element 110, a current from the p-type of the main semiconductor element 110 flows. + The collector region 113 faces n +The main current (drift current) Id of the type emitter region 104 is caused to turn on the main semiconductor element 110. When the main semiconductor element 110 is energized, a main current (drift current: hereinafter referred to as sense current) Is flows through the current sensing unit 120 under the same conditions as the main semiconductor element 110, turning on the current sensing unit 120.

[0046] A voltage drop is generated in the sensing resistor 141 by flowing the sensing current Is through the current sensing unit 120 and flowing through the sensing resistor 141. The voltage fluctuation in the sensing resistor 141 is monitored by an external circuit, and the potential difference between the ends of the sensing resistor 141 is obtained as the sensing voltage; the sensing current Is (= sensing voltage / resistance value Rs of the sensing resistor 141) of the current sensing unit 120 is calculated. When the sensing current Is exceeds a predetermined value set in advance, it is considered that an overcurrent is flowing through the main semiconductor element 110, and the protection function of the main semiconductor element 110 stops supplying a gate voltage to the main semiconductor element 110, etc.

[0047] Thus, when the main semiconductor element 110 is short-circuited (conducted), the main current Id (short-circuit current) of the main semiconductor element 110 increases to become a large current (overcurrent), or the main current Id of the main semiconductor element 110 becomes an excessive current value (overcurrent) in an abnormal situation, the main semiconductor element 110 is protected. However, during the switching transition period (a period during which the Miller effect occurs) when the IGBT (the main semiconductor element 110 and the current sensing unit 120) turns from off to on, the sense voltage generated by the sense resistor 141 rises instantaneously, and when the IGBT is normally turned on, there is a risk that the protection function of the main semiconductor element 110 malfunctions.

[0048] For example, the malfunction of the protection function of the main semiconductor element 110 can be prevented by setting a dead time during which the protection action of the main semiconductor element 110 does not react when the IGBT is turned on. However, in the state where the protection action of the main semiconductor element 110 does not react, the period during which the main semiconductor element 110 is short-circuited (on) becomes longer. If an overcurrent flows through the main semiconductor element 110 during this period, there is a risk of thermal runaway of the semiconductor device 130 or combustion and scorching of the semiconductor substrate 140 (semiconductor device 130). Therefore, the dead time during which the protection action of the main semiconductor element 110 does not react can be omitted or shortened as much as possible.

[0049] Therefore, as a problem to be solved in the present embodiment, there is the improvement of the protection performance against overcurrent.

[0050] Hereinafter, a preferred embodiment of the semiconductor device of the present invention will be described in detail with reference to the accompanying drawings. In this specification and the accompanying drawings, in the layers and regions marked with n or p, it means that electrons or holes are multiple carriers, respectively. In addition, + and - marked to n and p respectively mean that the impurity concentration is high and low compared to the layers and regions not marked with + and -. It should be noted that in the following description of the embodiments and the accompanying drawings, the same symbols are marked for the same configurations and repeated descriptions are omitted.

[0051] (Details of Embodiment 1) A semiconductor device according to Embodiment 1 that solves the above-mentioned problems will be described below. Figure 1 This is a plan view showing the layout of the semiconductor device according to the first embodiment as viewed from the front side of the semiconductor substrate. Figure 2 This is a plan view showing another example of the layout of the semiconductor device according to the first embodiment as viewed from the front side of the semiconductor substrate. Figure 3 It is shown Figure 1 A cross-sectional view showing a schematic cross-sectional structure at the cutting line A1 - A2 . Figure 4 It is shown Figure 3 Circuit diagram of the equivalent circuit. Figure 5 It is shown in detail Figure 1 A cross-sectional view of the cross-sectional structure at the cutting line A1-A2-A3. Figure 6 : is a cross-sectional view showing a layout example of a CS region of a current sensing unit.

[0052] Figure 1 The semiconductor device 30 of the first embodiment shown is an electronic component mounted on a semiconductor circuit device such as an intelligent power module (IPM), and includes a main semiconductor element (first element) 10 and a circuit portion, i.e., a high-function portion, for protecting / controlling the main semiconductor element 10. The main semiconductor element 10 is arranged in an effective region (active effective region: first element region) 32 of an active region 31 of a semiconductor substrate (semiconductor chip) 40. The main semiconductor element 10 is composed of a plurality of units 9 (first unit: see FIG. 1 ) of the same structure connected in parallel via an emitter electrode 12. Figure 3 , 5 ) constitutes a vertical IGBT, which performs the main operation of the semiconductor device 30.

[0053] The active region 31 has a substantially rectangular planar shape and is disposed substantially in the center of the semiconductor substrate 40 (the center of the chip). The active effective region 32 is a region in which the main current of the main semiconductor element 10 flows, and occupies most of the surface area of ​​the active region 31. The active effective region 32 has, for example, a substantially rectangular planar shape with a portion recessed toward the center of the chip. The emitter electrode 12 of the main semiconductor element 10 has substantially the same planar shape as the active effective region 32 and covers substantially the entire surface of the active effective region 32. The portion exposed at the opening of the passivation film of the emitter electrode 12 functions as an emitter pad (electrode pad) 41 of the main semiconductor element 10. At the emitter pad 41, the emitter electrode 12 of the main semiconductor element 10 is connected to an emitter terminal E of an external circuit (not shown) (see Figure 3 , 4 ).

[0054] The high-function portion, such as the current sensing portion (second element) 20, the temperature sensing portion (not shown), the overvoltage protection portion (not shown), and the operation circuit portion (not shown), is arranged in a portion (control pad region) 33 other than the active effective region 32 in the active region 31. The control pad region 33 is a region that does not function as the main semiconductor element 10. The cell 9 of the main semiconductor element 10 is not arranged in the control pad region 33. The control pad region 33 may be arranged between the active effective region 32 and the edge terminal region 36, or may be arranged in the approximate center of the active region 31 and surrounded by the active effective region 32.

[0055] The control pad region 33 has a substantially rectangular planar shape, for example, and is disposed between the active region 32 and the edge termination region 36 in a recessed portion of the active region 32, with three sides ( Figure 1 ) or around both sides ( Figure 2 ) is surrounded by the active region 32. In the control pad region 33, the gate pad (electrode pad) 42 of the main semiconductor element 10 and the electrode pads of the high-function portion (in Figure 1 , 2 Only the OC pads 43 are shown as being arranged adjacent to each other. The gate pad 42 and the electrode pads of the high-function portion have, for example, a substantially rectangular planar shape and are arranged apart from the emitter pad 41 and apart from each other. The gate pad 42 is connected to a gate terminal G of an external circuit.

[0056] The current sensing unit 20 is disposed in a sensing region 34 described later in the control pad region 33. The current sensing unit 20 is composed of cells 29 (second cell: see Figure 3 , 5) vertical IGBT, and contributes to the protection action of the main semiconductor element 10. The substantially identical structure means that the CS region 23 is not configured in a part of the plurality of cells 29, so that the cells 29 having the same structure as the main semiconductor element 10 and the cells 29 having the same structure as the cell 9 of the main semiconductor element 10 excluding the CS region 3 exist in a mixed manner.

[0057] The multiple cells 29 of the current sensing unit 20 are connected in parallel through the emitter electrode 21. The current sensing unit 20 is connected in parallel with the main semiconductor element 10. By operating the current sensing unit 20 under the same conditions as the main semiconductor element 10 and measuring the sense voltage generated in the sense resistor 47, it is possible to detect the overcurrent (OC: OverCurrent) flowing in the main semiconductor element 10. The emitter electrode 21 of the current sensing unit 20 has a planar shape substantially the same as that of the sensing region 34, and covers the entire surface of the sensing region 34. The sensing region (second element region) 34 is a region where the main current of the current sensing unit 20 flows when the current sensing unit 20 is turned on.

[0058] The portion of the emitter electrode 21 of the current sensing unit 20 exposed in the opening of the passivation film functions as an emitter pad (hereinafter referred to as an OC pad) 43 of the current sensing unit 20. The emitter electrode 21 is connected to an emitter terminal E of an external circuit via a sense resistor 47 at the OC pad 43 (see Figure 3 , 4 The emitter electrode 21 of the current sensing unit 20 is electrically connected to the emitter electrode 12 of the main semiconductor element 10 via the sense resistor 47 and the emitter terminal E of the external circuit. The sense resistor 47 and the external circuit are mounted on the IPM together with the semiconductor device 30 (semiconductor substrate 40 ), for example.

[0059] The sensing region 34 has, for example, a substantially rectangular planar shape and is surrounded by the extraction region 35. At least one side of the sensing region 34 (current sensing unit 20) faces the active region 32 (main semiconductor element 10) via the extraction region 35. For example, when the control pad region 33 is surrounded by the active region 32 on three sides and the sensing region 34 is disposed on the outermost side of the control pad region 33, two sides of the sensing region 34 face the active region 32 via the extraction region 35 ( Figure 1 When the sensing region 34 is disposed at a corner of the active region 31, one or both sides of the sensing region 34 are opposed to the active region 32 via the extraction region 35 ( Figure 2 ).

[0060] The temperature sensing unit has a function of detecting the temperature of the main semiconductor element 10 (semiconductor substrate 40) by utilizing the temperature characteristics of a diode. The overvoltage protection unit is, for example, a diode that protects the main semiconductor element 10 from overvoltage (OV: OverVoltage) such as surge. The current sensing unit 20, the temperature sensing unit, and the overvoltage protection unit are controlled by the operation circuit unit. The operation circuit unit controls the main semiconductor element 10 based on the output signals of the current sensing unit 20, the temperature sensing unit, and the overvoltage protection unit. The operation circuit unit is composed of a plurality of semiconductor elements such as a CMOS (Complementary MOS: Complementary MOS) circuit.

[0061] The edge termination region 36 is a region between the active region 31 and the end (chip end) of the semiconductor substrate 40, and surrounds the active region 31 adjacent to the active region 31. The edge termination region 36 has a function of relaxing the electric field on the front side of the semiconductor substrate 40 to maintain a withstand voltage. For example, a general withstand voltage structure (not shown) such as a field limiting ring (FLR) and a junction termination (JTE) structure is configured in the edge termination region 36. The withstand voltage refers to the limit voltage at which a semiconductor device will not malfunction or breakdown.

[0062] In addition, in the edge termination region 36, a gate channel 44 is arranged between the active region 31 and the voltage-resistant structure. The gate channel 44 surrounds the periphery of the active region 31. The gate channel 44 is composed of a gate polysilicon (poly-Si) wiring layer and a gate metal wiring layer. The gate polysilicon wiring layer of the gate channel 44 is arranged on the field oxide film 53 (refer to Figure 5 ) and the interlayer insulating film 11 (refer to Figure 5 The gate polysilicon wiring layer of the gate channel 44 connects the gate electrodes 8 of all the cells 9 of the main semiconductor element 10 and is electrically connected to the gate pad 42 via the gate resistor 46.

[0063] In addition, the gate polysilicon wiring layer of the gate flow channel 44 is connected via the sensing gate polysilicon layer 54 (see Figure 5 ) and the gate resistor 45 are connected to the gate electrodes 28 of all the cells 29 of the current sensing unit 20 (see Figure 5 ). The sensing gate polysilicon layer 54 (refer to Figure 5 ) surrounds the sensing region 34. The gate resistors 45 and 46 are arranged between the field oxide film 53 and the interlayer insulating film 11 in the edge termination region 36 or the extraction region 35. The sensing gate polysilicon layer 54 is arranged between the field oxide film 53 and the interlayer insulating film 11 in the extraction region 35.

[0064] The gate resistors 45, 46 and the sense gate polysilicon layer 54 are polysilicon layers provided at the same level as the gate polysilicon wiring layer of the gate flow channel 44. The gate metal wiring layer of the gate flow channel 44 is provided on the gate polysilicon wiring layer of the gate flow channel 44 and is connected to the gate polysilicon wiring layer via a contact hole of the interlayer insulating film 11. The gate metal wiring layer of the gate flow channel 44 is arranged at the same level as the electrode pads of the high-function parts except the emitter pad 41, the gate pad 42, the OC pad 43, and the current sensing part 20.

[0065] Reference Figure 3 , 5 6, the cross-sectional structure of the semiconductor device 30 of the first embodiment is described. The semiconductor device 30 of the first embodiment has a trench gate structure of the main semiconductor element 10 on the front side of the semiconductor substrate 40 in the active region 32, and has a trench gate structure of the current sensing unit 20 on the front side of the semiconductor substrate 40 in the sensing region 34 of the control pad region 33. The semiconductor substrate 40 is a common substrate for the main semiconductor element 10 and the current sensing unit 20. - n type drift region (first semiconductor region) 1 - The semiconductor material of the semiconductor substrate 40 is, for example, silicon (Si) or silicon carbide (SiC).

[0066] The trench gate structure of the main semiconductor element 10 is composed of a p-type base region (third semiconductor region) 2, a CS region (first storage region) 3, and an n + Type emitter region (fourth semiconductor region) 4, p ++ The p-type base region 2, the CS region 3, the n-type contact region 5, the trench (first trench) 6, the gate insulating film (first gate insulating film) 7, and the gate electrode (first gate electrode) 8. + Type 4 emitter region and p ++ The n-type contact region 5 is a diffusion region formed by ion implantation into the semiconductor substrate 40 and is disposed between the front surface of the semiconductor substrate 40 and the n-type contact region 5. - The p-type base region 2 is disposed between the front surface of the semiconductor substrate 40 in the active region 32 and the n-type drift region 1. - The entire surface between the drift zone 1.

[0067] The CS region 3 is located between the adjacent trenches 6 and between the p-type base region 2 and the n-type base region 3. - The entire region between the n-type drift regions 1 is provided in a manner that is in contact with these regions and reaches the sidewalls of the trench 6. The CS region 3 is a diffusion region formed by, for example, ion implanting n-type impurities such as phosphorus (P) and arsenic (As) at high acceleration energy. The CS region 3 is an impurity concentration ratio of n -The n-type region with high impurity concentration in the drift region 1 becomes a barrier for minority carriers (holes) and has the function of accumulating minority carriers. The CS region 3 is configured in all cells 9 of the main semiconductor element 10. The IE (Injection Enhanced: electron injection enhancement) effect is enhanced by the CS region 3 and the conductivity modulation effect is enhanced, thereby reducing the on-voltage Von of the cell 9.

[0068] n + Type 4 emitter and p ++ The p-type contact regions 5 are selectively disposed between the front surface of the semiconductor substrate 40 and the p-type base region 2. + Type 4 emitter and p ++ The contact area 5 is on the lower surface (described later) + The surface on the side of the p-type collector region 13 is in contact with the p-type base region 2, and is in contact with the emitter electrode (first electrode) 12 on the front surface of the semiconductor substrate 40. + The p-type emitter region 4 and the p-type base region 2 are adjacent to the sidewalls of the trench 6. ++ In this case, the p-type base region 2 replaces the p ++ The type contact region 5 reaches the front surface of the semiconductor substrate 40 .

[0069] The trench 6 penetrates the semiconductor substrate 40 from the front surface in the depth direction Z. + type emitter region 4 and p-type base region 2 while in n - The groove 6 is terminated inside the drift region 1. In the portion where the CS region 3 is provided, the groove 6 also penetrates the CS region 3. The groove 6 extends linearly in the first direction X parallel to the front surface of the semiconductor substrate 40, for example, and a plurality of grooves 6 are arranged adjacent to each other in a stripe shape in the second direction Y parallel to the front surface of the semiconductor substrate 40 and orthogonal to the first direction X. A gate electrode 8 is provided inside the groove 6 via a gate insulating film 7. The centers of the grooves 6 adjacent to each other in the second direction Y (centers in the second direction Y) constitute a unit 9.

[0070] p-type base region 2, CS region 3, n + Type 4 emitter region and p ++ The contact region 5 extends linearly between adjacent trenches 6 along the first direction X with a length substantially equal to the length of the longitudinal direction (first direction X) of the trench 6 and with a uniform thickness. The semiconductor substrate 40 includes the trench gate structure of the main semiconductor element 10, the trench gate structure of the current sensing unit 20, and the p-type contact region 5 described later. + The type regions 51 and 52, a diffusion region (not shown) formed in the surface region of the front side of the semiconductor substrate 40 in the edge termination region 36, and a later-described p-type region on the back side of the semiconductor substrate 40 + The portion outside the collector region 13 becomes n -Type drift region 1.

[0071] Some of the plurality of cells 9 of the main semiconductor element 10 may also be configured without n + Type 4 emitter unit 9c. No configuration n + The p-type base region 2 of the cell 9c of the p-type emitter region 4 can be electrically insulated from the emitter electrode 12 by the interlayer insulating film 11 and electrically floated (refer to Figure 5 ), or through the p ++ The type contact region 5 is electrically connected to the emitter electrode 12, or is directly connected to the emitter electrode 12, so as to be fixed to the potential of the emitter electrode 12 (not shown). + The cell 9 c of the type emitter region 4 does not contribute to the IGBT operation of the main semiconductor element 10 .

[0072] If no configuration is made + The p-type base region 2 of the cell 9c of the type emitter region 4 is electrically floating. When the main semiconductor element 10 is turned on, n - The minority carriers near the p-type base region 2 inside the p-type drift region 1 become difficult to be moved to the emitter electrode 12, so the IE effect in the active effective region 32 becomes high. + The p-type base region 2 of the cell 9c of the p-type emitter region 4 is fixed to the potential of the emitter electrode 12. When the main semiconductor element 10 is turned off, n - The minority carriers in the drift region 1 can be easily moved to the emitter electrode 12 , and the local electric field concentration in the active region 32 can be suppressed.

[0073] Configured + The cell 9a of the type emitter region 4 (a cell that contributes to the IGBT operation of the main semiconductor element 10), and the ... + The cells 9c of the type emitter region 4 are repeatedly arranged in a certain period. The cells 9d arranged in the outer peripheral portion of the active region 32 (the portion on the control pad region 33 side and the edge terminal region 36 side) of the plurality of cells 9 of the main semiconductor element 10 may not be arranged. + Type emission region 4 becomes p ++ The p-type contact region 5 and the p-type base region 2 are fixed to the potential of the emitter electrode 12. In this case, the cells 9d in the peripheral portion of the active region 32 do not contribute to the IGBT operation of the main semiconductor element 10.

[0074] The interlayer insulating film 11 is provided on the entire front surface of the semiconductor substrate 40, covering the gate electrodes 8 of all the cells 9 of the main semiconductor element 10 and the gate electrodes 28 of all the cells 29 of the current sensing unit 20. In addition, the interlayer insulating film 11 covers the sensing gate polysilicon layer 54 of the extraction area 35 of the control pad area 33 and the gate polysilicon layer (not shown) constituting the gate flow channel 44 of the edge termination area 36. The emitter electrode 12 is provided on the interlayer insulating film 11 in the active effective area 32, and is in ohmic contact with the semiconductor substrate 40 in the contact hole of the interlayer insulating film 11, and is in contact with the n + Type emission region 4, p ++ The p-type contact region 5 is electrically connected to the p-type base region 2 .

[0075] The emitter electrode 12 extends to the extraction area 35 of the control pad area 33 and terminates on the interlayer insulating film 11 in the extraction area 35. The outermost surface of the front surface of the semiconductor substrate 40 is protected by a passivation film (not shown). Different electrode pads are exposed in each opening of the passivation film. - type drift region 1, and n - The drift region 1 is connected to a p-type drift region 10 and a p-type drift region 10 is connected to a drift region 10 and a p-type drift region 10 + Type collector region (second semiconductor region) 13. p + The collector region 13 is, for example, a diffusion region formed by ion implantation into the semiconductor substrate 40. - Type drift region 1 and p + The impurity concentration ratio n is set between the collector regions 13 - The n-type field stop layer has a high impurity concentration in the type drift region 1. The collector electrode (back electrode) 14 is provided on the entire back side of the semiconductor substrate 40 and is connected to the p + The collector region 13 is electrically connected to the collector electrode 14. The collector electrode 14 is connected to a collector terminal C of an external circuit.

[0076] The trench gate structure of the current sensing unit 20 is formed simultaneously with the trench gate structure of the main semiconductor element 10, and is composed of a p-type base region (fifth semiconductor region) 22, a CS region (second storage region) 23, and an n + Type emitter region (sixth semiconductor region) 24, p ++ The p-type base region 22 and the n-type contact region 25 of the current sensing unit 20 are formed by a trench (second trench) 26, a gate insulating film (second gate insulating film) 27, and a gate electrode (second gate electrode) 28. + Type emission area 24, p ++ The p-type contact region 25, the trench 26, the gate insulating film 27 and the gate electrode 28 are respectively formed in accordance with the p-type base region 2, the n-type base region 2 and the n-type base region 3 of the main semiconductor element 10. + Type emission region 4, p ++The type contact region 5, the trench 6, the gate insulating film 7 and the gate electrode 8 are the same.

[0077] The CS region 23 of the current sensing unit 20 is arranged differently from the CS region 3 of the main semiconductor element 10 and is thinly arranged in the sensing region 34. Specifically, the p-type base region 22 is disposed on the front surface of the semiconductor substrate 40 in the sensing region 34 and on the n-type base region 23 of the current sensing unit 20. - The CS region 23 is formed between the predetermined adjacent trenches 26 and the p-type base region 22 and the n-type drift region 1. - The CS region 23 is the entire region between the type drift regions 1 and is provided in a manner that is in contact with these regions and reaches the sidewalls of the trench 26. - The n-type region with a high impurity concentration in the drift region 1 serves as a barrier for minority carriers and has a function of accumulating minority carriers.

[0078] The CS region 23 is thinly arranged in the sensing region 34 by being arranged in a part of the plurality of cells 29 of the current sensing unit 20. As a result, the average carrier concentration per unit area of ​​the CS region 23 in the sensing region 34 (the concentration of activated n-type impurities) becomes lower than the average carrier concentration per unit area of ​​the CS region 3 in the active region 32. Although the on-state voltage Von is lowered in the cell 29 in which the CS region 23 is arranged, similarly to the cell 9 of the main semiconductor element 10, the IE effect is hindered in the cell 29 in which the CS region 23 is not arranged, and the on-state characteristic of the current sensing unit 20 is lowered than the on-state characteristic of the main semiconductor element 10.

[0079] For example, if the CS region 23 is not arranged in all the cells 29 that contribute to the IGBT operation of the current sensing unit 20, there is a tendency to become a high-speed switch (dV / dt becomes steeper) when the current sensing unit 20 is turned off, and when the sense current Is of the current sensing unit 20 under the high-speed switching condition is cut off, there is a risk of causing breakdown even if the current sensing unit 20 is within the specification range. On the other hand, in the present embodiment 1, by arranging the CS region 23 in the sensing region 34 at intervals, the rise of the sense voltage is suppressed within a certain range when the IGBT (the main semiconductor element 10 and the current sensing unit 20) is turned on, and the breakdown tolerance of the current sensing unit 20 relative to the dV / dt (time change rate) of the emitter-collector voltage when the IGBT is turned off is improved.

[0080] The average carrier concentration per unit area of ​​the CS region 23 in the sensing region 34 may be about 0.2 times or more and 0.6 times or less relative to the average carrier concentration per unit area of ​​the CS region 3 in the active region 32. The average carrier concentration per unit area of ​​the CS regions 3 and 23 refers to a value obtained by dividing the total dose (total charge amount) of n-type impurities activated by ion implantation to form the CS regions 3 and 23 in the active region 32 and the sensing region 34, respectively, by the thickness of the CS regions 3 and 23, and the area of ​​the active region 32 and the sensing region 34. As described later, the cell 29a in which the CS region 23 is arranged and the cell 29b in which the CS region 23 is not arranged may be repeatedly arranged in a certain period.

[0081] The maximum carrier concentration of the CS region 23 may be substantially the same as the maximum carrier concentration of the CS region 3 of the active effective region 32, or may be lower than the maximum carrier concentration of the CS region 3 of the active effective region 32. For example, by forming the CS region 3 of the active effective region 32 and the CS region 23 of the sensing region 34 at the same time, the maximum carrier concentrations of the CS regions 3 and 23 may be substantially the same. Substantially the same carrier concentration refers to the same impurity concentration within the allowable error range including process variations. A method for making the maximum carrier concentration of the CS region 23 lower than the maximum carrier concentration of the CS region 3 of the active effective region 32 will be described later (see Figures 7 to 9 ).

[0082] n + Type emitter region 24 and p ++ The p-type contact regions 25 are selectively disposed between the front surface of the semiconductor substrate 40 and the p-type base region 22. + Type emitter region 24 and p ++ The p-type contact region 25 is in contact with the p-type base region 22 on the lower surface, and is in contact with the emitter electrode (second electrode) 21 on the front surface of the semiconductor substrate 40. + The p-type emitter region 24 and the p-type base region 22 are adjacent to the sidewalls of the trench 26. ++ In this case, the p-type base region 22 replaces the p ++ The type contact region 25 reaches the front surface of the semiconductor substrate 40 .

[0083] The trench 26 penetrates the semiconductor substrate 40 from the front surface in the depth direction Z. + The p-type emitter region 24 and the p-type base region 22 are - The p-type drift region 1 is terminated inside. In the portion where the CS region 23 is provided, the trench 26 also penetrates the CS region 23. A plurality of trenches 26 are arranged in a stripe shape in parallel with the trench 6 of the main semiconductor element 10. A gate electrode 28 is provided inside the trench 26 via a gate insulating film 27. +Type emitter region 24 and p ++ The type contact region 25 extends linearly between adjacent trenches 26 along the first direction X with a length substantially equal to the length in the longitudinal direction (first direction X) of the trench 26 and with a uniform thickness.

[0084] The centers of the grooves 26 adjacent to each other in the second direction Y (centers in the second direction Y) constitute one unit 29. + The CS region 23 is not configured in a portion of the cells 29b of the cells 29 having the type emitter region 24. As a result, the average carrier concentration per unit area of ​​the CS region 23 in the current sensing unit 20 becomes lower than the average carrier concentration per unit area of ​​the CS region 3 in the main semiconductor element 10. By not configuring the CS region 23 in a portion of the cells 29 that contribute to the IGBT operation of the current sensing unit 20, the conduction characteristics of the current sensing unit 20 are reduced. + Among the cells 29 of the type emitter region 24 , the cell 29 a (third cell) in which the CS region 23 is arranged and the cell 29 b (fourth cell) in which the CS region 23 is not arranged may be repeatedly arranged in a certain cycle.

[0085] Some of the multiple units 29 of the current sensing unit 20 may also be configured without n + The unit 29c of the type emission area 24 is not configured + The p-type base region 22 of the cell 29c of the p-type emitter region 24 can be electrically insulated from the emitter electrode 21 by the interlayer insulating film 11 and electrically floated (see Figure 5 ), or through the p ++ The contact region 25 is electrically connected to the emitter electrode 21, or is directly connected to the emitter electrode 21 and fixed to the potential of the emitter electrode 21 (see Figure 6 ). No configuration + The cell 29 c of the type emitter region 24 does not contribute to the IGBT operation of the current sensing unit 20 .

[0086] Configured + The unit 29 (29a, 29b) of the type emission region 24, and the ... + The units 29c of the type emission region 24 are repeatedly arranged according to a certain period. + The cells 29a with the CS region 23 and the cells 29b without the CS region 23 are alternately and repeatedly arranged with the same number of cells ( Figure 6 In the case of one each), an unconfigured n is configured between adjacent units 29a and 29b, between adjacent units 29a, and between adjacent units 29b at a certain period (for example, every other one). +The unit 29c of the type emission region 24 (refer to Figure 6 ).

[0087] It can also be used without configuring n + Among the cells 29 of the type emitter region 24 (cells that do not contribute to the IGBT operation of the current sensing unit 20), a portion of the cells 29c are not provided with the CS region 23. + The p-type base region 22 of the cell 29c of the p-type emitter region 24 is electrically floating. When the current sensing unit 20 is turned on, n - Minority carriers near the p-type base region 22 in the p-type drift region 1 become difficult to be moved to the emitter electrode 21. Therefore, regardless of whether the CS region 23 is provided in the cell 29c, the IE effect in the sensing region 34 can be improved by the cell 29c.

[0088] On the other hand, if no configuration is given + The p-type base region 22 of the cell 29c of the p-type emitter region 24 is fixed to the potential of the emitter electrode 21. When the current sensing unit 20 is turned off, n - The minority carriers in the drift region 1 are easily moved to the emitter electrode 21, which can suppress the local electric field concentration in the sensing region 34. + When the p-type base region 22 of the cell 29c of the p-type emitter region 24 is fixed to the potential of the emitter electrode 21, the cell 29c may not be provided with the CS region 23. If the cell 29c is not provided with the CS region 23, the IE effect in the sensing region 34 can be hindered in the same manner as the cell 29b.

[0089] Among the plurality of cells 29 of the current sensing unit 20, the cell 29d disposed in the outer peripheral portion of the sensing region 34 (the portion on the extraction region 35 side) may be a cell not disposed. + Type emission region 24 and the p ++ The p-type contact region 25 and the p-type base region 22 are fixed to the potential of the emitter electrode 21. In this case, the cell 29d in the peripheral portion of the sensing region 34 does not contribute to the IGBT operation of the main semiconductor element 10. The CS region 23 may not be arranged in the cell 29d arranged in the peripheral portion of the sensing region 34 adjacent to the active region 32 via the extraction region 35.

[0090] When the IGBT is turned off, n in the active region 32 -The minority carriers in the p-type drift region 1 flow into the p-type base region 22 of the portion adjacent to the active effective region 32 in the peripheral portion of the sensing region 34. Therefore, the cell 29d disposed in the portion adjacent to the active effective region 32 in the peripheral portion of the sensing region 34 may not be disposed with the CS region 23. Thus, since the IE effect is hindered in the peripheral portion of the sensing region 34 and the conductivity modulation effect is reduced, it is possible to prevent the hole current from bypassing the active effective region 32 into the sensing region 34 when the IGBT is turned off.

[0091] In addition, the CS region 23 may be arranged in a certain period without depending on the arrangement of the cells 29a, 29b, and 29c (see Figure 6 ). By arranging the CS regions 23 at a certain period, it is possible to suppress the unbalanced withstand voltage in the plane of the sensing region 34. On the other hand, although there is a risk of lowering the withstand voltage due to the unbalanced electric field in the plane of the semiconductor substrate 40 due to the CS regions 23 being arranged in a spaced-out manner in the plane of the sensing region 34, the p-type of the extraction region 35 can be used as described later. + The type region 51 isolates the sensing region 34 from the pn junction of other regions, thereby suppressing the electric field concentration and current concentration in the sensing region 34 .

[0092] The configuration of the current sensing unit 20 is the same as that of the CS region 3 of the main semiconductor element 10 except for the arrangement of the CS region 23 (ie, the thinned-out arrangement). Figure 3 , 5 In the figure, for the unit 9 of the main semiconductor element 10, n + Type emitting region 4 unit 9a and no configuration n + The arrangement of the units 9 (9a, 9c) of the main semiconductor element 10 can be appropriately set. Figure 3 , 5 In FIG. 1 , the current sensing unit 20 is simplified and only one cell 29 is illustrated, and the CS region 23 is omitted from illustration. Figure 6 An example of the layout of the CS region 23 is shown.

[0093] The emitter electrode 21 is disposed on the interlayer insulating film 11 in the sensing region 34, and is in ohmic contact with the semiconductor substrate 40 in the contact hole of the interlayer insulating film 11. + Type emission area 24, p ++ The emitter electrode 21 extends toward the extraction region 35 of the control pad region 33, and terminates at a position separated from the emitter electrode 12 in the extraction region 35 on the interlayer insulating film 11 in the extraction region 35. The emitter electrode 21 is connected to the emitter terminal E of the external circuit via the sense resistor 47, and is fixed to the same potential as the emitter electrode 12 of the main semiconductor element 10 ( Figure 3 ,4 ).

[0094] In the extraction area 35 of the control pad area 33, the front surface of the semiconductor substrate 40 is connected to the n - type drift region 1, and n - The drift region 1 is connected to each other and selectively provided with p + Type area 51, 52. + The sensing regions 51 and 52 are separated from each other and concentrically surround the sensing region 34. + Between the type areas 51 and 52, n - The type drift region 1 reaches the front surface of the semiconductor substrate 40. + The type regions 51 and 52 are electrically connected to the emitter electrodes 12 and 21 and have the function of extracting n when the IGBT (semiconductor device 60) is turned off. - The function of minority carriers (holes) in the drift region 1.

[0095] By p + Type area 51 and n - The pn junction of the drift region 1 and the p + Type area 52 and n - The pn junction of the drift region 1 is formed so that the main semiconductor element 10 and the current sensing unit 20 are separated from each other (pn junction isolation). + The p-type regions 51, 52 and the gate runner 44 of the edge termination region 36 are directly below + The p-type region (not shown) directly below the gate channel 44 is connected. + The n-type region is configured in the edge termination region 36 between the front surface and the n-type region of the semiconductor substrate 40. - The p-type drift region 1 and the gate channel 44 are opposed to each other via the field oxide film 53. + type region, and surrounds the active region 31.

[0096] p + The type region 51 is disposed on the extraction region 35 on the active region 32 side (the side opposite to the sensing region 34 side). + The type region 51 surrounds the outer periphery of the active effective region 32 in a portion adjacent to the active effective region 32. + The type region 51 extends from the front surface of the semiconductor substrate 40 to a position closer to the trench 6 of the active region 32 in the depth direction Z. + The position of the collector region 13 side. + The type region 51 is electrically connected to the emitter electrode 12 of the main semiconductor element 10 via the contact hole of the interlayer insulating film 11. + Between the type region 51 and the emitter electrode 12, a p ++ Type contact area 5 (5a).

[0097] p + The portion of the p-type region 51 adjacent to the active region 32 in the first direction X is connected to the p-type base region 2 and the CS region 3 of the active region 32 and surrounds the adjacent end portion (not shown) of the trench 6 of the active region 32 (main semiconductor element 10) in the long side direction (first direction X). + The portion of the molded region 51 adjacent to the active region 32 in the second direction Y (the short side direction of the trench 6 ) surrounds the trench 6 on the side of the active region 32 closest to the extraction region 35 . + The p-type region 51 may extend in the second direction Y toward the inner side of the active region 32 relative to the trench 6 closest to the extraction region 35 in the active region 32 , and may be in contact with the p-type base region 2 and the CS region 3 .

[0098] p + The mold area 52 is disposed at a position close to the sensing area 34 of the extraction area 35. + The type region 52 surrounds the outer periphery of the sensing region 34. + The region 52 extends from the front surface of the semiconductor substrate 40 to a position closer to the trench 26 of the sensing region 34 (current sensing unit 20 ) in the depth direction Z. + The position of the collector region 13 side. + The type region 52 is electrically connected to the emitter electrode 21 of the current sensing unit 20 via the contact hole of the interlayer insulating film 11. + Between the type region 52 and the emitter electrode 21, a p ++ Type contact area 25 (25a).

[0099] p + The p-type region 52 is in contact with the p-type base region 22 and the CS region 23 of the sensing region 34 in the first direction X, and surrounds adjacent ends (not shown) of the trench 26 of the sensing region 34 in the longitudinal direction (the first direction X). + The molded region 52 surrounds the groove 26 on the side of the sensing region 34 closest to the extraction region 35 in the second direction Y (the short side direction of the groove 26 ). + The p-type region 52 may extend in the second direction Y toward the inner side of the sensing region 34 relative to the trench 26 on the extraction region 35 side of the sensing region 34 and contact the p-type base region 22 (and contact the CS region 23 if the cell 29 d is provided with the CS region 23 ).

[0100] In the extraction area 35, a sense gate polysilicon layer 54 made of polysilicon (poly-Si) is arranged on the front surface of the semiconductor substrate 40 via a field oxide film 53. The sense gate polysilicon layer 54 covers almost the entire area of ​​the extraction area 35 via the field oxide film 53. The sense gate polysilicon layer 54 connects the gate electrodes 28 of all the cells 29 of the current sensing unit 20, and is electrically connected to the gate polysilicon wiring layer of the gate flow channel 44 via the gate resistor 45. The emitter electrodes 12 and 21 extend on the sense gate polysilicon layer 54 via the interlayer insulating film 11.

[0101] The operation of the semiconductor device 30 of the first embodiment will be described. When a positive voltage (forward voltage) is applied to the collector electrode 14 relative to the emitter electrode 12 (emitter pad 41) of the main semiconductor element 10, and a voltage greater than the gate threshold voltage is applied to the gate electrode 8 of the main semiconductor element 10, a channel (n-type inversion layer) is formed in the portion of the p-type base region 2 of the main semiconductor element 10 along the trench 6. As a result, the p-type current from the main semiconductor element 10 flows. + The collector region 13 is connected to the n + The main current (drift current) Id of the type emitter region 4 is turned on, and the main semiconductor element 10 is turned on.

[0102] Under the same conditions as the main semiconductor element 10, when a positive voltage (forward voltage) is applied to the collector electrode 14 relative to the emitter electrode 21 (OC pad 43) of the current sensing unit 20, if a voltage greater than the gate threshold voltage is applied to the gate electrode 28 of the current sensing unit 20, a channel (n-type inversion layer) is formed in the portion of the p-type base region 22 of the sensing region 34 along the trench 26. As a result, the main current (drift current: hereinafter referred to as the sensing current) Is is transferred from the p-type base region 22 of the current sensing unit 20 to the gate electrode 28 of the current sensing unit 20. + Type collector region 13 to n + The type emitter region 24 flows, and the current sensing unit 20 is turned on.

[0103] When the sense current Is flows through the current sensing unit 20, a voltage drop occurs in the sense resistor 47 connected between the emitter electrode 12 of the main semiconductor element 10 and the emitter electrode 21 of the current sensing unit 20. The sense current Is of the current sensing unit 20 increases in accordance with the magnitude of the main current Id flowing through the main semiconductor element 10, and the voltage drop in the sense resistor 47 also increases. For example, the voltage fluctuation in the sense resistor 47 is monitored and acquired by an external circuit, and the sense current Is of the current sensing unit 20 is calculated to detect an overcurrent flowing through the main semiconductor element 10.

[0104] Specifically, the external circuit obtains the magnitude of the voltage drop in the sensing resistor 47 (the potential difference between the ends of the sensing resistor 47) as a sensing voltage, and calculates the sensing current Is of the current sensing unit 20 (=sensing voltage / resistance value Rs of the sensing resistor 47) based on the sensing voltage. Furthermore, when the sensing current Is of the current sensing unit 20 exceeds a predetermined value set in advance, the high-function unit provided in the external circuit or the same semiconductor substrate 40 regards that an overcurrent flows through the main semiconductor element 10, and protects the main semiconductor element 10 by stopping the supply of the gate voltage to the main semiconductor element 10, etc.

[0105] Thus, when the main current Id (short-circuit current) of the main semiconductor element 10 increases and becomes a large current (overcurrent) exceeding a predetermined value when the main semiconductor element 10 is short-circuited, or when the main current Id of the main semiconductor element 10 becomes an excessive current value (overcurrent), the main semiconductor element 10 can be prevented from breaking down. It is preferable that the resistance value Rs of the sense resistor 47 is as low as possible. By reducing the resistance value Rs of the sense resistor 47 (for example, 2 kΩ), the power loss caused by the sense current Is flowing through the sense resistor 47 and the heat generation of the sense resistor 47 can be suppressed.

[0106] Since the conductivity modulation in the current sensing unit 20 is slower than that in the main semiconductor element 10 and the rise of the sense current Is is slower when the IGBT (main semiconductor element 10 and current sensing unit 20) is turned on, the rise of the sense voltage when the IGBT is turned on is suppressed within a certain range. As a result, it is possible to suppress the malfunction of the protection function of the main semiconductor element 10 when the IGBT is normally turned on. In addition, since it is possible to eliminate or shorten the dead time in which the protection action of the main semiconductor element 10 does not react, it is possible to detect an overcurrent flowing in the main semiconductor element 10 even if the main semiconductor element 10 is turned on at a high speed.

[0107] On the other hand, if the voltage applied to the gate electrode 8 is lower than the gate threshold voltage, the p-type base region 2 is electrically connected to the CS region 3 and the n-type base region 2. - The pn junction between the p-type drift region 1 and the p-type base region 22 is reverse biased, so the main semiconductor element 10 remains in the off state. Similar to the main semiconductor element 10, a voltage lower than the gate threshold voltage is applied to the gate electrode 28 of the current sensing unit 20. - The pn junctions between the two drift regions 1 are reverse biased, so the current sensing unit 20 also remains in the off state. At this time, since the depletion layer flows from these pn junctions to the n - The type drift region 1 is expanded, so the predetermined withstand voltage is ensured.

[0108] As described above, according to the first embodiment, the average carrier concentration per unit area of ​​the CS region in the sensing region is made lower than the average carrier concentration per unit area of ​​the CS region in the active region, so that the conduction characteristics of the current sensing portion can be made lower than the conduction characteristics of the main semiconductor element. As a result, when the IGBT (main semiconductor element and current sensing portion) is turned on, the conductivity modulation in the current sensing portion can be slowed down and the rise of the sense current can be slowed down compared to the main semiconductor element, so the rise of the sense voltage when the IGBT is turned on can be suppressed within a certain range.

[0109] Therefore, it is possible to suppress the malfunction of the protection function of the main semiconductor element when the IGBT is normally turned on, and the protection performance of the main semiconductor element can be improved. On the other hand, by suppressing the rise of the sense voltage when the IGBT is turned on, the steady-state sense voltage (the sense voltage when the main semiconductor element is normally operating) becomes lower, but by appropriately setting the detection threshold (lower limit value) of the overcurrent flowing in the main semiconductor element on the external circuit side that monitors the voltage fluctuation in the sense resistor, it is possible to suppress the malfunction of the protection function of the main semiconductor element when the IGBT is normally turned on.

[0110] In addition, since the rise of the sense voltage can be suppressed within a certain range when the IGBT is turned on, the dead time during which the protection action of the main semiconductor element does not react can be eliminated or shortened. As a result, since the period during which the main semiconductor element is short-circuited (conducted) when the protection action of the main semiconductor element does not react can be eliminated or shortened, even when the design condition is set to turn on the main semiconductor element at a high speed, when an overcurrent flows through the main semiconductor element abnormally, the overcurrent can be detected and the main semiconductor element can be protected. Therefore, the saturation characteristics of the main semiconductor element can be improved.

[0111] (Details of Embodiment 2) A semiconductor device according to Embodiment 2 that solves the above-mentioned problems will be described below. Figure 7 This is a cross-sectional view showing the structure of a semiconductor device according to a second embodiment. Figure 8 , 9 1 is a cross-sectional view showing an example of a state in which the semiconductor device of the second embodiment is in the process of being manufactured. Figure 1 , 2 The layout is the same as that in which the symbol 30 is replaced by the symbol 60. In the semiconductor device 60 of the second embodiment, Figure 1 The cross-sectional structures at the cutting lines A1-A2 and A1-A2-A3 are respectively Figure 3 , 5 same, Figure 3 , 5 The layout example of the sensing area 34 in FIG. Figure 6Same. Figure 7 The bottom surface of the trench 26 of the current sensing part 20 is shown by a dotted line.

[0112] The semiconductor device 60 of the second embodiment is different from the semiconductor device 30 of the first embodiment (see Figures 1 to 6 ) is that the average carrier concentration per unit volume of each CS region (second storage region) 61 of the sensing region 34 is lower than the average carrier concentration per unit volume of the CS region 3 in the active region 32 ( Figure 7 Specifically, the CS region 61 of each cell 29 of the sensing region 34 has a structure in which a first portion 61 a having a relatively high carrier concentration and a second portion 61 b ​​having a relatively low carrier concentration are alternately and repeatedly arranged adjacent to each other in the long side direction (first direction X) of the trench 26 .

[0113] The maximum carrier concentration of the first portion 61a of the CS region 61 is substantially the same as the maximum carrier concentration of the CS region 3 of the active effective region 32. The thickness d1 of the first portion 61a of the CS region 61 is, for example, substantially the same as the thickness of the CS region 3 of the active effective region 32. The carrier concentration of the second portion 61b of the CS region 61 is lower than the carrier concentration of the first portion 61a of the CS region 61. By making the thickness d2 of the second portion 61b of the CS region 61 thinner than the thickness d1 of the first portion 61a of the CS region 61, the carrier concentration of the second portion 61b of the CS region 61 can be lower than the carrier concentration of the first portion 61a of the CS region 61.

[0114] In the case where the thickness of the CS region 61 is made relatively thin in the second portion 61 b, the lower surface (p + The surface on the side of the p-type collector region 13) is formed into a shape that is recessed and undulated toward the p-type base region 22 in the second portion 61b. That is, the lower portion (p + In this way, by configuring the second portion 61 b ​​in each CS region 61 to locally reduce the carrier concentration, the average carrier concentration per unit volume of each CS region 61 can be made lower than the average carrier concentration per unit volume of the CS region 3 in the active region 32.

[0115] The first portion 61a and the second portion 61b of the CS region 61 can be formed simultaneously by appropriately setting the opening pattern of the ion implantation mask 71 and performing a single ion implantation 72 (a single ion implantation step). Figure 8). For example, an ion implantation mask 71 that opens a formation region (not shown) of the CS region 3 of the active region 32 and a formation region 73 of the first portion 61a of the CS region 61 is used to perform ion implantation 72 of an n-type impurity into the semiconductor substrate 40. Since the CS region 3 and the first portion 61a of the CS region 61 are formed at the same time, the thickness d1 of the first portion 61a of the CS region 61 becomes substantially the same as the thickness of the CS region 3 of the active region 32.

[0116] The impurities injected into the first portion 61a of the CS region 61 are diffused by subsequent heat treatment (impurity diffusion), thereby connecting the first portions 61a of the CS region 61 that are dispersed in the first direction X. The connecting portion between the first portions 61a adjacent to each other in the first direction X becomes the second portion 61b of the CS region 61. In the formation region of the second portion 61b of the CS region 61, the n-type impurities are not ion-implanted 72 ( Figure 8 ). Therefore, the carrier concentration of the second portion 61b of the CS region 61 becomes lower than the carrier concentration of the first portion 61a of the CS region 61. Before the heat treatment step for impurity diffusion, ion implantation 75 may be performed separately at a dose lower than that of ion implantation 72 for forming the first portion 61a of the CS region 61 in order to form the second portion 61b of the CS region 61 ( Fig. 9 ).

[0117] The ion implantation mask 71 may be formed with an opening pattern covering the formation region of the second portion 61b of the CS region 61 of the sensing region 34. Specifically, the ion implantation mask 71 in the active region 32 forms openings (not shown) in an opening pattern extending in a stripe shape in the first direction X so as to expose the entire surface of the formation region of the CS region 3. The ion implantation mask 71 in the sensing region 34 forms openings 71a in an opening pattern extending in a stripe shape in the second direction Y, for example, over the entire region of the sensing region 34, for example, so as to expose only the formation region 73 of the first portion 61a of the CS region 61.

[0118] The ion implantation 72 is performed in the sensing region 34 at least in the formation region 73 of the first portion 61a of the CS region 61. Therefore, the maximum carrier concentration of the first portion 61a of the CS region 61 becomes substantially the same as the maximum carrier concentration of the CS region 3 of the active region 32. In the case where the ion implantation 72 is performed from a direction perpendicular to the front surface of the semiconductor substrate 40 ( Figure 8), in the formation region of the second portion 61b of the CS region 61, the n-type impurity is not ion-implanted 72. Since the second portion 61b of the CS region 61 is formed by thermal diffusion of the n-type impurity from the first portion 61a of the CS region 61, the maximum carrier concentration of the second portion 61b of the CS region 61 becomes lower than the maximum carrier concentration of the first portion 61a of the CS region 61.

[0119] When multiple ion implantations 72 and 75 are performed on the front surface of the semiconductor substrate 40 to form the CS region 61 ( Figure 8 , 9 ), the maximum carrier concentration of the first portion 61a and the maximum carrier concentration of the second portion 61b of the CS region 61 can be controlled by the doses of the multiple ion implantations 72 and 75. In this case, as long as the maximum carrier concentration of the second portion 61b of the CS region 61 is made lower than the maximum carrier concentration of the first portion 61a of the CS region 61, the implantation depth of the ion implantation 75 for forming the second portion 61b of the CS region 61 may be deeper than the formation region 73 of the first portion 61a of the CS region 61 (the implantation depth of the ion implantation 72), or may be shallower than the formation region 73 of the first portion 61a of the CS region 61 (the implantation depth of the ion implantation 72).

[0120] The ion implantation mask 74 used for the ion implantation 75 for forming the second portion 61b of the CS region 61 may be formed with an opening pattern covering the formation region 73 of the first portion 61a of the CS region 61. Therefore, the ion implantation mask 74 may be formed with an opening pattern extending in a stripe shape in the second direction Y over the entire region of the sensing region 34, for example, so as to expose only the formation region of the second portion 61b of the CS region 61. Fig. 9 ). In addition, in the ion implantation 75 for forming the second portion 61 b ​​of the CS region 61 , an oblique ion implantation performed in a direction oblique to the front surface of the semiconductor substrate 40 may be used.

[0121] The second portion 61b may be arranged in a certain period in the CS region 61. Thus, the unbalanced withstand voltage in the plane of the sensing region 34 can be suppressed. In addition, since the average carrier concentration per unit area of ​​each CS region 61 is reduced by arranging the second portion 61b in each CS region 61, the CS region 61 may be arranged in all the cells 29 of the current sensing unit 20. In addition, the first portion 61a and the second portion 61b of the CS region 61 may be arranged alternately and repeatedly adjacent to each other in the second direction Y (the short side direction of the groove 26), and may be extended in a stripe shape in the first direction X (the long side direction of the groove 26).

[0122] As described above, according to the second embodiment, even when the average carrier concentration per unit area of ​​the CS region of the sensing region is locally reduced, the same effects as those of the first embodiment can be obtained.

[0123] As described above, the present invention is not limited to the above-mentioned embodiments, and various changes can be made without departing from the scope of the present invention. For example, in the above-mentioned embodiments, the carrier concentration of the CS region (or the first part of the CS region) of the current sensing part can be lower than the carrier concentration of the CS region of the main semiconductor element throughout the entire area. In this case, the CS region can be configured in all units of the current sensing part. In order to make the carrier concentration of the CS region of the current sensing part lower than the carrier concentration of the CS region of the main semiconductor element, the CS region of the current sensing part can be formed at a different time from the CS region of the main semiconductor element.

[0124] In addition, the voltage fluctuation in the sense resistor and the overcurrent detection of the main semiconductor element can be performed by configuring a high-function portion on the same semiconductor substrate. In addition, the present invention is not limited to IGBTs, but can also be applied to MOSFETs (Metal Oxide Semiconductor Field Effect Transistor: a MOS field effect transistor with an insulated gate composed of a three-layer structure of metal-oxide film-semiconductor). In addition, in each embodiment, the first conductivity type is set to n-type and the second conductivity type is set to p-type, but the present invention also holds true when the first conductivity type is set to p-type and the second conductivity type is set to n-type.

[0125] Industrial Applicability As described above, the semiconductor device of the present invention is useful as a power semiconductor device used in a power conversion device, a power supply device for various industrial machines, and the like.

Claims

1. A semiconductor device, characterized in that: have: a first device region of a semiconductor substrate; a second device region of the semiconductor substrate other than the first device region; A first element, which is disposed in the first element region; a second element disposed in the second element region; A first semiconductor region of a first conductivity type, which is disposed inside the semiconductor substrate and is shared by the first element and the second element; a second semiconductor region provided between the back surface of the semiconductor substrate and the first semiconductor region and shared by the first element and the second element; and a back electrode, which is disposed on the back side of the semiconductor substrate and is electrically connected to the second semiconductor region, The first element comprises: A third semiconductor region of the second conductivity type, which is arranged between the front surface of the semiconductor substrate and the first semiconductor region in the first element region; A fourth semiconductor region of the first conductivity type, which is selectively disposed between the front surface of the semiconductor substrate and the third semiconductor region; a first accumulation region of a first conductivity type, which is disposed between the third semiconductor region and the first semiconductor region and has an impurity concentration higher than that of the first semiconductor region; a first trench, which penetrates the fourth semiconductor region and the third semiconductor region from the front surface of the semiconductor substrate and terminates inside the first semiconductor region; a first gate electrode provided inside the first trench via a first gate insulating film; and a first electrode, which is disposed on the front surface of the semiconductor substrate and is electrically connected to the third semiconductor region and the fourth semiconductor region, The second element comprises: a fifth semiconductor region of the second conductivity type, which is provided between the front surface of the semiconductor substrate and the first semiconductor region in the second element region; a sixth semiconductor region of the first conductivity type, which is selectively disposed between the front surface of the semiconductor substrate and the fifth semiconductor region; a second accumulation region of the first conductivity type, which is disposed between the fifth semiconductor region and the first semiconductor region and has an impurity concentration higher than that of the first semiconductor region; a second trench, which penetrates the sixth semiconductor region and the fifth semiconductor region from the front surface of the semiconductor substrate and terminates inside the first semiconductor region; a second gate electrode disposed inside the second trench via a second gate insulating film; as well as a second electrode, which is disposed on the front surface of the semiconductor substrate and is electrically connected to the fifth semiconductor region and the sixth semiconductor region, An average carrier concentration per unit area of ​​the second accumulation region in the second element region is lower than an average carrier concentration per unit area of ​​the first accumulation region in the first element region.

2. The semiconductor device according to claim 1, wherein: An average carrier concentration per unit area of ​​the second accumulation region in the second element region is greater than or equal to 0.2 times and less than or equal to 0.6 times an average carrier concentration per unit area of ​​the first accumulation region in the first element region.

3. The semiconductor device according to claim 1 or 2, characterized in that: The second accumulation region includes a first portion and a second portion having a carrier concentration lower than that of the first portion.

4. The semiconductor device according to claim 3, wherein: The thickness of the second portion is thinner than the thickness of the first portion.

5. The semiconductor device according to claim 4, wherein: The surface of the second storage region on the back electrode side is formed into an undulating shape that is recessed toward the second electrode side in the second portion.

6. The semiconductor device according to claim 3, wherein: The carrier concentration of the first portion is the same as the carrier concentration of the first accumulation region.

7. The semiconductor device according to claim 1 or 2, characterized in that: The carrier concentration of the second accumulation region is lower than the carrier concentration of the first accumulation region throughout the entire region of the second accumulation region.

8. The semiconductor device according to claim 1 or 2, characterized in that: All first cells of the first element include the third semiconductor region, the fourth semiconductor region, the first accumulation region, and the first gate electrode. The second element has a number of second units which is smaller than the number of the first element, The second unit comprises: a third unit having the fifth semiconductor region, the sixth semiconductor region, the second accumulation region, and the second gate electrode; and A fourth unit includes the fifth semiconductor region, the sixth semiconductor region, and the second gate electrode, and does not include the second accumulation region.

9. The semiconductor device according to claim 8, wherein: The third unit and the fourth unit are repeatedly configured according to a certain period.

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