Semiconductor device, method for manufacturing semiconductor device, electronic apparatus, and vehicle

Abstract

The invention discloses a semiconductor device, a preparation method of the semiconductor device, electronic equipment and a vehicle. The semiconductor device comprises a drift layer of a first conduction type; a carrier storage layer of a first conductivity type, the carrier storage layer being located on the drift layer in a first direction perpendicular to the drift layer; a body region of the second conductive type, wherein the body region is located on the carrier storage layer along the first direction; an emitter region of the first conductive type, wherein the emitter region is located on the body region along the first direction; each groove true gate structure penetrates through the carrier storage layer, the body region and the emission region in the first direction and extends into the drift layer, the width of the groove true gate structure is larger and larger in the second direction from the carrier storage layer to the drift layer in the first direction, and the second direction is parallel to the drift layer and perpendicular to the first direction. By adopting the semiconductor device, the anti-short-circuit capability of the semiconductor device can be effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of vehicle technology, and in particular to a semiconductor device, a method for preparing a semiconductor device, an electronic device and a vehicle. Background Art

[0002] In the related art, in order to pursue lower saturation voltage drop and loss, the channel density of trench gate IGBT in existing semiconductor devices has been made larger and larger. However, as the channel density increases, while the channel resistance is reduced, the saturation current density will increase, thereby reducing the short-circuit tolerance of the device. In other words, existing semiconductor devices have the problem of poor short-circuit reliability. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, one object of the present invention is to provide a semiconductor device, which can effectively improve the short circuit resistance of the semiconductor device.

[0004] A second object of the present invention is to provide a method for preparing a semiconductor device.

[0005] A third objective of the present invention is to provide an electronic device.

[0006] A fourth object of the present invention is to provide a vehicle.

[0007] In order to solve the above problems, an embodiment of the first aspect of the present invention provides a semiconductor device, comprising: a drift layer of a first conductivity type; a carrier storage layer of a first conductivity type, the carrier storage layer being located on the drift layer in a first direction perpendicular to the drift layer; a body region of a second conductivity type, the body region being located on the carrier storage layer along the first direction; an emitter region of a first conductivity type, the emitter region being located on the body region along the first direction; and at least one trench true gate structure, each of the trench true gate structures penetrating the carrier storage layer, the body region and the emitter region along the first direction and extending into the drift layer, and along the first direction from the carrier storage layer to the drift layer, the width of the trench true gate structure along the second direction becomes larger and larger, and the second direction is parallel to the drift layer and perpendicular to the first direction.

[0008] According to the semiconductor device of the embodiment of the present invention, by setting a trench true gate structure with increasing width along the second direction, part of the current channel is increased to limit the short-circuit current of the semiconductor device, thereby improving the short-circuit resistance of the semiconductor device.

[0009] In some embodiments, along the first direction from the carrier storage layer to the drift layer, at least one side of the trench true gate structure in the second direction is stepped.

[0010] In some embodiments, the trench true gate structure includes: a first gate oxide layer, the first gate oxide layer is constructed as a first oxide layer trench, the first oxide layer trench penetrates the carrier storage layer, the body region and the emitter region along the first direction and extends into the drift layer, along the first direction from the carrier storage layer to the drift layer, and the first oxide layer trench is stepped on at least one side in the second direction.

[0011] In some embodiments, the trench true gate structure also includes: a first polysilicon layer of a first conductivity type and a second polysilicon layer of a second conductivity type, the first polysilicon layer and the second polysilicon layer are filled in the first oxide layer trench, the first polysilicon layer is located on the second polysilicon layer in the first direction, the width of the second polysilicon layer along the second direction is greater than the width of the first polysilicon layer along the second direction, and at least one side of the first polysilicon layer and the second polysilicon layer in the second direction matches the step shape.

[0012] In some embodiments, along the first direction from the carrier storage layer to the drift layer, the first oxide layer trench has multiple steps on at least one side in the second direction; the first polysilicon layer fills at least one step of the multiple steps, and the second polysilicon layer fills at least one step of the multiple steps.

[0013] In some embodiments, the first polysilicon layer is in contact with the second polysilicon layer.

[0014] In some embodiments, the first polysilicon layer and the second polysilicon layer are both connected to a gate potential.

[0015] In some embodiments, the first gate oxide layer is further filled between the first polysilicon layer and the second polysilicon layer.

[0016] In some embodiments, the first polysilicon layer is connected to a gate potential, and the second polysilicon layer is connected to an emitter potential.

[0017] In some embodiments, the second polysilicon layer includes: a plurality of sub-polysilicon layers, the plurality of sub-polysilicon layers are arranged along the first direction, and the widths of the plurality of sub-polysilicon layers along the second direction increase from close to the first polysilicon layer to far away from the first polysilicon layer in the first direction.

[0018] In some embodiments, the second polysilicon layer fills multiple steps of the multiple steps of the first oxide layer trench; and the multiple sub-polysilicon layers fill different step positions corresponding to the first oxide layer trench.

[0019] In some embodiments, the first gate oxide layer further surrounds each of the sub-polysilicon layers.

[0020] In some embodiments, the first polysilicon layer is connected to a gate potential, and each sub-polysilicon layer is connected to an emitter potential.

[0021] In some embodiments, the first oxide layer trench constructed by the first gate oxide layer has three steps on at least one side in the second direction, from the carrier storage layer to the drift layer along the first direction, and the three steps include a first step, a second step and a third step.

[0022] In some embodiments, the first polysilicon layer fills the first oxide layer trench corresponding to the first step; the second polysilicon layer fills the first oxide layer trench corresponding to the second step and the third step, and the second polysilicon layer matches the second step and the third step in a stepped shape.

[0023] In some embodiments, a lower surface of the first polysilicon layer is flush with a lower surface of the body region.

[0024] In some embodiments, the semiconductor device further includes: at least one trench dummy gate structure, the at least one trench dummy gate structure and the at least one trench true gate structure are arranged at intervals along the second direction, and each of the trench dummy gate structures penetrates the carrier storage layer, the body region and the emitter region along the first direction and extends into the drift layer.

[0025] In some embodiments, the trench pseudo-gate structure includes: a second gate oxide layer, the second gate oxide layer is constructed as a second oxide layer trench, the second oxide layer trench penetrates the carrier storage layer, the body region and the emitter region along the first direction and extends into the drift layer; a third polysilicon layer of the first conductivity type, the third polysilicon layer is filled in the second oxide layer trench.

[0026] In some embodiments, the semiconductor device further includes: a dielectric layer, the dielectric layer being located on the emitter region along the first direction; an emitter metal layer, the emitter metal layer being located on the dielectric layer along the first direction, the emitter metal layer being connected to the body region and the third polysilicon layer through a contact hole.

[0027] In some embodiments, the semiconductor device includes a plurality of trench true gate structures, and in the second direction, the at least one trench dummy gate structure is located between the plurality of trench true gate structures.

[0028] In some embodiments, the semiconductor device includes two of the trench true gate structures and two of the trench dummy gate structures. In the second direction, the two trench dummy gate structures and the two trench dummy gate structures are arranged at intervals, and the two trench dummy gate structures are located between the two trench true gate structures.

[0029] In some embodiments, the trench true gate structure is stepped in the second direction toward one side of the trench dummy gate structure.

[0030] In some embodiments, the body region between the two trench dummy gate structures is floating.

[0031] In some embodiments, the semiconductor device further includes: a substrate layer of a first conductivity type, the substrate layer being located on a side of the drift layer away from the carrier storage layer; a collector region of a first conductivity type, the collector region being located on a side of the substrate layer away from the drift layer; and a collector metal layer, the collector metal layer being located on a side of the collector region away from the substrate layer.

[0032] A second aspect of the present invention provides a method for preparing a semiconductor device, comprising: providing a drift layer of a first conductivity type; sequentially preparing a carrier storage layer of a first conductivity type, a body region of a second conductivity type, and an emitter region of a first conductivity type on the drift layer along a first direction, wherein the first direction is a direction perpendicular to the drift layer; preparing at least one trench true gate structure, each of the trench true gate structures penetrating the carrier storage layer, the body region, and the emitter region along the first direction and extending into the drift layer, and along the first direction from the carrier storage layer to the drift layer, the width of the trench true gate structure along the second direction becomes larger and larger, and the second direction is parallel to the drift layer and perpendicular to the first direction.

[0033] According to the method for preparing a semiconductor device in an embodiment of the present invention, at least one trench true gate structure is prepared by penetrating the carrier storage layer, the body region and the emitter region and extending into the drift layer, and the width of the trench true gate structure along the second direction becomes larger and larger, so that part of the current channel is increased, thereby improving the short-circuit resistance of the semiconductor device 100.

[0034] In some embodiments, at least one trench true gate structure is prepared, including: preparing a first trench along the first direction penetrating the carrier storage layer, the body region and the emitter region and extending into the drift layer, preparing a first gate oxide layer in the first trench, the first gate oxide layer being constructed as a first oxide layer trench, from the carrier storage layer to the drift layer along the first direction, the first oxide layer trench being stepped on at least one side in the second direction; filling a first polysilicon layer of a first conductivity type and a second polysilicon layer of a second conductivity type in the first oxide layer trench, wherein the first polysilicon layer is located on the second polysilicon layer in the first direction, the width of the second polysilicon layer along the second direction is greater than the width of the first polysilicon layer along the second direction, and at least one side of the first polysilicon layer and the second polysilicon layer in the second direction matches the stepped shape.

[0035] In some embodiments, along the first direction from the carrier storage layer to the drift layer, the first oxide layer trench is multi-stepped on at least one side in the second direction; a first polysilicon layer of a first conductivity type and a second polysilicon layer of a second conductivity type are filled in the first oxide layer trench, including: filling the first polysilicon layer in the first oxide layer trench corresponding to at least one step in the multi-step steps, and filling the second polysilicon layer in the first oxide layer trench corresponding to at least one step in the multi-step steps.

[0036] In some embodiments, the first polysilicon layer is in contact with the second polysilicon layer, and both the first polysilicon layer and the second polysilicon layer are connected to a gate potential.

[0037] In some embodiments, the first gate oxide layer is further filled between the first polysilicon layer and the second polysilicon layer, the first polysilicon layer is connected to a gate potential, and the second polysilicon layer is connected to an emitter potential.

[0038] In some embodiments, the second polysilicon layer includes a plurality of sub-polysilicon layers, and a first polysilicon layer of a first conductivity type and a second polysilicon layer of a second conductivity type are filled in the first oxide layer trench, including: preparing a plurality of sub-polysilicon layers in the first oxide layer trench near the bottom of the first oxide layer trench, the plurality of sub-polysilicon layers are arranged along the first direction, and the widths of the plurality of sub-polysilicon layers along the second direction are increasing from close to the first polysilicon layer to far away from the first polysilicon layer in the first direction; preparing the first polysilicon layer in the first oxide layer trench, the first polysilicon layer is located above the plurality of sub-polysilicon layers in the first direction; wherein the first gate oxide layer also surrounds each of the sub-polysilicon layers, the first polysilicon layer is connected to the gate potential, and each sub-polysilicon layer is connected to the emitter potential.

[0039] In some embodiments, the preparation method also includes: preparing at least one trench dummy gate structure, the at least one trench dummy gate structure and the at least one trench true gate structure are arranged at intervals along the second direction, each of the trench dummy gate structures penetrates the carrier storage layer, the body region and the emitter region along the first direction and extends into the drift layer; preparing a dielectric layer on the emitter region along the first direction; preparing an emitter metal layer on the dielectric layer along the first direction, and the emitter metal layer is connected to the body region and the third polysilicon layer through a contact hole.

[0040] In some embodiments, the preparation method further includes: preparing the drift layer on a substrate layer of a first conductivity type; preparing a collector region of a first conductivity type on a side of the substrate layer away from the drift layer; and preparing a collector metal layer on a side of the collector region away from the substrate layer.

[0041] A third aspect of the present invention provides an electronic device, comprising the semiconductor device described in the above embodiment.

[0042] According to the electronic device of the embodiment of the present invention, the short circuit resistance of the semiconductor device can be effectively improved through the semiconductor device of the above embodiment.

[0043] A fourth aspect of the present invention provides a vehicle, wherein the vehicle includes the electronic device described in the above embodiment, or the vehicle includes the semiconductor device described in the above embodiment.

[0044] According to the vehicle of the embodiment of the present invention, the short-circuit resistance of the semiconductor device can be effectively improved by using the semiconductor device of the above embodiment.

[0045] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which: Figure 1 It is a schematic diagram of the structure of an existing semiconductor device; Figure 2 It is a schematic diagram of the structure of an existing semiconductor device; Figure 3 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention; Figure 4 is a schematic structural diagram of a semiconductor device according to another embodiment of the present invention; Figure 5 is a schematic structural diagram of a semiconductor device according to another embodiment of the present invention; Figure 6 is a flow chart of a method for preparing a semiconductor device according to an embodiment of the present invention; Figure 7 is a structural block diagram of an electronic device according to an embodiment of the present invention; Figure 8 is a structural block diagram of an electronic device according to an embodiment of the present invention; Fig. 9 is a structural block diagram of an electronic device according to an embodiment of the present invention.

[0047] Reference numerals: Existing semiconductor device 100'; True gate 5'; Vehicle 1000; electronic device 200; semiconductor device 100; Drift layer 1; carrier storage layer 2; body region 3; emitter region 4; trench true gate structure 5; first gate oxide layer 51; first polysilicon layer 52; sub-polysilicon layer 53; second polysilicon layer 54; trench false gate structure 6; second gate oxide layer 61; third polysilicon layer 62; dielectric layer 7; emitter metal layer 8; substrate layer 9; collector region 10; collector metal layer 11. DETAILED DESCRIPTION

[0048] Embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Embodiments of the present invention are described in detail below.

[0049] At present, the semiconductor device is IGBT (Insulated gate bipolar transistor), and trench gate IGBT has the advantages of reduced forward conduction voltage, low loss, strong anti-latch capability, etc. Trench gate technology has been used as the main means to improve chip current density. It can eliminate the JFET (Junction Field-Effect Transistor) area and transform the planar channel into a vertical channel to save device area, which is conducive to the design of compact cells, that is, more IGBT cells can be made on the same chip area, thereby increasing the width of the conductive channel, reducing the channel resistance, and effectively reducing the overall on-state voltage drop of the device.

[0050] However, in order to pursue lower saturation voltage drop and loss, the channel density of trench gate IGBT is getting larger and larger. However, as the channel density increases, while the channel resistance is reduced, the saturation current density will increase, thereby reducing the short-circuit withstand capability of the device. In addition, as the depth of the trench structure increases, the gate-drain capacitance of the IGBT will also increase, reducing the switching speed of the IGBT.

[0051] In addition, low-loss IGBTs have become the main development trend of IGBTs in recent years. Usually, an N-type carrier storage layer (CS layer) with a higher doping concentration than the N-drift region is introduced at the bottom of the P-type base region to form a hole barrier. When the device is turned on, the CS layer will act as a hole blocking layer to enhance the accumulation of holes on the side of the drift region close to the emitter, and the electrons required by electrical neutrality will also accumulate here, thereby greatly increasing the carrier concentration in the drift region and reducing the forward conduction voltage drop. Since the increase in carrier accumulation is on the side close to the emitter, it will not have a great impact on the extraction during shutdown, that is, it will not cause the device to increase the turn-off loss, so the carrier storage trench IGBT device can improve the trade-off relationship between the conduction voltage drop and the turn-off loss. However, this structure has a performance defect: as the doping concentration of the CS layer increases, the forward conduction voltage drop continues to decrease while the device withstand voltage will be greatly degraded, thereby affecting the reliability of the device.

[0052] In the related art, the structure of the existing semiconductor device 100' is as follows Figure 1 As shown in the figure, existing semiconductor devices can make more IGBT cells on the same chip area, thereby increasing the width of the conductive channel and reducing the channel resistance. In addition, because the trench IGBT vertically eliminates the JFET area, the resistance of the entire current path is lower. Therefore, compared with the planar IGBT, the trench IGBT can significantly reduce the on-state voltage drop without increasing the switching loss, thereby optimizing the overall performance of the chip, but the gate-drain capacitance of the structure will increase and the switching characteristics will deteriorate.

[0053] The dummy gate technology is added to the structure of the traditional trench gate IGBT, such as Figure 2 As shown, a dummy gate 6' is added to the structure of a traditional semiconductor device 100'. The dummy gate technology can not only further reduce the trench size, which is more conducive to optimizing the compromise characteristics of the IGBT chip, but also reduce the channel density and reduce the short-circuit current of the IGBT chip. Moreover, since the dummy gate is connected to the low potential of the emitter, it has a lower gate-drain capacitance, so its switching characteristics will be improved.

[0054] Despite this, trench gate IGBTs still have problems such as low switching speed and poor short-circuit reliability.

[0055] In order to solve the above problems, a first embodiment of the present invention provides a semiconductor device, which can effectively improve the short-circuit resistance of the semiconductor device.

[0056] Reference below Figure 3 A semiconductor device 100 according to an embodiment of the present invention is described. Figure 3 As shown, the semiconductor device 100 includes: a drift layer 1 of a first conductivity type, a carrier storage layer 2 of a first conductivity type, a body region 3 of a second conductivity type, an emitter region 4 of a first conductivity type, and at least one trench true gate structure 5.

[0057] Among them, the carrier storage layer 2 is located on the drift layer 1 in a first direction perpendicular to the drift layer 1; the body region 3 of the second conductivity type, the body region 3 is located on the carrier storage layer 2 along the first direction; the emitter region 4 is located on the body region 3 along the first direction; each trench true gate structure 5 passes through the carrier storage layer 2, the body region 3 and the emitter region 4 along the first direction and extends into the drift layer 1, and the width of the trench true gate structure 5 along the second direction from the carrier storage layer 2 to the drift layer 1 along the first direction is getting larger and larger, and the second direction is parallel to the drift layer 1 and perpendicular to the first direction. The first conductivity type can be N-type, and the second conductivity type can be P-type. Conversely, the first conductivity type can be P-type and the second conductivity type can be N-type. The semiconductor device 100 can be an IGBT, and can be made of other semiconductor materials such as body silicon, silicon carbide, etc. The number of trench true gate structures is not limited.

[0058] Specifically, since the short current channel can easily cause a short circuit in the semiconductor device 100, in order to solve this problem, the semiconductor device 100 in the present application is provided with a trench true gate structure 5, that is, at least one trench true gate structure 5 is prepared in the carrier storage layer 2, the body region 3, the emitter region 4 and the drift layer 1, each trench true gate structure 5 penetrates the carrier storage layer 2, the body region 3 and the emitter region 4 along a first direction and extends into the drift layer 1, and the width of the trench true gate structure 5 along the second direction becomes larger and larger, that is, the trench true gate structure 5 presents a shape that is narrow at the top and wide at the bottom, so that part of the current channel is increased to limit the short-circuit current of the semiconductor device, thereby improving the short-circuit resistance of the semiconductor device.

[0059] According to the semiconductor device 100 of the embodiment of the present invention, by setting the trench true gate structure 5 with increasing width along the second direction, part of the current channel is increased to limit the short-circuit large current of the semiconductor device, thereby improving the short-circuit resistance of the semiconductor device.

[0060] In some embodiments, along the first direction from the carrier storage layer 2 to the drift layer 1, the trench true gate structure 5 is stepped on at least one side in the second direction, that is, the trench true gate structure 5 presents a stepped shape that is narrow at the top and wide at the bottom. For example, the trench true gate structure 5 is stepped on either side in the second direction, or the trench true gate structure 5 is stepped on both sides in the second direction. Thus, through the trench true gate structure 5 with a stepped shape that is narrow at the top and wide at the bottom, part of the current channel is increased, thereby improving the short-circuit resistance of the semiconductor device 100 and enhancing the short-circuit reliability of the device.

[0061] In some embodiments, Figure 3 As shown, the trench true gate structure 5 includes: a first gate oxide layer 51 .

[0062] Among them, the first gate oxide layer 51 is constructed as a first oxide layer groove, and the first oxide layer groove penetrates the carrier storage layer 2, the body region 3 and the emitter region 4 along the first direction and extends into the drift layer 1. Along the first direction from the carrier storage layer 2 to the drift layer 1, at least one side of the first oxide layer groove in the second direction is stepped. For example, the first oxide layer groove is stepped on either side in the second direction, or both sides of the first oxide layer groove are stepped in the second direction. The first gate oxide layer 51 is used to isolate the carrier storage layer, the body region 3, the emitter region 4 and the drift layer 1 inside the trench from outside the trench, and at the same time, at least one side of the first oxide layer groove in the second direction is stepped, so that part of the current channel is increased, thereby improving the short circuit resistance of the semiconductor device 100.

[0063] In some embodiments, Figure 3 As shown, the trench true gate structure 5 further includes: a first polysilicon layer 52 of the first conductivity type and a second polysilicon layer 54 of the second conductivity type.

[0064] The first polysilicon layer 52 and the second polysilicon layer 54 are filled in the first oxide layer trench, the first polysilicon layer 52 is located on the second polysilicon layer 54 in the first direction, the width of the second polysilicon layer 54 along the second direction is greater than the width of the first polysilicon layer 52 along the second direction, and at least one side of the first polysilicon layer 52 and the second polysilicon layer 54 in the second direction matches the step shape, such as Figure 3 As shown, the first polysilicon layer 52 and the second polysilicon layer 54 are in a stepped shape, that is, the width of at least one side of the first polysilicon layer 52 along the second direction is lower than the width of at least one side of the second polysilicon layer 54 along the second direction, and the first polysilicon layer 52 and the second polysilicon layer 54 are in a multi-step shape that is narrow at the top and wide at the bottom.

[0065] Specifically, the first polysilicon layer 52 and the second polysilicon layer 54 form a PN junction, and the PN junction capacitance is in series with the original gate-drain capacitance, so that the total capacitance is reduced, thereby reducing the total gate-drain capacitance, so as to improve the switching characteristics of the semiconductor device 100. In addition, in the trench true gate structure 5, since at least one side of the first polysilicon layer 52 and the second polysilicon layer 54 in the second direction matches the step shape, the electric field peak of the emitter can be further weakened, thereby improving the withstand voltage capability of the semiconductor device 100.

[0066] In an embodiment, in a withstand voltage state, electric lines of force emitted by positive charges in the depletion regions of the drift layer 1 and the carrier storage layer 2 may terminate at negative charges in the first polysilicon layer 52 and the second polysilicon layer 54 .

[0067] In some embodiments, along the first direction from the carrier storage layer 2 to the drift layer 1, at least one side of the first oxide layer trench in the second direction is multi-stepped, and the multi-stepped stairs can be two-stepped, three-stepped, four-stepped, five-stepped, etc.; the first polysilicon layer 52 fills at least one level of the multi-stepped stairs, and the second polysilicon layer 54 fills at least one level of the multi-stepped stairs, that is, the second polysilicon layer 54 can fill one level of the multi-stepped stairs, or can also fill multiple levels of the multi-stepped stairs, that is, when the first polysilicon layer 52 and the second polysilicon layer 54 are filled in the first When forming the oxide layer groove, the first polysilicon layer 52 is filled in at least one of the multi-level steps of the first oxide layer groove, and the second polysilicon layer 54 is filled in at least one of the multi-level steps other than the first polysilicon layer 52, that is, at least one layer of the first polysilicon layer 52 and at least one layer of the second polysilicon layer 54 are stacked in the multi-level steps. Thus, the at least one layer of the first polysilicon layer 52 and the at least one layer of the second polysilicon layer 54 are in a stepped shape, which can further weaken the electric field peak of the emitter, thereby improving the voltage resistance of the semiconductor device 100.

[0068] In addition, the trench true gate structure 5 is in the form of multiple steps. The shape of the trench true gate structure can be three-layer steps with narrow top and wide bottom, four-layer steps, five-layer steps, etc., and there is no limitation on this.

[0069] In some embodiments, Figure 3 , which is a schematic diagram of a structure of a semiconductor device 100 according to an embodiment of the present invention, in which the first polysilicon layer 52 and the second polysilicon layer 54 are in contact with each other in the trench true gate structure 5 .

[0070] In some embodiments, the first polysilicon layer 52 and the second polysilicon layer 54 are both connected to the gate potential, that is, the first polysilicon layer 52 and the second polysilicon layer 54 are connected to a high potential.

[0071] Exemplarily, when the semiconductor device 100 is turned on, a positive voltage is applied to the gate, and the PN junction formed by the first polysilicon layer 52 and the second polysilicon layer 54 is reverse biased. The second polysilicon layer 54 also serves to isolate the gate electrode from the drain electrode, thereby improving the switching characteristics.

[0072] In some embodiments, the first gate oxide layer 51 is also filled between the first polysilicon layer 52 and the second polysilicon layer 54 to isolate the first polysilicon layer 52 from the second polysilicon layer 54. Figure 4 As shown, the first polysilicon layer 52 and the second polysilicon layer 54 of the semiconductor structure in the present application may not be in contact with each other.

[0073] In some embodiments, the first polysilicon layer 52 is connected to a gate potential, and the second polysilicon layer 54 is connected to an emitter potential.

[0074] In some embodiments, Figure 5 , which is a schematic diagram of the structure of a semiconductor device 100 according to an embodiment of the present invention, the second polysilicon layer 54 includes a plurality of sub-polysilicon layers 53 .

[0075] For example, Figure 5 As shown, a structure diagram of a semiconductor device 100 according to an embodiment of the present invention is shown. The sub-polysilicon layer 53 separates the contact between the first polysilicon layer of the gate and the collector, so that part of the gate-drain capacitance is converted into the gate-source capacitance, thereby reducing the gate-drain capacitance, so as to better improve the switching characteristics of the device.

[0076] The plurality of sub-polysilicon layers 53 are arranged along the first direction, and the widths of the plurality of sub-polysilicon layers 53 along the second direction are increasing from close to the first polysilicon layer 52 to far away from the first polysilicon layer 52 in the first direction. Thus, the plurality of sub-polysilicon layers 53 are presented in a multi-step shape with narrow top and wide bottom, which can further weaken the electric field peak of the emitter, thereby improving the withstand voltage capability of the semiconductor device 100.

[0077] In some embodiments, the second polysilicon layer 54 fills multiple steps of the multi-step steps of the first oxide layer trench; multiple sub-polysilicon layers 53 fill different step positions corresponding to the first oxide layer trench, that is, the multiple sub-polysilicon layers 53 are stacked at different step positions in the multi-step steps of the first oxide layer trench, thereby making the multiple sub-polysilicon layers 53 present a stepped shape, which can further weaken the electric field peak of the emitter, thereby improving the voltage resistance of the semiconductor device 100.

[0078] In some embodiments, Figure 5 As shown, the first gate oxide layer 51 further surrounds each sub-polysilicon layer 53 to isolate each sub-polysilicon layer 53 .

[0079] In some embodiments, the first polysilicon layer 52 is connected to a gate potential, each sub-polysilicon layer 53 is connected to an emitter potential, and the split sub-polysilicon layers 53 and the first polysilicon layer are in a step shape.

[0080] In some embodiments, the first oxide layer groove constructed by the first gate oxide layer 51 is three-stepped on at least one side in the second direction, from the carrier storage layer 2 to the drift layer 1 along the first direction, and the three-stepped steps include a first step, a second step, and a third step. Exemplarily, the first polysilicon layer 52 is filled in the first step, and the second polysilicon layer 54 is filled in the second step and the third step, or the first polysilicon layer 52 is filled in the first step and the second step, and the second polysilicon layer 54 is filled in the third step. Thus, at least one layer of the first polysilicon layer 52 and at least one layer of the second polysilicon layer 54 are stepped, which can further weaken the electric field peak of the emitter, thereby improving the voltage resistance of the semiconductor device 100.

[0081] In some embodiments, the first polysilicon layer 52 fills the first oxide layer trench corresponding to the first step; the second polysilicon layer 54 fills the first oxide layer trench corresponding to the second step and the third step, and the second polysilicon layer 54 matches the second step and the third step in a stepped shape.

[0082] In some embodiments, Figure 3 , which is a schematic diagram of a structure of a semiconductor device 100 according to an embodiment of the present invention, the lower surface of the first polysilicon layer 52 of the semiconductor device 100 is flush with the lower surface of the body region 3 .

[0083] In some embodiments, the semiconductor device 100 further includes: at least one trench dummy gate structure 6 .

[0084] Among them, at least one trench dummy gate structure 6 and at least one trench true gate structure 5 are arranged at intervals along the second direction, each trench dummy gate structure 6 penetrates the carrier storage layer 2, the body region 3 and the emitter region 4 along the first direction and extends into the drift layer 1, and at least one trench dummy gate structure 6 is distributed inside the drift layer 1. That is to say, the number of trench dummy gate structures 6 is not specifically limited in the present application. The trench dummy gate structure 6 can be rectangular, or it can be consistent with the shape of the trench true gate structure 5, which is narrow at the top and wide at the bottom.

[0085] Specifically, due to the high channel density of the semiconductor device 100, the channel resistance will be reduced and the proportion of electronic current will be increased, thereby reducing the on-state voltage drop. However, the attendant disadvantage is that the short-circuit current will be increased. The short-circuit current is so large that the semiconductor device 100 will be damaged in a very short time when a short circuit occurs. In order to solve this problem, in the present application, at least one trench dummy gate structure 6 is introduced into the semiconductor device 100 to reduce the proportion of electronic current, thereby reducing the short-circuit current and improving the short-circuit capability.

[0086] In some embodiments, Figure 3 As shown, the trench dummy gate structure 6 includes: a second gate oxide layer 61 and a third polysilicon layer 62 of the first conductivity type.

[0087] Among them, the second gate oxide layer 61 is constructed as a second oxide layer groove, the second oxide layer groove penetrates the carrier storage layer 2, the body region 3 and the emitter region 4 along the first direction and extends into the drift layer 1, and the second gate oxide layer 61 is used to isolate the third polysilicon layer 62 filled in the groove from the carrier storage layer 2, the body region 3, the emitter region 4 and the drift layer 1 outside the groove; the third polysilicon layer 62 is filled in the second oxide layer groove, the third polysilicon layer 62 is short-circuited with the emitter metal layer 8, and the third polysilicon layer 62 and the emitter metal layer 8 are equipotential, which effectively reduces the Miller capacitance, so that the semiconductor device 100 is turned on faster. At the same time, the trench pseudo-gate structure 6 can also effectively reduce the channel density and reduce the short-circuit current of the semiconductor device 100.

[0088] In an embodiment, under the withstand voltage state, the electric lines of force emitted by the positive charges in the depletion regions of the drift layer 1 and the carrier storage layer 2 can terminate at the third polysilicon layer 62 of the first conductivity type and the body region 3 , and the trench pseudo-gate structure 6 can assist in depleting the carriers in the carrier storage layer 2 .

[0089] In some embodiments, Figure 3 As shown, the semiconductor device 100 further includes a dielectric layer 7 and an emitter metal layer 8 .

[0090] Among them, the dielectric layer 7 is located on the emitter region 4 along the first direction, that is, the dielectric layer 7 is located on the upper surface of the emitter region 4, and the dielectric layer 7 is used to isolate the emitter metal layer 8; the emitter metal layer 8 is located on the dielectric layer 7 along the first direction, the emitter metal layer 8 is located on the upper surface of the dielectric layer 7, and the emitter metal layer 8 is connected to the body region 3 and the third polysilicon layer 62 through the contact hole.

[0091] In some embodiments, Figure 3 As shown, the semiconductor device 100 includes a plurality of trench true gate structures 5 .

[0092] In the second direction, at least one trench dummy gate structure 6 is located between the plurality of trench true gate structures 5 , so that the plurality of trench true gate structures 5 are separated by the trench dummy gate structure 6 , so as to avoid excessive current density.

[0093] In the embodiment, when the semiconductor device is turned on, the trench true gate structure 5 is connected to a positive voltage.

[0094] In some embodiments, Figure 3 As shown, the semiconductor device 100 includes two trench true gate structures 5 and two trench dummy gate structures 6 .

[0095] Among them, in the second direction, the two trench dummy gate structures 6 and the two trench dummy gate structures 6 are arranged at intervals, and the two trench real gate structures 5 are distributed on both sides of the edge of the entire drift layer 1, and their shape presents a multi-step shape that is narrow at the top and wide at the bottom. The two trench dummy gate structures 6 are located between the two trench real gate structures 5, that is, the two trench dummy gate structures 6 are surrounded by the two trench real gate structures 5. The trench dummy gate structure 6 is connected to a negative voltage.

[0096] In some embodiments, the trench true gate structure 5 is stepped on one side of the trench dummy gate structure 6 in the second direction, so that part of the current channel is increased, thereby improving the short circuit resistance of the semiconductor device 100 .

[0097] In some embodiments, the body region 3 between the two trench dummy gate structures 6 is floating. According to this design, the holes in the drift layer 1 can only flow to the emitter through the bottom of the dummy gate, and a higher concentration of holes is accumulated in the drift layer 1 close to the emitter side, so that the conductivity modulation effect is further enhanced and the saturation voltage drop is reduced, but the turn-off loss is not increased.

[0098] In some embodiments, Figure 3 As shown, the semiconductor device 100 further includes: a substrate layer of a first conductivity type, a collector region 10 of a first conductivity type, and a collector metal layer 11 .

[0099] Among them, the substrate layer is located on the side of the drift layer 1 away from the carrier storage layer 2, the drift region is located on the upper surface of the substrate layer; the collector region 10 is located on the side of the substrate layer away from the drift layer 1; the collector metal layer 11 is located on the side of the collector region 10 away from the substrate layer.

[0100] In the embodiment, the semiconductor device 100 is an IGBT. When the current density of the IGBT is too large, an excessively high hole current flows through the body region 3. The current generates a voltage drop on the path resistance of this region. When the voltage drop is large enough, the body region 3 and the emitter region 4 will form a forward-biased PN junction, and the parasitic NPN will enter the amplification region to work, and drive the lower PNP transistor to form positive feedback, so that the IGBT gate loses its ability to control the current, the current increases rapidly, and severe overheating and burning may occur. In order to avoid the above-mentioned latch-up phenomenon and prevent the parasitic NPN transistor from being turned on, it is necessary in the present application to ensure that the depth of the active area metal hole, i.e., the contact hole, near the trench true gate structure 5 is slightly deeper than the junction depth of the emitter area 4. Therefore, the body area 3, the emitter area 4 and the emitter potential near the trench true gate structure 5 are all at the same potential, and the base and emitter of the parasitic NPN transistor are short-circuited, that is, the body area 3 and the emitter area 4 are short-circuited, to ensure that the voltage of the base and emitter of the parasitic NPN transistor is zero or very small, thereby ensuring that the semiconductor device 100 will not be turned on to avoid the latch-up effect.

[0101] A second aspect of the present invention provides a method for manufacturing a semiconductor device 100, such as Figure 6 As shown, the method includes: Step S1, providing a drift layer of a first conductivity type.

[0102] For example, an N-type semiconductor substrate is selected as the drift layer 1 .

[0103] Step S2 , sequentially preparing a carrier storage layer of the first conductivity type, a body region of the second conductivity type, and an emitter region of the first conductivity type on the drift layer along a first direction, wherein the first direction is a direction perpendicular to the drift layer.

[0104] Exemplarily, first, a carrier storage layer 2 of a first conductivity type is formed on the surface of the drift layer 1 by ion implantation, and then a body region 3 of a second conductivity type is formed on the surface of the carrier storage layer 2 by photolithography and ion implantation, and finally, an emitter region 4 of a first conductivity type is formed on the surface of the body region 3 by photolithography and the injection of phosphorus or arsenic.

[0105] Step S3, preparing at least one trench true gate structure, each trench true gate structure penetrates the carrier storage layer, the body region and the emitter region along a first direction and extends into the drift layer, and along the first direction from the carrier storage layer to the drift layer, the width of the trench true gate structure along a second direction becomes larger and larger, and the second direction is parallel to the drift layer and perpendicular to the first direction.

[0106] The at least one trench true gate structure 5 can be prepared by a deposition process and an etching process.

[0107] Specifically, since the short current channel can easily cause a short circuit in the semiconductor device 100, in order to solve this problem, the semiconductor device 100 in the present application is provided with a trench true gate structure 5, that is, when preparing at least one trench true gate structure 5, each trench true gate structure 5 penetrates the carrier storage layer 2, the body region 3 and the emitter region 4 along the first direction and extends into the drift layer 1, and the width of the trench true gate structure 5 along the second direction becomes larger and larger, that is, the trench true gate structure 5 presents a shape that is narrow at the top and wide at the bottom, so that part of the current channel is increased, thereby improving the short circuit resistance of the semiconductor device 100.

[0108] According to the method for preparing the semiconductor device 100 of an embodiment of the present invention, at least one trench true gate structure 5 is prepared by penetrating the carrier storage layer 2, the body region 3 and the emitter region 4 and extending into the drift layer 1, and the width of the trench true gate structure 5 along the second direction becomes larger and larger, so that part of the current channel is increased, thereby improving the short-circuit resistance of the semiconductor device 100.

[0109] In some embodiments, at least one trench true gate structure 5 is prepared, including: preparing a first trench along a first direction penetrating the carrier storage layer 2, the body region 3 and the emitter region 4 and extending into the drift layer 1, for example, preparing a first trench along a first direction penetrating the carrier storage layer 2, the body region 3 and the emitter region 4 and extending into the drift layer 1 by an etching process, preparing a first gate oxide layer 51 in the first trench, the first gate oxide layer 51 being constructed as a first oxide layer trench, from the carrier storage layer 2 to the drift layer 1 along the first direction, and the first oxide layer trench being stepped on at least one side in the second direction; filling a first polysilicon layer 52 of a first conductivity type and a second polysilicon layer 54 of a second conductivity type in the first oxide layer trench, wherein the first polysilicon layer 52 is located on the second polysilicon layer 54 in the first direction, the width of the second polysilicon layer 54 along the second direction is greater than the width of the first polysilicon layer 52 along the second direction, and the first polysilicon layer 52 and the second polysilicon layer 54 in the second direction are matched with the stepped shape on at least one side. For example, a polysilicon material can be deposited in the first oxide layer trench through a deposition process to form a first polysilicon layer 52 of a first conductivity type and a second polysilicon layer 54 of a second conductivity type, and the first polysilicon layer 52 is located on the second polysilicon layer 54 in the first direction, the width of the second polysilicon layer 54 along the second direction is greater than the width of the first polysilicon layer 52 along the second direction, and the first polysilicon layer 52 and the second polysilicon layer 54 are matched with a step shape on at least one side in the second direction.

[0110] That is, the first polysilicon layer 52 and the second polysilicon layer 54 form a PN junction, and the PN junction capacitance is in series with the original gate-drain capacitance, so that the total capacitance is reduced, thereby reducing the total gate-drain capacitance, so as to improve the switching characteristics of the semiconductor device 100. In addition, in the trench true gate structure 5, since at least one side of the first polysilicon layer 52 and the second polysilicon layer 54 in the second direction matches the step shape, the electric field peak of the emitter can be further weakened, thereby improving the withstand voltage capability of the semiconductor device 100.

[0111] In some embodiments, along the first direction from the carrier storage layer 2 to the drift layer 1, at least one side of the first oxide layer trench in the second direction is multi-stepped; filling the first polysilicon layer 52 of the first conductivity type and the second polysilicon layer 54 of the second conductivity type in the first oxide layer trench includes: filling the first polysilicon layer 52 in the first oxide layer trench corresponding to at least one step in the multi-stepped stairs, and filling the second polysilicon layer 54 in the first oxide layer trench corresponding to at least one step in the multi-stepped stairs. Each step in the multi-stepped stairs is not doped with the same type of doping.

[0112] Specifically, when filling the first polysilicon layer 52 and the second polysilicon layer 54 in the first oxide layer trench, the first polysilicon layer 52 is filled in at least one of the multi-level steps in the first oxide layer trench, and the second polysilicon layer 54 is filled in at least one of the multi-level steps other than the first polysilicon layer 52, that is, at least one layer of the first polysilicon layer 52 and at least one layer of the second polysilicon layer 54 are stacked in the multi-level steps, thereby making the first polysilicon layer 52 and the second polysilicon layer 54 present a stepped shape, which can further weaken the electric field peak of the emitter, thereby improving the voltage resistance of the semiconductor device 100.

[0113] In some embodiments, the first polysilicon layer 52 is in contact with the second polysilicon layer 54 , and both the first polysilicon layer 52 and the second polysilicon layer 54 are connected to a gate potential.

[0114] In some embodiments, the first gate oxide layer 51 is also filled between the first polysilicon layer 52 and the second polysilicon layer 54 , the first polysilicon layer 52 is connected to the gate potential, and the second polysilicon layer 54 is connected to the emitter potential.

[0115] In some embodiments, Figure 5As shown, the second polysilicon layer 54 includes a plurality of sub-polysilicon layers 53, and a first polysilicon layer 52 of a first conductivity type and a second polysilicon layer 54 of a second conductivity type are filled in the first oxide layer trench, including: preparing a plurality of sub-polysilicon layers 53 in the first oxide layer trench near the bottom of the first oxide layer trench, the plurality of sub-polysilicon layers 53 are arranged along a first direction, and the widths of the plurality of sub-polysilicon layers 53 along a second direction are increasing from close to the first polysilicon layer 52 to far away from the first polysilicon layer 52 in the first direction; preparing a first polysilicon layer 52 in the first oxide layer trench, the first polysilicon layer 52 is located above the plurality of sub-polysilicon layers 53 in the first direction; wherein the first gate oxide layer 51 also surrounds each sub-polysilicon layer 53, the first polysilicon layer 52 is connected to the gate potential, and each sub-polysilicon layer 53 is connected to the emitter potential. The plurality of sub-polysilicon layers 53 can be prepared by a deposition process.

[0116] Thus, the plurality of sub-polysilicon layers 53 are arranged in a stepped shape, which can further weaken the electric field peak of the emitter, thereby improving the withstand voltage capability of the semiconductor device 100 .

[0117] In some embodiments, the preparation method also includes: preparing at least one trench dummy gate structure 6, at least one trench dummy gate structure 6 and at least one trench true gate structure 5 are arranged at intervals along the second direction, each trench dummy gate structure 6 penetrates the carrier storage layer 2, the body region 3 and the emitter region 4 along the first direction and extends into the drift layer 1; preparing a dielectric layer 7 on the emitter region 4 along the first direction; preparing an emitter metal layer 8 on the dielectric layer 7 along the first direction, and the emitter metal layer 8 is connected to the body region 3 and the third polysilicon layer 62 through a contact hole.

[0118] Specifically, due to the high channel density of the semiconductor device 100, the channel resistance will be reduced and the proportion of electronic current will be increased, thereby reducing the on-state voltage drop. However, the attendant disadvantage is that the short-circuit current will be increased. The short-circuit current is so large that the semiconductor device 100 will be damaged in a very short time when a short circuit occurs. In order to solve this problem, in the present application, at least one trench dummy gate structure 6 is introduced into the semiconductor device 100 to reduce the proportion of electronic current, thereby reducing the short-circuit current and improving the short-circuit capability.

[0119] In some embodiments, the preparation method also includes: preparing a drift layer 1 on a substrate layer of a first conductivity type, for example, an epitaxial process can be used to epitaxially grow SiC material on the substrate layer to form the drift layer 1; preparing a collector region 10 of a first conductivity type on a side of the substrate layer away from the drift layer 1, for example, forming the collector region by ion implantation; preparing a collector metal layer 11 on a side of the collector region 10 away from the substrate layer, for example, depositing the collector metal layer 11 on a side of the collector region 10 away from the substrate layer.

[0120] Therefore, the semiconductor device 100 is prepared by the method for preparing the semiconductor device 100 in the present application. A third aspect of the present invention provides an electronic device, such as Figure 7 As shown, the electronic device 200 includes the semiconductor device 100 of the above embodiment.

[0121] According to the electronic device of the embodiment of the present invention, the short circuit resistance capability of the semiconductor device can be effectively improved by using the semiconductor device 100 of the above embodiment.

[0122] A fourth aspect of the present invention provides a vehicle, such as Figure 8 As shown, the vehicle 1000 includes the electronic device 200 of the above embodiment, or, as Fig. 9 As shown, a vehicle 1000 includes the semiconductor device 100 of the above-described embodiment.

[0123] According to the vehicle of the embodiment of the present invention, the short-circuit resistance of the semiconductor device can be effectively improved through the electronic device or the semiconductor device 100 of the above embodiment.

[0124] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0125] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A semiconductor device, characterized in that: include: a drift layer of a first conductivity type; a carrier storage layer of a first conductivity type, the carrier storage layer being located on the drift layer in a first direction perpendicular to the drift layer; a body region of a second conductivity type, the body region being located on the carrier storage layer along the first direction; An emitter region of a first conductivity type, the emitter region being located on the body region along the first direction; At least one trench true gate structure, each of the trench true gate structures penetrates the carrier storage layer, the body region and the emitter region along the first direction and extends into the drift layer, and along the first direction from the carrier storage layer to the drift layer, the width of the trench true gate structure along the second direction becomes larger and larger, and the second direction is parallel to the drift layer and perpendicular to the first direction.

2. The semiconductor device according to claim 1, wherein: Along the first direction from the carrier storage layer to the drift layer, at least one side of the trench true gate structure in the second direction is in a step shape.

3. The semiconductor device according to claim 2, characterized in that The trench true gate structure comprises: A first gate oxide layer, wherein the first gate oxide layer is structured as a first oxide layer groove, wherein the first oxide layer groove penetrates the carrier storage layer, the body region and the emitter region along the first direction and extends into the drift layer, and along the first direction from the carrier storage layer to the drift layer, the first oxide layer groove is stepped on at least one side in the second direction.

4. The semiconductor device according to claim 3, characterized in that The trench true gate structure further comprises: A first polysilicon layer of a first conductivity type and a second polysilicon layer of a second conductivity type, the first polysilicon layer and the second polysilicon layer are filled in the first oxide layer trench, the first polysilicon layer is located on the second polysilicon layer in the first direction, the width of the second polysilicon layer along the second direction is greater than the width of the first polysilicon layer along the second direction, and at least one side of the first polysilicon layer and the second polysilicon layer in the second direction matches the stepped shape.

5. The semiconductor device according to claim 4, characterized in that Along the first direction from the carrier storage layer to the drift layer, at least one side of the first oxide layer trench in the second direction is multi-step; The first polysilicon layer fills at least one of the multiple steps, and the second polysilicon layer fills at least one of the multiple steps.

6. The semiconductor device according to claim 5, characterized in that The first polysilicon layer contacts the second polysilicon layer.

7. The semiconductor device according to claim 6, characterized in that The first polysilicon layer and the second polysilicon layer are both connected to a gate potential.

8. The semiconductor device according to claim 5, characterized in that The first gate oxide layer is also filled between the first polysilicon layer and the second polysilicon layer.

9. The semiconductor device according to claim 8, characterized in that The first polysilicon layer is connected to a gate potential, and the second polysilicon layer is connected to an emitter potential.

10. The semiconductor device according to claim 8, characterized in that The second polysilicon layer comprises: A plurality of sub-polysilicon layers are arranged along the first direction, and the widths of the plurality of sub-polysilicon layers along the second direction are increasing from close to the first polysilicon layer to far away from the first polysilicon layer in the first direction.

11. The semiconductor device according to claim 10, characterized in that The second polysilicon layer fills multiple steps of the multiple steps of the first oxide layer trench; The plurality of sub-polysilicon layers fill different step positions corresponding to the first oxide layer trenches.

12. The semiconductor device according to claim 11, characterized in that The first gate oxide layer also surrounds each of the sub-polysilicon layers.

13. The semiconductor device according to claim 12, characterized in that The first polysilicon layer is connected to a gate potential, and each sub-polysilicon layer is connected to an emitter potential.

14. The semiconductor device according to any one of claims 5 to 13, characterized in that: The first oxide layer trench constructed by the first gate oxide layer has three steps on at least one side in the second direction, and the three steps from the carrier storage layer to the drift layer along the first direction include a first step, a second step and a third step.

15. The semiconductor device according to claim 14, characterized in that The first polysilicon layer fills the first oxide layer trench corresponding to the first step; The second polysilicon layer fills the first oxide layer trenches corresponding to the second step and the third step, and the second polysilicon layer matches the second step and the third step in a stepped shape.

16. The semiconductor device according to claim 15, characterized in that A lower surface of the first polysilicon layer is flush with a lower surface of the body region.

17. The semiconductor device according to any one of claims 1 to 13, characterized in that: The semiconductor device further comprises: At least one trench false gate structure, the at least one trench false gate structure and the at least one trench true gate structure are arranged at intervals along the second direction, and each of the trench false gate structures penetrates the carrier storage layer, the body region and the emitter region along the first direction and extends into the drift layer.

18. The semiconductor device according to claim 17, characterized in that The trench false gate structure comprises: a second gate oxide layer, wherein the second gate oxide layer is configured as a second oxide layer trench, and the second oxide layer trench penetrates the carrier storage layer, the body region, and the emitter region along the first direction and extends into the drift layer; A third polysilicon layer of the first conductivity type is filled in the second oxide layer trench.

19. The semiconductor device according to claim 18, characterized in that The semiconductor device further comprises: a dielectric layer, the dielectric layer being located on the emitting region along the first direction; An emitter metal layer, wherein the emitter metal layer is located on the dielectric layer along the first direction, and the emitter metal layer is connected to the body region and the third polysilicon layer through a contact hole.

20. The semiconductor device according to claim 17, wherein: The semiconductor device includes a plurality of trench true gate structures. In the second direction, the at least one trench dummy gate structure is located between the plurality of trench true gate structures.

21. The semiconductor device according to claim 20, characterized in that The semiconductor device includes two trench true gate structures and two trench dummy gate structures. In the second direction, the two trench dummy gate structures and the two trench dummy gate structures are arranged at intervals, and the two trench dummy gate structures are located between the two trench true gate structures.

22. The semiconductor device according to claim 21, characterized in that The trench true gate structure is in a step shape on a side facing the trench false gate structure in the second direction.

23. The semiconductor device according to claim 21, characterized in that The body region between the two trench false gate structures is arranged in a floating manner.

24. The semiconductor device according to any one of claims 1 to 13, characterized in that: The semiconductor device further comprises: a substrate layer of a first conductivity type, the substrate layer being located on a side of the drift layer away from the carrier storage layer; A collector region of a first conductivity type, the collector region being located on a side of the substrate layer away from the drift layer; A collector metal layer is located on a side of the collector region away from the substrate layer.

25. A method for preparing a semiconductor device, characterized in that: include: providing a drift layer of a first conductivity type; Preparing a carrier storage layer of a first conductivity type, a body region of a second conductivity type, and an emitter region of a first conductivity type in sequence on the drift layer along a first direction, wherein the first direction is a direction perpendicular to the drift layer; At least one trench true gate structure is prepared, each of the trench true gate structures penetrates the carrier storage layer, the body region and the emitter region along the first direction and extends into the drift layer, and along the first direction from the carrier storage layer to the drift layer, the width of the trench true gate structure along the second direction becomes larger and larger, and the second direction is parallel to the drift layer and perpendicular to the first direction.

26. The preparation method according to claim 25, characterized in that: Preparing at least one trench true gate structure, comprising: A first trench is formed along the first direction, penetrating the carrier storage layer, the body region and the emitter region and extending into the drift layer, and a first gate oxide layer is formed in the first trench, wherein the first gate oxide layer is structured as a first oxide layer trench, and at least one side of the first oxide layer trench in the second direction is stepped from the carrier storage layer to the drift layer along the first direction; A first polysilicon layer of a first conductivity type and a second polysilicon layer of a second conductivity type are filled in the first oxide layer trench, wherein the first polysilicon layer is located on the second polysilicon layer in the first direction, the width of the second polysilicon layer along the second direction is greater than the width of the first polysilicon layer along the second direction, and at least one side of the first polysilicon layer and the second polysilicon layer in the second direction matches the stepped shape.

27. The preparation method according to claim 26, characterized in that: Along the first direction from the carrier storage layer to the drift layer, at least one side of the first oxide layer trench in the second direction is multi-step; Filling a first polysilicon layer of a first conductivity type and a second polysilicon layer of a second conductivity type in the first oxide layer trench, comprising: The first polysilicon layer is filled in the first oxide layer trench corresponding to at least one step in the multi-step steps, and the second polysilicon layer is filled in the first oxide layer trench corresponding to at least one step in the multi-step steps.

28. The preparation method according to claim 27, characterized in that: The first polysilicon layer is in contact with the second polysilicon layer, and both the first polysilicon layer and the second polysilicon layer are connected to a gate potential.

29. The preparation method according to claim 27, characterized in that: The first gate oxide layer is also filled between the first polysilicon layer and the second polysilicon layer, the first polysilicon layer is connected to a gate potential, and the second polysilicon layer is connected to an emitter potential.

30. The preparation method according to claim 27, characterized in that: The second polysilicon layer includes a plurality of sub-polysilicon layers, and a first polysilicon layer of a first conductivity type and a second polysilicon layer of a second conductivity type are filled in the first oxide layer trench, including: Preparing a plurality of sub-polysilicon layers in the first oxide layer trench near the bottom of the first oxide layer trench, the plurality of sub-polysilicon layers being arranged along the first direction, and the widths of the plurality of sub-polysilicon layers along the second direction becoming larger from close to the first polysilicon layer to far away from the first polysilicon layer in the first direction; Preparing the first polysilicon layer in the first oxide layer trench, wherein the first polysilicon layer is located above the plurality of sub-polysilicon layers in the first direction; The first gate oxide layer also surrounds each of the sub-polysilicon layers, the first polysilicon layer is connected to the gate potential, and each sub-polysilicon layer is connected to the emitter potential.

31. The preparation method according to any one of claims 25 to 30, characterized in that: The preparation method further comprises: Prepare at least one trench dummy gate structure, wherein the at least one trench dummy gate structure and the at least one trench true gate structure are arranged at intervals along the second direction, and each of the trench dummy gate structures penetrates the carrier storage layer, the body region and the emitter region along the first direction and extends into the drift layer; Preparing a dielectric layer on the emitting region along the first direction; An emitter metal layer is prepared on the dielectric layer along the first direction, and the emitter metal layer is connected to the body region and the third polysilicon layer through a contact hole.

32. The preparation method according to claim 31, characterized in that: The preparation method further comprises: preparing the drift layer on a substrate layer of a first conductivity type; Preparing a collector region of a first conductivity type on a side of the substrate layer away from the drift layer; A collector metal layer is prepared on a side of the collector region away from the substrate layer.

33. An electronic device, characterized in that: A semiconductor device comprising any one of claims 1 to 24.

34. A vehicle, characterized in that: The vehicle includes the electronic device described in claim 33, or the vehicle includes the semiconductor device described in any one of claims 1-24.

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