Semiconductor device and forming method thereof

Abstract

The embodiment of the invention provides a semiconductor device and a forming method thereof. A method according to one embodiment of the present disclosure includes forming a stack of channel layers interleaved with sacrificial layers over a substrate; patterning the stack to form a fin-shaped structure; forming a dummy gate stack over the fin-shaped structure; recessing the fin-shaped structure to form a source / drain trench; recessing the sacrificial layer portion to form an internal spacer recess; forming an inner spacer in the inner spacer groove; selectively depositing a segregation prevention layer on a surface of the internal spacer; and forming an epitaxial feature in the source / drain trench. A surface of the internal spacer includes a first surface exposed in the source / drain trench and a second surface facing an adjacent one of the channel layers. A portion of the segregation prevention layer is stacked between the internal spacer and the epitaxial feature.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each with smaller and more complex circuits than the previous generation. In the course of IC development, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs. Such shrinking has also increased the complexity of processing and manufacturing ICs.

[0003] For example, as IC technology moves toward smaller nodes, multi-gate metal oxide semiconductor field effect transistors (multi-gate MOSFETs or multi-gate devices) have been introduced to improve gate control by increasing gate-channel coupling; reducing off-state current; and reducing short channel effect (SCE). A multi-gate device generally refers to a device having a gate structure or portion thereof disposed above more than one side of a channel region. Fin field effect transistors (FinFETs) and multi-bridge channel (MBC) transistors are examples of multi-gate devices, which have become popular and promising candidate devices for high performance and low leakage applications. FinFETs have an elevated channel wrapped by a gate on more than one side (e.g., a gate wraps around the top and sidewalls of a semiconductor material "fin" extending from a substrate). MBC transistors have a gate structure that can extend partially or completely around a channel region to provide access to a channel region on two or more sides. Because its gate structure surrounds the channel region, MBC transistors can also be referred to as gate-around transistors (SGTs) or gate-all-around (GAA) transistors.

[0004] To improve the performance of multi-gate transistors, including FinFET transistors or MBC transistors, efforts have been made to develop strained channels and appropriate source / drain structures that provide reduced resistance. Although conventional source / drain structures are generally adequate for their intended purposes, they are not satisfactory in all respects. Summary of the invention

[0005] Some embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a stack above a substrate, the stack comprising a plurality of channel layers interlaced with a plurality of sacrificial layers; patterning the stack and a top portion of the substrate to form a fin-shaped structure, the fin-shaped structure comprising a channel region and a source / drain region; forming a dummy gate stack above the channel region of the fin-shaped structure; depositing gate spacers on sidewalls of the dummy gate stack; recessing the source / drain region to form source / drain trenches exposing sidewalls of the channel layer and the sacrificial layer; recessing the sacrificial layer portion to form a plurality of internal spacer grooves; and depositing a plurality of internal spacer grooves on the internal A plurality of internal spacers are formed in the spacer groove, wherein each of the internal spacers includes a first surface exposed in the source / drain trench and a second surface facing an adjacent one of the channel layers; a segregation prevention layer is selectively deposited on the first surface and the second surface of the internal spacer; an epitaxial component is formed in the source / drain trench, wherein a portion of the segregation prevention layer is stacked between the internal spacer and the epitaxial component; after forming the epitaxial component, the pseudo gate stack is removed; the channel layer in the channel region is released as a plurality of channel components; and a gate structure is formed that wraps each of the channel components.

[0006] Other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a plurality of channel components disposed above a fin-shaped substrate; forming a plurality of internal spacers interlaced with the channel components, wherein the internal spacers include a nitride; depositing an arsenic-containing layer on the sidewalls of the internal spacers; forming an epitaxial component adjacent to the channel component, wherein the arsenic-containing layer is stacked between the epitaxial component and the internal spacers; and forming a gate structure encapsulating each of the channel components.

[0007] Still other embodiments of the present application provide a semiconductor device, comprising: a fin-shaped base protruding from a substrate; a plurality of channel components disposed above a top surface of the fin-shaped base; a plurality of internal spacers interlaced with the channel components; a gate structure wrapping each of the channel components; a gate spacer disposed on a side wall of the gate structure; a source / drain component adjacent to the channel component; and an arsenic-containing film between the source / drain component and the internal spacers. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The disclosed embodiments are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustration purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0009] Figure 1A flow chart of a method for forming a semiconductor device according to one or more aspects of an embodiment of the present disclosure is shown.

[0010] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 , Fig.18 , Fig.19 , Fig. 20 , Fig.21 and Fig. 22 The workpiece according to one or more aspects of the embodiments of the present disclosure is shown in Figure 1 A partial cross-sectional view during the manufacturing process of the method.

[0011] Fig.23A , Fig. 23B , Fig.23C and Fig.23D A partial cross-sectional view of an alternative embodiment of a workpiece is shown in accordance with one or more aspects of an embodiment of the present disclosure. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0013] For ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0014] In addition, when "about," "approximately," or the like is used to describe a numerical value or a range of numerical values, as understood by one of ordinary skill in the art, the term is intended to encompass numerical values ​​within a reasonable range that takes into account variations that inherently occur during manufacturing. For example, based on known manufacturing tolerances associated with manufacturing components having properties associated with the numerical values, the numerical value or range of numerical values ​​encompasses a reasonable range that includes the described numerical value, such as within + / - 10% of the described numerical value. For example, a material layer having a thickness of "about 5 nm" may include a size range from 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with the deposited material layer known to one of ordinary skill in the art is + / - 15%. Further, the disclosed embodiments may repeat reference numerals and / or characters in various instances. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0015] The disclosed embodiments generally relate to multi-gate transistors and manufacturing methods, and more particularly to structures that prevent phosphorus segregation in the source / drain regions of multi-gate transistors. The term "phosphorus segregation" refers to the phenomenon that phosphorus atoms aggregate or segregate in certain regions and become unable to provide electrons as carriers. The segregated phosphorus atoms are no longer considered active phosphorus atoms, but inactive (or aggregated, or segregated) phosphorus atoms because these atoms have lost the ability to contribute electrons as carriers. When phosphorus atoms as dopants in epitaxial components diffuse outward from the doped source / drain regions to the channel region of the transistor, the phosphorus atoms may begin to contact adjacent nitride-containing dielectric components, such as the surface of nitride-containing internal spacers and / or gate spacers, causing phosphorus aggregation and producing "phosphorus segregation". Phosphorus segregation causes a reduced active phosphorus concentration and, therefore, reduces the drive current in the transistor.

[0016] The following disclosure will continue with one or more MBC transistor examples to illustrate various embodiments of the present disclosure. However, it should be understood that the present application should not be limited to a specific type of device unless otherwise stated. For example, aspects of the embodiments of the present disclosure may also be applicable to implementations based on FinFET transistors. The channel region of the MBC transistor may be arranged in a nanowire channel member, a strip channel member, a nanosheet channel member, a nanostructure channel member, a columnar channel member, a rod-shaped channel member, and / or other suitable channel configurations. Depending on the shape of the channel member, the MBC transistor may also be referred to as a nanowire transistor or a nanosheet transistor. Regardless of the shape, the channel member of the MBC transistor may also be referred to as a nanostructure. Each of the channel members extends between two epitaxial components in two opposing source / drain regions and is coupled to two epitaxial components in two opposing source / drain regions. Epitaxial components are also referred to as source / drain components or source / drain epitaxial components. The source / drain region may refer to a source or a drain, individually or collectively depending on the context.

[0017] The source / drain components of the MBC transistor introduce strain on the channel component and provide low resistance. The dopant in the source / drain component can diffuse into the end portion of the channel component to form a lightly doped region, also referred to as a source / drain extension (SDE) region or an LDD region. For n-type transistors, the source / drain component can be doped with dopants such as phosphorus (P) or arsenic (As). Typically, the source / drain component contacts the gate spacer and the internal spacer of the MBC transistor. Phosphorus atoms diffused into the SDE region may begin to contact the surface of the gate spacer and the internal spacer, and are captured by the dangling bonds extending from these surfaces, particularly when the gate spacer and the internal spacer include nitrides, causing phosphorus segregation. Phosphorus segregation produces an uneven junction profile between the source / drain region and the channel region, and increases the source / drain resistance, which may deteriorate the performance of the n-type transistor.

[0018] The disclosed embodiments provide embodiments of semiconductor devices, wherein a segregation prevention layer is formed on the surface of an internal spacer and / or a gate spacer to prevent phosphorus segregation. That is, the segregation prevention layer controls the extent to which phosphorus atoms are captured by dangling bonds extending from the nitride-containing dielectric surface of the internal spacer and / or the gate spacer. In some embodiments, the segregation prevention layer is an arsenic-containing layer, such as a film made primarily of arsenic atoms in a two-dimensional (2-D) lattice of a stack of monoatomic layers or polyatomic layers, or a layer composed of arsenic-containing compounds including silicon, nitrogen, and arsenic. The segregation prevention layer results in a more uniform junction profile between the source / drain region and the channel region, and reduces the source / drain resistance by providing more active phosphorus atoms in the SDE region.

[0019] Various aspects of the disclosed embodiments will now be described in more detail with reference to the accompanying drawings. Figure 1 1 is a flow chart illustrating a method 100 of forming a semiconductor device from a workpiece according to an embodiment of the present disclosure. The method 100 is merely an example and is not intended to limit the disclosed embodiments to what is explicitly shown in the method 100. Additional steps may be provided before, during, and after the method 100, and some of the steps described may be replaced, eliminated, or moved around for additional embodiments of the method. For the sake of simplicity, not all steps are described in detail herein. Figures 2 to 22 Describing method 100, Figures 2 to 22 is based on Figure 1 1 and 1 . The workpiece 200 of the embodiment of the method 100 in FIG. 1 is a partial cross-sectional view of a workpiece 200 at different manufacturing stages. Because the workpiece 200 will be manufactured into a semiconductor device, the workpiece 200 may be referred to herein as a semiconductor device (or device) 200 as the context requires. For avoidance of doubt, Figures 2 to 22 The X, Y and Z directions are perpendicular to each other. Throughout the embodiments of the present disclosure, the same reference numerals represent the same components unless otherwise specified.

[0020] refer to Figure 1 and Figure 2 , the method 100 includes a block 102, in which a stack 204 of alternating semiconductor layers is formed above a workpiece 200. Figure 2 As shown in , workpiece 200 includes substrate 202. In some embodiments, substrate 202 may be a semiconductor substrate, such as a silicon (Si) substrate. Substrate 202 may include various doping configurations, depending on design requirements as known in the art. In embodiments where the semiconductor device is p-type, an n-type doping profile (i.e., an n-type well or n-well) may be formed on substrate 202. In some embodiments, an n-type dopant for forming an n-type well may include phosphorus (P) or arsenic (As). In embodiments where the semiconductor device is n-type, a p-type doping profile (i.e., a p-type well or p-well) may be formed on substrate 202. In some embodiments, an n-type dopant for forming a p-type well may include boron (B) or gallium (Ga). Suitable doping may include ion implantation and / or diffusion processes of dopants. Substrate 202 may also include other semiconductors, such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, substrate 202 may include a compound semiconductor and / or an alloy semiconductor. Additionally, the substrate 202 may optionally include an epitaxial layer (epi layer), may be strained for performance enhancement, may include a silicon-on-insulator (SOI) or germanium-on-insulator (GeOI) structure, and / or may have other suitable enhancement features.

[0021] In some embodiments, the stack 204 includes sacrificial layers 206 of a first semiconductor composition interleaved with channel layers 208 of a second semiconductor composition. The first semiconductor composition and the second semiconductor composition may be different. In some embodiments, the sacrificial layers 206 include silicon germanium (SiGe) and the channel layers 208 include silicon (Si). It should be noted that the three (3) layers of the sacrificial layers 206 and the three (3) layers of the channel layers 208 are arranged alternately, as shown in FIG. Figure 2 , which is for illustrative purposes only and is not intended to be limiting beyond what is specifically recited in the claims. It is understood that any number of epitaxial layers may be formed in the stack 204. The number of layers depends on the desired number of channel components for the semiconductor device 200. In some embodiments, the number of channel layers 208 is between 1 and 20.

[0022] In some embodiments, all sacrificial layers 206 may have a substantially uniform first thickness between about 3 nm and about 10 nm, and all channel layers 208 may have a substantially uniform second thickness between about 3 nm and about 15 nm. The first thickness and the second thickness may be the same or different. As described in more detail below, the channel layer 208 or a portion thereof may be used as a channel member for a subsequently formed multi-gate device, and the thickness of each of the channel layers 208 is selected based on device performance considerations. The sacrificial layer 206 in the channel region may be eventually removed and used to define the vertical distance between adjacent channel regions for a subsequently formed multi-gate device, and the thickness of each of the sacrificial layers 206 is selected based on device performance considerations.

[0023] The layers in stack 204 may be deposited using a molecular beam epitaxy (MBE) process, a vapor phase epitaxy (VPE) process, and / or other suitable epitaxial growth processes. Therefore, stack 204 is also referred to as epitaxial stack 204. As described above, in at least some examples, sacrificial layer 206 includes an epitaxially grown silicon germanium (SiGe) layer, and channel layer 208 includes an epitaxially grown silicon (Si) layer. In some embodiments, sacrificial layer 206 and channel layer 208 are substantially free of dopants (i.e., have a dopant content of from about 0 cm -3 About 1×10 17 cm -3 extrinsic dopant concentration), where, for example, no intentional doping is performed during the epitaxial growth process for stack 204. In some embodiments, the top surface of substrate 202 lies in the (100) crystal plane, and thus each layer of stack 204 has a (100) top surface. In some alternative embodiments, the top surface of substrate lies in the (110) crystal plane, and thus each layer of stack 204 has a (110) top surface.

[0024] refer to Figure 1 , Figure 2 and Figure 3 , the method 100 includes a block 104, in which a fin structure 212 is formed by patterning the stack 204 and the top portion of the substrate 202. To pattern the stack 204, a hard mask layer 210 ( Figure 2 ) to form an etching mask. The hard mask layer 210 may be a single layer or multiple layers. For example, the hard mask layer 210 may include a pad oxide layer and a pad nitride layer above the pad oxide layer. The fin structure 212 may be patterned from the top portion of the stack 204 and the substrate 202 using a photolithography process and an etching process. The photolithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching, and / or other etching methods. The etching process in frame 104 forms a groove extending through a portion of the stack 204 and the substrate 202. The groove defines the fin structure 212. In some embodiments, a double patterning or multiple patterning process may be used to define a fin structure having, for example, a pitch that is smaller than that obtainable using a single, direct photolithography process. For example, in one embodiment, a material layer is formed above a substrate and patterned using a photolithography process. Spacers are formed next to the patterned material layer using a self-aligned process. The material layer is then removed, and then the remaining spacers or mandrels can be used to pattern the fin structure 212 by etching the top portion of the stack 204 and the substrate 202. The patterned top portion of the substrate 202 is also represented as the fin base 212B. The horizontal plane including the interface between the stack 204 and the fin base 212B is represented as plane 202T, which marks the location of the bottom surface of the stack 204 and / or the top surface of the fin base 212B. As the context requires, the fin base 212B can still be considered as the top portion of the substrate 202. Therefore, plane 202T can also be considered to mark the location of the top surface of the substrate 202. Figure 3 As shown in FIG. 1 , the fin structure 212 (which includes the patterned stack 204 and the fin base 212B) extends vertically along the Z direction and longitudinally along the X direction. In some examples, the width of the fin structure 212 along the Y direction is measured between about 6 nm and about 80 nm, and the distance between the opposite sidewalls of two adjacent fin structures 212 along the Y direction is measured between about 6 nm and about 115 nm.

[0025] An isolation feature 214 is formed adjacent to the fin structure 212. In some embodiments, the isolation feature 214 may be formed in a trench to isolate the fin structure 212 from an adjacent active area. The isolation feature 214 may also be referred to as a shallow trench isolation (STI) feature 214. For example, in some embodiments, a dielectric layer is first deposited over the substrate 202 to fill the trench with the dielectric layer. In some embodiments, the dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics, combinations thereof, and / or other suitable materials. In various examples, the dielectric layer may be deposited by a CVD process, a sub-atmospheric pressure CVD (SACVD) process, a flowable CVD process, a spin coating process, and / or other suitable processes. Then, the deposited dielectric material is thinned and planarized, for example, by a chemical mechanical polishing (CMP) process. The planarized dielectric layer is further recessed or pulled back by a dry etching process, a wet etching process, and / or a combination thereof to form the STI feature 214. After being recessed, the fin structure 212 rises above the STI feature 214. The recessed top surface of the STI feature 214 may be flush with the plane 202T or below the plane 202T.

[0026] refer to Figure 1 , Figure 4 and Figure 5 The method 100 includes block 106 in which a dummy gate stack 220 is formed over the channel region 212C of the fin structure 212 . Figure 5 It passes through Figure 4 In some embodiments, a gate replacement process (or a gate-last process) is used, wherein the dummy gate stack 220 ( Figure 4 and Figure 5 ) is used as a placeholder to undergo various processes and will be removed and replaced by a functional gate structure. Other processes and configurations are also possible. Figure 5 In some embodiments shown in , the dummy gate stack 220 is formed above the fin structure 212, and the fin structure 212 can be divided into a channel region 212C located below the dummy gate stack 220 and a source / drain region 212SD not located below the dummy gate stack 220. The channel region 212C is adjacent to the source / drain region 212SD. Figure 5 As shown in FIG. 2 , the channel region 212C is disposed between two source / drain regions 212SD along the X direction.

[0027] The formation of the dummy gate stack 220 may include depositing layers in the dummy gate stack 220 and patterning the layers. Figure 4, a dummy dielectric layer 216, a dummy electrode layer 218, and a gate top hard mask layer 222 may be blanket deposited over the workpiece 200. In some embodiments, the dummy dielectric layer 216 may be formed on the fin structure 212 using a chemical vapor deposition (CVD) process, an ALD process, an oxygen plasma oxidation process, or other suitable process. In some instances, the dummy dielectric layer 216 may include silicon oxide. Thereafter, the dummy electrode layer 218 may be deposited over the dummy dielectric layer 216 using a CVD process, an ALD process, or other suitable process. In some instances, the dummy electrode layer 218 may include polysilicon. For patterning purposes, the gate top hard mask layer 222 may be deposited on the dummy electrode layer 218 using a CVD process, an ALD process, or other suitable process. Then, the gate top hard mask layer 222, the dummy electrode layer 218, and the dummy dielectric layer 216 may be patterned to form a dummy gate stack 220, such as Figure 5 As shown in . For example, the patterning process may include a lithography process (e.g., photolithography or electron beam lithography), and the lithography process may further include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching and / or other etching methods. In some embodiments, the gate top hard mask layer 222 may include a silicon oxide layer 223 and a silicon nitride layer 224 above the silicon oxide layer 223. As shown in Figure 5 As shown in FIG. 2 , no dummy gate stack 220 is disposed over the source / drain region 212SD of the fin structure 212 .

[0028] refer to Figure 1 and Figure 6 , the method 100 includes a frame 108, wherein a gate spacer 226 is deposited over the dummy gate stack 220. In some embodiments, the gate spacer 226 is conformally deposited over the workpiece 200, including over the top surface and sidewalls of the dummy gate stack 220. The term "conformal" may be used herein to facilitate describing a layer having a substantially uniform thickness over various regions. The gate spacer 226 may be a single layer or multiple layers. In some embodiments, at least one layer of the gate spacer 226 may include a nitride, such as silicon nitride, silicon oxynitride, silicon carbonitride, or silicon carbon nitride. The gate spacer 226 may be deposited over the dummy gate stack 220 using a process such as a CVD process, a sub-atmospheric pressure CVD (SACVD) process, an ALD process, or other suitable process. In one embodiment, the gate spacer 226 includes a first layer and a second layer disposed over the first layer. The first layer may include silicon oxynitride, and the second layer may include silicon nitride. In some examples, the thickness of the gate spacer 226 along the X direction is measured to be between about 3nm and about 8nm.

[0029] refer to Figure 1 and Figure 7 , the method 100 includes a frame 110, in which the source / drain region 212SD of the fin structure 212 is recessed to form a source / drain trench 228. In some embodiments, the source / drain region 212SD not covered by the dummy gate stack 220 and the gate spacer 226 is etched by dry etching or a suitable etching process to form the source / drain trench 228. For example, the dry etching process can be implemented with an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBR3), an iodine-containing gas, other suitable gases and / or plasmas and / or combinations thereof. Figure 7 In some embodiments shown in , the source / drain region 212SD of the fin structure 212 is recessed to expose the sidewalls of the sacrificial layer 206 and the channel layer 208. In some embodiments, the source / drain trench 228 extends into the substrate 202 (below the plane 202T) under the stack 204. Figure 7 As shown in FIG. 1 , in block 110 , the sacrificial layer 206 and the channel layer 208 in the source / drain region 212SD are removed to expose the substrate 202 .

[0030] refer to Figure 1 , Figure 8 , Fig. 9 and Fig.10 , the method 100 includes a block 112, in which an internal spacer 234 is formed. Although not explicitly shown, the operations in block 112 may include: selectively and partially removing the sacrificial layer 206 to form an internal spacer recess 230; depositing an internal spacer material 232 over the workpiece 200; and etching back the internal spacer material 232 to form the internal spacer 234 in the internal spacer recess 230. Figure 8206 is selectively and partially recessed to form an internal spacer recess 230, while the gate spacer 226, the exposed portion of the substrate 202, and the channel layer 208 are substantially unetched. In an embodiment where the channel layer 208 is primarily composed of silicon (Si) and the sacrificial layer 206 is primarily composed of silicon germanium (SiGe), the selective recessing of the sacrificial layer 206 may be performed using a selective wet etching process or a selective dry etching process. Selectively and partially recessing the sacrificial layer 206 may include a SiGe oxidation process and subsequent SiGe oxide removal. In this embodiment, the SiGe oxidation process may include the use of ozone. In some other embodiments, the selective dry etching process may include the use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. The selective wet etching process may include APM etching (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture).

[0031] After forming the inner spacer recess 230, the inner spacer material 232 is deposited over the workpiece 200, including over the inner spacer recess 230, such as Fig. 9 . Although not explicitly shown, the internal spacer material 232 can be a single layer or multiple layers. In some embodiments, at least one layer of the internal spacer material 232 can include a nitride, such as silicon nitride, silicon oxynitride, silicon carbonitride, or silicon carbon oxynitride. In some embodiments, the gate spacer 226 and the internal spacer material 232 include the same material, such as silicon nitride. In some embodiments, the gate spacer 226 and the internal spacer material 232 include different material compositions, such as silicon oxynitride in the gate spacer 226 and silicon nitride in the internal spacer material 232. In some embodiments, the internal spacer material 232 can be deposited using CVD, PECVD, SACVD, ALD, or other suitable methods. The internal spacer material 232 is deposited into the internal spacer recess 230 and over the sidewalls of the channel layer 208 exposed in the source / drain trench 228. Reference Fig.10 , and then etch back the deposited internal spacer material 232 to remove the internal spacer material 232 from the sidewalls of the channel layer 208 to form an internal spacer 234 in the internal spacer recess 230. In block 112, the internal spacer material 232 may also be removed from the top surface and / or sidewalls of the gate top hard mask layer 222 and the gate spacer 226. In some embodiments, the etch back operation performed in block 112 may include using hydrogen fluoride (HF), fluorine gas (F2), hydrogen gas (H2), ammonia (NH3), nitrogen trifluoride (NF3), or other fluorine-based etchants. Fig.10As shown in , each of the internal spacers 234 contacts the recessed sacrificial layer 206 and is disposed between two adjacent channel layers 208. In some examples, the thickness of each of the internal spacers 234 along the X direction is measured to be between about 3 nm and about 5 nm. In the depicted embodiment, each of the internal spacers 234 has a concave sidewall surface facing the corresponding source / drain trench 228 (i.e., curving inward toward the corresponding sacrificial layer 206). Optionally, the sidewall surface can be flat (e.g., substantially vertical) or convex (i.e., curving outward toward the corresponding source / drain trench 228). As shown in FIG. Fig.10 As shown in , although the selective etching process and etch-back process in box 112 are selective to the sacrificial layer 206 and the internal spacer material 232, the channel layer 208 is moderately etched and has rounded ends. In the depicted embodiment, the source / drain trench 228 extends a depth D1 (measured from the plane 202T) in the substrate 202, and the depth D1 is between about 3nm and about 115nm. In some embodiments, the width of the source / drain trench 228 (e.g., as measured between opposite sidewalls of the gate spacers 226 on adjacent dummy gate stacks 220 along the X direction) is between about 9nm and about 32nm.

[0032] refer to Figure 1 and Fig.11 , method 100 includes frame 114, in which a cleaning process 300 is implemented. The cleaning process 300 may include dry cleaning, wet cleaning, or a combination thereof. In some instances, the wet cleaning may include using standard cleaning 1 (RCA SC-1, a mixture of deionized (DI) water, ammonium hydroxide, and hydrogen peroxide), standard cleaning 2 (RCA SC-2, a mixture of DI water, hydrochloric acid, and hydrogen peroxide), SPM (sulfuric acid peroxide mixture), and / or hydrofluoric acid for oxide removal. The dry cleaning process may include helium (He) and hydrogen (H2) treatment at a temperature between about 250° C. and about 550° C. and at a pressure between about 75 mTorr and about 155 mTorr. The hydrogen treatment may convert silicon on the surface into silane (SiH4), which may be extracted for removal. In some embodiments, the cleaning process is configured to selectively remove or trim portions of the channel layer without substantially removing the internal spacer 234. The cleaning process 300 may remove surface oxides and debris to ensure a clean semiconductor surface, which facilitates growth of the base epitaxial layer in block 116 .

[0033] refer to Figure 1 and Fig.12, the method 100 includes a frame 116, wherein a base epitaxial layer 236 is deposited in the bottom of the source / drain trench 228. In some embodiments, the base epitaxial layer 236 includes the same material as the substrate 202 and the channel layer 208, such as silicon (Si), except for the dopant conditions (doping elements and / or doping concentrations). For example, the base epitaxial layer 236 is made of undoped silicon, the substrate 202 is made of doped silicon, and the channel layer 208 is made of undoped or doped silicon. In some embodiments, the base epitaxial layer 236 includes the same material as the sacrificial layer 206, such as silicon germanium (SiGe), wherein the germanium (Ge) content is the same or different from each other. In various embodiments, the base epitaxial layer 236 has no dopant, for example, no intentional doping is performed during the epitaxial growth process. In comparison, in one example, the substrate 202 is lightly doped with a p-type dopant in an n-type region for forming an n-type transistor, and therefore has a higher doping concentration than the base epitaxial layer 236. The base epitaxial layer 236 without dopants provides a high resistance path from subsequently formed source / drain features to the substrate 202 , thereby suppressing leakage current into the substrate 202 .

[0034] Suitable epitaxial processes for block 116 include vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), selective CVD, and / or other suitable processes. Various deposition parameters may be adjusted to selectively deposit semiconductor material on the exposed semiconductor surface in the source / drain trench 228, such as deposition gas composition, carrier gas composition, deposition gas flow rate, carrier gas flow rate, deposition time, deposition pressure, deposition temperature, source power, RF bias voltage, DC bias voltage, RF bias voltage, DC bias voltage, other suitable deposition parameters, or combinations thereof. In some embodiments, when forming the base epitaxial layer 236, the workpiece 200 is exposed to a deposition mixture including DCS and / or SiH4 (silicon-containing precursor), H2 (carrier precursor), and HCl (etchant-containing precursor). In some embodiments, the selective CVD process implements a deposition temperature of about 600°C to about 750°C. In some embodiments, the selective CVD process implements a deposition pressure of about 10 Torr to about 100 Torr. In some embodiments, the selective CVD process is configured as a bottom-up deposition process so that the base epitaxial layer 236 grows from the exposed semiconductor surface at the bottom of the source / drain trench 228, but does not grow from the exposed end portion of the channel layer 208. The growth of the base epitaxial layer 236 is controlled by time so that the top surface of the base epitaxial layer 236 is located below the top surface of the fin-shaped base 212B (i.e., below the plane 202T). In some embodiments, a post-deposition etch is performed after the selective CVD process to recess the base epitaxial layer 236 below the plane 202T and to remove the semiconductor material (if any) of the base epitaxial layer 236 that may remain on the end portion of the channel layer 208. The post-deposition etch includes dry etching, wet etching, other suitable etching processes, or combinations thereof. In some embodiments, the top surface of the base epitaxial layer 236 is located about 2 nm to about 20 nm below the plane 202T.

[0035] refer to Figure 1 , Fig.13 and Fig.14 , the method 100 includes a block 118, in which a dielectric film 240 is formed in the bottom of the source / drain trench 228 and on the base epitaxial layer 236. Although not explicitly shown, the operations in block 118 may include: depositing a dielectric material 238 over the workpiece 200; and etching back the dielectric material 238 to form the dielectric film 240 in the bottom of the source / drain trench 228. The dielectric material 238 is deposited over the workpiece 200, including over the sidewalls and bottom surface of the source / drain trench 228 and over the sidewalls and top surface of the dummy gate stack 220, as shown. Fig.13. In some embodiments, dielectric material 238 may include a metal oxide or a metal nitride, such as La2O3, Al2O3, ZnO, ZrN, Zr2Al3O9, TiO2, TaO2, ZrO2, HfO2, Y2O3, AlON, TaCN, other suitable materials, or combinations thereof. In some embodiments, dielectric material 238 may include silicon oxide, silicon nitride, silicon carbon nitride oxide, silicon nitride, silicon oxynitride, carbon-rich silicon carbon nitride, or a low-k dielectric material. In one embodiment, dielectric material 238 includes a nitride material, such as silicon nitride. Dielectric material 238 is selected so that it has a different etch selectivity than inner spacer 234, allowing dielectric material 238 to be etched back without causing etching loss to inner spacer 234. In some embodiments, dielectric material 238 may be deposited using a directional deposition process, such as PECVD or other suitable methods. The directional deposition process forms the dielectric material 238 having thicker horizontal portions (eg, on the bottom surfaces of the source / drain trenches 228 and the top surface of the dummy gate stack 220 ) and thinner vertical portions (eg, on the sidewalls of the dummy gate stack 220 and the fin structure 212 ).

[0036] refer to Fig.14 , and then etch back the deposited dielectric material 238 to remove thinner vertical portions from the sidewalls of the dummy gate stack 220 and the fin structure 212. In some embodiments, the etch back operation performed in box 118 may include using hydrogen fluoride (HF), fluorine gas (F2), hydrogen gas (H2), ammonia (NH3), nitrogen trifluoride (NF3), or other fluorine-based etchants. Due to the loading effect, the thicker horizontal portions on the top of the dummy gate stack 220 may also be removed, while the thicker horizontal portions in the bottom of the source / drain trench 228 are thinned downward, but still remain as a dielectric film 240, which covers the base epitaxial layer 236. In some embodiments, the dielectric film 240 has a thickness (measured in the Z direction) of more than about 2nm to about 20nm, so that the top surface of the dielectric film 240 is approximately plane 202T. In the depicted embodiment, the dielectric film 240 is in contact with the bottommost one of the inner spacers 234.

[0037] refer to Figure 1 and Fig.15, the method 100 includes a block 120, wherein a segregation prevention layer 242 is selectively deposited on the nitride-containing dielectric surface. In the depicted embodiment, the segregation prevention layer 242 is an arsenic-containing film. In one example, the segregation prevention layer 242 is mainly made of arsenic atoms in a two-dimensional (2-D) lattice of a single atomic layer or a stack of two, three or more atomic layers. In another example, arsenic atoms can be diffused into the nitride-containing dielectric surface, and the segregation prevention layer 242 is an arsenic-containing compound including silicon, nitrogen, arsenic and / or other suitable elements (e.g., carbon). In some embodiments, the thickness of the segregation prevention layer 242 can be in a range from about 0.13 nm to about 1 nm. The nitride-containing dielectric surfaces to which the segregation prevention layer 242 is deposited include those exposed surfaces of the gate spacers 226, the inner spacers 234, and the dielectric film 240, and also include those unexposed surfaces that are in contact with the channel layer 208, and those unexposed surfaces between the bottommost one of the inner spacers 234 and the dielectric film 240. Selective deposition on the nitride-containing dielectric surfaces is possible because arsenic atoms are easily captured by dangling bonds from nitrogen atoms in the nitride-containing dielectric surfaces. In some embodiments, the selective deposition process is performed at a temperature between about 450° C. and about 800° C., at a pressure between about 5 Torr and about 600 Torr, and with a carrier gas (e.g., an inert gas) and an arsenic-containing process gas (e.g., arsine (AsH 3 )). On the exposed nitride-containing dielectric surface, arsenic atoms will be directly captured by dangling bonds; in addition, some arsenic atoms can diffuse along the interface between the nitride-containing dielectric surface and the semiconductor (e.g., Si) surface of the channel layer 208 and be captured by dangling bonds of those unexposed nitride-containing dielectric surfaces. Therefore, the arsenic-containing segregation prevention layer 242 is formed on the exposed surfaces of the gate spacer 226, the inner spacer 234, and the dielectric film 240, and is also formed on the unexposed surfaces that interface with the channel layer 208, and those unexposed surfaces between the bottommost one of the inner spacers 234 and the dielectric film 240. In addition, the portion of the segregation prevention layer 242 formed on the exposed surface can be thicker than the other portions of the segregation prevention layer 242 formed on the unexposed surface.

[0038] In addition to the arsenic atoms that form the segregation prevention layer 242, there are also some arsenic atoms diffused into the end portion of the channel layer 208, forming a lightly doped region 208D. The lightly doped region 208D is positioned at the terminal of the channel layer 208. In some embodiments, the lightly doped region 208D includes an arsenic (As) content between about 2% and about 10% atomic percentage and a silicon (Si) content between about 98% and about 90% atomic percentage.

[0039] It should be noted that the arsenic-containing segregation preventing layer 242 represents one embodiment of the segregation preventing layer 242. Segregation preventing layers composed of other materials effective in reducing dangling bonds on nitride-containing dielectric surfaces are also contemplated in the disclosed embodiments.

[0040] refer to Figure 1 and Fig.16 , method 100 includes frame 122, wherein a first epitaxial layer 244A is deposited on the rounded end of the channel layer 208. The first epitaxial layer 244A is wrapped above the rounded end and has a curved shape. In these embodiments, the first epitaxial layer 244A is formed to a thickness that completely covers the rounded end. In some instances, the first epitaxial layer 244A has a thickness between about 1nm and about 6nm along the X direction. The first epitaxial layer 244A can be formed by epitaxy and selection from the exposed sidewalls of the channel layer 208, while the sidewalls of the sacrificial layer 206 remain covered by the internal spacer 234. Suitable epitaxial processes for frame 122 include vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE) and / or other suitable processes. The epitaxial growth process in frame 122 can use a gaseous precursor that interacts with the composition of the channel layer 208. According to an embodiment of the present disclosure, at least some of the internal spacers 234 remain exposed at the end of the operation in block 122. That is, at least some of the internal spacers 234 are not completely covered by the first epitaxial layer 244A. The first epitaxial layer 244A is in contact with the segregation prevention layer 242. The segregation prevention layer 242 separates the first epitaxial layer 244A from the internal spacers 234 so that the first epitaxial layer 244A does not contact the internal spacers 234.

[0041] In some instances, the first epitaxial layer 244A includes silicon arsenide (SiAs). In some embodiments, the first epitaxial layer 244A includes an arsenic (As) content between about 10% and about 40% atomic percentage and a silicon (Si) content between about 90% and about 60% atomic percentage. This arsenic (As) content range is not insignificant. When the arsenic content is greater than about 40%, the lattice mismatch between silicon and arsenic may cause too many defects at the interface between the first epitaxial layer 244A and the channel layer 208, which may cause increased resistance or device failure. When the arsenic content is less than about 10%, the channel layer 208 may not be sufficiently strained for improved carrier mobility. The arsenic content in the first epitaxial layer 244A is higher than the arsenic content in the lightly doped region 208D.

[0042] refer to Figure 1 and Fig.17, method 100 includes frame 124, wherein a second epitaxial layer 244B is deposited over the first epitaxial layer 244A, and a third epitaxial layer 244C is deposited over the second epitaxial layer 244B. Epitaxial layers 244A, 244B, and 244C are collectively referred to as epitaxial components 244. Epitaxial components 244 are also referred to as source / drain components or source / drain epitaxial components. Epitaxial components 244 are bonded to a horizontal portion of segregation prevention layer 242 deposited on the top surface of dielectric film 240. Suitable epitaxial processes for frame 124 include vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. The epitaxial growth process in frame 124 can use a gaseous precursor that interacts with the composition of the first epitaxial layer 244A. The second epitaxial layer 244B is allowed to overgrow and merge over the inner spacer 234 and contact the segregation prevention layer 242 on the inner spacer 234; the third epitaxial layer 244C substantially fills the source / drain trench 228. The top surface of the third epitaxial layer 244C can be grown above the top surface of the fin structure 212 (i.e., the top surface of the topmost channel layer 208) and intersect the segregation prevention layer 242 on the sidewall of the gate spacer 226. In some embodiments, the second epitaxial layer 244B and the third epitaxial layer 244C each include silicon (Si) doped with phosphorus (P), but at different concentrations. The third epitaxial layer 244C serves as a low resistance layer and includes a doping concentration greater than the doping concentration in the second epitaxial layer 244B. In some instances, the doping concentration in the third epitaxial layer 244C can be about 1×10 20 Atom / cm 3 and about 3×10 21 Atom / cm 3 The doping concentration in the second epitaxial layer 244B may be between about 0.5×10 20 Atom / cm 3 and about 1×10 20 Atom / cm 3 Some phosphorus atoms will diffuse through the first epitaxial layer 244A and diffuse into the lightly doped region 208D. Therefore, the lightly doped region 208D includes two n-type dopants, arsenic (As) and phosphorus (P).

[0043] refer to Figure 1 and Fig.18, the method 100 includes a block 126, wherein the workpiece 200 is annealed in an annealing process 400. In some embodiments, the annealing process 400 may include a rapid thermal annealing (RTA) process, a laser spike annealing process, a rapid annealing process, or a furnace annealing process. The annealing process 400 may include a peak annealing temperature between about 900° C. and about 1000° C. In these embodiments, the peak annealing temperature may be maintained for a duration measured in seconds or microseconds. Through the annealing process 400, a desired electron contribution of an n-type dopant in a semiconductor body, such as silicon arsenic (SiAs) or silicon (Si), may be obtained. The annealing process 400 may generate vacancies that promote the movement of dopants from interstitial positions to substitutional lattice positions and reduce damage or defects in the lattice of the semiconductor body.

[0044] The annealing process 400 also accelerates more phosphorus atoms to diffuse through the first epitaxial layer 244A and diffuse into the lightly doped region 208D. The lightly doped region 208D further expands laterally toward the center of the channel region. As the doped region 208D is similar to an extension from the source / drain region, the lightly doped region 208D is also referred to as a source / drain extension (SDE) region 208D. In one embodiment, in the SDE region 208D, the concentration of arsenic is less than the concentration of phosphorus. In another embodiment, in the SDE region 208D, the concentration of arsenic is greater than the concentration of phosphorus. The SDE region 208D does not extend beyond the inner spacer 234 in the X direction to avoid direct contact with the sacrificial layer 206. Although the SDE region 208D is stacked between the nitride-containing dielectric surfaces of adjacent inner spacers 234, the segregation prevention layer 242 prevents phosphorus atoms from aggregating or segregating on the nitride-containing dielectric surface. Therefore, the concentration of active phosphorus increases in the SDE region 208D, which improves the drive current capability. The junction profile of the SDE region 208D (at Fig.18 The θ values ​​(represented by the dashed curve in the figure) are also more evenly distributed, which improves the uniformity of device performance.

[0045] refer to Figure 1 and Figures 19 to 22 , the method 100 includes block 128, where further processing is performed. Such further processing may include, for example, depositing a contact etch stop layer (CESL) 248 ( Fig.19 ); an interlayer dielectric (ILD) layer 250 is deposited over the CESL 248 ( Fig.19 ); removing the dummy gate stack 220 ( Fig. 20 ); selectively removing the sacrificial layer 206 in the channel region 212C to release the channel layer 208 as a channel member ( Fig.21 ); and forming a gate structure 256 ( Fig. 22 ). Now refer to Fig.19 , the CESL 248 is formed before forming the ILD layer 250. In some instances, the CESL 248 includes silicon nitride, silicon oxynitride, and / or other materials known in the art. The CESL 248 may be formed by an ALD, a plasma enhanced chemical vapor deposition (PECVD) process, and / or other suitable deposition processes. The ILD layer 250 is then deposited over the CESL 248. In some embodiments, the ILD layer 250 includes materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused quartz glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG), and / or other suitable dielectric materials. The ILD layer 250 may be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after forming the ILD layer 250, the workpiece 200 may be annealed to improve the integrity of the ILD layer 250. Fig.19 As shown in FIG. 2 , the CESL 248 is disposed directly on the top surface of the source / drain features 244 .

[0046] refer to Fig.19 and Fig. 20 After depositing the CESL 248 and the ILD layer 250, the workpiece 200 may be planarized by a planarization process to expose the dummy gate stack 220. For example, the planarization process may include a chemical mechanical planarization (CMP) process. After the CMP process, the distance from the top surface of the dummy gate stack 220 to the top surface of the topmost channel layer 208 may be measured along the Z direction to be between 5 nm and about 50 nm. The exposure of the dummy gate stack 220 allows the dummy gate stack 220 to be removed and the channel layer 208 to be released. Fig. 20 . In some embodiments, removing the dummy gate stack 220 creates a gate trench 252 above the channel region 212C. Removing the dummy gate stack 220 may include one or more etching processes that are selective to the material of the dummy gate stack 220. For example, removing the dummy gate stack 220 may be implemented using a selective wet etch, a selective dry etch, or a combination thereof that is selective to the dummy gate stack 220. After removing the dummy gate stack 220, the sidewalls of the channel layer 208 and the sacrificial layer 206 in the channel region 212C are exposed in the gate trench 252. In addition, a portion of the segregation prevention layer 242 stacked between the gate spacer 226 and the topmost one of the channel layer 208 may also be exposed in the gate trench 252.

[0047] refer to Fig.21, after removing the pseudo gate stack 220, the method 100 includes the operation of selectively removing the sacrificial layer 206 between the channel layers 208 in the channel region 212C. The selective removal of the sacrificial layer 206 releases the channel layer 208 to form a channel member (also labeled 208). The selective removal of the sacrificial layer 206 also leaves a space 254 between the channel members 208. The space 254 can be considered as a portion of the gate trench 252 that extends continuously downward to the bottom of the channel member 208. The selective removal of the sacrificial layer 206 can be implemented by selective dry etching, selective wet etching or other selective etching processes. An exemplary selective dry etching process may include the use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. An exemplary selective wet etching process may include APM etching (e.g., ammonia hydroxide-hydrogen peroxide-water mixture). In addition, the portion of the segregation prevention layer 242 stacked between the internal spacer 234 and the channel member 208 may also be exposed in the space 254.

[0048] refer to Fig. 22, method 100 includes further operations to form a gate structure 256 to wrap around each of the channel members 208. In some embodiments, the gate structure 256 is formed within the gate trench 252 (and into the space 254 left by removing the sacrificial layer 206). At this point, the gate structure 256 wraps around each of the channel members 208. The gate structure 256 includes a gate dielectric layer 258 and a gate electrode layer 260 above the gate dielectric layer 258. In some embodiments, although not explicitly shown in the figure, the gate dielectric layer 258 includes an interface layer and a high-K gate dielectric layer. High-K dielectric materials as used and described herein include dielectric materials with high dielectric constants, for example, greater than the dielectric constant of thermal silicon oxide (~3.9). The interface layer may include a dielectric material such as silicon oxide, hafnium silicate, or silicon oxynitride. The interface layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The high-K gate dielectric layer may include hafnium oxide. Alternatively, the high-K gate dielectric layer may include other high-K dielectric materials, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium dioxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba, Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. The high-K gate dielectric layer may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and / or other suitable methods. In addition, the exposed end of the segregation preventing layer 242 may contact the gate dielectric layer 258, particularly the interface layer. If the interface layer is thinner than the segregation preventing layer 242, the segregation preventing layer 242 may contact both the interface layer and the high-k gate dielectric layer.

[0049] The gate electrode layer 260 of the gate structure 256 may include a single layer or optionally a multi-layer structure, such as a metal layer (work function metal layer) having a selected work function to enhance device performance, a liner layer, a wetting layer, an adhesion layer, a metal alloy or various combinations of metal silicides. For example, the gate electrode layer 260 may include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals or other suitable metal materials or combinations thereof. In various embodiments, the gate electrode layer 260 may be formed by ALD, PVD, CVD, electron beam evaporation or other suitable processes. In various embodiments, a CMP process may be performed to remove excess metal, thereby providing a substantially planar top surface of the gate structure 256. The gate structure 256 includes a portion between the channel members 208 in the channel region 212C.

[0050] Still reference Fig. 22 , at the end of the operation in frame 128, a transistor 280, in particular an n-type transistor 280, is substantially formed. The transistor 280 includes a channel member 208 vertically stacked along the Z direction. Each of the channel members 208 is wrapped by a gate structure 256. The channel member 208 extends along the X direction or is sandwiched between two source / drain components 244. Each of the source / drain components 244 includes a first epitaxial layer 244A in contact with the channel member 208, a second epitaxial layer 244B in contact with the first epitaxial layer 244A, and a third epitaxial layer 244C in contact with the second epitaxial layer 244B. The second epitaxial layer 244B is spaced apart from the channel member 208 by the first epitaxial layer 244A. The first epitaxial layer 244A may include SiAs, and the second epitaxial layer 244B and the third epitaxial layer 244C may include SiP. In forming the SDE region 208D stacked between the inner spacers 234, phosphorus atoms also diffuse into the first epitaxial layer 244A and diffuse into the end portion of the channel member 208. The arsenic-containing segregation prevention layer 242 separates the SEC region 208D from the inner spacers 234 and the gate spacers 226 so that the SEC region 208D does not contact the inner spacers 234 and the gate spacers 226, preventing phosphorus segregation.

[0051] Fig.23A An alternative embodiment of transistor 280 is shown in FIG. Fig. 22 and Fig.23AMany aspects of transistor 280 in FIG. 1 are identical or similar. For clarity and ease of reference, reference numerals for identical or similar components are repeated. One difference is that for example, Fig.23A In the depicted embodiment of FIG, the gate spacer 226 may be formed of a dielectric material other than a nitride (e.g., an oxide), and thus lacks dangling bonds when trapping arsenic atoms. Therefore, the selective deposition process may form the segregation prevention layer 242 on the surface of the inner spacer 234 and the dielectric film 240 instead of on the surface of the gate spacer 226.

[0052] Fig. 23B An alternative embodiment of transistor 280 is shown in FIG. Fig. 22 and Fig. 23B Many aspects of transistor 280 in FIG. 1 are identical or similar. For clarity and ease of reference, reference numerals for identical or similar components are repeated. One difference is that for example, Fig. 23B In the depicted embodiment of FIG. 1 , the dielectric film 240 may be formed of a dielectric material other than a nitride (e.g., an oxide), and thus lacks dangling bonds when trapping arsenic atoms. Therefore, the selective deposition process may form the segregation prevention layer 242 on the surfaces of the inner spacer 234 and the gate spacer 226 instead of on the surface of the dielectric film 240.

[0053] Fig.23C An alternative embodiment of transistor 280 is shown in FIG. Fig. 22 and Fig.23C Many aspects of transistor 280 in FIG. 1 are identical or similar. For clarity and ease of reference, reference numerals for identical or similar components are repeated. One difference is that for example, Fig.23C In the depicted embodiment of FIG. 1 , the gate spacer 226 and the dielectric film 240 can each be formed of a dielectric material other than a nitride (e.g., an oxide), and thus lack dangling bonds when trapping arsenic atoms. Therefore, the selective deposition process can form the segregation prevention layer 242 on the surface of the inner spacer 234 instead of on the surface of the gate spacer 226 and the dielectric film 240.

[0054] Fig.23D An alternative embodiment of transistor 280 is shown in FIG. Fig. 22 and Fig.23D Many aspects of transistor 280 in FIG. 1 are identical or similar. For clarity and ease of reference, reference numerals for identical or similar components are repeated. One difference is that for example, Fig.23D In the depicted embodiment, the selective deposition of the segregation prevention layer 242 is performed before forming the base epitaxial layer 236 and the dielectric film 240 (in Figure 1In the embodiment, frame 120 is before frames 116 and 118), so that the segregation prevention layer 242 is also formed on the interface between the bottommost one of the inner spacers 234 and the dielectric film 240 and on the interface between the bottommost one of the inner spacers 234 and the fin-shaped substrate 212B. Because in this optional embodiment, the dielectric film 240 is formed after the segregation prevention layer 242 is selectively deposited, no segregation prevention layer 242 is formed on the top surface of the dielectric film 240, regardless of whether the dielectric film 240 is a nitride, an oxide, or other dielectric material. However, whether the segregation prevention layer 242 is deposited on the surface of the gate spacer 226 depends on whether the gate spacer 226 is a nitride, such as Fig.23A The changes depicted in .

[0055] Although not intended to be limiting, one or more embodiments of the present disclosure provide many benefits to semiconductor devices and their formation. For example, embodiments of the present disclosure provide transistors, particularly n-type transistors, comprising a vertical stack of channel members extending between two source / drain components. The source / drain components are separated from the internal spacer and / or gate spacer by a segregation prevention layer. The segregation prevention layer prevents segregation of phosphorus, increases the active phosphorus concentration in the SDE region, and improves junction profile uniformity.

[0056] In one exemplary aspect, the disclosed embodiments relate to a method. The method includes: forming a stack above a substrate, the stack including a plurality of channel layers interlaced with a plurality of sacrificial layers; patterning the stack and a top portion of the substrate to form a fin-shaped structure, the fin-shaped structure including a channel region and a source / drain region; forming a dummy gate stack above the channel region of the fin-shaped structure; depositing gate spacers on sidewalls of the dummy gate stack; recessing the source / drain region to form a source / drain trench that exposes the sidewalls of the channel layer and the sacrificial layer; recessing a portion of the sacrificial layer to form a plurality of internal spacer grooves; and depositing a gate spacer on the sidewalls of the dummy gate stack. In some embodiments, the segregation prevention layer comprises arsenic. In some embodiments, the segregation prevention layer comprises arsenic. In some embodiments, the segregation prevention layer is a two-dimensional (2-D) lattice of a single atomic layer. In some embodiments, the segregation prevention layer is an arsenic-containing compound. In some embodiments, the segregation prevention layer has a thickness ranging from about 0.13 nm to about 1 nm. In some embodiments, the segregation prevention layer separates the epitaxial component from the internal spacer so that the epitaxial component does not contact the internal spacer. In some embodiments, the selective deposition of the segregation prevention layer also deposits the segregation prevention layer on the sidewalls of the gate spacer. In some embodiments, forming an epitaxial component includes: forming a first epitaxial layer in contact with a channel layer; and forming a second epitaxial layer in contact with a segregation prevention layer over the first epitaxial layer. The first epitaxial layer includes a first n-type dopant, and the second epitaxial layer includes a second n-type dopant different from the first n-type dopant. In some embodiments, the first n-type dopant is arsenic, the second n-type dopant is phosphorus, and the segregation prevention layer includes arsenic. In some embodiments, during the selective deposition of the segregation prevention layer, the segregation prevention layer is selectively deposited on a nitride-containing dielectric surface, and wherein the internal spacer includes a nitride.

[0057] In another exemplary aspect, the disclosed embodiments relate to a method. The method includes: forming a plurality of channel members disposed above a fin-shaped substrate; forming a plurality of internal spacers interlaced with the channel members, the internal spacers including a nitride; depositing an arsenic-containing layer on the sidewalls of the internal spacers; forming an epitaxial member adjacent to the channel member, the arsenic-containing layer stacked between the epitaxial member and the internal spacers; and forming a gate structure that wraps each of the channel members. In some embodiments, the gate structure includes a gate dielectric layer and a gate electrode layer, and the arsenic-containing layer contacts the gate dielectric layer. In some embodiments, forming the epitaxial member includes: forming a first epitaxial layer adjacent to the channel member, wherein the first epitaxial layer includes arsenic; and forming a second epitaxial layer above the first epitaxial layer, wherein the second epitaxial layer is substantially free of arsenic. In some embodiments, a portion of the arsenic-containing layer is vertically stacked between the internal spacers and the channel member. In some embodiments, the method further includes: forming a dielectric layer between the bottom surface of the epitaxial member and the top surface of the fin-shaped substrate. The arsenic-containing layer is between the bottom surface of the epitaxial member and the top surface of the dielectric layer. In some embodiments, the arsenic containing layer separates the epitaxial features from the internal spacers such that the epitaxial features do not contact the internal spacers.

[0058] In another exemplary aspect, the disclosed embodiments relate to a semiconductor device. The semiconductor device includes: a fin-shaped base protruding from a substrate; a plurality of channel members disposed above the top surface of the fin-shaped base; a plurality of internal spacers interlaced with the channel members; a gate structure wrapping each of the channel members; a gate spacer disposed on the sidewall of the gate structure; a source / drain component adjacent to the channel member; and an arsenic-containing film between the source / drain component and the internal spacer. In some embodiments, the arsenic-containing film is also between the internal spacer and the channel member. In some embodiments, the arsenic-containing film has a first thickness measured between the source / drain component and the internal spacer and a second thickness measured between the internal spacer and the channel member, and the first thickness is greater than the second thickness. In some embodiments, the semiconductor device further includes: a dielectric film between the substrate and the source / drain component. The arsenic-containing film is also between the dielectric film and the source / drain component.

[0059] Some embodiments of the present application provide a method, comprising: forming a stack above a substrate, the stack comprising a plurality of channel layers interlaced with a plurality of sacrificial layers; patterning the stack and a top portion of the substrate to form a fin-shaped structure, the fin-shaped structure comprising a channel region and a source / drain region; forming a dummy gate stack above the channel region of the fin-shaped structure; depositing gate spacers on sidewalls of the dummy gate stack; recessing the source / drain region to form source / drain trenches exposing sidewalls of the channel layer and the sacrificial layer; recessing the sacrificial layer portion to form a plurality of internal spacer grooves; depositing gate spacers on the sidewalls of the dummy gate stack; recessing the source / drain region to form source / drain trenches exposing sidewalls of the channel layer and the sacrificial layer; recessing the sacrificial layer portion to form a plurality of internal spacer grooves; and depositing gate spacers on the sidewalls of the internal spacer grooves. A plurality of internal spacers are formed in the groove, wherein each of the internal spacers includes a first surface exposed in the source / drain groove and a second surface facing an adjacent one of the channel layers; a segregation prevention layer is selectively deposited on the first surface and the second surface of the internal spacer; an epitaxial component is formed in the source / drain groove, wherein a portion of the segregation prevention layer is stacked between the internal spacer and the epitaxial component; after forming the epitaxial component, the pseudo gate stack is removed; the channel layer in the channel region is released as a plurality of channel components; and a gate structure is formed to wrap each of the channel components.

[0060] In some embodiments, the segregation prevention layer includes arsenic. In some embodiments, the segregation prevention layer is a two-dimensional (2-D) lattice of a single atomic layer. In some embodiments, the segregation prevention layer is an arsenic-containing compound. In some embodiments, the segregation prevention layer has a thickness in a range from about 0.13 nm to about 1 nm. In some embodiments, the segregation prevention layer separates the epitaxial component from the internal spacer so that the epitaxial component does not contact the internal spacer. In some embodiments, selectively depositing the segregation prevention layer also deposits the segregation prevention layer on the sidewalls of the gate spacer. In some embodiments, forming the epitaxial component includes: forming a first epitaxial layer in contact with the channel layer; and forming a second epitaxial layer in contact with the segregation prevention layer over the first epitaxial layer, wherein the first epitaxial layer includes a first n-type dopant, and the second epitaxial layer includes a second n-type dopant different from the first n-type dopant. In some embodiments, the first n-type dopant is arsenic, the second n-type dopant is phosphorus, and the segregation prevention layer includes arsenic. In some embodiments, during the selective deposition of the segregation prevention layer, the segregation prevention layer is selectively deposited on a nitride-containing dielectric surface, and wherein the inner spacer comprises a nitride.

[0061] Other embodiments of the present application provide a method comprising: forming a plurality of channel components disposed above a fin-shaped substrate; forming a plurality of internal spacers interlaced with the channel components, wherein the internal spacers comprise a nitride; depositing an arsenic-containing layer on the sidewalls of the internal spacers; forming an epitaxial component adjacent to the channel component, wherein the arsenic-containing layer is stacked between the epitaxial component and the internal spacers; and forming a gate structure encapsulating each of the channel components.

[0062] In some embodiments, the gate structure includes a gate dielectric layer and a gate electrode layer, and wherein the arsenic-containing layer contacts the gate dielectric layer. In some embodiments, forming the epitaxial component includes: forming a first epitaxial layer adjacent to the channel component, wherein the first epitaxial layer includes arsenic; and forming a second epitaxial layer above the first epitaxial layer, wherein the second epitaxial layer is substantially free of arsenic. In some embodiments, a portion of the arsenic-containing layer is vertically stacked between the internal spacer and the channel component. In some embodiments, the method further includes: forming a dielectric layer between a bottom surface of the epitaxial component and a top surface of the fin-shaped substrate, wherein the arsenic-containing layer is between the bottom surface of the epitaxial component and the top surface of the dielectric layer. In some embodiments, the arsenic-containing layer separates the epitaxial component from the internal spacer so that the epitaxial component does not contact the internal spacer.

[0063] Still other embodiments of the present application provide a semiconductor device, comprising: a fin-shaped base protruding from a substrate; a plurality of channel components disposed above a top surface of the fin-shaped base; a plurality of internal spacers interlaced with the channel components; a gate structure wrapping each of the channel components; a gate spacer disposed on a side wall of the gate structure; a source / drain component adjacent to the channel component; and an arsenic-containing film between the source / drain component and the internal spacers.

[0064] In some embodiments, the arsenic-containing film is also between the internal spacer and the channel member. In some embodiments, the arsenic-containing film has a first thickness measured between the source / drain component and the internal spacer and a second thickness measured between the internal spacer and the channel member, and wherein the first thickness is greater than the second thickness. In some embodiments, the semiconductor device further comprises: a dielectric film between the substrate and the source / drain component, wherein the arsenic-containing film is also between the dielectric film and the source / drain component. The features of several embodiments are summarized above so that a person of ordinary skill in the art can better understand the various aspects of the embodiments of the present disclosure. A person of ordinary skill in the art should understand that they can easily use the embodiments of the present disclosure as a substrate to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments described herein. A person of ordinary skill in the art should also be aware that such equivalent constructions do not depart from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method for forming a semiconductor device, comprising: forming a stack over a substrate, the stack comprising a plurality of channel layers interleaved with a plurality of sacrificial layers; patterning the stack and a top portion of the substrate to form a fin structure, the fin structure including a channel region and source / drain regions; forming a dummy gate stack over the channel region of the fin structure; depositing gate spacers on sidewalls of the dummy gate stack; recessing the source / drain region to form a source / drain trench exposing sidewalls of the channel layer and the sacrificial layer; recessing the sacrificial layer portion to form a plurality of inner spacer grooves; forming a plurality of inner spacers in the inner spacer recess, wherein each of the inner spacers includes a first surface exposed in the source / drain trench and a second surface facing an adjacent one of the channel layers; selectively depositing a segregation prevention layer on the first surface and the second surface of the inner spacer; forming an epitaxial feature in the source / drain trench, wherein a portion of the segregation prevention layer is stacked between the inner spacer and the epitaxial feature; After forming the epitaxial component, removing the dummy gate stack; releasing the channel layer in the channel region as a plurality of channel members; and A gate structure is formed surrounding each of the channel members.

2. The method according to claim 1, wherein: The segregation prevention layer includes arsenic.

3. The method according to claim 2, wherein: The segregation prevention layer is a two-dimensional (2-D) lattice of a single atomic layer.

4. The method according to claim 2, wherein: The segregation prevention layer contains an arsenic compound.

5. The method according to claim 1, wherein: The segregation prevention layer has a thickness in a range from about 0.13 nm to about 1 nm.

6. The method according to claim 1, wherein: The segregation prevention layer separates the epitaxial member from the internal spacer so that the epitaxial member does not contact the internal spacer.

7. The method according to claim 1, wherein: Selectively depositing the segregation preventing layer also deposits the segregation preventing layer on sidewalls of the gate spacers.

8. The method according to claim 1, wherein: Forming the epitaxial component includes: forming a first epitaxial layer in contact with the channel layer; and forming a second epitaxial layer on the first epitaxial layer and in contact with the segregation prevention layer, The first epitaxial layer includes a first n-type dopant, and the second epitaxial layer includes a second n-type dopant different from the first n-type dopant.

9. A method of forming a semiconductor device, comprising: forming a plurality of channel members disposed over the fin-shaped substrate; forming a plurality of internal spacers interlaced with the channel members, wherein the internal spacers comprise a nitride; depositing an arsenic-containing layer on sidewalls of the inner spacer; forming an epitaxial feature adjacent to the channel member, wherein the arsenic containing layer is stacked between the epitaxial feature and the internal spacer; and A gate structure is formed surrounding each of the channel members.

10. A semiconductor device comprising: fin-shaped base, protruding from the substrate; a plurality of channel members disposed above the top surface of the fin-shaped substrate; a plurality of internal spacers interlaced with the channel members; a gate structure wrapping each of the channel members; a gate spacer disposed on a sidewall of the gate structure; a source / drain member adjacent to the channel member; as well as An arsenic-containing film is interposed between the source / drain features and the inner spacer.

Images