Semiconductor device with sloped field plate

Abstract

The present disclosure generally relates to a semiconductor device having a sloped field plate. In an example, a semiconductor device includes a semiconductor substrate (1802), a gate (G), a drain contact (1902), a source contact (1904), and a field plate (2404, 2816). The gate (G) is on a surface of the semiconductor substrate (1802). The drain contact (1902) and the source contact (1904) are on the semiconductor substrate (1802). The field plate (2404, 2816) is over the surface of the semiconductor substrate (1802) and extends from a side of the gate (G) toward the drain contact (1902). The field plate (2404, 2816) includes a plurality of field plate portions (2404, 2816). Each of the plurality of field plate portions (2404, 2816) has a uniform respective slope with respect to the surface, and the plurality of field plate portions (2404, 2816) have different slopes.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of U.S. Provisional Patent Application Serial No. 63 / 589,040, filed on October 10, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present application relates to a semiconductor device having a tilted field plate. Background Art

[0004] One type of semiconductor device is a high electron mobility transistor (HEMT). A HEMT typically employs different semiconductor materials to form a heterojunction, wherein a channel may be formed near the heterojunction and between a source and a drain. A HEMT may have high speed operation, which makes the HEMT attractive for high frequency applications, among other things. Summary of the invention

[0005] This summary is provided to introduce a brief selection of the disclosed concepts in a simplified form, which concepts are further described in the following detailed description including the provided figures. Various disclosed devices and methods can be advantageously applied to semiconductor devices with tilted field plates. Although such embodiments can be expected to achieve reduced peak electric field, increased electric field curve, improved gate time dependent dielectric breakdown (TDDB), increased breakdown voltage (BV) and / or reduced gate-drain capacitance and leakage current, no specific results are required unless explicitly stated in a particular claim.

[0006] The example described herein is a semiconductor device. The semiconductor device includes a semiconductor substrate, a gate, a drain contact, a source contact, and a field plate. The gate is on the surface of the semiconductor substrate. The drain contact and the source contact are on the semiconductor substrate. The field plate is above the surface of the semiconductor substrate and extends from one side of the gate toward the drain contact. The field plate includes a plurality of field plate portions. Each of the plurality of field plate portions has a uniform corresponding slope relative to the surface, and the plurality of field plate portions have different slopes.

[0007] Another example is a method. An etch stop layer is formed on a surface of a semiconductor substrate of a semiconductor device. The semiconductor device includes a gate, a drain contact, and a source contact on the surface. One or more dielectric layers are formed on the etch stop layer. One or more photoresist layers are formed on the dielectric layer between the gate and the drain contact. One or more photoresist layers are patterned with one or more grayscale masks to form a first plurality of inclined surfaces. Each first inclined surface has a corresponding uniform slope, and the first inclined surfaces have different slopes. The one or more dielectric layers are etched to form a second plurality of inclined surfaces based on the first inclined surfaces of the one or more photoresist layers and expose a portion of the etch stop layer. A field plate having a plurality of field plate portions is formed between the gate and the drain contact on the second plurality of inclined surfaces and on the exposed portion of the etch stop layer. Each of the plurality of field plate portions has a uniform corresponding slope relative to the surface of the semiconductor substrate, and the plurality of field plates have different slopes.

[0008] The foregoing summary of the invention has been quite extensively summarized various features of examples of the present disclosure so that the following detailed description may be better understood. Additional features and advantages of such examples will be described below. The described examples may be readily used as a basis for modifying or designing other examples within the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 FIG. 5 is a schematic diagram illustrating a cross-sectional view of a high electron mobility transistor (HEMT) including a field plate according to some examples.

[0010] Figure 2 To illustrate the representation according to some examples Figure 1 Schematic diagram of the HEMT circuit.

[0011] Figure 3A and 3B is a graph illustrating electric field distribution in a substrate of a HEMT according to some examples.

[0012] Figure 4A and 4B is a graph illustrating electric field distribution in a substrate of a HEMT according to some examples.

[0013] Figure 5A and 5B is a graph illustrating electric field distribution in a substrate of a HEMT according to some examples.

[0014] Figure 6 Included are schematic diagrams showing a HEMT including multiple leveling field plates according to some examples and graphs showing electric field distribution in a substrate of the HEMT.

[0015] Figure 7Included are schematic diagrams showing a HEMT including a single-sided tilted gate field plate according to some examples and a graph showing electric field distribution in a substrate of the HEMT.

[0016] Figure 8 Included are schematic diagrams illustrating a HEMT including a single-sided tilted gate field plate having multiple slopes according to some examples and a graph illustrating electric field distribution in a substrate of the HEMT.

[0017] Fig. 9 Included are schematic diagrams illustrating a HEMT including a single-sided tilted source field plate having multiple slopes according to some examples and a graph illustrating electric field distribution in a substrate of the HEMT.

[0018] Fig.10 , 11 12 are schematic diagrams illustrating aspects of grayscale lithography and etching processes for forming tilted field plates according to some examples.

[0019] Fig.13 and 14 Schematic diagrams illustrating additional aspects of grayscale lithography and etching processes according to some examples.

[0020] Fig.15 and 16 Schematic diagram illustrating aspects of a mask that may be implemented in grayscale lithography according to some examples.

[0021] Fig.17 is a flow chart of a method of manufacturing a semiconductor device according to some examples.

[0022] Fig.18 , 19 , 20, 21, 22, 23, 24, 25, 26, 27, 28 and 29 are diagrams showing some examples of Fig.17 Schematic diagram of a cross-sectional view of a semiconductor device at various manufacturing stages in a method.

[0023] Fig. 30A and 30B is a flow chart of a method of manufacturing a semiconductor device according to some examples.

[0024] Fig.31 , 32 , 33 and 34 are diagrams showing the Fig. 30A and 30B Schematic diagram of a cross-sectional view of a semiconductor device at various manufacturing stages in a method.

[0025] Fig.35A and 35B is a flow chart of a method of manufacturing a semiconductor device according to some examples.

[0026] Fig.36 , 37 , 38, 39, 40, 41 and 42 are diagrams showing the Fig.35A and 35B Schematic diagram of a cross-sectional view of a semiconductor device at various manufacturing stages in a method.

[0027] Fig.43A and 43B is a flow chart of a method of manufacturing a semiconductor device according to some examples.

[0028] Fig.44 , 45 46, 47, 48 and 49 are diagrams showing the Fig.43A and 43B Schematic diagram of a cross-sectional view of a semiconductor device at various manufacturing stages in a method.

[0029] Fig.50A and 50B is a flow chart of a method of manufacturing a semiconductor device according to some examples.

[0030] Fig.51 , 52 , 53, 54, 55 and 56 are diagrams showing the Fig.50A and 50B Schematic diagram of a cross-sectional view of a semiconductor device at various manufacturing stages in a method.

[0031] The drawings and accompanying detailed description are provided for understanding the features of the various examples and do not limit the scope of the appended claims. The examples illustrated in the drawings and described in the accompanying detailed description can be easily used as a basis for modifying or designing other examples within the scope of the appended claims. Where possible, the same reference numerals may be used to refer to the same elements that are common among the drawings. The drawings are drawn to clearly illustrate the relevant elements or features and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0032] Various features are described below with reference to the drawings. The illustrated examples may not have all aspects or advantages shown. An aspect or advantage described in conjunction with a particular example is not necessarily limited to that example and may be practiced in any other example, even if not so illustrated or not explicitly described. In addition, the methods described herein may be described in a particular order of operations, but other methods according to other examples may be implemented with various other orders of more or fewer operations (e.g., including different serial or parallel executions of various operations).

[0033] The present disclosure relates to a semiconductor device with a tilted field plate. In some examples described herein, the semiconductor device is a high electron mobility transistor (HEMT). The semiconductor device may have one or more field plates. The field plate may have one or more tilted field plate portions, and the tilted field plate portions have corresponding slopes that may be different for different tilted field plate portions. In other examples, the field plate may have different configurations, such as having different surfaces, such as convex surfaces or concave surfaces. In some examples, the field plate may be formed on a dielectric structure patterned using a grayscale lithography process. The various examples of the field plates described herein can achieve reduced peak electric fields, increased electric field curves, improved gate time-dependent dielectric breakdown (TDDB), increased breakdown voltage (BV) and / or reduced gate-drain capacitance and leakage current. Other benefits and advantages can be achieved.

[0034] Various examples are described herein. Although specific examples may illustrate various aspects of the features generally described above, examples may incorporate any combination of the features described in detail in the following examples. Some cross-sectional views of various semiconductor devices herein may be general depictions used to convey various aspects or concepts about such semiconductor devices. More specifically, some field plates and semiconductor devices depicted in cross-sectional views may not necessarily accurately depict the structure of such field plates and semiconductor devices, except to the extent described herein. The illustrations of those field plates and semiconductor devices are intended to convey various aspects or concepts about those field plates and semiconductor devices.

[0035] In a high electron mobility transistor (HEMT), one or more field plates may manage the electric field between the source and drain of the HEMT to increase the breakdown voltage (BV) when the HEMT is turned off. Figure 1An example HEMT 100 including a field plate is depicted. HEMT 100 is on and / or in a semiconductor substrate 102. Semiconductor substrate 102 includes a support substrate 104, one or more transition layers 106 on or above support substrate 104, a channel layer 108 on or above one or more transition layers 106, and a barrier layer 110 on or above channel layer 108. Examples of such layers are described in more detail later. A gate layer 112 is on or above barrier layer 110. Channel layer 108, barrier layer 110, and gate layer 112 may each be a gallium nitride-based material, as described in subsequent examples. A source contact 114 is electrically coupled to a source of HEMT 100, and a drain contact 116 is electrically coupled to a drain of HEMT 100. As depicted, contacts 114, 116 extend through barrier layer 110 and channel layer 108 into one or more transition layers 106 and on / over supporting substrate 104. In some examples, contacts 114, 116 may contact and / or extend into barrier layer 110, but not extend through barrier layer 110. In some examples, contacts 114, 116 may extend through barrier layer 110 and may contact and / or extend into channel layer 108, but not extend through channel layer 108. Gate layer 112 is laterally between source contact 114 and drain contact 116. The channel of HEMT 100 is below gate layer 112 in channel layer 108 and laterally between a source and a drain, both of which are in channel layer 108. In some examples, HEMT 100 is an enhancement mode (E-mode) device.

[0036] HEMT 100 further includes a first field plate 118 and a second field plate 120. First field plate 118 is above gate layer 112 and extends laterally from gate layer 112 toward drain contact 116. Second field plate 120 is above first field plate 118 and gate layer 112 and extends laterally from gate layer 112 toward drain contact 116 a greater distance than first field plate 118. In various examples, multiple field plates may be formed between the source and the drain above the barrier layer.

[0037] In operation, the first field plate voltage V FP1 is applied to the first field plate 118, and the second field plate voltage V FP2 Applied to the second field plate 120. The first field plate voltage V FP1 can be the same as the second field plate voltage V FP2 Different voltages are applied to provide different electric fields through the field plates 118 and 120. In some examples, the first field plate voltage V FP1 may be a voltage applied to the gate layer 112 (eg, the first field plate 118 may be electrically coupled to the gate layer 112), and the second field plate voltage V FP2may be a voltage applied to the source (eg, the second field plate 120 may be electrically coupled to the source contact 114).

[0038] A region 122 of the HEMT 100 below the first field plate 118 and immediately adjacent to the gate layer 112 may form a first field plate transistor, and a region 124 of the HEMT 100 below the second field plate 120 and extending laterally beyond the first field plate 118 may form a second field plate transistor. Each field plate transistor may be a depletion mode (D-mode) device having a negative threshold voltage.

[0039] Figure 2 2 is a circuit 200 representing the HEMT 100. The circuit 200 includes access transistors 202 and 210, a core transistor 204, a first field plate transistor 206, and a second field plate transistor 208. The core transistor 204 is a HEMT formed by the gate layer 112, the source, the channel, and the drain in the HEMT 100, and can be driven by a gate voltage V G The first field plate transistor 206 is a HEMT formed with the first field plate 118, and the second field plate transistor 208 is a HEMT formed with the second field plate 120. The access transistors 202 and 210 represent transistors formed in an access region including a gate-source region and a gate-drain region, wherein the channel is not covered by either gate of the field plate. The source of the access transistor 202 is the source of the HEMT 100. The drain of the access transistor 202 is electrically coupled to the source of the core transistor 204. The drain of the core transistor 204 is electrically coupled to the source of the first field plate transistor 206. The drain of the first field plate transistor 206 is electrically coupled to the source of the second field plate transistor 208. The drain of the second field plate transistor 208 is electrically coupled to the source of the access transistor 210. The drain of the access transistor 210 is the drain of the HEMT 100. The gate of the core transistor 204 is the gate layer 112 of the HEMT 100 and is electrically coupled to a gate voltage V G The gate of the first field plate transistor 206 is the first field plate 118 of the HEMT 100 and is electrically coupled to the first field plate voltage V FP1 The gate of the second field plate transistor 208 is the second field plate 120 of the HEMT 100 and is electrically coupled to the second field plate voltage V FP2 . Source voltage V S is electrically coupled to the source of the HEMT 100, and the drain voltage V D is electrically coupled to the drain of the HEMT 100 .

[0040] In addition, the intrinsic source voltage of the core transistor 204 is V si , and the intrinsic drain voltage of the core transistor 204 is represented by V di, the intrinsic drain voltage is also the intrinsic source voltage of the first field plate transistor 206. The intrinsic source voltage of the access transistor 210 is V spi , the intrinsic source voltage also represents the intrinsic drain voltage of the second field plate transistor 208. The intrinsic source voltage of the second field plate transistor 208 is represented by V gpi It indicates that the intrinsic source voltage may also be the intrinsic drain voltage of the first field plate transistor 206 .

[0041] Figure 3A , 4A 5A each illustrate an example HEMT with electric field distribution in substrate 300 under different circumstances. The HEMT includes a gate G 302, a gate coupled field plate (GFP) 304, and a source coupled field plate (SFP) 306 on substrate 300. A source S and a drain D in substrate 300 are also indicated. Figure 3B , 4B and 5B are shown in Figure 3A , 4A 304 and 5A. In these figures, GFP 304 can be interchangeably referred to as the first field plate (FP1), and SFP 306 can be interchangeably referred to as the second field plate (FP2). GFP 304 can be represented by Figure 2 The first field plate transistor 206 is represented by the SFP 306, and the SFP 306 can be Figure 2 The second field plate transistor 208 is represented.

[0042] exist Figure 3A In the gate-source voltage V GS Less than the core transistor threshold voltage V T . Source voltage V S can be zero volts, and the gate voltage V G can be zero volts or another voltage such that the gate-source voltage V GS Less than the threshold voltage V T . Drain voltage V D Start ramping up.

[0043] Initially, the gate voltage V G Lower than the core transistor threshold voltage V T The disabled core transistor can maintain an electric field (E field) that peaks in the substrate 300 at the edge of the gate G 302 and decreases across the GFP transistor, as shown in FIG. Figure 3A and 3B As shown in .

[0044] As the drain voltage V D Further increase, the first field plate voltage V (of GFP 304) FP1 The intrinsic drain voltage Vdi The difference between the GFP transistor’s intrinsic source voltage and the GFP transistor’s threshold voltage (V to,FP1 )(For example, V FP1 -V di <V to,FP1 ), and the GFP transistor is turned off / depleted. Another E field may be maintained across the GFP transistor. The E field may peak at the edge of GFP 304 and decrease across the SFP transistor that remains turned on, as Figure 4A and 4B As shown in .

[0045] As the drain voltage V D Further increase, the second field plate voltage V FP2 The intrinsic drain voltage V gpi The difference between the SFP transistor’s intrinsic source voltage and the SFP transistor’s threshold voltage (V to,FP2 )(For example, V FP2 -V gpi <V to,FP2 ), the SFP transistor is turned off / depleted, and yet another E field may be maintained across the depleted SFP transistor. The E field may peak at the edge of the SFP 306, as shown in FIG. Figure 5A and 5B As shown in .

[0046] The additional E-field means that the depleted GFP transistor and SFP transistor can account for an additional voltage drop between the source and drain and can reduce the peak E-field of the core transistor, which can increase the overall breakdown voltage of the HEMT transistor.

[0047] The threshold voltages of the GFP transistor and the SFP transistor (V to,FP1 and V to,FP2 ) can be based on the height of the field plates (e.g., GFP 304 and SFP 306) above the barrier layers of substrate 300. The threshold voltage (V to,FP1 and V to,FP2 ) can be configured to move the E-field distribution and improve breakdown voltage and reliability.

[0048] BV can be increased by increasing the voltage maintained across the field plate, which reduces the drain-source voltage V across the core transistor. DS One way is to have multiple leveling field plates 602, such as Figure 6 , where each field plate 602 has a different height above the barrier layer of the HEMT transistor. Each field plate 602 provides a field plate transistor with a different threshold voltage. Figure 6The magnitude of the electric field (|Ech|) from gate G to drain D is shown, where the area under the electric field curve is equal to the drain-source voltage V DS In the case of multiple leveling field plates 602, multiple E field peaks appear at the discontinuities between adjacent field plates 602. The E field drops rapidly after each peak, resulting in a small area under the E field curve. The small area results in an inefficient drain-source voltage V DS Blocking and reduced BV. The first E field peak at the edge of gate G is high, which reduces gate TDDB.

[0049] like Figure 7 The single-sided tilted gate field plate 702 shown in FIG. 7 , which extends from one side of the gate G toward the drain D and has a slope (with a tilt angle φ) relative to the top surface of the semiconductor substrate (e.g., barrier layer), can increase BV. The tilted gate field plate 702 can also represent multiple field plates with multiple heights above the barrier layer, where each field plate provides a field plate transistor with a different threshold voltage. In the case of a single-sided tilted gate field plate, there is no gap between the field plates, and the number of peaks is reduced. This increases the area under the E-field curve, which represents a more efficient drain-source voltage V DS Blocking and increasing BV. For the same drain-source voltage V DS Block, with Figure 6 The lateral dimension 710 of the tilted gate field plate 702 can be reduced compared to the total lateral dimension 610 of the plurality of leveling field plates 602 in the gate. The distance between the gate and the drain can be reduced, which can increase the gate-drain capacitance (Miller capacitance) and the gate-drain leakage current. Slope considerations can be conflicting. A small slope (e.g., a small bevel angle φ) can reduce the peak E field and improve TDDB; however, a small slope (e.g., a small bevel angle φ) can also reduce the area under the E field slope and the area under the E field curve, which can reduce BV for the same E field peak magnitude and can reduce the drain-source voltage V DS Blocking. Conversely, for the same drain-source voltage V as the high slope DS , a small slope can produce a higher E-field peak magnitude.

[0050] The single-sided inclined gate field plate 802 with multiple slopes (with corresponding slope angles φ1, φ2) can be combined with the single-sided inclined source field plate 804 with a slope (with slope angle φ3), such as Figure 8. The first slope of the inclined gate field plate 802 (with an angle of inclination φ1) can be made smaller to reduce the peak E field at the gate and improve the gate TDDB, and the second slope of the inclined gate field plate 802 (with an angle of inclination φ2) and the third slope of the inclined source field plate 804 (with an angle of inclination φ3) can be made larger to increase the E field curve slope (and the E field curve area) and increase BV. The inclined source field plate 804 can shield the gate G and the drain D and reduce the gate-drain capacitance and leakage current. The inclined source field plate 804 can be used for power routing to the source S. An E field peak may occur at the gap between the gate field plate 802 and the source field plate 804. The gate field plate 802 and the source field plate 804 can be separated by a dielectric to avoid electrical shorting or jumping between the gate field plate 802 and the source field plate 804.

[0051] The single-sided tilted source field plate 902 with multiple slopes (with corresponding tilt angles φ1, φ2) can also improve the E field distribution alone, such as Fig. 9 . The first slope (with bevel angle φ1) can be made smaller and extend closer to the gate G to reduce the peak E field and improve the gate TDDB, and the second slope (with bevel angle φ2) can be made larger to increase the E field curve slope (and E field curve area) and increase BV. The dependence of TDDB on process, voltage and temperature (PVT) can be reduced. The larger second slope (with bevel angle φ2) can reduce the overall lateral dimension 910 of the tilted source field plate 902 and reduce the source-drain capacitance. The tilted source field plate 902 can shield the gate G from the drain D and reduce the gate-drain capacitance and leakage current. The tilted source field plate 902 can be used for power routing to the source S. The tilted source field plate 902 can have reduced effectiveness in improving TDDB because metal discontinuities may remain.

[0052] Although described individually or in combination with other aspects Figures 7 to 9 but Figures 7 to 9 Any aspect of Figures 7 to 9 Any other aspect combination of. The examples described later may include Figures 7 to 9 and other examples may include Figures 7 to 9 More generally, any aspect of an example described herein may be combined with any other aspect of another example described herein.

[0053] Fig.10 , 11 12 illustrate aspects of grayscale lithography and etching processes implemented in some examples for forming tilted field plates. Fig.10Shown is a first dielectric layer 1002, an etch stop layer 1004 over the first dielectric layer 1002, and a second dielectric layer 1006 over the etch stop layer 1004. A patterned photoresist 1008 is over the second dielectric layer 1006 and is patterned to have an inclined surface 1010 relative to a top surface 1012 of the second dielectric layer 1006 on which the patterned photoresist 1008 is disposed. The inclined surface 1010 forms a first angle α11014 with the plane of the top surface 1012.

[0054] To form the patterned photoresist 1008, a photoresist layer is formed (e.g., deposited by spin coating) and patterned into the patterned photoresist 1008 using grayscale lithography. In grayscale lithography according to some examples, a mask 1020 is implemented that allows light 1022 (e.g., ultraviolet (UV) light or other electromagnetic radiation) to be blocked or pass therethrough. The intensity of the light 1022 passing through the mask 1020 varies across the photoresist layer (e.g., in grayscale) to achieve the slanted surface 1010 in the patterned photoresist 1008. Examples of light intensity variations that can be achieved using different masks are described in more detail later.

[0055] exist Fig.11 , an anisotropic etching process is performed to form an inclined surface 1104 in a dielectric structure 1102 formed by a second dielectric layer 1006. The anisotropic etching may be, for example, reactive ion etching (RIE). The etching process consumes the patterned photoresist 1008 and the second dielectric layer 1006 at the same time, so that the inclined surface 1104 is formed in the dielectric structure 1102. The consumption of the patterned photoresist 1008 may result in a patterned photoresist 1008' and a remaining inclined surface 1010' remaining after the etching process, which may then be removed, for example, by an ashing process. The etching process typically does not consume the etch stop layer 1004, or consumes the etch stop layer 1004 at a significantly lower rate than the second dielectric layer 1006, so that the etching stops at the etch stop layer 1004.

[0056] The inclined surface 1104 forms a second angle α2 1106 with a plane parallel to the plane of the top surface 1012 (e.g., the plane of the bottom surface of the dielectric structure 1102). In some examples, the second angle α2 1106 is less than 90° and greater than 0°. More particularly, the second angle α2 1106 may be equal to or greater than 6°, 9°, 12°, 15°, 18°, etc., and may be equal to or less than 60°, 50°, 35°, 30°, etc. Any of the bevel angles in the various examples described herein may be the same or similar angles. The second angle α2 1106 may be less than, equal to, or greater than the first angle α1 1014. For example, if the etching process consumes the patterned photoresist 1008 at a greater or faster rate than the rate at which the second dielectric layer 1006 is consumed, the second angle α2 1106 may be less than the first angle α1 1014. If the etching process consumes the patterned photoresist 1008 at a rate equal to the rate at which the second dielectric layer 1006 is consumed, the second angle α2 1106 may be equal to the first angle α1 1014. If the etching process consumes the patterned photoresist 1008 at a rate less than or slower than the rate at which the second dielectric layer 1006 is consumed, the second angle α2 1106 may be greater than the first angle α1 1014. The difference between the respective rates at which the patterned photoresist 1008 and the second dielectric layer 1006 are consumed by the etching process may be configured to produce a sloped surface in the dielectric structure 1102. Thus, the chemistry of the etching process may be tuned to achieve the sloped surface 1104 of the dielectric structure 1102.

[0057] exist Fig.12 , a field plate 1202 is formed on the inclined surface 1104 of the dielectric structure 1102. As described in detail later, the field plate 1202 can be formed by depositing one or more metals on the exposed portion of the etch stop layer 1004 and on the inclined surface 1104 and the remaining top surface 1012 of the dielectric structure 1102. The one or more metals can then be patterned using a photolithography process (e.g., binary photolithography) and an etching process.

[0058] Fig.13 and 14 Additional aspects of the grayscale lithography and etching processes implemented in some examples are shown. Fig.13 and 14 As shown in , multiple slopes can be generated in a dielectric structure. Multiple slopes can be generated using one mask or multiple masks.

[0059] Fig.13A first dielectric layer 1302, an etch stop layer 1304 over the first dielectric layer 1302, and a second dielectric layer 1306 over the etch stop layer 1304 are shown. A photoresist 1308 is over the second dielectric layer 1306 and is patterned to have a multi-slant inclined surface relative to a top surface 1312 of the second dielectric layer 1306 on which the photoresist 1308 is disposed. The multi-slant inclined surface includes a first inclined surface portion 1310a and a second inclined surface portion 1310b. The first inclined surface portion 1310a extends from the top surface 1312 of the second dielectric layer 1306 to the second inclined surface portion 1310b, and the second inclined surface portion 1310b extends from the first inclined surface portion 1310a to the top surface of the photoresist 1308.

[0060] The first inclined surface portion 1310a forms a first angle β1 1314a with the plane of the top surface 1312, and the second inclined surface portion 1310b forms a second angle γ1 1314b with a plane parallel to the plane of the top surface 1312. The first angle β1 1314a and the second angle γ1 1314b are unequal angles. In some examples, the first angle β1 1314a is greater than the second angle γ1 1314b (e.g., β1>γ1). In some examples, the first angle β1 1314a is less than the second angle γ1 1314b (e.g., β1<γ1). Grayscale lithography is used to pattern the photoresist 1308, as described above with respect to Fig.10 The mask used to pattern the photoresist 1308 implements a complex intensity function of light to be incident on the photoresist 1308 to achieve a multi-skew inclined surface.

[0061] exist Fig.14 In the embodiment, an anisotropic etching process is performed to form multiple skewed inclined surfaces in the dielectric structure 1401 formed by the second dielectric layer 1306. The anisotropic etching process may be as described above with respect to Fig.11 The multi-slanted inclined surface of the dielectric structure 1401 includes a first inclined surface portion 1402a and a second inclined surface portion 1402b. The first inclined surface portion 1402a extends from the top surface of the etch stop layer 1304 to the second inclined surface portion 1402b, and the second inclined surface portion 1402b extends from the first inclined surface portion 1402a to the remaining top surface 1312 of the dielectric structure 1401.

[0062] The first inclined surface portion 1402a forms a third angle β2 1404a with a plane parallel to the plane of the top surface 1312 (e.g., the plane of the bottom surface of the dielectric structure 1401). The second inclined surface portion 1402b forms a fourth angle γ2 1404b with a plane parallel to the plane of the top surface 1312 (e.g., the plane of the bottom surface of the dielectric structure 1401). The third angle β2 1404a and the fourth angle γ2 1404b may be less than, equal to, or greater than the first angle β1 1314a and the second angle γ1 1314b, respectively, as described above with respect to Fig.11 In some examples, the third angle β2 1404a and the fourth angle γ2 1404b are respectively smaller than the first angle β1 1314a and the second angle γ1 1314b (e.g., β2<β1, γ2<γ1). In some examples, the third angle β2 1404a and the fourth angle γ2 1404b are respectively equal to the first angle β1 1314a and the second angle γ1 1314b (e.g., β2=β1, γ2=γ1). In some examples, the third angle β2 1404a and the fourth angle γ2 1404b are respectively greater than the first angle β1 1314a and the second angle γ1 1314b (e.g., β2>β1, γ2>γ1).

[0063] Although the respective transitions from the first inclined surface portion 1310a to the second inclined surface portion 1310b or from the first inclined surface portion 1402a to the second inclined surface portion 1402b are shown at an acute angle, another surface may be between the respective inclined surface portions. For example, a gradual change in slope may transition from the slope of the first inclined surface portion to the slope of the second inclined surface portion in the transition surface portion. The transition surface may be a flat surface, a curved surface, a convex surface, a concave surface, any polynomial surface, etc. Grayscale lithography may be tuned to implement such a transition surface.

[0064] In some examples, multiple masks may be implemented to achieve multiple slopes, wherein each of the multiple slopes is in a corresponding dielectric structure formed by a dielectric layer. An etch stop layer may be between vertically adjacent dielectric layers. Each mask may be used to pattern a photoresist having a sloped surface, which is transferred into a corresponding dielectric layer to form a corresponding dielectric structure.

[0065] Fig.15 and 16 Aspects of a mask that may be implemented in grayscale lithography are shown. Fig.15 and 16Cross-sections of respective masks 1502, 1602 and corresponding intensity distributions and photoresist thickness distributions are shown. Masks 1502, 1602 have respective grayscale regions 1512, 1612. Grayscale regions 1512, 1612 produce equal photoresist thickness distributions. Grayscale regions 1512, 1612 have respective fill factor distributions that achieve corresponding intensity distributions and photoresist thickness distributions.

[0066] exist Fig.15 In the grayscale region 1512 of the mask 1502, the mask 1502 includes an opaque pattern 1514 and a transparent pattern 1516. The opaque pattern 1514 has a corresponding size 1522 that varies throughout the grayscale region 1512 (e.g., increases from the fully exposed region 1532 to the fully blocked region 1534). The transparent pattern 1516 has a corresponding size 1524 that is equal to each other throughout the grayscale region 1512. Each size 1524 can be below the resolution limit. The spacing (e.g., center-to-center spacing) between adjacent opaque patterns 1514 varies throughout the grayscale region 1512 (e.g., increases from the fully exposed region 1632 to the fully blocked region 1634). The varying size 1522 of the opaque pattern 1514 and the constant size 1524 of the transparent pattern 1516 produce a fill factor distribution in the grayscale region 1512 of the mask 1502.

[0067] exist Fig.16 In the grayscale region 1612 of the mask 1602, the mask 1602 includes an opaque pattern 1614 and a transparent pattern 1616. The opaque pattern 1614 has a corresponding size 1622 that varies throughout the grayscale region 1612 (e.g., increases from the fully exposed region 1632 to the fully blocked region 1634). The spacing 1624 (e.g., center-to-center spacing) between adjacent opaque patterns 1614 is equal throughout the grayscale region 1612. The transparent pattern 1616 has a corresponding size that varies throughout the grayscale region 1612 (e.g., decreases from the fully exposed region 1632 to the fully blocked region 1634). Each size of the transparent pattern 1616 can be below the resolution limit. The varying sizes 1622 and the constant spacing 1624 of the opaque pattern 1614 produce a fill factor distribution in the grayscale region 1612 of the mask 1602.

[0068] The intensity of the light exposed by the mask 1502, 1602 in the grayscale area 1512, 1612 is locally accumulated to achieve the slope of the corresponding photoresist distribution. The accumulation can be mathematically represented by a convolution function. Therefore, the intensity accumulation can be larger in the corresponding grayscale area 1512, 1612 near the corresponding fully exposed area 1532, 1632, and linearly decreases to the corresponding fully blocked area 1534, 1634. The accumulated intensity may produce the slope of the photoresist. The local accumulation or effective intensity is related to the resulting thickness of the photoresist. No image (e.g., discrete or binary image) is generated in the photoresist in the grayscale area 1512, 1612. In the illustrated example, the fill factor distribution of the grayscale area 1512, 1612 results in a linear accumulation of intensity, which produces an inclined surface in the photoresist with a uniform slope throughout the inclined surface.

[0069] about Fig.15 , when using a constant size 1524, it may be difficult to calculate the local accumulated intensity. Small local changes can be corrected by laterally shifting the transparent pattern. Any change will affect adjacent areas on the photoresist. If the transparent pattern is shifted to increase the intensity at one local area of ​​the photoresist, the intensity at the adjacent local area may decrease. Additional space can be added to the adjacent local area, but this may result in overcompensation.

[0070] about Fig.16 , when using a constant spacing, the filling (e.g., fill factor) of the transparent and opaque patterns can be adjusted to adjust the photoresist thickness. There may be an almost linear correlation between the fill factor and the photoresist thickness. A transfer function can be easily defined. Small local variations can be modified by changing the fill factor of a single element without affecting adjacent elements. Using a constant spacing can reduce the complexity of designing and producing photomasks for tilted field plates with multiple slopes.

[0071] The above examples of grayscale lithography have been shown and described with respect to positive photoresists. In other examples, grayscale lithography may implement negative photoresists. Furthermore, although described in the context of grayscale lithography using a mask, grayscale lithography may be implemented using maskless grayscale lithography techniques or digital grayscale lithography techniques. In addition, the grayscale lithography described above may be used for one-dimensional (1D) grayscale patterns (e.g., linear 1D patterns), and in other examples, grayscale lithography may implement two-dimensional (2D) grayscale patterns (e.g., linear 2D patterns) to adjust the field plate along the length of the channel and wherein the FP terminates near the width edge of the active area (e.g., finger active area) where the channel is disposed.

[0072] In addition, the above described inclined surfaces or inclined surface portions have a uniform slope throughout the corresponding inclined surface or inclined surface portion. Each inclined surface or inclined surface portion is a plane that runs through the corresponding inclined surface or inclined surface portion. In other examples, grayscale lithography can be implemented to achieve different types of surfaces. For example, grayscale lithography can be used to form a concave surface, a convex surface, etc., or another inclined surface.

[0073] Fig.17 is a flow chart of a method 1700 of fabricating a semiconductor device (eg, a HEMT) according to some examples. Fig.17 Method 1700 by Figures 18 to 29 Draw and Figures 18 to 29 Described in the context of Figures 18 to 29 Cross-sectional views of a semiconductor device at various fabrication stages are shown.

[0074] refer to Fig.17 Box 1702 and Fig.18 , providing a semiconductor substrate 1802. As shown, providing the semiconductor substrate 1802 may include providing a support substrate 1804, forming one or more transition layers 1806 above and on the support substrate 1804, forming a channel layer 1808 above and on the one or more transition layers 1806, and forming a barrier layer 1810 above and on the channel layer 1808. The support substrate 1804 may be a bulk semiconductor or an isolation substrate, a semiconductor on insulator (SOI) substrate, or any other suitable substrate. For example, the support substrate 1804 may be or include bulk silicon, silicon oxide, silicon carbide wafer, sapphire wafer, QROMIS substrate technology Substrate, etc. The one or more transition layers 1806 may include any number of layers of any material configured to accommodate the lattice mismatch between the support substrate 1804 and the channel layer 1808 (e.g., to reduce or minimize the generation and / or propagation of lattice defects in the channel layer 1808). For example, the one or more transition layers 1806 may have a gradient concentration of one or more elements in a direction orthogonal to the upper surface of the support substrate 1804. In addition, one of the one or more transition layers 1806 may be a doped buffer layer. The one or more transition layers 1806 may be formed on the support substrate 1804 by epitaxially growing the one or more transition layers 1806 using, for example, metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), low pressure chemical vapor deposition (LPCVD), or another epitaxial process.

[0075] The channel layer 1808 is configured to conduct and confine charge carriers (e.g., electrons) in two dimensions, possibly in combination with the barrier layer 1810. In some instances, the channel layer 1808 is configured to include a two-dimensional electron gas (2DEG). The 2DEG may be formed by band bending caused by the barrier layer 1810 over and on the channel layer 1808. In some instances, the channel layer 1808 may be part of the supporting substrate 1804 (e.g., without one or more transition layers 1806). In some instances, the channel layer 1808 includes a gallium nitride (GaN) layer, and in such instances, may be referred to as a GaN channel layer. In some instances, the channel layer 1808 may be or include indium aluminum gallium nitride (InAluminum Gallium Nitride (InGaN)). i Al j Ga 1-i-j N) (where 0≤i≤1, 0≤j≤1 and 0≤i+j≤1). In some examples, the material of the channel layer 1808 is or includes an unintentionally doped material, such as a material doped by diffusion of a dopant from another layer, or is or includes an intrinsic material. Other materials may be implemented for the channel layer 1808. The channel layer 1808 may be formed on the uppermost transition layer 1806 by epitaxially growing the channel layer 1808 using MOCVD, MBE, LPCVD, or another epitaxial process.

[0076] In some examples, the barrier layer 1810 may be or include an aluminum gallium nitride (AlGaN) layer, and in such examples, may be referred to as an AlGaN barrier layer. In some examples, the barrier layer 1810 may be or include an aluminum gallium nitride (InGaN) layer. k Al l Ga 1-k-l N) (where 0≤k≤1, 0≤l≤1 and 0≤k+l≤1). Other materials may be implemented for barrier layer 1810. Barrier layer 1810 may be formed on channel layer 1808 by epitaxially growing barrier layer 1810 using MOCVD, MBE, LPCVD or another epitaxial process.

[0077] At block 1704, a gate layer 1812 is formed over and on the barrier layer 1810. In some examples, the gate layer 1812 is or includes a semiconductor layer of a semiconductor material. Further, in some examples, the gate layer 1812 is doped with a dopant. In some examples, the gate layer 1812 is doped with a p-type dopant. In some examples, the gate layer 1812 may be or include a gallium nitride (GaN) layer, or more generally, an indium aluminum gallium nitride (InAluminum Gallium Nitride (InGaN) layer. m Al n Ga 1-m-nN) (where 0≤m<1, 0≤n<1 and 0≤m+n≤1), and the dopant doped with the gate layer 1812 is a p-type dopant, and the p-type dopant may be or include magnesium (Mg), carbon (C), zinc (Zn), etc. or a combination thereof. In the example where the gate layer 1812 is gallium nitride (GaN) doped with a p-type dopant, the gate layer 1812 may be referred to as a p-type doped GaN (pGaN) layer. In addition, in the example where the gate layer 1812 is gallium nitride (GaN) doped with magnesium, the gate layer 1812 may be referred to as a magnesium-doped gallium nitride (GaN:Mg) layer. In some examples, the concentration of the dopant in the electrically activated gate layer 1812 is equal to or greater than 1×10 17 cm -3 In some examples, the concentration is equal to or greater than 1×10 18 cm -3 In some examples, the dopant in the gate layer 1812 can have a uniform concentration. In some examples, the dopant in the gate layer 1812 can have a gradient concentration. In other examples, other materials, dopants, and / or concentrations can be implemented.

[0078] The gate layer 1812 may be formed by depositing the material of the gate layer 1812 and patterning the material into the gate layer 1812. In some examples, the material of the gate layer 1812 may be deposited by epitaxial growth, such as by MOCVD, MBE, LPCVD, plasma enhanced chemical vapor deposition (PECVD), atomic layer epitaxy, or another epitaxial process. The material in the gate layer 1812 may be in-situ doped during deposition (e.g., epitaxial growth) or after deposition by implantation (e.g., ion implantation). The material of the gate layer 1812 may be patterned into the gate layer 1812 using appropriate photolithography and etching processes. For example, a photoresist is deposited (e.g., by spin coating) on ​​the material of the gate layer 1812, and the photoresist is patterned using photolithography. In the case of a patterned photoresist, an etching process, such as anisotropic etching, such as RIE, etc., is performed using the patterned photoresist as a mask to pattern the gate layer 1812. After the etching process, the photoresist is removed, such as by ashing.

[0079] Fig.18 The example illustrated in also includes a silicon layer 1814 formed above and on the gate layer 1812. In other examples, the silicon layer 1814 may be omitted. In some examples, the silicon layer 1814 is or includes polysilicon. In addition, in some examples, the silicon layer 1814 is doped with a dopant, such as a p-type dopant. The dopant doped with the silicon layer 1814 may be of the same conductivity type (e.g., p-type) as the dopant doped with the gate layer 1812. An example p-type dopant of the silicon layer 1814 includes boron (B) and the like. In some examples, the concentration of the dopant (e.g., p-type dopant) in the silicon layer 1814 may be equal to or greater than 1×10 19 cm-3 , and more particularly, equal to or greater than 1×10 20 cm -3 (For example, 2×10 20 cm -3 In some examples, the concentration of dopants in silicon layer 1814 may be less than 5×10 21 cm -3 In some examples, the concentration of a dopant (e.g., a p-type dopant such as boron (B)) in the silicon layer 1814 is at least two (2) times (e.g., two (2) times to ten (10) times or one hundred (100) times) the concentration of a dopant (e.g., a p-type dopant such as magnesium (Mg), carbon (C), or zinc (Zn)) in the gate layer 1812. In some examples, the silicon layer 1814 forms a Schottky junction with the gate layer 1812 at the interface between the gate layer 1812 and the silicon layer 1814. In other examples, another conductive layer may be included in place of the silicon layer 1814 or together with the silicon layer 1814 (e.g., above and on the silicon layer 1814). Such other conductive layers may be or include refractory metals (e.g., chromium, molybdenum, tantalum, tungsten, titanium, hafnium, or iridium), conductive ceramics (e.g., indium tin oxide (ITO)), or any other front-end-of-line (FEOL) compatible conductive material. Incorporating a silicon layer on the gate layer may enable improved gate depletion, decoupling of parasitic capacitances, and retention of high energy barrier height Schottky junctions during operation of the semiconductor device.

[0080] To form the silicon layer 1814, the silicon material (e.g., polysilicon) of the silicon layer 1814 may be deposited after the material of the gate layer 1812 is deposited, and the silicon may be patterned into the silicon layer 1814 by patterning the gate layer 1812. In some examples, the silicon may be deposited by chemical vapor deposition (CVD) (e.g., PECVD) or another deposition process. The silicon material of the silicon layer 1814 may be in-situ doped by implantation (e.g., ion implantation) during or after deposition. Other processes to form the silicon layer 1814 may be implemented.

[0081] At block 1706, a first dielectric layer 1820 is formed over the semiconductor substrate 1802 (e.g., barrier layer 1810) and gate layer 1812. If included, the first dielectric layer 1820 is also formed over the silicon layer 1814. The first dielectric layer 1820 may be a pre-metal dielectric layer (PMD). In some examples, the first dielectric layer 1820 is or includes silicon nitride (SiN); however, in other examples, the first dielectric layer 1820 may be or include another one or more other dielectric materials. The first dielectric layer 1820 may be deposited using any suitable deposition process (e.g., CVD, LPCVD, PECVD, etc.).

[0082] refer to Fig.17 Box 1708 and Fig.19 , forming a drain metal contact 1902 and a source metal contact 1904 through the first dielectric layer 1820. The drain metal contact 1902 and the source metal contact 1904 can be in the MET0 metal layer. As shown, the drain metal contact 1902 is conformally in the source / drain contact opening and contacts the barrier layer 1810 to electrically couple the drain in the channel layer 1808. Similarly, as shown, the source metal contact 1904 is conformally in the source / drain contact opening and contacts the barrier layer 1810 to electrically couple the source in the channel layer 1808. In other examples, the drain metal contact 1902 and the source metal contact 1904 may extend into the barrier layer 1810 , through the barrier layer 1810 to and / or into the channel layer 1808 , or through the barrier layer 1810 and the channel layer 1808 to and / or into one or more transition layers 1806 .

[0083] Corresponding source / drain contact openings may be formed, the source / drain contact openings reaching and / or entering the barrier layer 1810 through the first dielectric layer 1820, reaching and / or entering the channel layer 1808 through the barrier layer 1810, or reaching and / or entering the one or more transition layers 1806 through the barrier layer 1810 and the channel layer 1808. The source / drain contact openings may be formed using appropriate photolithography and etching processes. One or more metals are deposited into the source / drain contact openings and deposited above and on the upper surface of the first dielectric layer 1820. The one or more metals deposited into the source / drain contact openings form the drain metal contact 1902 and the source metal contact 1904. The one or more metals may be deposited using one or more appropriate deposition processes (e.g., CVD, physical vapor deposition (PVD), etc.). In some examples, the one or more metals may be one or more corresponding conformal layers in the source / drain contact openings that do not fill the source / drain contact openings, and in some examples, the one or more metals may fill the source / drain contact openings. The one or more metals over the upper surface of the first dielectric layer 1820 are patterned into portions of the drain metal contact 1902 and the source metal contact 1904 on the upper surface of the first dielectric layer 1820. The one or more metals may be patterned using appropriate photolithography and etching processes.

[0084] refer to Fig.17 Box 1710 and Fig. 20, a second dielectric layer 2002 is formed over the first dielectric layer 1820, the drain metal contact 1902, and the source metal contact 1904. The second dielectric layer 2002 is conformally over and on the first dielectric layer 1820, the drain metal contact 1902, and the source metal contact 1904. The second dielectric layer 2002 may be an etch stop layer that permits selective etching of one or more layers formed over the second dielectric layer 2002. In some examples, the second dielectric layer 2002 is or includes aluminum oxide (Al2O3). In other examples, the second dielectric layer 2002 may be or include a nitride, such as silicon nitride (SiN) or another one or more other dielectric materials. The second dielectric layer 2002 may be deposited using any suitable deposition process, such as CVD, LPCVD, PECVD, atomic layer deposition (ALD), etc.

[0085] refer to Fig.17 Box 1712 and Fig.21 , forming a gate contact opening 2102 through the second dielectric layer 2002 and the first dielectric layer 1820. In the illustrated example where the silicon layer 1814 is implemented, the gate contact opening 2102 leads to the silicon layer 1814. In other examples, the gate contact opening 2102 can pass through the silicon layer 1814 to the gate layer 1812. In examples where the silicon layer 1814 is not implemented, the gate contact opening 2102 can lead to the gate layer 1812. The gate contact opening 2102 can be formed using appropriate photolithography and etching processes.

[0086] refer to Fig.17 Box 1714 and Fig. 22 , a dielectric material 2202 is deposited on and above the second dielectric layer 2002 and in the gate contact opening 2102. The dielectric material 2202 will be patterned and configured to have an inclined surface, as described later. In some examples, the dielectric material 2202 is or includes silicon nitride (SiN); but in other examples, the dielectric material 2202 may be or include another one or more other dielectric materials. The dielectric material 2202 may be deposited using any suitable deposition process (e.g., CVD, LPCVD, PECVD, ALD, etc.).

[0087] At block 1716, a photoresist 2204 having an inclined surface 2206 is formed using grayscale lithography. The photoresist 2204 may be formed as described above (including with respect to Fig.10 , 15 1 and 16). The photoresist 2204 can be formed by depositing (e.g., by spin coating) a photoresist layer over and on the dielectric material 2202 and patterning the photoresist layer into the photoresist 2204 using grayscale lithography. In the illustrated example, the inclined surface 2206 has a uniform slope throughout the inclined surface 2206.

[0088] refer to Fig.17 Box 1718 and Fig.23 , using the photoresist 2204 as a mask to etch the dielectric material 2202 to form a dielectric structure 2302 having an inclined surface 2304. Fig.11 The dielectric material 2202 is etched as described. The etching transfers the slope from the photoresist 2204 to the dielectric material 2202 to form a dielectric structure 2302 having an inclined surface 2304. The inclined surface 2304 has a uniform slope throughout the inclined surface 2304. The angle of the inclined surface 2304 may correspond to Fig.10 and 11 The angle of the inclined surface 2206 is described.

[0089] The etching process may include multiple sub-processes. For example, the first sub-process may be an anisotropic etch that etches the dielectric material 2202 without significantly consuming the photoresist. After the first sub-process, the second sub-process may be as described above. Fig.11 Thus, for example, the first sub-process may remove dielectric material 2202 from gate contact opening 2102, while the second sub-process patterns dielectric structure 2302 having inclined surface 2304. In other examples, photoresist 2204 may be patterned (e.g., with sufficient thickness and / or lateral dimensions) such that, as described with respect to Fig.11 The described etching process may overetch the dielectric material 2202 (overetch relative to the level of the second dielectric layer 2002 ) to remove the dielectric material 2202 from the gate contact opening 2102 while permitting the dielectric structure 2302 to remain.

[0090] Reference box 1720 and Fig.24, forming a gate metal contact 2402 and a first field plate portion 2404. As depicted, the gate metal contact 2402 is conformally in the gate contact opening 2102 and contacts the silicon layer 1814 and / or the gate layer 1812 (e.g., depending on the presence of the gate contact opening 2102 and / or the silicon layer 1814 as described above). The first field plate portion 2404 is above and on the inclined surface 2304 of the dielectric structure 2302. In the illustrated example, the gate metal contact 2402 and the first field plate portion 2404 are in the same metal layer (e.g., a METBGT layer). The gate metal contact 2402 and the first field plate portion 2404 are formed by a continuous metal portion that electrically couples the gate metal contact 2402 and the first field plate portion 2404. In other examples, the gate metal contact 2402 and the first field plate portion 2404 may be separate metal portions. In such examples, the gate metal contact 2402 and the first field plate portion 2404 can be electrically coupled through another metal layer, such as through stacked metal vias and / or routing metal outside the active area. The gate metal contact 2402 can include or be any suitable metal. In some semiconductor devices, the gate metal contact can form a Schottky junction with the gate layer, or can form an ohmic junction with the gate layer. As an example, when the gate layer is magnesium-doped gallium nitride (GaN:Mg), the metal that can form a Schottky junction with the gate layer can be or include titanium (Ti), titanium tungsten (TiW), titanium nitride (TiN), nickel (Ni), platinum (Pt), tantalum nitride (TaN), copper (Cu), tungsten (W), or an alloy thereof. As an example, when the gate layer is magnesium-doped gallium nitride (GaN:Mg), the metal that can form an ohmic junction with the gate layer can be or include gold (Au), aluminum (Al), or an alloy thereof. Examples of such alloys can include titanium tungsten aluminum (TiWAl) and titanium aluminum nitride (TiAlN).

[0091] One or more metals are deposited into the gate contact opening 2102 and over and on the second dielectric layer 2002 and the dielectric structure 2302. The one or more metals deposited into the gate contact opening 2102 form the gate metal contact 2402, and the one or more metals deposited on the inclined surface 2304 form the first field plate portion 2404. The one or more metals may be deposited using one or more appropriate deposition processes (e.g., CVD, PVD, etc.). In some examples, the one or more metals may be, for example, one or more corresponding conformal layers in the gate contact opening 2102 that do not fill the gate contact opening 2102, and in some examples, the one or more metals may fill the gate contact opening 2102. The one or more metals over the second dielectric layer 2002 and the dielectric structure 2302 are patterned into the gate metal contact 2402 and the first field plate portion 2404. The one or more metals may be patterned using appropriate photolithography and etching processes.

[0092] Reference box 1722 and Fig.25, a third dielectric layer 2502 is formed over and on the second dielectric layer 2002, the gate metal contact 2402, and the first field plate portion 2404. The third dielectric layer 2502 may be an interlayer dielectric layer (ILD). In some examples, the third dielectric layer 2502 is or includes silicon nitride (SiN); however, in other examples, the third dielectric layer 2502 may be or include another one or more other dielectric materials. The third dielectric layer 2502 may be deposited using any suitable deposition process (e.g., CVD, LPCVD, PECVD, etc.). The third dielectric layer 2502 may be planarized, for example, by chemical mechanical polishing (CMP).

[0093] At block 1724, a fourth dielectric layer 2504 is formed over and on the third dielectric layer 2502. The fourth dielectric layer 2504 may be an etch stop layer that permits selective etching of one or more layers formed over the fourth dielectric layer 2504. In some examples, the fourth dielectric layer 2504 is or includes aluminum oxide (Al2O3). In other examples, the fourth dielectric layer 2504 may be or include a nitride, such as silicon nitride (SiN), or another one or more other dielectric materials. The fourth dielectric layer 2504 may be deposited using any suitable deposition process, such as CVD, LPCVD, PECVD, ALD, etc.

[0094] At block 1726, dielectric material 2506 is deposited on and over fourth dielectric layer 2504. Dielectric material 2506 will be patterned and configured to have an inclined surface, as described subsequently. In some examples, dielectric material 2506 is or includes silicon nitride (SiN); however, in other examples, dielectric material 2506 may be or include another one or more other dielectric materials. Dielectric material 2506 may be deposited using any suitable deposition process, such as CVD, LPCVD, PECVD, etc.

[0095] At block 1728, a photoresist 2508 having an inclined surface 2510 is formed using grayscale lithography. The photoresist 2508 may be formed as described above (including with respect to Fig.10 , 15 1 and 16). Photoresist 2508 can be formed by depositing (e.g., by spin coating) a photoresist layer over and on dielectric material 2506 and patterning the photoresist layer into photoresist 2508 using grayscale lithography. In the illustrated example, inclined surface 2510 has a uniform slope throughout inclined surface 2510.

[0096] refer to Fig.17 Box 1730 and Fig.26 , using photoresist 2508 as a mask to etch dielectric material 2506 to form dielectric structure 2602 having inclined surface 2604. Fig.11The dielectric material 2506 is etched as described. The etching transfers the slope from the photoresist 2508 to the dielectric material 2506 to form a dielectric structure 2602 having an inclined surface 2604. The inclined surface 2604 has a uniform slope throughout the inclined surface 2604. The angle of the inclined surface 2604 may correspond to Fig.10 and 11 Angle of inclined surface 2510 is described. The angle of inclined surface 2604 can be less than, equal to, or greater than the angle of inclined surface 2304.

[0097] refer to Fig.17 Box 1732 and Fig. 27 , forming via openings 2702, 2704, 2706. A via opening 2702 is formed through the fourth dielectric layer 2504, the third dielectric layer 2502, and the second dielectric layer 2002 to reach the drain metal contact 1902. A via opening 2704 is formed through the fourth dielectric layer 2504, the third dielectric layer 2502, and the second dielectric layer 2002 to reach the source metal contact 1904. A via opening 2706 is formed through the fourth dielectric layer 2504 and the third dielectric layer 2502 to reach the first field plate portion 2404. The via openings 2702, 2704, 2706 may be formed using appropriate photolithography and etching processes.

[0098] refer to Fig.17 Box 1734 and Fig.28 , forming metal vias 2802, 2804, 2806, metal lines 2812, 2814, and a second field plate portion 2816. Metal via 2802 is in the via opening 2702 and contacts the drain metal contact 1902. Metal line 2812 is above and on the fourth dielectric layer 2504 and the metal via 2802, and metal via 2802 extends from metal line 2812 into the via opening 2702. Metal via 2804 is in the via opening 2704 and contacts the source metal contact 1904. Metal line 2814 is above and on the fourth dielectric layer 2504 and the metal via 2804, and metal via 2804 extends from metal line 2814 into the via opening 2704. Metal via 2806 is in the via opening 2706 and contacts the first field plate portion 2404. The second field plate portion 2816 is above and on the sloped surface 2604 of the dielectric structure 2602, the fourth dielectric layer 2504, and the metal via 2806, and the metal via 2806 extends from the second field plate portion 2816 into the via opening 2706. Thus, the second field plate portion 2816 is electrically coupled to the first field plate portion 2404. In the illustrated example, the metal lines 2812, 2814, and the second field plate portion 2816 are in the same metal layer (e.g., MET1 layer).

[0099] The metal vias 2802, 2804, 2806 may each include: (i) one or more metal barriers and / or adhesion layers (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc., or a combination thereof) conformal in the respective via openings; and (ii) a fill metal (e.g., aluminum (Al), copper (Cu), tungsten (W), etc., or a combination thereof) over and / or on the one or more metal barriers and / or adhesion layers. The metal lines 2812, 2814, and the second field plate portion 2816 may each include one or more metal barriers and / or adhesion layers (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc., or a combination thereof) and a bulk metal (e.g., aluminum (Al), copper (Cu), etc., or a combination thereof) over and / or on the one or more metal barriers and / or adhesion layers. One or more metals are deposited in the via openings 2702, 2704, 2706 and over and on the fourth dielectric layer 2504 and the dielectric structure 2602. The one or more metals may be deposited using one or more suitable deposition processes, such as CVD, PVD, etc. The one or more metals are patterned over the fourth dielectric layer 2504 and the dielectric structure 2602 into the metal lines 2812, 2814, and the second field plate portion 2816. The one or more metals may be patterned using suitable photolithography and etching processes.

[0100] Metal vias, metal lines, and, where appropriate, field plate portions formed in the MET1 layer or subsequently formed metal layers (e.g., MET2 layer, MET3 layer, etc.) may be formed as described above to form metal vias 2802, 2804, metal lines 2812, 2814, and second field plate portion 2816. The same or similar metal or metals may be used in the MET1 layer and subsequent metal layers. Any differences in processing will be readily understood from the drawings and descriptions herein.

[0101] At block 1736, a fifth dielectric layer 2822 is formed over and on the fourth dielectric layer 2504, the metal lines 2812, 2814, the second field plate portion 2816, and the dielectric structure 2602. The fifth dielectric layer 2822 may be an ILD. In some examples, the fifth dielectric layer 2822 is or includes silicon nitride (SiN); however, in other examples, the fifth dielectric layer 2822 may be or include another one or more other dielectric materials. The fifth dielectric layer 2822 may be deposited using any suitable deposition process, such as CVD, LPCVD, PECVD, etc. The fifth dielectric layer 2822 may be planarized, for example, by CMP.

[0102] Reference box 1738 and Fig.29, forming metal vias 2902, 2904 and metal lines 2912, 2914. Metal vias 2902, 2904 are in respective via openings through fifth dielectric layer 2822. Metal via 2902 contacts metal line 2812. Metal line 2912 is above and on fifth dielectric layer 2822 and metal via 2902, and metal via 2902 extends from metal line 2912 into respective via openings. Metal via 2904 contacts metal line 2814. Metal line 2914 is above and on fifth dielectric layer 2822 and metal via 2904, and metal via 2904 extends from metal line 2914 into respective via openings. In the illustrated example, metal lines 2912, 2914 are in the same metal layer (e.g., MET2 layer).

[0103] At block 1740, a sixth dielectric layer 2922 is formed over and on the fifth dielectric layer 2822 and the metal lines 2912, 2914. The sixth dielectric layer 2922 may be an ILD. In some examples, the sixth dielectric layer 2922 is or includes a silicon oxide-based material (e.g., phosphosilicate glass (PSG) or tetraethyl orthosilicate (TEOS) oxide) or silicon nitride (SiN); but in other examples, the sixth dielectric layer 2922 may be or include another one or more other dielectric materials. The sixth dielectric layer 2922 may be deposited using any suitable deposition process (e.g., CVD, LPCVD, PECVD, etc.). The sixth dielectric layer 2922 may be planarized, for example, by CMP.

[0104] Fig.29A cross-sectional view of a semiconductor device 2900 is depicted. The semiconductor device 2900 includes a source S, a channel C, a drain D, and a gate G. The gate G is or includes a gate layer 1812, which is on an upper surface of a semiconductor substrate 1802 (e.g., an upper surface of a barrier layer 1810). The channel C is in a channel layer 1808 in the semiconductor substrate 1802 and below the gate G. The channel C is laterally between the drain D and the source S, which are also in the channel layer 1808. The drain metal contact 1902 is electrically coupled to the drain D, and the source metal contact 1904 is electrically coupled to the source S. The gate metal contact 2402 is electrically coupled to the gate G (e.g., the gate layer 1812). The gate G and the gate metal contact 2402 are laterally between the drain metal contact 1902 and the source metal contact 1904. The semiconductor device 2900 includes a field plate including a first field plate portion 2404 and a second field plate portion 2816 coupled together by a metal via 2806. The field plate extends from the drain side of the gate G toward the drain metal contact 1902. The field plate portions 2404, 2816 each have a respective uniform slope relative to the upper surface of the semiconductor substrate 1802, as depicted by respective slope angles α1, α2 relative to respective planes parallel to the upper surface of the semiconductor substrate 1802. In some examples, the slope of the first field plate portion 2404 may be less than the slope of the second field plate portion 2816 (e.g., such that α1<α2). In some examples, the slope of the first field plate portion 2404 may be greater than the slope of the second field plate portion 2816 (e.g., such that α1>α2). The first field plate portion 2404 abuts the gate metal contact 2402 (eg, as a continuous metal pattern), and thus, the field plate is electrically coupled to the gate G (eg, is a gate-coupled field plate).

[0105] Fig. 30A and 30B Flowcharts of methods 3000A, 3000B of fabricating a semiconductor device (eg, HEMT) according to some examples. Fig. 30A and 30B Methods 3000A and 3000B are as follows: Figures 31 to 34 Draw and Figures 31 to 34 Described in the context of Figures 31 to 34 A cross-sectional view of a semiconductor device at various stages of fabrication is shown. Methods 3000A, 3000B include processing of blocks 1702 to 1734, as described above with respect to Figures 18 to 28 described.

[0106] refer to Fig. 30B Box 3002 and Fig.31, after forming metal vias 2802, 2804, 2806, metal lines 2812, 2814, and second field plate portion 2816, dielectric material 3102 is deposited on and above fourth dielectric layer 2504, dielectric structure 2602, metal lines 2812, 2814, and second field plate portion 2816. Dielectric material 3102 will be patterned and configured to have an inclined surface for subsequent description. In some examples, dielectric material 3102 is or includes silicon nitride (SiN); however, in other examples, dielectric material 3102 may be or include another or more other dielectric materials. Dielectric material 3102 may be deposited using any suitable deposition process (e.g., CVD, LPCVD, PECVD, etc.).

[0107] At block 3004, a photoresist 3104 having an inclined surface 3106 is formed using grayscale lithography. The photoresist 3104 may be formed as described above (including with respect to Fig.10 , 15 1 and 16). Photoresist 3104 can be formed by depositing (e.g., by spin coating) a photoresist layer over and on dielectric material 3102 and patterning the photoresist layer into photoresist 3104 using grayscale lithography. In the illustrated example, inclined surface 3106 has a uniform slope throughout inclined surface 3106.

[0108] refer to Fig. 30B Box 3006 and Fig.32 , the dielectric material 3102 is etched using the photoresist 3104 as a mask to form a fifth dielectric layer 3202 and a dielectric structure 3204 having an inclined surface 3206. Fig.11 The dielectric material 3102 is described as being etched. The etching transfers the slope from the photoresist 3104 to the dielectric material 3102 to form a dielectric structure 3204 having an inclined surface 3206, and the dielectric material 3102 is thinned to form a fifth dielectric layer 3202. Thus, in the illustrated example, the fifth dielectric layer 3202 and the dielectric structure 3204 are a single dielectric component. The dielectric material 3102 is thinned to form the fifth dielectric layer 3202 to expose an upper portion of the second field plate portion 2816. The inclined surface 3206 has a uniform slope throughout the inclined surface 3206. The angle of the inclined surface 3206 may correspond to, for example, Fig.10 and 11 Angle of inclined surface 3106 described. The angle of inclined surface 3206 can be less than, equal to, or greater than each of the angle of inclined surface 2304 and the angle of inclined surface 2604.

[0109] refer to Fig. 30B Box 3008 and Fig.33, forming via openings 3302, 3304 through the fifth dielectric layer 3202. Forming a via opening 3302 through the fifth dielectric layer 3202 to reach the metal line 2812. Forming a via opening 3304 through the fifth dielectric layer 3202 to reach the metal line 2814. The via openings 3302, 3304 may be formed using appropriate photolithography and etching processes.

[0110] refer to Fig. 30B Box 3010 and Fig.34 , forming metal vias 3402, 3404, metal lines 3412, 3414, and a third field plate portion 3416. Metal via 3402 is in the via opening 3302 and contacts metal line 2812. Metal line 3412 is above and on the fifth dielectric layer 3202 and metal via 3402, and metal via 3402 extends from metal line 3412 into the via opening 3302. Metal via 3404 is in the via opening 3304 and contacts metal line 2814. Metal line 3414 is above and on the fifth dielectric layer 3202 and metal via 3404, and metal via 3404 extends from metal line 3414 into the via opening 3304. Third field plate portion 3416 is above and on the inclined surface 3206 of dielectric structure 3204 and the fifth dielectric layer 3202. As depicted, the third field plate portion 3416 is separated from the exposed portion of the second field plate portion 2816 by a gap. In such examples, the field plate portions 2816, 3416 can be electrically coupled through another metal layer to form corresponding portions of the field plate, or can be electrically isolated from each other to form separate field plates. In some examples, if separated, the third field plate portion 3416 can be coupled to the source S (e.g., a source-coupled field plate). In some examples, the third field plate portion 3416 can be formed on and above the exposed portion of the second field plate portion 2816, which electrically couples the field plate portions 2816, 3416. In the illustrated example, the metal lines 3412, 3414 and the third field plate portion 3416 are in the same metal layer (e.g., MET2 layer).

[0111] At block 3012, a sixth dielectric layer 3422 is formed over and on the fifth dielectric layer 3202, the dielectric structure 3204, the metal lines 3412, 3414, and the third field plate portion 3416. The sixth dielectric layer 3422 may be an ILD. In some examples, the sixth dielectric layer 3422 is or includes silicon nitride (SiN); however, in other examples, the sixth dielectric layer 3422 may be or include another one or more other dielectric materials. The sixth dielectric layer 3422 may be deposited using any suitable deposition process, such as CVD, LPCVD, PECVD, etc. The sixth dielectric layer 3422 may be planarized, for example, by CMP.

[0112] Fig.34A cross-sectional view of a fabricated semiconductor device 3400 is depicted. The semiconductor device 3400 includes a source S, a channel C, a drain D, and a gate G. The gate G is or includes a gate layer 1812, which is on an upper surface of a semiconductor substrate 1802 (e.g., an upper surface of a barrier layer 1810). The channel C is in a channel layer 1808 in the semiconductor substrate 1802 and below the gate G. The channel C is laterally between the drain D and the source S, which are also in the channel layer 1808. The drain metal contact 1902 is electrically coupled to the drain D, and the source metal contact 1904 is electrically coupled to the source S. The gate metal contact 2402 is electrically coupled to the gate G (e.g., the gate layer 1812). The gate G and the gate metal contact 2402 are laterally between the drain metal contact 1902 and the source metal contact 1904. The semiconductor device 3400 includes a first field plate and a second field plate. The first field plate includes a first field plate portion 2404 and a second field plate portion 2816 coupled together by a metal via 2806. The second field plate includes a third field plate portion 3416. The first field plate extends from the drain side of the gate G toward the drain metal contact 1902. The field plate portions 2404, 2816, 3416 each have a respective uniform slope relative to the upper surface of the semiconductor substrate 1802, as depicted by respective oblique angles α1, α2, α3 relative to respective planes parallel to the upper surface of the semiconductor substrate 1802. The slopes of the field plate portions 2404, 2816 may be as described above with respect to Fig.29 As described. In some examples, the slope of the third field plate portion 3416 can be greater than either or both of the slopes of the first field plate portion 2404 and the second field plate portion 2816. In some examples, the slope of the third field plate portion 3416 can be less than either or both of the slopes of the first field plate portion 2404 and the second field plate portion 2816. The first field plate portion 2404 abuts the gate metal contact 2402 (e.g., as a continuous metal pattern), and therefore, the field plate is electrically coupled to the gate G (e.g., is a gate-coupled field plate). In some examples, the second field plate (e.g., the third field plate portion 3416) can be electrically coupled to the source S, such as by routing in one or more metal layers, and the second field plate can be a source-coupled field plate.

[0113] In some examples, the third field plate portion 3416 can be electrically coupled to the field plate portions 2404, 2816 to become another portion of the first field plate. For example, instead of having a gap between an upper portion of the second field plate portion 2816 protruding through the fifth dielectric layer 3202 and a lower portion of the third field plate portion 3416 on the fifth dielectric layer 3202, the lower portion of the third field plate portion 3416 can overlap and abut an upper portion of the second field plate portion 2816. In other examples, routing in one or more metal layers can electrically couple the third field plate portion 3416 to the field plate portions 2404, 2816 with a gap between the field plate portions 2816, 3416.

[0114] Fig.35A and 35B Flowcharts of methods 3500A, 3500B of fabricating a semiconductor device (eg, a HEMT) according to some examples. Fig.35A and 35B Methods 3500A and 3500B are as follows: Figures 36 to 42 Draw and Figures 36 to 42 Described in the context of Figures 36 to 42 A cross-sectional view of a semiconductor device at various stages of fabrication is shown. Methods 3500A, 3500B include processing of blocks 1702 to 1712, 1720 to 1730, as described above with respect to Figures 18 to 26 However, forming the dielectric structure 2302 and the first field plate portion 2404 and associated processing are omitted (eg, wherein the first field plate portion is omitted from block 1720). Fig.36 The resulting structure without the dielectric structure 2302 and the first field plate portion 2404 is shown in FIG.

[0115] refer to Fig.35A Box 3502 and Fig.37 , forming via openings 3702, 3704. A via opening 3702 is formed through the fourth dielectric layer 2504, the third dielectric layer 2502, and the second dielectric layer 2002 to reach the drain metal contact 1902. A via opening 3704 is formed through the fourth dielectric layer 2504, the third dielectric layer 2502, and the second dielectric layer 2002 to reach the source metal contact 1904. The via openings 3702, 3704 may be formed using appropriate photolithography and etching processes.

[0116] refer to Fig.35A Box 3504 and Fig.38, forming metal vias 3802, 3804, metal lines 3812, 3814, and a first field plate portion 3816. Metal via 3802 is in the via opening 3702 and contacts the drain metal contact 1902. Metal line 3812 is above and on the fourth dielectric layer 2504 and the metal via 3802, and the metal via 3802 extends from the metal line 3812 into the via opening 3702. Metal via 3804 is in the via opening 3704 and contacts the source metal contact 1904. Metal line 3814 is above and on the fourth dielectric layer 2504 and the metal via 3804, and the metal via 3804 extends from the metal line 3814 into the via opening 3704. A third field plate portion 3816 is above and on the inclined surface 2604 of the dielectric structure 2602 and the fourth dielectric layer 2504. As depicted, metal line 3814 and first field plate portion 3816 are formed of a continuous metal portion that electrically couples metal line 3814 and first field plate portion 3816. Thus, first field plate portion 3816 is electrically coupled to a source of a semiconductor device (e.g., a HEMT). In the illustrated example, metal lines 3812, 3814, and first field plate portion 3816 are in the same metal layer (e.g., MET1 layer).

[0117] refer to Fig.35B Box 3506 and Fig.39 , a fifth dielectric layer 3902 is formed above and on the fourth dielectric layer 2504, the dielectric structure 2602, the metal lines 3812, 3814, and the first field plate portion 3816. The fifth dielectric layer 3902 may be an ILD. In some examples, the fifth dielectric layer 3902 is or includes silicon nitride (SiN); but in other examples, the fifth dielectric layer 3902 may be or include another or more other dielectric materials. The fifth dielectric layer 3902 may be deposited using any suitable deposition process (e.g., CVD, LPCVD, PECVD, etc.). The fifth dielectric layer 3902 may be planarized, for example, by an etch-back process. The etch-back process exposes an upper portion of the first field plate portion 3816.

[0118] At block 3508, a sixth dielectric layer 3904 is formed over and on the exposed portion of the fifth dielectric layer 3902 and the second field plate portion 2816. The sixth dielectric layer 3904 may be an etch stop layer that permits selective etching of one or more layers formed over the sixth dielectric layer 3904. In some examples, the sixth dielectric layer 3904 is or includes aluminum oxide (Al2O3). In other examples, the sixth dielectric layer 3904 may be or include a nitride, such as silicon nitride (SiN), or another one or more other dielectric materials. The sixth dielectric layer 3904 may be deposited using any suitable deposition process, such as CVD, LPCVD, PECVD, ALD, etc.

[0119] At block 3510, dielectric material 3906 is deposited on and over sixth dielectric layer 3904. Dielectric material 3906 will be patterned and configured to have an inclined surface, as described subsequently. In some examples, dielectric material 3906 is or includes silicon nitride (SiN); however, in other examples, dielectric material 3906 may be or include another one or more other dielectric materials. Dielectric material 3906 may be deposited using any suitable deposition process, such as CVD, LPCVD, PECVD, etc.

[0120] At block 3512, a photoresist 3908 having an inclined surface 3910 is formed using grayscale lithography. The photoresist 3908 may be formed as described above (including with respect to Fig.10 , 15 1 and 16). Photoresist 3908 can be formed by depositing (e.g., by spin coating) a photoresist layer over and on dielectric material 3102 and patterning the photoresist layer into photoresist 3908 using grayscale lithography. In the illustrated example, inclined surface 3910 has a uniform slope throughout inclined surface 3910.

[0121] refer to Fig.35B Box 3514 and Fig.40 , using photoresist 3908 as a mask to etch dielectric material 3906 to form dielectric structure 4002 having inclined surface 4004. Fig.11 The dielectric material 3906 is etched as described. The etching transfers the slope from the photoresist 3908 to the dielectric material 3906 to form a dielectric structure 4002 having an inclined surface 4004. The inclined surface 4004 has a uniform slope throughout the inclined surface 4004. The angle of the inclined surface 4004 may correspond to Fig.10 and 11 Angle of inclined surface 3910 is described. The angle of inclined surface 4004 can be less than, equal to, or greater than the angle of inclined surface 2604.

[0122] refer to Fig.35B Box 3516 and Fig.41 , forming via openings 4102, 4104, 4106 through the sixth dielectric layer 3904 and / or the fifth dielectric layer 3902. Forming a via opening 4102 through the sixth dielectric layer 3904 and the fifth dielectric layer 3902 to reach the metal line 3812. Forming a via opening 4104 through the sixth dielectric layer 3904 and the fifth dielectric layer 3902 to reach the metal line 3814. Forming a via opening 4106 through the sixth dielectric layer 3904 to reach the upper portion of the first field plate portion 3816 exposed by the fifth dielectric layer 3902. The via openings 4102, 4104, 4106 may be formed using appropriate photolithography and etching processes.

[0123] refer to Fig.35B Box 3518 and Fig.42 , forming metal vias 4202, 4204, metal lines 4212, 4214, and a second field plate portion 4216. Metal via 4202 is in via opening 4102 and contacts metal line 3812. Metal line 4212 is above and on the sixth dielectric layer 3904 and metal via 4202, and metal via 4202 extends from metal line 4212 into via opening 4102. Metal via 4204 is in via opening 4104 and contacts metal line 3814. Metal line 4214 is above and on the sixth dielectric layer 3904 and metal via 4204, and metal via 4204 extends from metal line 4214 into via opening 4104. Second field plate portion 4216 is above and on the inclined surface 4004 of dielectric structure 4002 and the sixth dielectric layer 3904, and in via opening 4106. As depicted, the second field plate portion 4216 is on the first field plate portion 3816 by being disposed in the via opening 4106. In such examples, the field plate portions 3816, 4216 are electrically coupled to each other. In other examples, the second field plate portion 4216 can be electrically isolated or electrically coupled (through another metal layer) to the first field plate portion 3816. In the illustrated example, the metal lines 4212, 4214, and the second field plate portion 4216 are in the same metal layer (e.g., MET2 layer).

[0124] At block 3520, a seventh dielectric layer 4222 is formed over and on the sixth dielectric layer 3904, the dielectric structure 4002, the metal lines 4212, 4214, and the second field plate portion 4216. The seventh dielectric layer 4222 may be an ILD. In some examples, the seventh dielectric layer 4222 is or includes a silicon oxide-based material (e.g., PSG or TEOS oxide) or silicon nitride (SiN); but in other examples, the seventh dielectric layer 4222 may be or include another one or more other dielectric materials. The seventh dielectric layer 4222 may be deposited using any suitable deposition process (e.g., CVD, LPCVD, PECVD, etc.). The seventh dielectric layer 4222 may be planarized, for example, by CMP.

[0125] Fig.42A cross-sectional view of a fabricated semiconductor device 4200 is depicted. The semiconductor device 4200 includes a source S, a channel C, a drain D, and a gate G. The gate G is or includes a gate layer 1812, which is on an upper surface of a semiconductor substrate 1802 (e.g., an upper surface of a barrier layer 1810). The channel C is in a channel layer 1808 in the semiconductor substrate 1802 and below the gate G. The channel C is laterally between the drain D and the source S, which are also in the channel layer 1808. The drain metal contact 1902 is electrically coupled to the drain D, and the source metal contact 1904 is electrically coupled to the source S. The gate metal contact 2402 is electrically coupled to the gate G (e.g., the gate layer 1812). The gate G and the gate metal contact 2402 are laterally between the drain metal contact 1902 and the source metal contact 1904. The semiconductor device 4200 includes a field plate including a first field plate portion 3816 and a second field plate portion 4216 coupled together by a second field plate portion 4216 overlapping and contacting the first field plate portion 3816. The field plate extends from the drain side of the gate G toward the drain metal contact 1902. The field plate portions 3816, 4216 each have a respective uniform slope relative to the upper surface of the semiconductor substrate 1802, as depicted by respective oblique angles α1, α2 relative to respective planes parallel to the upper surface of the semiconductor substrate 1802. In some examples, the slope of the first field plate portion 3816 may be less than the slope of the second field plate portion 4216 (e.g., such that α1<α2). In some examples, the slope of the first field plate portion 3816 may be greater than the slope of the second field plate portion 4216 (e.g., such that α1>α2). The field plate is electrically coupled to the source S through the metal line 3814 , the metal via 3804 , and the source metal contact 1904 (eg, a source-coupled field plate).

[0126] Fig.43A and 43B 4300A, 4300B are flow charts of methods 4300A, 4300B of manufacturing a semiconductor device (eg, HEMT) according to some examples. Fig.43A and 43B Methods 4300A and 4300B are as follows: Figures 44 to 49 Draw and Figures 44 to 49 Described in the context of Figures 44 to 49 A cross-sectional view of a semiconductor device at various stages of fabrication is shown. Methods 4300A, 4300B include processing of blocks 1702 to 1712, 1720 to 1726, as described above with respect to Figures 18 to 24 Described, and formed Fig.25 2504 and dielectric material 2506. However, forming dielectric structure 2302 and first field plate portion 2404 and associated processing are omitted. Fig.44The resulting structure without the dielectric structure 2302 and the first field plate portion 2404 is shown in FIG.

[0127] refer to Fig.43A Box 4302 and Fig.44 , using grayscale lithography to form a photoresist 4402 having a first inclined surface 4404 and a second inclined surface 4406. The photoresist 4402 may be formed as described above (including Fig.13 , 15 16). The photoresist 4402 can be formed by depositing (e.g., by spin coating) a photoresist layer over and on the dielectric material 2506 and patterning the photoresist layer into the photoresist 4402 using grayscale lithography. In the illustrated example, each inclined surface 4404, 4406 has a respective uniform slope throughout the respective inclined surface 4404, 4406. The respective angles formed by the inclined surfaces 4404, 4406 are different. The transition surface can be between the inclined surfaces 4404, 4406, as described above with respect to Fig.13 described.

[0128] refer to Fig.43A Box 4304 and Fig.45 , the dielectric material 2506 is etched using the photoresist 4402 as a mask to form a dielectric structure 4502 having a first inclined surface 4504 and a second inclined surface 4506. Fig.11 and 14 The dielectric material 2506 is etched as described. The etching transfers the slope from the photoresist 4402 to the dielectric material 2506 to form a dielectric structure 4502 having inclined surfaces 4504, 4506. Each inclined surface 4504, 4506 has a uniform slope throughout the respective inclined surface 4504, 4506. The angle of the inclined surface 4504 may correspond to Fig.13 and 14 The angle of the inclined surface 4404 described above and the angle of the inclined surface 4506 may correspond to the angle of the inclined surface 4404 described above. Fig.13 and 14 The angle of inclined surface 4406 is described.

[0129] refer to Fig.43A Box 4306 and Fig.46 , forming via openings 4602, 4604. A via opening 4602 is formed through the fourth dielectric layer 2504, the third dielectric layer 2502, and the second dielectric layer 2002 to reach the drain metal contact 1902. A via opening 4604 is formed through the fourth dielectric layer 2504, the third dielectric layer 2502, and the second dielectric layer 2002 to reach the source metal contact 1904. The via openings 4602, 4604 may be formed using appropriate photolithography and etching processes.

[0130] refer to Fig.43A Box 4308 and Fig.47 , forming metal vias 4702, 4704, metal lines 4712, 4714, and a field plate including a first field plate portion 4716 and a second field plate portion 4718. Metal via 4702 is in via opening 4602 and contacts drain metal contact 1902. Metal line 4712 is above and on fourth dielectric layer 2504 and metal via 4702, and metal via 4702 extends from metal line 4712 into via opening 4602. Metal via 4704 is in via opening 4604 and contacts source metal contact 1904. Metal line 4714 is above and on fourth dielectric layer 2504 and metal via 4704, and metal via 4704 extends from metal line 4714 into via opening 4604. The first field plate portion 4716 is above and on the first slanted surface 4504 of the dielectric structure 4502 and the fourth dielectric layer 2504, and the second field plate portion 4718 is above and on the second slanted surface 4506 of the dielectric structure 4502. As depicted, the metal line 4714 and the field plate (including the first field plate portion 4716 and the second field plate portion 4718) are formed by a continuous metal portion that electrically couples the metal line 4714 and the field plate (including the first field plate portion 4716 and the second field plate portion 4718). Thus, the field plate is electrically coupled to the source of the semiconductor device (e.g., HEMT). In the illustrated example, the metal lines 4712, 4714, and the field plates are in the same metal layer (e.g., MET1 layer).

[0131] exist Fig.43B At block 4310 of the present invention, a fifth dielectric layer 4722 is conformally formed over and on the fourth dielectric layer 2504, the dielectric structure 4502, the metal lines 4712, 4714, and the field plate including the field plate portions 4716, 4718. The fifth dielectric layer 4722 may be an ILD. In some examples, the fifth dielectric layer 4722 is or includes silicon nitride (SiN); however, in other examples, the fifth dielectric layer 4722 may be or include another one or more other dielectric materials. The fifth dielectric layer 4722 may be deposited using any suitable deposition process, such as CVD, LPCVD, PECVD, etc.

[0132] refer to Fig.43B Box 4312 and Fig.48 , forming via openings 4802, 4804 through the fifth dielectric layer 4722. Forming a via opening 4802 through the fifth dielectric layer 4722 to reach the metal line 4712. Forming a via opening 4804 through the fifth dielectric layer 4722 to reach the metal line 4714. The via openings 4802, 4804 may be formed using appropriate photolithography and etching processes.

[0133] refer to Fig.43B Box 4314 and Fig.49 , forming metal vias 4902, 4904 and metal lines 4912, 4914. Metal via 4902 is in via opening 4802 and contacts metal line 4712. Metal line 4912 is above and on fifth dielectric layer 4722 and metal via 4902, and metal via 4902 extends from metal line 4912 into via opening 4802. Metal via 4904 is in via opening 4804 and contacts metal line 4714. Metal line 4914 is above and on fifth dielectric layer 4722 and metal via 4904, and metal via 4904 extends from metal line 4914 into via opening 4804. In the illustrated example, metal lines 4912, 4914 are in the same metal layer (e.g., MET2 layer).

[0134] At block 4316, a sixth dielectric layer 4922 is formed over and on the fifth dielectric layer 4722 and the metal lines 4912, 4914. The sixth dielectric layer 4922 may be an ILD. In some examples, the sixth dielectric layer 4922 is or includes a silicon oxide-based material (e.g., PSG or TEOS oxide) or silicon nitride (SiN); but in other examples, the sixth dielectric layer 4922 may be or include another one or more other dielectric materials. The sixth dielectric layer 4922 may be deposited using any suitable deposition process (e.g., CVD, LPCVD, PECVD, etc.). The sixth dielectric layer 4922 may be planarized, for example, by CMP.

[0135] Fig.49A cross-sectional view of a fabricated semiconductor device 4900 is depicted. The semiconductor device 4900 includes a source S, a channel C, a drain D, and a gate G. The gate G is or includes a gate layer 1812, which is on an upper surface of a semiconductor substrate 1802 (e.g., an upper surface of a barrier layer 1810). The channel C is in a channel layer 1808 in the semiconductor substrate 1802 and below the gate G. The channel C is laterally between the drain D and the source S, which are also in the channel layer 1808. The drain metal contact 1902 is electrically coupled to the drain D, and the source metal contact 1904 is electrically coupled to the source S. The gate metal contact 2402 is electrically coupled to the gate G (e.g., the gate layer 1812). The gate G and the gate metal contact 2402 are laterally between the drain metal contact 1902 and the source metal contact 1904. The semiconductor device 4900 includes a field plate including a first field plate portion 4716 and a second field plate portion 4718 coupled together by a second field plate portion 4718 extending continuously from the first field plate portion 4716. The field plate extends from the drain side of the gate G toward the drain metal contact 1902. The field plate portions 4716, 4718 each have a respective uniform slope relative to the upper surface of the semiconductor substrate 1802, as depicted by respective oblique angles α1, α2 relative to respective planes parallel to the upper surface of the semiconductor substrate 1802. In some examples, the slope of the first field plate portion 4716 may be less than the slope of the second field plate portion 4718 (e.g., such that α1<α2). In some examples, the slope of the first field plate portion 4716 may be greater than the slope of the second field plate portion 4718 (e.g., such that α1>α2). The field plate is electrically coupled to the source S through the metal line 4714 , the metal via 4704 , and the source metal contact 1904 (eg, a source coupled field plate).

[0136] Fig.50A and 50B 5000A, 5000B are flow charts of methods 5000A, 5000B of manufacturing a semiconductor device (eg, HEMT) according to some examples. Fig.50A and 50B Methods 5000A and 5000B are as follows: Figures 51 to 56 Draw and Figures 51 to 56 Described in the context of Figures 51 to 56 A cross-sectional view of a semiconductor device at various stages of fabrication is shown. Methods 5000A, 5000B include processing of blocks 1702 to 1712, 1720 to 1726, as described above with respect to Figures 18 to 24 Described, and formed Fig.25 2504 and dielectric material 2506. However, forming dielectric structure 2302 and first field plate portion 2404 and associated processing are omitted. Fig.51The resulting structure without the dielectric structure 2302 and the first field plate portion 2404 is shown in FIG.

[0137] refer to Fig.50A Box 5002 and Fig.51 , using grayscale lithography to form a photoresist 5102 having a first inclined surface 5104, a separation surface 5106, and a second inclined surface 5108. The photoresist 5102 may be formed as described above (including Fig.13 , 15 16). The photoresist 5102 can be formed by depositing (e.g., by spin coating) a photoresist layer over and on the dielectric material 2506 and patterning the photoresist layer into the photoresist 5102 using grayscale lithography. In the illustrated example, each inclined surface 5104, 5108 has a respective uniform slope throughout the respective inclined surface 5104, 5108. The respective angles formed by the inclined surfaces 5104, 5108 are different. The separation surface 5106 is between the inclined surfaces 5104, 5108. The first inclined surface 5104 extends from the top surface of the dielectric material 2506 to the separation surface 5106, and the second inclined surface 5108 extends from the separation surface 5106 in a direction away from the first inclined surface 5104. The separation surface 5106 is parallel to the top surface of the dielectric material 2506. In other examples, the separation surface 5106 may be any other transition surface, such as the one described above with respect to Fig.13 described.

[0138] refer to Fig.50A Box 5004 and Fig.52 , the dielectric material 2506 is etched using the photoresist 5102 as a mask to form a dielectric structure 5202 having a first inclined surface 5204, a separation surface 5206, and a second inclined surface 5208. Fig.11 and 14 The dielectric material 2506 is etched as described. The etching transfers the slope from the photoresist 5102 to the dielectric material 2506 to form a dielectric structure 5202 having inclined surfaces 5204, 5208 and separating surfaces 5206. Each inclined surface 5204, 5208 has a uniform slope throughout the respective inclined surface 5204, 5208. The angle of the inclined surface 5204 may correspond to Fig.13 and 14 The angle of the inclined surface 5104 described above and the angle of the inclined surface 5208 may correspond to the angle of the inclined surface 5104 described above. Fig.13 and 14The angle of the inclined surface 5108 is described. The separation surface 5206 is between the inclined surfaces 5204, 5208. The first inclined surface 5204 extends from the top surface of the fourth dielectric layer 2504 to the separation surface 5206, and the second inclined surface 5208 extends from the separation surface 5206 in a direction away from the first inclined surface 5204. The separation surface 5206 is parallel to the top surface of the fourth dielectric layer 2504.

[0139] refer to Fig.50A Box 5006 and Fig.53 , forming via openings 5302, 5304. A via opening 5302 is formed through the fourth dielectric layer 2504, the third dielectric layer 2502, and the second dielectric layer 2002 to reach the drain metal contact 1902. A via opening 5304 is formed through the fourth dielectric layer 2504, the third dielectric layer 2502, and the second dielectric layer 2002 to reach the source metal contact 1904. The via openings 5302, 5304 can be formed using appropriate photolithography and etching processes.

[0140] refer to Fig.50A Box 5008 and Fig.54 , forming metal vias 5402, 5404, metal lines 5412, 5414, a first field plate portion 5416, and a second field plate portion 5418. Metal via 5402 is in the via opening 5302 and contacts the drain metal contact 1902. Metal line 5412 is above and on the fourth dielectric layer 2504 and metal via 5402, and metal via 5402 extends from metal line 5412 into the via opening 5302. Metal via 5404 is in the via opening 5304 and contacts the source metal contact 1904. Metal line 5414 is above and on the fourth dielectric layer 2504 and metal via 5404, and metal via 5404 extends from metal line 5414 into the via opening 5304. The first field plate portion 5416 is above and on the first slanted surface 5204 of the dielectric structure 5202 and the fourth dielectric layer 2504, and the second field plate portion 5418 is above and on the second slanted surface 5208 of the dielectric structure 5202. As shown, the metal line 5414 and the first field plate portion 5416 are formed by a continuous metal portion that electrically couples the metal line 5414 and the first field plate portion 5416. Therefore, the first field plate portion 5416 is electrically coupled to the source of the semiconductor device (e.g., HEMT). The second field plate portion 5418 is separated from the first field plate portion 5416 by a gap (e.g., at the separation surface 5106) and is electrically isolated from the first field plate portion 5416. In the illustrated example, the metal lines 5412, 5414 and the field plate portions 5416, 5418 are in the same metal layer (e.g., MET1 layer).

[0141] exist Fig.50BAt block 5010 of the present invention, a fifth dielectric layer 5422 is conformally formed over and on the fourth dielectric layer 2504, the metal lines 5412, 5414, and the field plate portions 5416, 5418. The fifth dielectric layer 5422 may be an ILD. In some examples, the fifth dielectric layer 5422 is or includes silicon nitride (SiN); however, in other examples, the fifth dielectric layer 5422 may be or include another one or more other dielectric materials. The fifth dielectric layer 5422 may be deposited using any suitable deposition process, such as CVD, LPCVD, PECVD, etc.

[0142] refer to Fig.50B Box 5012 and Fig.55 , forming via openings 5502, 5504, 5506 through the fifth dielectric layer 5422. Forming a via opening 5502 through the fifth dielectric layer 5422 to the metal line 5412. Forming a via opening 5504 through the fifth dielectric layer 5422 to the metal line 5414. Forming a via opening 5506 through the fifth dielectric layer 5422 to the second field plate portion 5418. The via openings 5502, 5504, 5506 may be formed using appropriate photolithography and etching processes.

[0143] refer to Fig.50B Box 5014 and Fig.56 , forming metal vias 5602, 5604, 5606 and metal lines 5612, 5614, 5616. Metal via 5602 is in the via opening 5502 and contacts the metal line 5412. Metal line 5612 is above and on the fifth dielectric layer 5422 and the metal via 5602, and the metal via 5602 extends from the metal line 5612 into the via opening 5502. Metal via 5604 is in the via opening 5504 and contacts the metal line 5414. Metal line 5614 is above and on the fifth dielectric layer 5422 and the metal via 5604, and the metal via 5604 extends from the metal line 5614 into the via opening 5504. Metal via 5606 is in the via opening 5506 and contacts the second field plate portion 5418. Metal line 5616 is over and on fifth dielectric layer 5422 and metal via 5606, and metal via 5606 extends from metal line 5616 into via opening 5506. In the illustrated example, metal lines 5612, 5614, 5616 are in the same metal layer (eg, MET2 layer).

[0144] At block 5016, a sixth dielectric layer 5622 is formed over and on the fifth dielectric layer 5422 and the metal lines 5612, 5614, 5616. The sixth dielectric layer 5622 may be an ILD. In some examples, the sixth dielectric layer 5622 is or includes a silicon oxide-based material (e.g., PSG or TEOS oxide) or silicon nitride (SiN); but in other examples, the sixth dielectric layer 5622 may be or include another one or more other dielectric materials. The sixth dielectric layer 5622 may be deposited using any suitable deposition process (e.g., CVD, LPCVD, PECVD, etc.). The sixth dielectric layer 5622 may be planarized, for example, by CMP.

[0145] Fig.56A cross-sectional view of a fabricated semiconductor device 5600 is depicted. The semiconductor device 5600 includes a source S, a channel C, a drain D, and a gate G. The gate G is or includes a gate layer 1812, which is on an upper surface of a semiconductor substrate 1802 (e.g., an upper surface of a barrier layer 1810). The channel C is in a channel layer 1808 in the semiconductor substrate 1802 and below the gate G. The channel C is laterally between the drain D and the source S, which are also in the channel layer 1808. The drain metal contact 1902 is electrically coupled to the drain D, and the source metal contact 1904 is electrically coupled to the source S. The gate metal contact 2402 is electrically coupled to the gate G (e.g., the gate layer 1812). The gate G and the gate metal contact 2402 are laterally between the drain metal contact 1902 and the source metal contact 1904. The semiconductor device 5600 includes a first field plate and a second field plate. The first field plate includes a first field plate portion 5416. The second field plate includes a second field plate portion 5418. The first field plate extends from the drain side of the gate G toward the drain metal contact 1902. The field plate portions 5416, 5418 each have a respective uniform slope relative to the upper surface of the semiconductor substrate 1802, as depicted by respective oblique angles α1, α2, α3 relative to respective planes parallel to the upper surface of the semiconductor substrate 1802. In some examples, the slope of the first field plate portion 5416 may be less than the slope of the second field plate portion 5418 (e.g., such that α1<α2). In some examples, the slope of the first field plate portion 5416 may be greater than the slope of the second field plate portion 5418 (e.g., such that α1>α2). The first field plate (e.g., first field plate portion 5416) is electrically coupled to the source S (e.g., being a source coupled field plate) through metal line 5414, metal via 5404, and source metal contact 1904. A gap is between the first field plate portion 5416 and the second field plate portion 5418, such as at the separation surface 5206. The second field plate can be electrically coupled to another terminal, such as by routing in one or more metal layers (e.g., metal line 5616). In some examples, rather than forming a second field plate, the second field plate portion 5418 can be electrically coupled to the first field plate portion 5416 to become another portion of the first field plate. For example, with a gap between the field plate portions 5416, 5418, routing in one or more metal layers can electrically couple the second field plate portion 5418 to the first field plate portion 5416.

[0146] Although the various methods described above are described in the context of a gate-last process (e.g., forming a gate metal contact after source and drain metal contacts), various examples may implement a gate-first process (e.g., forming a gate metal contact before source and drain metal contacts). In addition, some examples may implement a self-alignment process of a gate metal contact and a corresponding gate layer (and / or silicon layer). Various other modifications may be made.

[0147] In this specification, the term "coupled" may cover connections (e.g., through circuits (buffer drivers, etc.) or external parts that may be monolithically integrated or co-packaged), communications, or signal paths that achieve a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B through a direct connection; or (b) in a second instance, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not change the functional relationship between device A and device B, so that device B is controlled by device A via the control signal generated by device A.

[0148] Additionally, in this specification, statements that are “based on” mean “based, at least in part, on.” Thus, if X is based on Y, then X may vary with Y and any number of other factors.

[0149] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function at the time of manufacture by the manufacturer, and / or may be configured (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. The configuration may be performed by firmware and / or software programming of the device, by the construction and / or layout of the hardware components and interconnections of the device, or a combination thereof.

[0150] As used herein, the terms "terminal", "node", "interconnect", "pin" and "lead" are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to an interconnection or an end thereof between device elements, circuit elements, integrated circuits, devices or other electronic devices or semiconductor components.

[0151] A circuit or device described herein as including certain components may actually be adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may actually include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure at the time of manufacture or after manufacture, for example, by an end user and / or a third party.

[0152] Although the use of specific transistors is described herein, other transistors (or equivalent devices) may be used alternatively with little or no change to the remaining circuitry. For example, field effect transistors ("FETs") (e.g., n-channel FETs (NFETs) or p-channel FETs (PFETs)), bipolar junction transistors (BJTs—e.g., NPN transistors or PNP transistors), insulated gate bipolar transistors (IGBTs), and / or junction field effect transistors (JFETs) may be used in place of or in conjunction with the devices described herein. The transistors may be depletion mode devices, drain extension devices, enhancement mode devices, native transistors, or other types of device structure transistors. Furthermore, the devices may be implemented in / on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0153] In the claims reference may be made to the control input of a transistor and its current terminals. In the context of a FET, the control input is the gate, and the current terminals are the drain and the source. In the context of a BJT, the control input is the base, and the current terminals are the collector and the emitter.

[0154] References herein to a FET being "on" or "enabled" mean that there is a conduction channel of the FET and drain current can flow through the FET. References herein to a FET being "off" or "disabled" mean that there is no conduction channel, and therefore drain current cannot flow through the FET. However, an "off" FET may have current flowing through the body diode of the transistor.

[0155] The circuits described herein may be reconfigured to include additional or different components to provide functionality at least partially similar to functionality available before component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or in parallel to provide the amount of impedance represented by the displayed resistor. For example, a resistor or capacitor shown and described as a single component herein may actually be a plurality of resistors or capacitors coupled in parallel between the same nodes, respectively. For example, a resistor or capacitor shown and described as a single component herein may actually be a plurality of resistors or capacitors coupled in series between the same two nodes as a single resistor or capacitor, respectively.

[0156] Although certain elements of the described examples are included in the integrated circuit and other elements are external to the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features depicted as external to the integrated circuit may be included in the integrated circuit, and / or some features depicted as internal to the integrated circuit may be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that: (i) are incorporated in / on a semiconductor substrate; (ii) are incorporated in a single semiconductor package; (iii) are incorporated in the same module; and / or (iv) are incorporated in / on the same printed circuit board.

[0157] Use of the phrase "ground" in the foregoing description includes chassis ground, ground line ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection that is applicable or suitable for the teachings of this specification.

[0158] In this specification, unless otherwise stated, “about”, “approximately” or “substantially” preceding a parameter means within + / - 10% of the parameter, or if the parameter is zero, within a reasonable value range of about zero.

[0159] Modifications may be made in the described embodiments, and other embodiments are possible, within the scope of the claims.

[0160] Although various examples have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the scope defined by the appended claims.

Claims

1. A semiconductor device comprising: Semiconductor substrate; a gate electrode on a surface of the semiconductor substrate; a drain contact and a source contact on the semiconductor substrate; and A field plate is provided above the surface of the semiconductor substrate and extends from a side of the gate toward the drain contact, the field plate comprising a plurality of field plate portions, each of the plurality of field plate portions having a uniform respective slope relative to the surface, and the plurality of field plate portions having different slopes.

2. The semiconductor device of claim 1 , wherein the plurality of field plate portions include a first field plate portion having a first slope and a second field plate portion having a second slope, the first field plate portion being between the gate and the second field plate portion, and the first slope being smaller than the second slope. 3 . The semiconductor device of claim 2 , wherein the first field plate portion abuts a gate contact electrically coupled to the gate.

4. The semiconductor device of claim 1 , wherein the field plate is a first field plate and is electrically coupled to a first terminal, and the semiconductor device further comprises a second field plate above the surface, the second field plate having a slope relative to the surface, and the second field plate is electrically coupled to a second terminal. The semiconductor device of claim 4 , wherein the second field plate is between the first field plate and the drain contact. 6 . The semiconductor device of claim 4 , wherein the first terminal is electrically coupled to the gate, and the second terminal is electrically coupled to the source contact. 7 . The semiconductor device of claim 4 , wherein the first field plate and the second field plate are separated by a gap.

8. The semiconductor device according to claim 1, further comprising: a dielectric structure on the semiconductor substrate; and An etch stop layer is between the dielectric structure and the semiconductor substrate, wherein the field plate is on the dielectric structure. 9 . The semiconductor device of claim 8 , wherein the etch stop layer comprises aluminum oxide.

10. The semiconductor device according to claim 1, further comprising a gallium nitride (GaN) layer on the semiconductor substrate, wherein the source contact and the drain contact are electrically coupled to a source and a drain in the GaN layer, respectively, and the field plate is above the GaN layer.

11. A method comprising: forming an etch stop layer on a surface of a semiconductor substrate of a semiconductor device including a gate, a drain contact, and a source contact on the surface; forming one or more dielectric layers on the etch stop layer; forming one or more photoresist layers on the dielectric layer between the gate and the drain contact; patterning one or more photoresist layers using one or more grayscale masks to form a first plurality of inclined surfaces, each first inclined surface having a corresponding uniform slope, and the first inclined surfaces having different slopes; etching the one or more dielectric layers to form a second plurality of inclined surfaces based on the first inclined surfaces of the one or more photoresist layers and to expose a portion of the etch stop layer; and A field plate having a plurality of field plate portions is formed on the second plurality of inclined surfaces and on the exposed portion of the etch stop layer between the gate and the drain contact, each of the plurality of field plate portions having a uniform respective slope relative to the surface of the semiconductor substrate, and the plurality of field plates having different slopes. 12 . The method of claim 11 , wherein patterning the one or more photoresist layers with the one or more grayscale masks comprises patterning a single photoresist layer with a single grayscale mask.

13. The method of claim 12, wherein the single grayscale mask comprises a single constant pitch grayscale mask having a first region and a second region, the first region having a first fill factor distribution defining a first slope, and the second region having a second fill factor distribution defining a second slope different from the first slope.

14. The method of claim 11, wherein patterning the one or more photoresist layers with the one or more grayscale masks comprises: patterning the first photoresist layer with a first grayscale mask to form a first one of the first plurality of inclined surfaces; patterning the first dielectric layer based on the patterned first photoresist layer to form a first one of the second plurality of inclined surfaces; forming a second dielectric layer on the first field plate portion and on the patterned first dielectric layer; forming a second photoresist layer on the second dielectric layer; patterning the second photoresist layer using a second grayscale mask to form a second one of the first plurality of inclined surfaces; and The second dielectric layer is patterned based on the patterned second photoresist layer to form a second one of the second plurality of inclined surfaces.

15. The method of claim 14, wherein the first grayscale mask comprises a first constant pitch grayscale mask having a first fill factor distribution defining a first slope; and The second grayscale mask includes a second constant pitch grayscale mask having a second fill factor distribution defining a second slope different from the first slope. 16 . The method of claim 11 , further comprising forming a metal layer electrically coupled between the gate and the field plate.

17. The method of claim 11, further comprising forming a metal layer electrically coupled between the source contact and the field plate.

18. The method of claim 11, wherein the etch stop layer comprises aluminum oxide. 19 . The method according to claim 11 , further comprising forming a gallium nitride (GaN) layer on the semiconductor substrate, wherein the etch stop layer is formed on the GaN layer. 20 . The method of claim 11 , further comprising forming a gate layer on the semiconductor substrate, wherein the first plurality of inclined surfaces and the second plurality of inclined surfaces are on one side of the gate layer.

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