Power semiconductor device

Abstract

The invention provides a power semiconductor device, and particularly relates to a transverse power semiconductor device in the field of low voltage. A trench gate structure is introduced into the power semiconductor device, so that the trench gate structure can extend the width of a channel, and can also play roles in assisting depletion of a drift region and reducing the conduction loss of the device. As the size of a power device is gradually reduced and the performance of the device is gradually improved nowadays, the development of a small-size device in the low-voltage field is limited most obviously. Based on the background, a design scheme of combining a trench gate and a plane gate is adopted, and on the premise of ensuring that the size of a device is not increased, power semiconductor structures with different low conduction losses and low switching losses including voltage level expansion, a trench stress technology and a shield gate structure are provided; and the performance of the low-voltage power semiconductor device is further improved.

Description

Technical Field

[0001] The present invention belongs to the field of power semiconductors, and in particular relates to a low-voltage power semiconductor device. Background Art

[0002] As integrated circuit technology gradually enters the post-Moore era, the size of power semiconductor devices is gradually reduced. The ensuing problems such as short channel effect, quantum tunneling effect and parasitic effect begin to restrict the further reduction of device size. Therefore, it is increasingly important to study the performance development of small-size devices. Laterally double-diffused metal oxide semiconductor (LDMOS) devices are widely used in the field of power integrated circuits due to their advantages such as easy integration, high input impedance and low conduction loss. However, in the context of the post-Moore era, the performance development of low-voltage LDMOS devices is also limited by the reduction in size.

[0003] In order to further optimize the static and dynamic characteristics of the device based on the traditional LDMOS device without involving small size problems such as short channel effect, the present invention proposes a LDMOS (Trench Gate LDMOS, TG-LDMOS) structure combined with a trench gate. Due to the reduction in device size, the channel resistance has gradually become the main part affecting the static loss of the device. Taking into account the limitations of the BCD manufacturing process, without changing the original device size and the process of the drift region and the channel, TG-LDMOS uses a trench structure to fold the original planar channel in the width direction, retaining the original channel width while introducing an extra width channel using the trench sidewall, which is equivalent to connecting multiple channel resistors in parallel to reduce the channel resistance; on the other hand, the trench gate in the drift region also has the function of a field plate, which can assist in depleting the drift region to optimize the breakdown voltage (BreakdownVoltage, BV) and specific on-resistance (Specific on-resistance, R on，sp ). In addition, the trench stress technology is used to grow a stress oxide layer inside the trench gate, and the stress is transmitted to the channel region and drift region of the trench sidewall through thermal expansion, introducing tensile stress in the current direction, thereby improving carrier mobility and further reducing channel resistance and drift region resistance.

[0004] However, the introduction of the additional trench gate electrode will increase the total gate charge of the device, which will affect the switching loss of the device. Therefore, in order to solve this problem, the present invention also adds a field oxide layer, a trench gate protection area, a shielding gate electrode and other structural designs to reduce the influence of the additional gate charge. In order to avoid the small size effect, the static and dynamic characteristics of the device are optimized without changing the device size, and the embodiments of the present invention are thus presented. Summary of the invention

[0005] To achieve the purpose of the above invention, the technical solution of the present invention is as follows:

[0006] A power semiconductor device comprises a first conductive type substrate 101, on which a first conductive type buried layer 102 is arranged, a first conductive type body region 103 and a second conductive type drift region 104 are arranged above the first conductive type buried layer 102; a first conductive type contact region 105 and a second conductive type source region 106 are arranged above the first conductive type body region 103, wherein the first conductive type contact region 105 is located to the left of the second conductive type source region 106; a second conductive type drain region 107 is arranged at the upper right inside the second conductive type drift region 104; a planar gate oxide layer 108 is arranged above the first conductive type body region 103 and above part of the second conductive type drift region 104, and a planar gate electrode 109 is arranged directly above the planar gate oxide layer 108.

[0007] The second power semiconductor device provided by the present invention is set as follows: the AA' cross section is a cross section from the first conductive type contact region 105 to the second conductive type drain region 107 and passing through the planar gate electrode 109; the BB' cross section is a cross section from the first conductive type contact region 105 to the second conductive type drain region 107 and passing through the trench gate electrode 110; the CC' longitudinal cross section is a cross section of the region where the planar gate electrode 109 and the trench gate electrode 110 are alternately arranged;

[0008] Along the BB' cross section, it includes a first conductive type substrate 101, a first conductive type buried layer 102 is arranged on the first conductive type substrate 101, a first conductive type body region 103 and a second conductive type drift region 104 are arranged above the first conductive type buried layer 102; a first conductive type contact region 105, a second conductive type source region 106, a second conductive type source region extension region 114 and a trench region are arranged above the first conductive type body region 103; wherein the first conductive type contact region 105 is located on the left side of the second conductive type source region 106, the second conductive type source region extension region 114 is located below the second conductive type source region 106, the trench region is located on the right side of the second conductive type source region 106 and the second conductive type source region extension region 114, and a part of the trench structure is located in the second conductive type drift region 104; wherein the bottom depth of the trench region is equal to or less than the depth of the second conductive type source region extension region 114;

[0009] The trench region is provided with a trench gate oxide layer 111 and a trench gate electrode 110 from bottom to top, and the trench gate oxide layer 111 is provided between the trench gate electrode 110 and the second conductivity type source region 106, the second conductivity type source region extension region 114, the first conductivity type body region 103 and the second conductivity type drift region 104 respectively;

[0010] A second conductivity type drain region 107 is disposed in the upper right corner of the second conductivity type drift region 104;

[0011] Along the CC' longitudinal section, a planar gate oxide layer 108 is arranged above the first conductivity type body region 103 and above a portion of the second conductivity type drift region 104, and a planar gate electrode 109 is arranged directly above the planar gate oxide layer 108; the planar gate electrode 109 and the trench gate electrode 110 are arranged alternately in the width direction, and in actual process manufacturing, the planar gate electrode 109 and the trench gate electrode 110 are connected, and the trench gate oxide layer 111 is connected to the planar gate oxide layer 108.

[0012] As a preferred embodiment, along the BB' cross section, inside the trench region, a field oxide layer 112 is provided on the side of the trench gate electrode 110 close to the drain region, and its thickness is greater than that of the trench gate oxide layer 111 and increases with the increase of the device voltage level.

[0013] As a preferred embodiment, along the BB' cross section, a first conductive type protection zone 119 is arranged inside the second conductive type drift zone 104, the first conductive type protection zone 119 is arranged on the right side of the trench zone and in contact with the trench gate oxide layer 111, and the depth of the first conductive type protection zone 119 is greater than or equal to the trench depth.

[0014] The third power semiconductor device provided by the present invention is a device structure including the trench stress technology, and it is set that: the A-A' cross section is a cross section from the first conductive type contact region 105 to the second conductive type drain region 107 and passing through the planar gate electrode 109; the BB' cross section is a cross section from the first conductive type contact region 105 to the second conductive type drain region 107 and passing through the trench gate electrode 110; the CC' longitudinal cross section is a cross section of the region where the planar gate electrode 109 and the trench gate electrode 110 are alternately arranged;

[0015] Along the BB' cross section, it includes a first conductive type substrate 101, a first conductive type buried layer 102 is arranged on the first conductive type substrate 101, a first conductive type body region 103 and a second conductive type drift region 104 are arranged above the first conductive type buried layer 102; a first conductive type contact region 105, a second conductive type source region 106, a second conductive type source region extension region 114 and a trench region are arranged above the first conductive type body region 103; wherein the first conductive type contact region 105 is located on the left side of the second conductive type source region 106, the second conductive type source region extension region 114 is located below the second conductive type source region 106, the trench region is located on the right side of the second conductive type source region 106 and the second conductive type source region extension region 114, and a part of the trench structure is located in the second conductive type drift region 104; wherein the bottom depth of the trench region is equal to or less than the depth of the second conductive type source region extension region 114;

[0016] The trench region is provided with a trench gate oxide layer 111, a trench gate electrode 110 and a stress oxide layer 113 from bottom to top, and is provided with a trench gate oxide layer 111, a trench gate electrode 110, a stress oxide layer 113 and a field oxide layer 112 from left to right, wherein the stress oxide layer 113 is surrounded by the trench gate electrode 110; the trench gate oxide layer 111 is provided between the trench gate electrode 110 and the second conductivity type source region 106, the second conductivity type source region extension region 114, the first conductivity type body region 103 and the second conductivity type drift region 104 respectively;

[0017] A second conductivity type drain region 107 is disposed in the upper right corner of the second conductivity type drift region 104;

[0018] Along the CC' longitudinal section, a planar gate oxide layer 108 is arranged above the first conductivity type body region 103 and above a portion of the second conductivity type drift region 104, and a planar gate electrode 109 is arranged directly above the planar gate oxide layer 108; the planar gate electrode 109 and the trench gate electrode 110 are arranged alternately in the width direction, and in actual process manufacturing, the planar gate electrode 109 and the trench gate electrode 110 are connected, and the trench gate oxide layer 111 is connected to the planar gate oxide layer 108.

[0019] As a preferred embodiment, along the BB' cross section, the trench region is provided with a trench gate oxide layer 111, a trench gate electrode 110 and a stress oxide layer 113 from bottom to top, and is provided with a trench gate oxide layer 111, a trench gate electrode 110, a stress oxide layer 113 and a field oxide layer 112 from left to right; wherein the stress oxide layer 113 is surrounded by the trench gate electrode 110 on three sides, and is in contact with the field oxide layer 112 on the side near the drain, wherein the thickness of the field oxide layer 112 is greater than the thickness of the trench gate oxide layer 111 and increases with the increase of the device voltage level.

[0020] The fourth power semiconductor device provided by the present invention is a high current device structure with extended voltage level, and it is set that: the A-A' cross section is a cross section from the first conductive type contact area 105 to the drain electrode metal 115 and passing through the planar gate electrode 109; the BB' cross section is a cross section from the first conductive type contact area 105 to the drain electrode metal 115 and passing through the trench gate electrode 110; the CC' longitudinal cross section is a cross section of the area where the planar gate electrode 109 and the trench gate electrode 110 are alternately arranged;

[0021] Along the BB' cross section, it includes a first conductive type substrate 101, a first conductive type buried layer 102 is arranged on the first conductive type substrate 101, a first conductive type body region 103 and a second conductive type drift region 104 are arranged above the first conductive type buried layer 102; a first conductive type contact region 105, a second conductive type source region 106, a second conductive type source region extension region 114 and a trench region are arranged above the first conductive type body region 103; the first conductive type contact region 105 is located on the left of the second conductive type source region 106; the second conductive type source region extension region 114 is located below the second conductive type source region 106; the trench region is located on the right of the second conductive type source region 106 and the second conductive type source region extension region 114, and a part of the trench structure is located in the second conductive type drift region 104; wherein the bottom depth of the trench region is equal to or less than the depth of the second conductive type source region extension region 114;

[0022] The trench region is provided with a trench gate oxide layer 111 and a trench gate electrode 110 from bottom to top, and the trench gate oxide layer 111 is provided between the trench gate electrode 110 and the second conductivity type source region 106, the second conductivity type source region extension region 114, the first conductivity type body region 103 and the second conductivity type drift region 104 respectively;

[0023] A second conductive type drain region 107 and a drain region electrode metal 115 are arranged in the upper right part of the second conductive type drift region 104; wherein the bottom depth of the drain region electrode metal 115 is greater than or equal to the bottom of the trench region, and the second conductive type drain region 107 is arranged in a surrounding manner on the left and below the drain region electrode metal 115;

[0024] Along the CC' longitudinal section, a planar gate oxide layer 108 is arranged above the first conductivity type body region 103 and above a portion of the second conductivity type drift region 104, and a planar gate electrode 109 is arranged directly above the planar gate oxide layer 108; wherein the planar gate electrode 109 and the trench gate electrode 110 are arranged alternately in the width direction, and during the actual process, the planar gate electrode 109 and the trench gate electrode 110 are connected, and the trench gate oxide layer 111 is connected to the planar gate oxide layer 108.

[0025] The fifth power semiconductor device provided by the present invention is a structure for preventing channel punch-through, and it is set that: the A-A' cross section is a cross section from the second conductive type source region 106 to the second conductive type drain region 107 and passing through the planar gate electrode 109; the BB' cross section is a cross section from the second conductive type source region 106 to the second conductive type drain region 107 and passing through the trench gate electrode 110; the CC' longitudinal cross section is a cross section of the area where the planar gate electrode 109 and the trench gate electrode 110 are alternately arranged;

[0026] Along the BB' cross section, it includes a first conductive type substrate 101, a first conductive type buried layer 102 is arranged on the first conductive type substrate 101, and a first conductive type body region 103 and a second conductive type drift region 104 are arranged above the first conductive type buried layer 102; a first conductive type body buried layer 120 is arranged inside the first conductive type body region 103, and a first conductive type contact region 105, a second conductive type source region 106, a second conductive type source region extension region 114, a source region electrode metal 116 and a trench region are arranged above; wherein the source region electrode metal 116 is located in the middle of the second conductive type source region 106 and the depth exceeds the second conductive type source region 106. region 106; the first conductive type contact region 105 is located below the source region electrode metal 116 and to the left of the second conductive type source region extension region 114; the second conductive type source region extension region 114 is located below the second conductive type source region 106 and in contact with the source region electrode metal 116, the trench region is located to the right of the second conductive type source region 106 and the second conductive type source region extension region 114, and part of the trench structure is located in the second conductive type drift region 104; wherein the bottom depth of the trench region is equal to or less than the depth of the second conductive type source region extension region 114; the first conductive type buried layer 120 is arranged below the trench region and is located in the first conductive type body region 103;

[0027] The trench region is provided with a trench gate oxide layer 111 and a trench gate electrode 110 from bottom to top, and the trench gate oxide layer 111 is provided between the trench gate electrode 110 and the second conductivity type source region 106, the second conductivity type source region extension region 114, the first conductivity type body region 103 and the second conductivity type drift region 104 respectively;

[0028] A second conductivity type drain region 107 is disposed in the upper right corner of the second conductivity type drift region 104;

[0029] Along the CC' longitudinal section, a planar gate oxide layer 108 is arranged above the first conductivity type body region 103 and above a portion of the second conductivity type drift region 104, and a planar gate electrode 109 is arranged directly above the planar gate oxide layer 108; wherein the planar gate electrode 109 and the trench gate electrode 110 are arranged alternately in the width direction, and during the actual process, the planar gate electrode 109 and the trench gate electrode 110 are connected, and the trench gate oxide layer 111 is connected to the planar gate oxide layer 108.

[0030] The sixth power semiconductor device provided by the present invention is a low gate-drain parasitic capacitance design, and is set as follows: the A-A' cross section is a cross section from the first conductive type contact region 105 to the second conductive type drain region 107 and passing through the planar gate electrode 109; the BB' cross section is a cross section from the first conductive type contact region 105 to the second conductive type drain region 107 and passing through the trench gate electrode 110 and the shielding gate electrode 118; the CC' longitudinal cross section is a cross section of the area where the planar gate electrode 109 and the trench gate electrode 110 are alternately arranged;

[0031] Along the BB' cross section, it includes a first conductive type substrate 101, a first conductive type buried layer 102 is arranged on the first conductive type substrate 101, a first conductive type body region 103 and a second conductive type drift region 104 are arranged above the first conductive type buried layer 102; a first conductive type contact region 105, a second conductive type source region 106, a second conductive type source region extension region 114 and a trench region are arranged above the first conductive type body region 103; wherein the first conductive type contact region 105 is located on the left side of the second conductive type source region 106, the second conductive type source region extension region 114 is located below the second conductive type source region 106, the trench region is located on the right side of the second conductive type source region 106 and the second conductive type source region extension region 114, and a part of the trench structure is located in the second conductive type drift region 104; wherein the bottom depth of the trench region is equal to or less than the depth of the second conductive type source region extension region 114;

[0032] The trench region is provided with a trench gate oxide layer 111, a trench gate electrode 110, a dielectric isolation layer 117, a shielding gate electrode 118, and a field oxide layer 112 from left to right; wherein the trench gate electrode 110 is provided with the second conductive type source region 106, the second conductive type source region extension region 114, the first conductive type body region 103, and the second conductive type drift region 104 respectively, and a dielectric isolation layer 117 is provided between the trench gate electrode 110 and the shielding gate electrode 118; and a field oxide layer 112 is provided between the shielding gate electrode 118 and the second conductive type drift region 104, wherein the thickness of the field oxide layer 112 is greater than the thickness of the trench gate oxide layer 111 and increases with the increase of the device voltage level;

[0033] A second conductivity type drain region 107 is disposed in the upper right corner of the second conductivity type drift region 104;

[0034] Along the CC' longitudinal section, a planar gate oxide layer 108 is arranged above the first conductivity type body region 103 and above a portion of the second conductivity type drift region 104, and a planar gate electrode 109 is arranged directly above the planar gate oxide layer 108; wherein the planar gate electrode 109 and the trench gate electrode 110 are arranged alternately in the width direction, and during the actual process, the planar gate electrode 109 and the trench gate electrode 110 are connected, and the trench gate oxide layer 111 is connected to the planar gate oxide layer 108.

[0035] The principle and beneficial effects of the present invention are as follows: the present invention is based on the traditional LDMOS structure. As the size of the LDMOS device gradually decreases, the proportion of the channel resistance in the device on-resistance gradually increases. Therefore, in order to optimize the device while avoiding the negative effects such as the small size effect caused by the small size, the present invention provides a series of power semiconductor devices to optimize the static and dynamic characteristics of LDMOS. Based on the advanced power semiconductor process, the trench gate and the planar gate are arranged alternately, and the extra width of the channel is introduced through the side wall of the trench. The source extension area formed by the oblique injection of the side wall of the trench is used to utilize the channel at the bottom of the trench, thereby maximizing the channel width to reduce the channel resistance. At the same time, combined with the trench stress technology, the oxide layer grown inside the trench gate is used to conduct stress to the channel area and the drift area, thereby improving the carrier mobility and reducing the on-resistance. On the other hand, by deforming the trench gate electrode structure, introducing the field oxide layer and designing the shielding gate electrode structure, the influence of the extra gate charge caused by the trench gate electrode is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 A power semiconductor device structure provided in Embodiment 1 of the present invention.

[0037] FIG. 2( a ) is a three-dimensional diagram of a power semiconductor device provided in Embodiment 2 of the present invention.

[0038] FIG2(b) is a layout structure of a power semiconductor device provided in Embodiment 2 of the present invention. The A-A' cross section is set as the cross section from the first conductive type contact region 105 to the second conductive type drain region 107 and passing through the planar gate electrode 109; the BB' cross section is the cross section from the first conductive type contact region 105 to the second conductive type drain region 107 and passing through the trench gate electrode 110; the CC' longitudinal cross section is the cross section of the region where the planar gate electrode 109 and the trench gate electrode 110 are alternately arranged.

[0039] FIG. 2( c ) is a BB′ cross section corresponding to a power semiconductor device structure provided in Embodiment 2 of the present invention.

[0040] FIG. 2( d ) is a CC′ longitudinal cross section corresponding to a power semiconductor device structure provided in Embodiment 2 of the present invention.

[0041] FIG3(a) is a layout structure of a power semiconductor device provided in Embodiment 3 of the present invention. The A-A' cross section is set as the cross section from the first conductive type contact region 105 to the second conductive type drain region 107 and passing through the planar gate electrode 109; the BB' cross section is the cross section from the first conductive type contact region 105 to the second conductive type drain region 107 and passing through the trench gate electrode 110; the CC' longitudinal cross section is the cross section of the region where the planar gate electrode 109 and the trench gate electrode 110 are alternately arranged.

[0042] FIG3( b ) is a BB′ cross section corresponding to a power semiconductor device structure provided in Embodiment 3 of the present invention.

[0043] FIG4(a) is a layout structure of a power semiconductor device provided in Embodiment 4 of the present invention. The A-A' cross section is set as the cross section from the first conductive type contact region 105 to the second conductive type drain region 107 and passing through the planar gate electrode 109; the BB' cross section is the cross section from the first conductive type contact region 105 to the second conductive type drain region 107 and passing through the trench gate electrode 110; the CC' longitudinal cross section is the cross section of the region where the planar gate electrode 109 and the trench gate electrode 110 are alternately arranged.

[0044] FIG. 4( b ) is a BB′ cross section corresponding to a power semiconductor device structure provided in Embodiment 4 of the present invention.

[0045] FIG5(a) is a layout structure of a power semiconductor device provided in Embodiment 5 of the present invention. The A-A' cross section is set as the cross section from the first conductive type contact region 105 to the second conductive type drain region 107 and passing through the planar gate electrode 109; the BB' cross section is the cross section from the first conductive type contact region 105 to the second conductive type drain region 107 and passing through the trench gate electrode 110; the CC' longitudinal cross section is the cross section of the region where the planar gate electrode 109 and the trench gate electrode 110 are alternately arranged.

[0046] FIG5( b ) is a BB′ cross section corresponding to a power semiconductor device structure provided in Embodiment 5 of the present invention.

[0047] FIG5( c ) is a CC′ longitudinal cross section corresponding to a power semiconductor device structure provided in Embodiment 5 of the present invention.

[0048] Fig. 6(a) is a layout structure of a power semiconductor device provided by Embodiment 6 of the present invention. The A-A' cross section is set as the cross section from the first conductive type contact region 105 to the second conductive type drain region 107 and passing through the planar gate electrode 109; the BB' cross section is the cross section from the first conductive type contact region 105 to the second conductive type drain region 107 and passing through the trench gate electrode 110; the CC' longitudinal cross section is the cross section of the region where the planar gate electrode 109 and the trench gate electrode 110 are alternately arranged.

[0049] FIG6( b ) is a BB′ cross section corresponding to a power semiconductor device structure provided in Embodiment 6 of the present invention.

[0050] FIG7(a) is a layout structure of a power semiconductor device provided by Embodiment 7 of the present invention. The A-A' cross section is set as the cross section from the first conductive type contact area 105 to the drain electrode metal 115 and passing through the planar gate electrode 109; the BB' cross section is the cross section from the first conductive type contact area 105 to the drain electrode metal 115 and passing through the trench gate electrode 110; the CC' longitudinal cross section is the cross section of the area where the planar gate electrode 109 and the trench gate electrode 110 are alternately arranged.

[0051] FIG. 7( b ) is a cross section taken along line AA′ corresponding to a power semiconductor device structure provided in Embodiment 7 of the present invention.

[0052] FIG. 7( c ) is a BB′ cross section corresponding to a power semiconductor device structure provided in Embodiment 7 of the present invention.

[0053] FIG. 7( d ) is a CC′ longitudinal cross section corresponding to a power semiconductor device structure provided in Embodiment 7 of the present invention.

[0054] FIG8(a) is a layout structure of a power semiconductor device provided by Embodiment 8 of the present invention. The A-A' cross section is set as the cross section from the second conductivity type source region 106 to the second conductivity type drain region 107 and passing through the planar gate electrode 109; the BB' cross section is the cross section from the second conductivity type source region 106 to the second conductivity type drain region 107 and passing through the trench gate electrode 110; the CC' longitudinal cross section is the cross section of the region where the planar gate electrode 109 and the trench gate electrode 110 are alternately arranged.

[0055] FIG8( b ) is a BB′ cross section corresponding to a power semiconductor device structure provided in Embodiment 8 of the present invention.

[0056] FIG8( c ) is a CC′ longitudinal cross section corresponding to a power semiconductor device structure provided in Embodiment 8 of the present invention.

[0057] FIG9(a) is a layout structure of a power semiconductor device provided by Embodiment 9 of the present invention. The A-A' cross section is set as a cross section from the first conductive type contact region 105 to the second conductive type drain region 107 and passing through the planar gate electrode 109; the BB' cross section is a cross section from the first conductive type contact region 105 to the second conductive type drain region 107 and passing through the trench gate electrode 110 and the shield gate electrode 118; the CC' longitudinal cross section is a cross section of the region where the planar gate electrode 109 and the trench gate electrode 110 are alternately arranged.

[0058] FIG9( b ) is a BB′ cross section corresponding to a power semiconductor device structure provided in Embodiment 9 of the present invention.

[0059] FIG9( c ) is a CC′ longitudinal cross section corresponding to a power semiconductor device structure provided in Embodiment 9 of the present invention.

[0060] Among them, 101 is a first conductive type substrate, 102 is a first conductive type buried layer, 103 is a first conductive type body region, 104 is a second conductive type drift region, 105 is a first conductive type contact region, 106 is a second conductive type source region, 107 is a second conductive type drain region, 108 is a planar gate oxide layer, 109 is a planar gate electrode, 110 is a trench gate electrode, 111 is a trench gate oxide layer, 112 is a field oxide layer, 113 is a stress oxide layer, 114 is a second conductive type source region extension region, 115 is a drain region electrode metal, 116 is a source region electrode metal, 117 is a dielectric isolation layer, 118 is a shielding gate electrode, 119 is a first conductive type protection region, and 120 is a first conductive type body buried layer. DETAILED DESCRIPTION

[0061] To make the description of the present invention clearer, the following describes the embodiments of the present invention through specific examples, and those skilled in the art can understand the advantages and application modes of the present invention from the contents disclosed in this specification. The details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the principles of the present invention.

[0062] In the following embodiments:

[0063] The planar gate electrode may be polysilicon, or other suitable materials such as metal.

[0064] The trench gate electrode may be made of polysilicon or other suitable materials such as metal.

[0065] The shielding gate electrode may be polysilicon, or other suitable materials such as metal.

[0066] The potential of the shielding gate electrode can be consistent with that of the source, or can be provided by a bias circuit.

[0067] The gate oxide layer can be silicon dioxide or a high dielectric constant material.

[0068] The dielectric isolation layer between the channel gate electrode and the shielding gate electrode may be silicon dioxide or other insulating materials.

[0069] The first conductivity type is P-type doping and the second conductivity type is N-type doping; or the first conductivity type is N-type doping and the second conductivity type is P-type doping. The description herein is based on the assumption that the first conductivity type is P-type doping and the second conductivity type is N-type doping.

[0070] Example 1

[0071] like Figure 1 As shown, the present embodiment provides a low-voltage small-size LDMOS structure with an advanced process, which is also the device mainly optimized by the present invention. The structure of the embodiment includes a first conductive type substrate 101, a first conductive type buried layer 102 is arranged on the first conductive type substrate 101, a first conductive type body region 103 and a second conductive type drift region 104 are arranged above the first conductive type buried layer 102; a first conductive type contact region 105 and a second conductive type source region 106 are arranged above the first conductive type body region 103, wherein the first conductive type contact region 105 is located to the left of the second conductive type source region 106; a second conductive type drain region 107 is arranged in the upper right of the second conductive type drift region 104; a planar gate oxide layer 108 is arranged above the first conductive type body region 103 and above part of the second conductive type drift region 104, and a planar gate electrode 109 is arranged directly above the planar gate oxide layer 108.

[0072] This embodiment is a low-voltage small-size device structure. The biggest difference from the high-voltage structure is that the length of its second conductive type drift region 104 is less than or equal to its depth; therefore, it is necessary to design a first conductive type body region 103 and a first conductive type buried layer 102 with appropriate doping concentrations, and use these two regions to two-dimensionally deplete the second conductive type drift region 104 according to the charge balance principle, so that the second conductive type drift region 104 can fully withstand the voltage and ensure the current control capability.

[0073] Example 2

[0074] As shown in FIG. 2( a ), FIG. 2( b ), FIG. 2( c ) and FIG. 2( d ), the AA′ cross section of this embodiment is consistent with that of Embodiment 1, and Embodiment 2 is a TG-LDMOS device combined with a trench gate.

[0075] Assume that: the AA' cross section is a cross section from the first conductive type contact region 105 to the second conductive type drain region 107 and passing through the planar gate electrode 109; the BB' cross section is a cross section from the first conductive type contact region 105 to the second conductive type drain region 107 and passing through the trench gate electrode 110; the CC' longitudinal cross section is a cross section of the region where the planar gate electrode 109 and the trench gate electrode 110 are alternately arranged;

[0076] As shown in FIG2(c), along the BB' cross section, it includes a first conductive type substrate 101, a first conductive type buried layer 102 is arranged on the first conductive type substrate 101, a first conductive type body region 103 and a second conductive type drift region 104 are arranged above the first conductive type buried layer 102; a first conductive type contact region 105, a second conductive type source region 106, a second conductive type source region extension region 114 and a trench region are arranged above the first conductive type body region 103; wherein the first conductive type contact region 105 is located to the left of the second conductive type source region 106, the second conductive type source region extension region 114 is located below the second conductive type source region 106, the trench region is located to the right of the second conductive type source region 106 and the second conductive type source region extension region 114, and a part of the trench structure is located in the second conductive type drift region 104; wherein the bottom depth of the trench region is equal to or less than the depth of the second conductive type source region extension region 114;

[0077] The trench region is provided with a trench gate oxide layer 111 and a trench gate electrode 110 from bottom to top, and the trench gate oxide layer 111 is provided between the trench gate electrode 110 and the second conductivity type source region 106, the second conductivity type source region extension region 114, the first conductivity type body region 103 and the second conductivity type drift region 104 respectively;

[0078] A second conductivity type drain region 107 is disposed in the upper right corner of the second conductivity type drift region 104;

[0079] As shown in Figure 2(d), along the CC' longitudinal section, a planar gate oxide layer 108 is arranged above the first conductivity type body region 103 and above a portion of the second conductivity type drift region 104, and a planar gate electrode 109 is arranged directly above the planar gate oxide layer 108; wherein the planar gate electrode 109 and the trench gate electrode 110 are arranged alternately in the width direction, and in actual process manufacturing, the planar gate electrode 109 and the trench gate electrode 110 are connected, and the trench gate oxide layer 111 is connected to the planar gate oxide layer 108.

[0080] The structure of Example 2 transfers the planar channel in the original groove area to the bottom of the groove by designing the groove and the second conductive type source region extension area 114 structure, while ensuring the original channel width, introducing a channel of additional width through the groove sidewall, which is equivalent to connecting multiple channel resistors in parallel to reduce the channel resistance. The additionally introduced channel width is equal to twice the trench depth, so the magnitude of the channel resistance decreases with the increase of the depth of the trench gate electrode; and in the width direction, the smaller the trench width, the greater the ratio of the trench gate to the planar gate, and the more obvious the reduction in channel resistance. On the other hand, the trench gate electrode 110 in the second conductive type drift region 104 is also equivalent to an additionally introduced field plate, which can assist in the depletion of the second conductive type drift region 104. And the more trench regions are introduced, the more obvious the field plate effect is, which has an impact on the overall BV and R of the device. SP In the actual manufacturing process, the trench gate electrode 110 and the planar gate electrode 109 are manufactured using the same process.

[0081] Example 3

[0082] As shown in Fig. 3(a) and Fig. 3(b), the A-A' cross section and the C-C' longitudinal section of this embodiment are consistent with those of Embodiment 2. Embodiment 3 is an optimization scheme for the structure of Embodiment 2, the main difference being that a field oxide layer 112 is provided on one side of the trench gate electrode 110 close to the drain region inside the trench region, the thickness of the field oxide layer 112 is greater than the thickness of the trench gate oxide layer 111 and increases with the increase of the device voltage level, as shown in Fig. 3(b). Due to the additional introduction of the trench gate electrode, the total gate charge of the device increases, and the gate-drain parasitic capacitance increases, which will increase the switching loss of the device. Therefore, in order to reduce the influence of the gate-drain parasitic capacitance, the present embodiment is provided with a field oxide layer 112, and by increasing the insulating region between the trench gate electrode 110 and the second conductive type drain region 107, the dielectric constant of the dielectric layer between the gate and the drain is reduced, thereby reducing the gate-drain parasitic capacitance and improving the dynamic characteristics of the device.

[0083] Example 4

[0084] As shown in FIG. 4(a) and FIG. 4(b), the A-A' cross section and the CC' longitudinal section of this embodiment are consistent with those of Embodiment 2. Embodiment 4 is another optimization scheme for the structure of Embodiment 2, and can also be further optimized on the basis of Embodiment 3. The main difference is that a first conductive type protection zone 119 is provided inside the second conductive type drift region 104, as shown in FIG. 4(b). The first conductive type protection zone 119 is provided on the right side of the trench region and contacts the trench gate oxide layer 111, and the depth of the first conductive type protection zone 119 is greater than or equal to the trench depth. The design principle is to use the PN junction depletion layer formed between the first conductive type protection zone 119 and the second conductive type drift region 104 to act as an isolation layer of the gate, thereby reducing the gate-drain parasitic capacitance and improving the dynamic characteristics of the device. On the other hand, the first conductive type protection zone 119 can protect the trench gate oxide layer 111 and assist in depleting the second conductive type drift region 104, thereby reducing the on-resistance while ensuring the device's withstand voltage capability and optimizing the device's static characteristics.

[0085] Example 5

[0086] As shown in FIG. 5( a ), FIG. 5( b ) and FIG. 5( c ), the AA′ cross section of this embodiment is consistent with that of Embodiment 2. Embodiment 5 is a structure provided by combining the structure of Embodiment 2 with the groove stress technology.

[0087] Assume that: the AA' cross section is a cross section from the first conductive type contact region 105 to the second conductive type drain region 107 and passing through the planar gate electrode 109; the BB' cross section is a cross section from the first conductive type contact region 105 to the second conductive type drain region 107 and passing through the trench gate electrode 110; the CC' longitudinal cross section is a cross section of the region where the planar gate electrode 109 and the trench gate electrode 110 are alternately arranged;

[0088] As shown in FIG5(b), along the BB' cross section, it includes a first conductive type substrate 101, a first conductive type buried layer 102 is arranged on the first conductive type substrate 101, a first conductive type body region 103 and a second conductive type drift region 104 are arranged above the first conductive type buried layer 102; a first conductive type contact region 105, a second conductive type source region 106, a second conductive type source region extension region 114 and a trench region are arranged above the first conductive type body region 103; wherein the first conductive type contact region 105 is located to the left of the second conductive type source region 106, the second conductive type source region extension region 114 is located below the second conductive type source region 106, the trench region is located to the right of the second conductive type source region 106 and the second conductive type source region extension region 114, and a portion of the trench structure is located in the second conductive type drift region 104; wherein the bottom depth of the trench region is equal to or less than the depth of the second conductive type source region extension region 114;

[0089] The trench region is provided with a trench gate oxide layer 111, a trench gate electrode 110 and a stress oxide layer 113 from bottom to top, and is provided with a trench gate oxide layer 111, a trench gate electrode 110, a stress oxide layer 113 and a trench gate electrode 110 from left to right, wherein the stress oxide layer 113 is surrounded by the trench gate electrode 110; the trench gate oxide layer 111 is provided between the trench gate electrode 110 and the second conductivity type source region 106, the second conductivity type source region extension region 114, the first conductivity type body region 103 and the second conductivity type drift region 104 respectively;

[0090] A second conductivity type drain region 107 is disposed in the upper right corner of the second conductivity type drift region 104;

[0091] As shown in Figure 5(c), along the CC' longitudinal section, a planar gate oxide layer 108 is arranged above the first conductivity type body region 103 and above a portion of the second conductivity type drift region 104, and a planar gate electrode 109 is arranged directly above the planar gate oxide layer 108; wherein the planar gate electrode 109 and the trench gate electrode 110 are arranged alternately in the width direction, and during the actual process, the planar gate electrode 109 and the trench gate electrode 110 are connected, and the trench gate oxide layer 111 is connected to the planar gate oxide layer 108.

[0092] In this embodiment, when the trench gate electrode 110 is manufactured in the actual process, a stress oxide layer 113 is grown inside the trench gate electrode 110, and the stress is transmitted to the channel region and the drift region around the trench through thermal expansion, thereby introducing tensile stress in the current direction, thereby improving the carrier mobility and reducing the channel resistance and the drift region resistance.

[0093] Example 6

[0094] As shown in Fig. 6(a) and Fig. 6(b), the A-A' cross section and CC' longitudinal section of this embodiment are consistent with those of Embodiment 2. Embodiment 6 is an optimization scheme for the structure of Embodiment 5. The difference from Embodiment 5 is that the trench region is provided with a trench gate oxide layer 111, a trench gate electrode 110 and a stress oxide layer 113 from bottom to top, and a trench gate oxide layer 111, a trench gate electrode 110, a stress oxide layer 113 and a field oxide layer 112 from left to right, wherein the stress oxide layer 113 is surrounded by the trench gate electrode 110 on three sides, and is in contact with the field oxide layer 112 on the side near the drain, and the thickness of the field oxide layer 112 is greater than the thickness of the trench gate oxide layer 111 and increases with the increase of the device voltage level. By removing the trench gate electrode 110 close to the drain side in the trench gate electrode 110 structure of Example 5 and providing a field oxide layer 112, the gate-drain overlap area is reduced and the dielectric constant of the dielectric layer between the gate and the drain is reduced to reduce the parasitic capacitance, thereby achieving the effect of optimizing the dynamic characteristics.

[0095] Example 7

[0096] As shown in Figure 7(a), Figure 7(b) , 7(c) As shown in FIG. 7( d ), this embodiment is a high-current TG-LDMOS structure with voltage level extension.

[0097] Assume that: the AA' cross section is a cross section from the first conductive type contact region 105 to the drain electrode metal 115 and passing through the planar gate electrode 109; the BB' cross section is a cross section from the first conductive type contact region 105 to the drain electrode metal 115 and passing through the trench gate electrode 110; the CC' longitudinal cross section is a cross section of the region where the planar gate electrode 109 and the trench gate electrode 110 are alternately arranged;

[0098] As shown in FIG. 7( c ), along the BB′ cross section, a first conductive type substrate 101 is included, a first conductive type buried layer 102 is provided on the first conductive type substrate 101, a first conductive type body region 103 and a second conductive type drift region 104 are provided above the first conductive type buried layer 102; a first conductive type contact region 105, a second conductive type source region 106, a second conductive type source region extension region 114 and a trench region are provided above the first conductive type body region 103; wherein the first conductive type contact region 105 is located to the left of the second conductive type source region 106, the second conductive type source region extension region 114 is located below the second conductive type source region 106, the trench region is located to the right of the second conductive type source region 106 and the second conductive type source region extension region 114, and a portion of the trench structure is located in the second conductive type drift region 104; wherein the bottom depth of the trench region is equal to or less than the depth of the second conductive type source region extension region 114;

[0099] The trench region is provided with a trench gate oxide layer 111 and a trench gate electrode 110 from bottom to top, and the trench gate oxide layer 111 is provided between the trench gate electrode 110 and the second conductivity type source region 106, the second conductivity type source region extension region 114, the first conductivity type body region 103 and the second conductivity type drift region 104 respectively;

[0100] A second conductive type drain region 107 and a drain region electrode metal 115 are arranged in the upper right part of the second conductive type drift region 104; wherein the bottom depth of the drain region electrode metal 115 is greater than or equal to the bottom of the trench region, and the second conductive type drain region 107 is arranged in a surrounding manner on the left and below the drain region electrode metal 115;

[0101] As shown in Figure 7(d), along the CC' longitudinal section, a planar gate oxide layer 108 is arranged above the first conductivity type body region 103 and above a portion of the second conductivity type drift region 104, and a planar gate electrode 109 is arranged directly above the planar gate oxide layer 108; wherein the planar gate electrode 109 and the trench gate electrode 110 are arranged alternately in the width direction, and in actual process manufacturing, the planar gate electrode 109 and the trench gate electrode 110 are connected, and the trench gate oxide layer 111 is connected to the planar gate oxide layer 108.

[0102] This embodiment is a voltage level extension structure of the structure of embodiment 2. The voltage-resistant part of the device is divided into a depletion region between the first conductive type body region 103 and the second conductive type drift region 104 in the horizontal direction, and a depletion region between the first conductive type buried layer 102 and the second conductive type drift region 104 in the vertical direction. By increasing the length of the drift region, the body region and the trench region in the vertical direction, the voltage-resistant capability of the device is increased while also increasing the width-to-length ratio of the channel region, so that the channel resistance can be further reduced. At the same time, the drain region electrode metal 115 is grooved into the device body, and the second conductive type drain region 107 is extended vertically, so that the current path of the channel current in the lower half of the trench region can be shortened, thereby reducing the on-resistance.

[0103] Example 8

[0104] As shown in FIG. 8( a ), FIG. 8( b ) and FIG. 8( c ), the AA′ cross section and the CC′ longitudinal section are consistent with those of Example 2. FIG.

[0105] Embodiment 8 is a small-size structure design for preventing channel punch-through.

[0106] Assume that: the AA' cross section is a cross section from the second conductivity type source region 106 to the second conductivity type drain region 107 and passing through the planar gate electrode 109; the BB' cross section is a cross section from the second conductivity type source region 106 to the second conductivity type drain region 107 and passing through the trench gate electrode 110; the CC' longitudinal cross section is a cross section of the region where the planar gate electrode 109 and the trench gate electrode 110 are alternately arranged;

[0107] As shown in FIG8(b), along the BB' cross section, it includes a first conductive type substrate 101, a first conductive type buried layer 102 is arranged on the first conductive type substrate 101, and a first conductive type body region 103 and a second conductive type drift region 104 are arranged above the first conductive type buried layer 102; a first conductive type body buried layer 120 is arranged inside the first conductive type body region 103, and a first conductive type contact region 105, a second conductive type source region 106, a second conductive type source region extension region 114, a source region electrode metal 116 and a trench region are arranged above; wherein the source region electrode metal 116 is located in the middle of the second conductive type source region 106 and the depth exceeds the second conductive type source region 106. The first conductive type source region 106; the first conductive type contact region 105 is located below the source region electrode metal 116 and to the left of the second conductive type source region extension region 114; the second conductive type source region extension region 114 is located below the second conductive type source region 106 and in contact with the source region electrode metal 116, the trench region is located to the right of the second conductive type source region 106 and the second conductive type source region extension region 114, and part of the trench structure is located in the second conductive type drift region 104; wherein the bottom depth of the trench region is equal to or less than the depth of the second conductive type source region extension region 114; the first conductive type buried layer 120 is arranged below the trench region and is located in the first conductive type body region 103;

[0108] The trench region is provided with a trench gate oxide layer 111 and a trench gate electrode 110 from bottom to top, and the trench gate oxide layer 111 is provided between the trench gate electrode 110 and the second conductivity type source region 106, the second conductivity type source region extension region 114, the first conductivity type body region 103 and the second conductivity type drift region 104 respectively;

[0109] A second conductivity type drain region 107 is disposed in the upper right corner of the second conductivity type drift region 104;

[0110] As shown in Figure 8(c), along the CC' longitudinal section, a planar gate oxide layer 108 is arranged above the first conductivity type body region 103 and above a portion of the second conductivity type drift region 104, and a planar gate electrode 109 is arranged directly above the planar gate oxide layer 108; wherein the planar gate electrode 109 and the trench gate electrode 110 are arranged alternately in the width direction, and in actual process manufacturing, the planar gate electrode 109 and the trench gate electrode 110 are connected, and the trench gate oxide layer 111 is connected to the planar gate oxide layer 108.

[0111] In this embodiment, the source electrode metal 116 is designed inside the device body, and a first conductive type contact region 105 is provided below the source electrode metal 116. This design can reduce the area of ​​the first conductive type contact region 105, thereby reducing the overall size of the device. Considering the doping method of the first conductive type body region 103 during actual process manufacturing, the channel at the bottom of the trench is prone to punch-through, and reliability requires extra attention; therefore, the first conductive type buried layer 120 is provided to control the threshold of the bottom channel to prevent it from punching through.

[0112] Example 9

[0113] As shown in FIG. 9( a ), FIG. 9( b ) and FIG. 9( c ), the AA′ cross section and the CC′ longitudinal section are consistent with those of Example 2. FIG.

[0114] Assume that: the AA' cross section is a cross section from the first conductive type contact region 105 to the second conductive type drain region 107 and passing through the planar gate electrode 109; the BB' cross section is a cross section from the first conductive type contact region 105 to the second conductive type drain region 107 and passing through the trench gate electrode 110 and the shielding gate electrode 118; the CC' longitudinal cross section is a cross section of the region where the planar gate electrode 109 and the trench gate electrode 110 are alternately arranged;

[0115] As shown in FIG9(b), along the BB' cross section, it includes a first conductive type substrate 101, a first conductive type buried layer 102 is arranged on the first conductive type substrate 101, a first conductive type body region 103 and a second conductive type drift region 104 are arranged above the first conductive type buried layer 102; a first conductive type contact region 105, a second conductive type source region 106, a second conductive type source region extension region 114 and a trench region are arranged above the first conductive type body region 103; wherein the first conductive type contact region 105 is located to the left of the second conductive type source region 106, the second conductive type source region extension region 114 is located below the second conductive type source region 106, the trench region is located to the right of the second conductive type source region 106 and the second conductive type source region extension region 114, and a part of the trench structure is located in the second conductive type drift region 104; wherein the bottom depth of the trench region is equal to or less than the depth of the second conductive type source region extension region 114;

[0116] The trench region is provided with a trench gate oxide layer 111, a trench gate electrode 110, a dielectric isolation layer 117, a shielding gate electrode 118, and a field oxide layer 112 from left to right; wherein the trench gate oxide layer 111 is provided between the trench gate electrode 110 and the second conductive type source region 106, the second conductive type source region extension region 114, the first conductive type body region 103, and the second conductive type drift region 104 respectively; a dielectric isolation layer 117 is provided between the trench gate electrode 110 and the shielding gate electrode 118; a field oxide layer 112 is provided between the shielding gate electrode 118 and the second conductive type drift region 104, wherein the thickness of the field oxide layer 112 is greater than the thickness of the trench gate oxide layer 111 and increases with the increase of the device voltage level;

[0117] A second conductivity type drain region 107 is disposed in the upper right corner of the second conductivity type drift region 104;

[0118] As shown in Figure 9(c), along the C-C' longitudinal section, a planar gate oxide layer 108 is arranged above the first conductivity type body region 103 and above a portion of the second conductivity type drift region 104, and a planar gate electrode 109 is arranged directly above the planar gate oxide layer 108; wherein the planar gate electrode 109 and the trench gate electrode 110 are arranged alternately in the width direction, and in actual process manufacturing, the planar gate electrode 109 and the trench gate electrode 110 are connected, and the trench gate oxide layer 111 is connected to the planar gate oxide layer 108.

[0119] This embodiment is a structural design for optimizing the dynamic characteristics of the device. The overlapping area of ​​the gate and the drain is reduced by introducing a shielded gate electrode 118 on the right side of the trench gate electrode 110, thereby reducing the gate-drain parasitic capacitance. The potential of the shielded gate electrode 118 can be connected to the source potential or to an external bias circuit. The shielded gate electrode 118 is located in the second conductive type drift region 104 and can act as a field plate to assist in depleting the drift region and thus optimize the static characteristics of the device. The field oxide layer 112 can prevent the gate oxide layer from being broken down due to the excessive field strength in the trench region due to its proximity to the drain.

[0120] In addition to the above embodiments, all structures provided herein can be combined with each other, and various parameters can be adjusted according to actual process conditions and application requirements to achieve optimal device characteristics.

[0121] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A power semiconductor device, characterized in that: The invention comprises a first conductive type substrate (101), a first conductive type buried layer (102) is arranged on the first conductive type substrate (101), a first conductive type body region (103) and a second conductive type drift region (104) are arranged above the first conductive type buried layer (102); a first conductive type contact region (105) and a second conductive type source region (106) are arranged above the first conductive type body region (103), wherein the first conductive type contact region (105) is located to the left of the second conductive type source region (106); a second conductive type drain region (107) is arranged at the upper right of the second conductive type drift region (104); a planar gate oxide layer (108) is arranged above the first conductive type body region (103) and above part of the second conductive type drift region (104), and a planar gate electrode (109) is arranged directly above the planar gate oxide layer (108).

2. A power semiconductor device, characterized in that: It is assumed that: the A-A' cross section is a cross section from the first conductive type contact region (105) to the second conductive type drain region (107) and passing through the planar gate electrode (109); the BB' cross section is a cross section from the first conductive type contact region (105) to the second conductive type drain region (107) and passing through the trench gate electrode (110); the CC' longitudinal cross section is a cross section of the region where the planar gate electrode (109) and the trench gate electrode (110) are alternately arranged; The invention relates to a first conductive type substrate (101) along a BB' cross section, wherein a first conductive type buried layer (102) is arranged on the first conductive type substrate (101), a first conductive type body region (103) and a second conductive type drift region (104) are arranged above the first conductive type buried layer (102); a first conductive type contact region (105), a second conductive type source region (106), a second conductive type source region extension region (114) and a second conductive type contact region (105) are arranged above the first conductive type body region (103) A trench region; wherein the first conductive type contact region (105) is located to the left of the second conductive type source region (106), the second conductive type source region extension region (114) is located below the second conductive type source region (106), the trench region is located to the right of the second conductive type source region (106) and the second conductive type source region extension region (114), and a portion of the trench structure is located in the second conductive type drift region (104); wherein the bottom depth of the trench region is equal to or less than the depth of the second conductive type source region extension region (114); The trench region is provided with a trench gate oxide layer (111) and a trench gate electrode (110) from bottom to top, and the trench gate oxide layer (111) is provided between the trench gate electrode (110) and the second conductive type source region (106), the second conductive type source region extension region (114), the first conductive type body region (103) and the second conductive type drift region (104); A second conductive type drain region (107) is arranged at the upper right inside the second conductive type drift region (104); Along the CC' longitudinal section, a planar gate oxide layer (108) is arranged above the first conductivity type body region (103) and above a portion of the second conductivity type drift region (104), and a planar gate electrode (109) is arranged directly above the planar gate oxide layer (108); the planar gate electrode (109) and the trench gate electrode (110) are arranged alternately in the width direction, and in actual process manufacturing, the planar gate electrode (109) and the trench gate electrode (110) are connected, and the trench gate oxide layer (111) and the planar gate oxide layer (108) are connected.

3. The power semiconductor device according to claim 2, characterized in that: Along the BB' cross section, inside the trench region, a field oxide layer (112) is provided on the side of the trench gate electrode (110) close to the drain region, and its thickness is greater than that of the trench gate oxide layer (111) and increases with the increase of the device voltage level.

4. The power semiconductor device according to claim 2, characterized in that: Along the BB' cross section, a first conductive type protection zone (119) is arranged inside the second conductive type drift zone (104), the first conductive type protection zone (119) is arranged on the right side of the trench zone and in contact with the trench gate oxide layer (111), and the depth of the first conductive type protection zone (119) is greater than or equal to the trench depth.

5. A power semiconductor device, characterized in that: It is assumed that: the A-A' cross section is a cross section from the first conductive type contact region (105) to the second conductive type drain region (107) and passing through the planar gate electrode (109); the BB' cross section is a cross section from the first conductive type contact region (105) to the second conductive type drain region (107) and passing through the trench gate electrode (110); the CC' longitudinal cross section is a cross section of the region where the planar gate electrode (109) and the trench gate electrode (110) are alternately arranged; The invention relates to a first conductive type substrate (101) along a BB' cross section, wherein a first conductive type buried layer (102) is arranged on the first conductive type substrate (101), a first conductive type body region (103) and a second conductive type drift region (104) are arranged above the first conductive type buried layer (102); a first conductive type contact region (105), a second conductive type source region (106), a second conductive type source region extension region (114) and a second conductive type contact region (105) are arranged above the first conductive type body region (103) A trench region; wherein the first conductive type contact region (105) is located to the left of the second conductive type source region (106), the second conductive type source region extension region (114) is located below the second conductive type source region (106), the trench region is located to the right of the second conductive type source region (106) and the second conductive type source region extension region (114), and a portion of the trench structure is located in the second conductive type drift region (104); wherein the bottom depth of the trench region is equal to or less than the depth of the second conductive type source region extension region (114); The trench region is provided with a trench gate oxide layer (111), a trench gate electrode (110) and a stress oxide layer (113) from bottom to top, and is provided with a trench gate oxide layer (111), a trench gate electrode (110), a stress oxide layer (113) and a field oxide layer (112) from left to right, wherein the stress oxide layer (113) is surrounded by the trench gate electrode (110); the trench gate oxide layer (111) is provided between the trench gate electrode (110) and the second conductive type source region (106), the second conductive type source region extension region (114), the first conductive type body region (103) and the second conductive type drift region (104); A second conductive type drain region (107) is arranged at the upper right inside the second conductive type drift region (104); Along the CC' longitudinal section, a planar gate oxide layer (108) is arranged above the first conductivity type body region (103) and above a portion of the second conductivity type drift region (104), and a planar gate electrode (109) is arranged directly above the planar gate oxide layer (108); the planar gate electrode (109) and the trench gate electrode (110) are arranged alternately in the width direction, and in actual process manufacturing, the planar gate electrode (109) and the trench gate electrode (110) are connected, and the trench gate oxide layer (111) and the planar gate oxide layer (108) are connected.

6. The power semiconductor device according to claim 5, characterized in that: Along the BB' cross section, the trench region is provided with a trench gate oxide layer (111), a trench gate electrode (110) and a stress oxide layer (113) from bottom to top, and is provided with a trench gate oxide layer (111), a trench gate electrode (110), a stress oxide layer (113) and a field oxide layer (112) from left to right, wherein the stress oxide layer (113) is surrounded by the trench gate electrode (110) on three sides, and is in contact with the field oxide layer (112) on the side close to the drain, wherein the thickness of the field oxide layer (112) is greater than the thickness of the trench gate oxide layer (111) and increases with the increase of the device voltage level.

7. A power semiconductor device, characterized in that: It is assumed that: the A-A' cross section is a cross section from the first conductive type contact area (105) to the drain electrode metal (115) and passing through the planar gate electrode (109); the BB' cross section is a cross section from the first conductive type contact area (105) to the drain electrode metal (115) and passing through the trench gate electrode (110); the CC' longitudinal cross section is a cross section of the area where the planar gate electrode (109) and the trench gate electrode (110) are alternately arranged; The invention comprises a first conductive type substrate (101) along a BB' cross section, a first conductive type buried layer (102) is arranged on the first conductive type substrate (101), a first conductive type body region (103) and a second conductive type drift region (104) are arranged above the first conductive type buried layer (102); a first conductive type contact region (105), a second conductive type source region (106), and a second conductive type source region extension region (114) are arranged above the first conductive type body region (103) and a groove region; the first conductive type contact region (105) is located to the left of the second conductive type source region (106); the second conductive type source region extension region (114) is located below the second conductive type source region (106); the groove region is located to the right of the second conductive type source region (106) and the second conductive type source region extension region (114), and part of the groove structure is located in the second conductive type drift region (104); wherein the bottom depth of the groove region is equal to or less than the depth of the second conductive type source region extension region (114); The trench region is provided with a trench gate oxide layer (111) and a trench gate electrode (110) from bottom to top, and the trench gate oxide layer (111) is provided between the trench gate electrode (110) and the second conductive type source region (106), the second conductive type source region extension region (114), the first conductive type body region (103) and the second conductive type drift region (104); A second conductive type drain region (107) and a drain region electrode metal (115) are arranged at the upper right inside the second conductive type drift region (104); wherein the bottom depth of the drain region electrode metal (115) is greater than or equal to the bottom of the trench region, and the second conductive type drain region (107) is arranged in a surrounding manner on the left and below the drain region electrode metal (115); Along the CC' longitudinal section, a planar gate oxide layer (108) is arranged above the first conductivity type body region (103) and above a portion of the second conductivity type drift region (104), and a planar gate electrode (109) is arranged directly above the planar gate oxide layer (108); wherein the planar gate electrode (109) and the trench gate electrode (110) are arranged alternately in the width direction, and during actual process manufacturing, the planar gate electrode (109) and the trench gate electrode (110) are connected, and the trench gate oxide layer (111) and the planar gate oxide layer (108) are connected.

8. A power semiconductor device, characterized in that: It is assumed that: the A-A' cross section is a cross section from the second conductive type source region (106) to the second conductive type drain region (107) and passing through the planar gate electrode (109); the BB' cross section is a cross section from the second conductive type source region (106) to the second conductive type drain region (107) and passing through the trench gate electrode (110); the CC' longitudinal cross section is a cross section of the region where the planar gate electrode (109) and the trench gate electrode (110) are alternately arranged; The invention relates to a first conductive type substrate (101) along a BB' cross section, wherein a first conductive type buried layer (102) is arranged on the first conductive type substrate (101), and a first conductive type body region (103) and a second conductive type drift region (104) are arranged above the first conductive type buried layer (102); a first conductive type body buried layer (120) is arranged inside the first conductive type body region (103), and a first conductive type contact region (105), a second conductive type source region (106), a second conductive type source region extension region (114), a source region electrode metal (116) and a trench region are arranged above the first conductive type body region (103); wherein the source region electrode metal (116) is located in the middle of the second conductive type source region (106) and has a depth exceeding the second conductive type. A source region (106); a first conductive type contact region (105) is located below the source region electrode metal (116) and to the left of the second conductive type source region extension region (114); the second conductive type source region extension region (114) is located below the second conductive type source region (106) and in contact with the source region electrode metal (116); a trench region is located to the right of the second conductive type source region (106) and the second conductive type source region extension region (114), and a portion of the trench structure is located in the second conductive type drift region (104); wherein the bottom depth of the trench region is equal to or less than the depth of the second conductive type source region extension region (114); a first conductive type buried layer (120) is arranged below the trench region and in the first conductive type body region (103); The trench region is provided with a trench gate oxide layer (111) and a trench gate electrode (110) from bottom to top, and the trench gate oxide layer (111) is provided between the trench gate electrode (110) and the second conductive type source region (106), the second conductive type source region extension region (114), the first conductive type body region (103) and the second conductive type drift region (104); A second conductive type drain region (107) is arranged at the upper right inside the second conductive type drift region (104); Along the CC' longitudinal section, a planar gate oxide layer (108) is arranged above the first conductivity type body region (103) and above a portion of the second conductivity type drift region (104), and a planar gate electrode (109) is arranged directly above the planar gate oxide layer (108); wherein the planar gate electrode (109) and the trench gate electrode (110) are arranged alternately in the width direction, and during actual process manufacturing, the planar gate electrode (109) and the trench gate electrode (110) are connected, and the trench gate oxide layer (111) and the planar gate oxide layer (108) are connected.

9. A power semiconductor device, characterized in that: It is assumed that: the A-A' cross section is a cross section from the first conductive type contact region (105) to the second conductive type drain region (107) and passing through the planar gate electrode (109); the BB' cross section is a cross section from the first conductive type contact region (105) to the second conductive type drain region (107) and passing through the trench gate electrode (110) and the shielding gate electrode (118); the CC' longitudinal cross section is a cross section of the region where the planar gate electrode (109) and the trench gate electrode (110) are alternately arranged; The invention relates to a first conductive type substrate (101) along a BB' cross section, wherein a first conductive type buried layer (102) is arranged on the first conductive type substrate (101), a first conductive type body region (103) and a second conductive type drift region (104) are arranged above the first conductive type buried layer (102); a first conductive type contact region (105), a second conductive type source region (106), a second conductive type source region extension region (114) and a second conductive type contact region (105) are arranged above the first conductive type body region (103) A trench region; wherein the first conductive type contact region (105) is located to the left of the second conductive type source region (106), the second conductive type source region extension region (114) is located below the second conductive type source region (106), the trench region is located to the right of the second conductive type source region (106) and the second conductive type source region extension region (114), and a portion of the trench structure is located in the second conductive type drift region (104); wherein the bottom depth of the trench region is equal to or less than the depth of the second conductive type source region extension region (114); The trench region is provided with a trench gate oxide layer (111), a trench gate electrode (110), a dielectric isolation layer (117), a shielding gate electrode (118), and a field oxide layer (112) from left to right; wherein the trench gate electrode (110) is provided with a trench gate oxide layer (111) respectively between the second conductive type source region (106), the second conductive type source region extension region (114), the first conductive type body region (103), and the second conductive type drift region (104); and a dielectric isolation layer (117) is provided between the trench gate electrode (110) and the shielding gate electrode (118); and a field oxide layer (112) is provided between the shielding gate electrode (118) and the second conductive type drift region (104); wherein the thickness of the field oxide layer (112) is greater than the thickness of the trench gate oxide layer (111) and increases with the increase of the device voltage level; A second conductive type drain region (107) is arranged at the upper right inside the second conductive type drift region (104); Along the CC' longitudinal section, a planar gate oxide layer (108) is arranged above the first conductivity type body region (103) and above a portion of the second conductivity type drift region (104), and a planar gate electrode (109) is arranged directly above the planar gate oxide layer (108); wherein the planar gate electrode (109) and the trench gate electrode (110) are arranged alternately in the width direction, and during actual process manufacturing, the planar gate electrode (109) and the trench gate electrode (110) are connected, and the trench gate oxide layer (111) and the planar gate oxide layer (108) are connected.

Images