A semi-superjunction high-reliability planar-gate silicon carbide VDMOS and its manufacturing method

Abstract

The present invention provides a semi-superjunction high-reliability planar-gate silicon carbide VDMOS and a manufacturing method thereof. The method includes: depositing metal on the lower side of a silicon carbide substrate to form a drain metal layer; epitaxially growing on the upper side of the silicon carbide substrate to form a first drift region; forming a blocking layer, etching, and ion implanting to form a column region; removing the blocking layer, epitaxially growing on the first drift region to form a second drift region, and the drift layer includes the first drift region and the second drift region; forming a blocking layer, etching, and ion implanting to form a first P-type well region, a protrusion, a second P-type well region, an N-type source region, and a Schottky region; reforming the blocking layer, etching, and depositing to form a gate dielectric layer; reforming the blocking layer, etching, and depositing metal to form a gate metal layer; reforming the blocking layer, etching, and depositing metal to form a source metal layer, and removing the blocking layer to complete the manufacturing, which can provide double protection during reverse voltage withstand, thereby improving the reliability of the device.

Description

Technical Field

[0001] The present invention relates to a semi-superjunction high-reliability planar-gate silicon carbide VDMOS and a preparation method thereof. Background Art

[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices and has wide applications in fields such as electric vehicles, aerospace, and power conversion. For silicon carbide power VDMOS, the performance requirements for the device vary in different fields. For the aerospace and automotive electronics fields, the requirement for the high reliability of the device is relatively high, and there is a continuous need to provide a VDMOS with high reliability. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a semi-superjunction high-reliability planar-gate silicon carbide VDMOS and a preparation method thereof, which can provide double protection during reverse voltage withstand, thereby improving the reliability of the device.

[0004] In a first aspect, the present invention provides a preparation method of a semi-superjunction high-reliability planar-gate silicon carbide VDMOS, including the following steps:

[0005] Step 1: Deposit metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially grow on the upper side of the silicon carbide substrate to form a first drift region;

[0006] Step 2: Form a blocking layer above the first drift region, etch the blocking layer to form a through hole, and perform ion implantation to form a column region;

[0007] Step 3: Remove the blocking layer, epitaxially grow on the first drift region to form a second drift region, and the drift layer includes the first drift region and the second drift region;

[0008] Step 4: Form a blocking layer above the second drift region, etch the blocking layer to form a through hole, and perform ion implantation into the second drift region to form a first P-type well region and a protrusion;

[0009] Step 5: Remove the original blocking layer, re-form a blocking layer, etch the blocking layer to form a through hole, and perform ion implantation into the first P-type well region to form a second P-type well region;

[0010] Step 6: Remove the original blocking layer, re-form a blocking layer, etch the blocking layer to form a through hole, and perform ion implantation into the second P-type well region to form an N-type source region;

[0011] Step 7: Remove the original blocking layer, re-form a blocking layer, etch the blocking layer to form a through hole, and perform ion implantation into the second drift region to form a Schottky region;

[0012] Step 8: Remove the original blocking layer, re-form a blocking layer, etch the blocking layer to form a through hole, and deposit to form a gate dielectric layer;

[0013] Step 9: Remove the original barrier layer, reform the barrier layer, etch the barrier layer to form a through hole, deposit metal, and form a gate metal layer;

[0014] Step 10: Remove the original barrier layer, reform the barrier layer, etch the barrier layer to form a through hole, deposit metal, form a source metal layer, remove the barrier layer, and complete the preparation.

[0015] In a second aspect, the present invention provides a semi-superjunction high-reliability planar-gate silicon carbide VDMOS, which is prepared by using the preparation method of a semi-superjunction high-reliability planar-gate silicon carbide VDMOS described in the first aspect.

[0016] The advantages of the present invention are as follows:

[0017] First, by constructing a column region in the drift layer, the present invention realizes the semi-superjunction device structure of the device, thereby improving the breakdown voltage capability of the device and reducing the on-resistance of the device;

[0018] Second, in the gate structure of the device, the present invention constructs a first P-type well region and a second P-type well region wrapped by the first P-type well region. The second P-type well region is located on the side away from the gate metal layer and below the N-type source region, and the first P-type well region is located on the side close to the gate metal layer. There is an overlap between the N-type source region of the device and the gate metal layer in the horizontal direction. Among them, the second P-type well region can ensure the reverse breakdown voltage capability of the device, and the first P-type well region on the side of the N-type source region close to the gate can ensure low gate charge and fast switching speed, improving the device performance in terms of the breakdown voltage reliability and switching characteristics of the device; the second P-type well region wraps the N-type source region, which can improve the freewheeling capability of the body diode of the device;

[0019] Third, the present invention constructs a Schottky region, which can construct a parasitic Schottky body diode of the device and reduce the freewheeling loss of the body diode of the device. Description of the Drawings

[0020] The following further describes the present invention with reference to the drawings in conjunction with embodiments.

[0021] Figure 1 It is a schematic diagram of a semi-superjunction high-reliability planar-gate silicon carbide VDMOS of the present invention.

[0022] Figure 2 It is a process cross-section of a semi-superjunction high-reliability planar-gate silicon carbide VDMOS of the present invention Figure 1 。

[0023] Figure 3 It is a process cross-section of a semi-superjunction high-reliability planar-gate silicon carbide VDMOS of the present invention Figure 2 。

[0024] Figure 4Process cross-section of a semi-superjunction high-reliability planar-gate silicon carbide VDMOS according to the present invention Figure 3 。

[0025] Figure 5 Process cross-section of a semi-superjunction high-reliability planar-gate silicon carbide VDMOS according to the present invention Figure 4 。

[0026] Figure 6 Process cross-section of a semi-superjunction high-reliability planar-gate silicon carbide VDMOS according to the present invention Figure 5 。

[0027] Figure 7 Process cross-section of a semi-superjunction high-reliability planar-gate silicon carbide VDMOS according to the present invention Figure 6 。

[0028] Figure 8 Process cross-section of a semi-superjunction high-reliability planar-gate silicon carbide VDMOS according to the present invention Figure 7 。

[0029] Figure 9 Process cross-section of a semi-superjunction high-reliability planar-gate silicon carbide VDMOS according to the present invention Figure 8 。

[0030] Figure 10 Process cross-section of a semi-superjunction high-reliability planar-gate silicon carbide VDMOS according to the present invention Figure 9 。

[0031] Figure 11 Process cross-section of a semi-superjunction high-reliability planar-gate silicon carbide VDMOS according to the present invention Figure 10 。 Detailed implementation manners

[0032] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this application belongs. The terms used in the specification of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0034] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "in contact with", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Thus, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below may be referred to as a second element, component, region, layer or part.

[0035] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. are used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientation depicted in the figures, spatial relationship terms also encompass different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. Additionally, the device may also assume additional orientations (such as, for example, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0036] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / include" or "has" etc. specify the presence of the stated features, wholes, steps, operations, components, parts or combinations thereof, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0037] As Figures 1 to 11 shown, an embodiment of the present application provides a method for preparing a semi-superjunction high-reliability planar-gate silicon carbide VDMOS, comprising the following steps:

[0038] Step 1: Deposit metal on the lower side of the silicon carbide substrate 1 to form a drain metal layer 8; epitaxially grow on the upper side of the silicon carbide substrate 1 to form a first drift region 23;

[0039] Step 2: Form a blocking layer 9 above the first drift region 23, etch the blocking layer 9 to form a through hole, and perform ion implantation to form a column region 21;

[0040] Step 3: Remove the blocking layer 9, epitaxially grow on the first drift region 23 to form a second drift region 24, and the drift layer 2 includes the first drift region 23 and the second drift region 24;

[0041] Step 4: Form a blocking layer 9 above the second drift region 24, etch the blocking layer 9 to form a through hole, and perform ion implantation into the second drift region 24 to form a first P-type well region 3 and a protrusion 22;

[0042] Step 5: Remove the original blocking layer, reform the blocking layer 9, etch the blocking layer 9 to form a through hole, and perform ion implantation into the first P-type well region 3 to form a second P-type well region 31;

[0043] Step 6: Remove the original blocking layer, reform the blocking layer 9, etch the blocking layer 9 to form a through hole, and perform ion implantation into the second P-type well region 31 to form an N-type source region 311;

[0044] Step 7: Remove the original blocking layer, reform the blocking layer 9, etch the blocking layer 9 to form a through hole, and perform ion implantation into the second drift region 24 to form a Schottky region 4;

[0045] Step 8: Remove the original blocking layer, reform the blocking layer 9, etch the blocking layer 9 to form a through hole, and deposit to form a gate dielectric layer 5;

[0046] Step 9: Remove the original blocking layer, reform the blocking layer 9, etch the blocking layer 9 to form a through hole, and deposit metal to form a gate metal layer 6;

[0047] Step 10: Remove the original blocking layer, reform the blocking layer 9, etch the blocking layer 9 to form a through hole, deposit metal to form a source metal layer 7, and remove the blocking layer 9 to complete the preparation.

[0048] In this embodiment, preferably, the thickness of the column region 21 is less than the thickness of the drift layer 2.

[0049] In this embodiment, preferably, the column region 21 is located directly below the first P-type well region 3 and the second P-type well region 31, and the column region 21 is not located directly below the N-type source region 311, the protrusion 22, and the Schottky region 4.

[0050] In this embodiment, preferably, the Schottky region 4, the drift layer 2, and the silicon carbide substrate 1 are all N-type; the column region 21 is P-type.

[0051] In this embodiment, preferably, the doping concentration of the Schottky region 4 is greater than that of the first P-type well region 3; the doping concentration of the Schottky region 4 is less than that of the second P-type well region 31.

[0052] As Figure 1 shown, the silicon carbide VDMOS obtained by the above manufacturing method includes:

[0053] A silicon carbide substrate 1;

[0054] A drift layer 2, the lower side of the drift layer 2 is connected to the upper side of the silicon carbide substrate 1; a column region 21 is provided in the drift layer 2, the lower side of the column region 21 is connected to the silicon carbide substrate 1, and a convex portion 22 is provided on the drift layer 2;

[0055] A first P-type well region 3, the lower side of the first P-type well region 3 is connected to the upper side of the drift layer 2, and the inner side of the first P-type well region 3 is connected to the outer side of the convex portion 22; a second P-type well region 31 is provided on the first P-type well region 3, and an N-type source region 311 is provided on the second P-type well region 31, and the inner side of the N-type source region 311 is connected to the first P-type well region 3;

[0056] A Schottky region 4, the lower side of the Schottky region 4 is connected to the upper side of the drift layer 2, and the inner side of the Schottky region 4 is respectively connected to the first P-type well region 3 and the second P-type well region 31;

[0057] A gate dielectric layer 5, the lower side of the gate dielectric layer 5 is respectively connected to the N-type source region 311 and the first P-type well region 3;

[0058] A gate metal layer 6, the gate metal layer 6 is connected to the gate dielectric layer 5;

[0059] A source metal layer 7, the source metal layer 7 is respectively connected to the Schottky region 4, the second P-type well region 31 and the N-type source region 311;

[0060] And a drain metal layer 8, the drain metal layer 8 is connected to the lower side of the silicon carbide substrate 1.

[0061] In another embodiment of the present invention, the doping concentration of the N-type silicon carbide substrate 1 is 2 - 8e18 cm -3 , the doping concentration of the N-type drift layer 2 is 1 - 5e17 cm -3 , the doping concentration of the P-type column region 21 is 1 - 5e16 cm -3 , the doping concentration of the first P-type well region 3 is 1 - 6e17 cm -3 , the doping concentration of the second P-type well region 31 is 1 - 5e18 cm -3, the doping concentration of the N-type Schottky region 4 is 6 - 9e17 cm -3 , the material of the gate dielectric layer 5 can be one or a composite of silicon dioxide and silicon nitride, and the doping concentration of the N-type source region 311 is 2 - 8e18 cm -3 ;

[0062] The doping concentration of the N-type silicon carbide substrate 1 is to ensure a low-resistance ohmic contact with the drain metal layer 8; the doping concentration of the P-type column region 21 is to form a laterally distributed pn junction when the device drain bears a high voltage, so as to change the single longitudinal voltage withstand structure of the device into a transverse and longitudinal combined voltage withstand structure and improve the voltage withstand ability of the device; the doping concentration of the first P-type well region 3 is to form a graded junction when the N-type drift layer 2 and the P-type column region 21 of the device are reverse biased, avoiding device reliability problems caused by sudden changes in electric field strength; the second P-type well region 31 is to protect the device from drain-source breakdown during reverse biasing. At the same time, the second P-type well region 31 forms an ohmic contact with the source metal layer 7 to reduce the conduction loss of the parasitic pn junction body diode of the device; the N-type Schottky region 4 is to form the parasitic Schottky body diode of the device and reduce the conduction loss of the body diode of the device; the doping concentration of the N-type drift layer 2 is a compromise between the reverse voltage withstand and the on-resistance of the device, and the doping concentration of the N-type source region 311 is to reduce the source contact resistance of the device and the on-resistance of the device.

[0063] The thickness of the N-type silicon carbide substrate 1 of the device is 2 μm, which provides support during the manufacturing process. The thickness of the N-type drift layer 2 is 50 - 100 μm and is adjusted within the above range according to different requirements for the voltage withstand characteristics of the device. The thickness of the P-type column region 21 is 80 - 90% of the thickness of the N-type drift layer 2 to achieve a transverse and longitudinal combined voltage withstand for the device, and during reverse biasing, the space charge region of the first P-type well region 3 can contact the region of the P-type column region 21, thus ensuring the reverse voltage withstand characteristics of the device. The width of the N-type source region 311 of the device is 500 nm - 2 μm, and the width of the second P-type well region 31 is 3 - 5 times the width of the N-type source region, which is to ensure the wrapping of the second P-type well region 31 at the bottom and on the side far from the gate to ensure the voltage withstand characteristics of the device; the width of the first P-type well region 3 is 300 nm larger than the width of the second P-type well region 31, which is to form the gate control structure of the device. The thickness of the N-type source region 311 is 200 nm, the thickness of the second P-type well region 31 is 400 nm, the thickness of the first P-type well region 3 is 600 nm, the thickness of the N-type Schottky region 4 is 600 nm, the width of the N-type Schottky region 4 is equal to the width of the N-type source region 311, the thickness of the gate dielectric layer 5 is 50 nm, the thickness of the source metal layer 7 is 200 nm, and the thickness of the gate metal layer 6 is 150 nm;

[0064] In this embodiment, a column region 21 is constructed in the drift layer 2 to implement a semi-superjunction device structure of the device, thereby improving the breakdown voltage capability of the device and reducing the on-resistance of the device; a first P-type well region 3 and a second P-type well region 31 wrapped by the first P-type well region 3 are constructed in the gate structure of the device. The side and the lower part of the N-type source region 311 away from the gate metal layer 6 are the second P-type well region 31, and the side close to the gate metal layer 6 is the first P-type well region 3. The N-type source region 311 of the device overlaps with the gate metal layer 6 in the transverse direction. Among them, the second P-type well region 31 can ensure the reverse breakdown voltage capability of the device, and the first P-type well region 3 on the side of the N-type source region 311 close to the gate metal layer 6 can ensure low gate charge and fast switching speed of the device, and improve the device performance from the aspects of breakdown voltage reliability and switching characteristics of the device; the second P-type well region 31 wraps the N-type source region 311, which can improve the freewheeling capability of the body diode of the device; the Schottky region 4 can construct a parasitic Schottky body diode of the device and reduce the freewheeling loss of the body diode of the device.

[0065] Although the specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments we described are illustrative rather than used to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be covered by the scope protected by the claims of the present invention.

Claims

1. A preparation method of a semi-superjunction high-reliability planar-gate silicon carbide VDMOS, characterized in that: It includes the following steps: Step 1: Deposit metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially grow on the upper side of the silicon carbide substrate to form a first drift region; Step 2: Form a blocking layer above the first drift region, etch the blocking layer to form a through hole, and perform ion implantation to form a column region; Step 3: Remove the blocking layer, epitaxially grow on the first drift region to form a second drift region, and the drift layer includes the first drift region and the second drift region; Step 4: Form a blocking layer above the second drift region, etch the blocking layer to form a through hole, and perform ion implantation into the second drift region to form a first P-type well region and a protrusion; Step 5: Remove the original blocking layer, re-form a blocking layer, etch the blocking layer to form a through hole, and perform ion implantation into the first P-type well region to form a second P-type well region; Step 6: Remove the original blocking layer, re-form a blocking layer, etch the blocking layer to form a through hole, and perform ion implantation into the second P-type well region to form an N-type source region; Step 7: Remove the original blocking layer, re-form a blocking layer, etch the blocking layer to form a through hole, and perform ion implantation into the second drift region to form a Schottky region; Step 8: Remove the original blocking layer, re-form a blocking layer, etch the blocking layer to form a through hole, and deposit to form a gate dielectric layer; Step 9: Remove the original blocking layer, re-form a blocking layer, etch the blocking layer to form a through hole, and deposit metal to form a gate metal layer; Step 10: Remove the original blocking layer, re-form a blocking layer, etch the blocking layer to form a through hole, deposit metal to form a source metal layer, and remove the blocking layer to complete the preparation; The second P-type well region wraps the first P-type well region. The N-type source region is on the side away from the gate metal layer and the second P-type well region is below it, and the first P-type well region is on the side close to the gate metal layer. The N-type source region has a lateral overlap with the gate metal layer.

2. The manufacturing method of a semi-superjunction high-reliability planar-gate silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the column region is less than the thickness of the drift layer.

3. The manufacturing method of a semi-super junction high-reliability planar-gate silicon carbide VDMOS according to claim 1, characterized in that: The column region is directly below the first P-type well region and the second P-type well region, and the column region is not directly below the N-type source region, the protrusion, and the Schottky region.

4. The manufacturing method of a semi-superjunction high-reliability planar-gate silicon carbide VDMOS as described in claim 1, characterized in that: The Schottky region, the drift layer, and the silicon carbide substrate are all N-type; the column region is P-type.

5. The manufacturing method of a semi-superjunction high-reliability planar-gate silicon carbide VDMOS as claimed in claim 1, wherein: The doping concentration of the Schottky region is greater than the doping concentration of the first P-type well region; the doping concentration of the Schottky region is less than the doping concentration of the second P-type well region.

6. A semi-superjunction high-reliability planar-gate silicon carbide VDMOS, characterized in that, The silicon carbide VDMOS is prepared by the preparation method described in any one of claims 1 to 5.

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