High-surge MOS device and preparation method thereof

Abstract

The invention relates to a high-surge MOS device and a preparation method thereof, the high-surge MOS device comprises at least two gate structures, a second conduction type body region, a first conduction type first source region and a first conduction type second source region, the number of the gate structures is at least two, and the second conduction type body region is arranged between the two gate structures. The first conduction type first source regions are arranged in the first direction, the first conduction type second source regions are arranged in the first direction, and the first conduction type first source regions and the first conduction type second source regions are located at different positions in the second direction. The first conduction type first source regions and the second conduction type second source regions are sequentially arranged in a staggered mode in the first direction, and the first conduction type first source regions are connected with the adjacent first conduction type second source regions. And the anti-surge capability of the MOS device is effectively enhanced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a high-surge MOS device and a preparation method thereof. Background Art

[0002] MOS (Metal Oxide Semiconductor) devices are important power semiconductor devices, widely used in power electronic equipment, industrial control systems and consumer electronics. They have attracted wide attention due to their high switching efficiency, low power consumption and excellent current control performance. In practical applications, MOS devices usually need to work in high voltage and high surge current environments, so their surge resistance directly affects the reliability and service life of the device.

[0003] Existing MOS devices such as Figure 1 As shown, a strip-shaped cell structure is usually adopted, a strip-shaped source region structure 14 is arranged in the body region structure 15, and the performance of the device is improved by optimizing the doping parameters and layout of the body region structure 15 and the source region structure 14.

[0004] However, in this design, the junction area of ​​the body structure is relatively small, which makes the junction area of ​​the P / N junction relatively small. When it needs to be used in a high surge current and high voltage impact environment, the carrier capacity of the P / N junction is limited and cannot effectively disperse the surge charge, which can easily lead to local overheating or even device breakdown, significantly affecting the surge resistance of the MOS device. Therefore, it is necessary to provide a MOS device that can significantly improve the surge resistance of the device to adapt to the application environment of high surge current and high voltage impact. Summary of the invention

[0005] In view of this, the purpose of the present invention is to provide a high surge MOS device and a preparation method thereof to solve the technical problems in the prior art that the junction area of ​​the body region is relatively small, the junction area of ​​the P / N junction is relatively small, and the surge resistance performance is poor.

[0006] The present invention provides a high-surge MOS device, comprising:

[0007] A gate structure, at least two of which are provided;

[0008] A second conductive type body region is disposed between the two gate structures;

[0009] A first conductive type first source region, disposed in a second conductive type body region and provided in plurality;

[0010] A second source region of the first conductivity type is disposed in the body region of the second conductivity type and is provided in plurality;

[0011] A plurality of first conductive type first source regions are arranged along a first direction, a plurality of first conductive type second source regions are arranged along the first direction, the first conductive type first source regions and the first conductive type second source regions are at different positions in the second direction, the first conductive type first source regions and the second conductive type second source regions are alternately arranged in sequence along the first direction, and the first conductive type first source regions are connected to adjacent first conductive type second source regions.

[0012] Optionally, a width of an overlapping portion of adjacent first conductivity type first source regions and first conductivity type second source regions in the second direction is less than half of a width of the first conductivity type first source region and / or the first conductivity type second source region in the second direction.

[0013] Optionally, a plurality of first conductive type first source regions and a plurality of first conductive type second source regions are arranged in an S-shape along the first direction.

[0014] Optionally, the first conductive type first source regions are arranged in two rows, the two rows of the first conductive type first source regions are arranged along the first direction, the first conductive type second source regions are located between the two rows of the first conductive type first source regions, and each row of the first conductive type first source regions is arranged alternately with multiple first conductive type second source regions along the first direction.

[0015] Optionally, the first conductive type first source region and the first conductive type second source region have the same size.

[0016] Optionally, it also includes:

[0017] a first conductive type substrate;

[0018] A first conductive type epitaxial layer is arranged on the front side of the first conductive type substrate, the gate structure is arranged on the front side of the first conductive type epitaxial layer, the second conductive type body region is arranged on the front side of the first conductive type epitaxial layer and is arranged in the first conductive type epitaxial layer, and the first conductive type first source region and the first conductive type second source region are located in the second conductive type body region.

[0019] Optionally, a first conductivity type high resistance region is disposed on the back side of the second conductivity type body region, and the resistivity of the first conductivity type high resistance region is higher than the resistivity of the first conductivity type epitaxial layer.

[0020] Optionally, a second conductive type extension column is further included, wherein the second conductive type extension column is arranged in the first conductive type high resistance region, and the second conductive type extension column is respectively connected to the second conductive type body region and the first conductive type epitaxial layer.

[0021] Optionally, at least two second conductivity type extension columns are correspondingly arranged at each second conductivity type body region, and a plurality of second conductivity type extension columns are arranged in the first conductivity type high resistance region at intervals along the first direction.

[0022] The present invention also provides a method for preparing a high-surge MOS device, comprising:

[0023] Selecting a first conductive type substrate, and growing a first conductive type epitaxial layer on the first conductive type substrate;

[0024] Depositing polysilicon on a partial area of ​​the front surface of the first conductive type epitaxial layer by photolithography masking to form a plurality of gate structures;

[0025] Implanting first conductivity type ions with high resistivity into the front surface of the first conductivity type epitaxial layer without a gate structure to form a first conductivity type high resistance region;

[0026] Implanting second conductive type ions at the first conductive type high resistance region to form second conductive type extension columns and second conductive type body regions;

[0027] Placing a plurality of staggered S-shaped photolithography shielding plates along a first direction on the front surface of the second conductive type body region, and implanting first conductive type ions in a region without the photolithography shielding plates on the front surface of the second conductive type body region, so as to form a first conductive type first source region and a first conductive type second source region;

[0028] An insulating dielectric layer and a front metal layer are formed on the front side of the first conductive type epitaxial layer, and a back metal layer is formed on the back side of the first conductive type substrate.

[0029] The technical solution of the present invention has the following advantages:

[0030] The high surge MOS device provided by the present invention can significantly increase the junction area of ​​the second conductivity type body region in the MOS device by setting a first conductivity type first source region and a first conductivity type second source region, and the first conductivity type first source region and the first conductivity type second source region are arranged in a staggered manner, thereby effectively increasing the junction area of ​​the P / N junction, and effectively enhancing the surge resistance of the MOS device, so that it can adapt to application environments with higher surge currents and high voltage shocks, and has wider adaptability. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0032] Figure 1 It is a schematic diagram of the prior art in the background technology of the present invention;

[0033] Figure 2 It is a schematic structural diagram of a high surge MOS device in the present invention;

[0034] Figure 3 It is a schematic diagram of the cross-sectional structure of the high surge MOS device in the present invention;

[0035] Figure 4 It is a step diagram of the method for preparing the high surge MOS device in the present invention.

[0036] Description of reference numerals:

[0037] 1. Gate structure; 2. Second conductivity type body region; 3. First conductivity type first source region; 4. First conductivity type second source region; 5. First conductivity type substrate; 6. First conductivity type epitaxial layer; 7. First conductivity type high resistance region; 8. Second conductivity type extension column; 9. Gate oxide layer; 10. Insulating dielectric layer; 11. Front metal layer; 12. Back metal layer; 13. Metal contact through hole; 14. Source region structure; 15. Body region structure. DETAILED DESCRIPTION

[0038] The specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the description of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0039] Unless otherwise clearly specified and limited, the terms "disposed", "installed", "connected" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0040] The directions or positional relationships indicated by terms such as “upper”, “lower”, “left”, “right”, “front”, “back”, “top”, “bottom”, “inside” and “outside” are based on the directions or positional relationships shown in the accompanying drawings, or are the directions or positional relationships in which the inventive product is usually placed when used. They are only for the convenience of description and simplified description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present invention.

[0041] The terms "first", "second", "third" and the like are merely used to distinguish elements of similar nature, and do not indicate or imply relative importance or a particular order.

[0042] The terms "comprises," "comprising," or any other variations thereof, are intended to cover a non-exclusive inclusion of the elements listed and may also include additional elements not expressly listed.

[0043] Example 1

[0044] The high surge MOS device includes an N-type MOS device and a P-type MOS device. For the N-type MOS device, the first conductivity type is N-type and the second conductivity type is P-type; for the P-type MOS device, the first conductivity type is P-type and the second conductivity type is N-type. In this embodiment, the N-type MOS device is taken as an example.

[0045] Reference Figure 2 and Figure 3 As shown, the present invention provides a high surge MOS device, comprising a gate structure 1, a second conductive type body region 2, a first conductive type first source region 3 and a first conductive type second source region 4, wherein at least two gate structures 1 are provided, and a gap is left between two adjacent gate structures 1 to provide the second conductive type body region 2, the first conductive type first source region 3 and the first conductive type second source region 4, the second conductive type body region 2 is provided between two adjacent gate structures 1, and the second conductive type body region 2 is provided between two adjacent gate structures 1;

[0046] Both the first conductive type first source region 3 and the first conductive type second source region 4 are arranged in the second conductive type body region 2 and are multiple. The multiple first conductive type first source regions 3 are arranged along the first direction, and the multiple first conductive type second source regions 4 are arranged along the first direction. The first conductive type first source regions 3 and the first conductive type second source regions 4 are at different positions in the second direction, that is, two rows of first conductive type first source regions 3 and first conductive type second source regions 4 are arranged in parallel but not overlapped. The first conductive type first source regions 3 and the second conductive type second source regions 4 are alternately arranged in sequence along the first direction, so that there is a second conductive type second source region 4 between two adjacent first conductive type first source regions 3, and there is a second conductive type first source region 3 between two adjacent first conductive type second source regions 4. The first conductive type first source region 3 is connected to two adjacent first conductive type second source regions 4, and the first conductive type second source region 4 is connected to two adjacent first conductive type first source regions 3, so that the multiple first conductive type first source regions 3 and the multiple first conductive type second source regions 4 are arranged in an S-shape along the first direction. In addition, for clarity of illustration, the arrow X direction in the figure is the first direction, and the arrow Y direction is the second direction.

[0047] By setting a first conductive type first source region 3 and a first conductive type second source region 4, and the first conductive type first source region 3 and the first conductive type second source region 4 are arranged in a staggered manner, the junction area of ​​the second conductive type body region 2 in the MOS device can be significantly increased, thereby effectively increasing the junction area of ​​the P / N junction, and effectively enhancing the surge resistance of the MOS device, so that it can adapt to application environments with higher surge currents and high voltage shocks, and has a wider adaptability.

[0048] As a specific implementation method, refer to Figure 2 As shown, the first conductive type first source region 3 and the first conductive type second source region 4 have the same size, and the first conductive type first source region 3 and the first conductive type second source region 4 have overlapping parts in the second direction, and the width of the overlapping part is smaller than half of the width of the first conductive type first source region 3 and / or the first conductive type second source region 4 along the second direction. Through such a setting, it can be ensured that the first conductive type first source region 3 and the first conductive type second source region 4 are connected, and at the same time, the junction area of ​​the P / N junction can be maximized, thereby ensuring that the MOS device has the strongest surge resistance.

[0049] As another embodiment, two rows of first conductive type first source regions 3 are arranged, and the two rows of first conductive type first source regions 3 are arranged along the first direction, and the first conductive type second source regions 4 are located between the two rows of first conductive type first source regions 3, and each row of first conductive type first source regions 3 and multiple first conductive type second source regions 4 are arranged alternately along the first direction, so that each first conductive type second source region 4 can be inserted between two adjacent first conductive type first source regions 3 in each row of first conductive type first source regions 3, and the overlapping parts of the first conductive type second source regions 4 and the two rows of first conductive type first source regions 3 in the second direction are less than half of the width of the first conductive type first source regions 3 in the second direction, thereby further increasing the junction area of ​​the P / N junction and effectively enhancing the surge resistance of the MOS device.

[0050] As a specific implementation, the high surge MOS device further includes a first conductive type substrate 5 and a first conductive type epitaxial layer 6, wherein the first conductive type substrate 5 selects N-type silicon as a substrate, the first conductive type epitaxial layer 6 is arranged on the front side of the first conductive type substrate 5, the gate structure 1 is arranged on the front side of the first conductive type epitaxial layer 6, and a plurality of gate structures 1 are arranged at intervals on the front side of the first conductive type epitaxial layer 6,

[0051] The second conductive type body region 2 is arranged on the front surface of the first conductive type epitaxial layer 6 and in the first conductive type epitaxial layer 6, the second conductive type body region 2 is arranged between two adjacent gate structures 1, and the first conductive type first source region 3 and the first conductive type second source region 4 are located in the second conductive type body region 2;

[0052] Further, a first conductive type high resistance region 7 is provided on the back side of the second conductive type body region 2, the first conductive type high resistance region 7 is located in the first conductive type epitaxial layer 6, the resistivity of the first conductive type high resistance region is higher than the resistivity of the first conductive type epitaxial layer 6, a second conductive type extension column 8 is provided in the first conductive type high resistance region 7, the second conductive type extension column 8 extends toward the second conductive type body region 2 until it is connected to the second conductive type body region 2, and the second conductive type extension column 8 also extends toward the first conductive type substrate 5 until it extends into the first conductive type epitaxial layer 6 and is connected to the first conductive type epitaxial layer 6, through the provision of the first conductive type high resistance region 7;

[0053] Under high current conditions, a considerable portion of the electron current will flow through the first conductive type high resistance region 7. There is a parasitic resistance in the first conductive type high resistance region 7. Therefore, a lateral voltage drop will be generated in the first conductive type high resistance region 7, causing the electric potential below the center of the second conductive type body region 2 to be significantly reduced. The P / N junction in the device can be opened more effectively to achieve a higher current capacity, thereby enabling the device to have a higher surge current resistance capability, further enhancing the surge resistance capability.

[0054] Example 2

[0055] Reference Figure 2-Figure 4 As shown, this embodiment provides a method for preparing a high-surge MOS device, comprising:

[0056] S1, selecting a first conductive type substrate 5, and growing a first conductive type epitaxial layer 6 on the first conductive type substrate 5, wherein the first conductive type substrate 5 selects N-type silicon as a substrate, and the first conductive type epitaxial layer 6 is grown by an epitaxial process;

[0057] S2, growing a gate oxide layer 9 on the front surface of the first conductive type epitaxial layer 6, and etching away a portion of the gate oxide layer 9 by photolithography blocking, and depositing polysilicon on the front surface of the gate oxide layer 9, i.e., a portion of the first conductive type epitaxial layer 6 by photolithography blocking again, to form a plurality of gate structures 1;

[0058] S3, injecting high-resistivity first-conductivity-type ions into the front surface of the first-conductivity-type epitaxial layer 6 of the gate-free structure 1, and advancing at high temperature to form a first-conductivity-type high-resistance region 7;

[0059] S4, injecting second conductive type ions into the first conductive type high resistance region 7 and advancing at high temperature to form second conductive type extension columns 8 and second conductive type body regions 2;

[0060] S5, by placing a plurality of staggered S-shaped photolithography shielding plates on the front surface of the second conductive type body region 2 along the first direction, and implanting the first conductive type ions in the area without the photolithography shielding plates on the front surface of the second conductive type body region 2, so as to form a first conductive type first source region 3 and a first conductive type second source region 4;

[0061] S6, an insulating dielectric layer 10 is deposited on the front side of the first conductive type epitaxial layer 6 so that the insulating dielectric layer 10 wraps the gate structure 1, and then the insulating dielectric layer 10 is etched to etch a plurality of through holes on the insulating dielectric layer 10, thereby forming a metal contact through hole 13, the metal contact through hole 13 is located above the second conductive type body region 2, and during etching, 0.3 mm to 0.4 mm more is etched into the first conductive type epitaxial layer 6 to ensure that the insulating dielectric layer 10 can be completely removed, so that the metal contact point is exposed, ensuring the stability and reliability of the electrical connection, depositing metal on the front side of the insulating dielectric layer 10, and filling the metal contact through hole 13 to form a front metal layer 11, and depositing metal on the back side of the first conductive type substrate 5 to form a back metal layer 12.

[0062] By setting a first conductive type first source region 3 and a first conductive type second source region 4, and the first conductive type first source region 3 and the first conductive type second source region 4 are arranged in a staggered manner, the junction area of ​​the second conductive type body region 2 in the MOS device can be significantly increased, thereby effectively increasing the junction area of ​​the P / N junction, and effectively enhancing the surge resistance of the MOS device, so that it can adapt to application environments with higher surge currents and high voltage shocks, and has a wider adaptability.

[0063] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0064] The above description is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A high surge MOS device, characterized in that: include: A gate structure, at least two of which are provided; A second conductive type body region is disposed between the two gate structures; A first conductive type first source region, disposed in a second conductive type body region and provided in plurality; A second source region of the first conductivity type is disposed in the body region of the second conductivity type and is provided in plurality; A plurality of first conductive type first source regions are arranged along a first direction, a plurality of first conductive type second source regions are arranged along the first direction, the first conductive type first source regions and the first conductive type second source regions are at different positions in the second direction, the first conductive type first source regions and the second conductive type second source regions are alternately arranged in sequence along the first direction, and the first conductive type first source regions are connected to adjacent first conductive type second source regions.

2. The high surge MOS device according to claim 1, characterized in that: The width of the overlapping portion of adjacent first conductivity type first source regions and first conductivity type second source regions in the second direction is smaller than half of the width of the first conductivity type first source region and / or the first conductivity type second source region in the second direction.

3. The high surge MOS device according to claim 1, characterized in that: A plurality of first conductive type first source regions and a plurality of first conductive type second source regions are arranged in an S-shape along a first direction.

4. The high surge MOS device according to claim 1, characterized in that: The first conductive type first source regions are arranged in two rows, and the two rows of the first conductive type first source regions are arranged along the first direction. The first conductive type second source regions are located between the two rows of the first conductive type first source regions, and each row of the first conductive type first source regions is arranged alternately with multiple first conductive type second source regions along the first direction.

5. The high surge MOS device according to claim 1, characterized in that: The first conductive type first source region and the first conductive type second source region have the same size.

6. The high surge MOS device according to claim 1, characterized in that: Also includes: a first conductive type substrate; A first conductive type epitaxial layer is arranged on the front side of the first conductive type substrate, the gate structure is arranged on the front side of the first conductive type epitaxial layer, the second conductive type body region is arranged on the front side of the first conductive type epitaxial layer and is arranged in the first conductive type epitaxial layer, and the first conductive type first source region and the first conductive type second source region are located in the second conductive type body region.

7. The high surge MOS device according to claim 6, characterized in that: A first conductivity type high resistance region is disposed on the back side of the second conductivity type body region, and the resistivity of the first conductivity type high resistance region is higher than the resistivity of the first conductivity type epitaxial layer.

8. The high surge MOS device according to claim 7, characterized in that: It also includes a second conductive type extension column, which is arranged in the first conductive type high resistance region and is respectively connected to the second conductive type body region and the first conductive type epitaxial layer.

9. The high surge MOS device according to claim 8, characterized in that: At least two second conductivity type extension columns are correspondingly arranged at each second conductivity type body region, and a plurality of second conductivity type extension columns are arranged in the first conductivity type high resistance region at intervals along the first direction.

10. A method for preparing a high surge MOS device, characterized in that: include: Selecting a first conductive type substrate, and growing a first conductive type epitaxial layer on the first conductive type substrate; Depositing polysilicon on a partial area of ​​the front surface of the first conductive type epitaxial layer by photolithography masking to form a plurality of gate structures; Implanting first conductivity type ions with high resistivity into the front surface of the first conductivity type epitaxial layer without a gate structure to form a first conductivity type high resistance region; Implanting second conductive type ions at the first conductive type high resistance region to form second conductive type extension columns and second conductive type body regions; Placing a plurality of staggered S-shaped photolithography shielding plates along a first direction on the front surface of the second conductive type body region, and implanting first conductive type ions in a region without the photolithography shielding plates on the front surface of the second conductive type body region, so as to form a first conductive type first source region and a first conductive type second source region; An insulating dielectric layer and a front metal layer are formed on the front side of the first conductive type epitaxial layer, and a back metal layer is formed on the back side of the first conductive type substrate.

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